Chip verification method and device, electronic equipment and storage medium

Abstract

The invention discloses a chip verification method and apparatus, an electronic device and a storage medium. The method comprises the steps of obtaining a plurality of first operation records generated by a target chip in a current operation process; wherein an occurrence time point corresponding to the first operation record is marked on the first operation record; selecting at least one first operation record representing abnormal operation of the target chip from the plurality of first operation records as a second operation record; and on the basis of the occurrence time points corresponding to the second operation records, the problem time point of abnormal operation of the target chip is determined, the problem time point is used for indicating the generation time of associated operation data needing to be acquired in the re-operation process of the target chip, and the associated operation data is used for carrying out anomaly analysis on the target chip. Through the above mode, the problem time point of abnormal operation of the target chip can be quickly and accurately determined.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip verification method, device, electronic device and storage medium. Background Art

[0002] As the scale of chips continues to expand and the functions of chip design become increasingly complex, the complexity and time of chip verification also increase exponentially. It is becoming increasingly difficult to locate the time point of the problem (the time point of the error). It is often difficult to locate the time point of the problem (the time point of the error), making it even more difficult to locate the specific problem of the error. This is a problem that plagues chip verifiers. Summary of the invention

[0003] The present application at least provides a chip verification method, device, electronic device and storage.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a chip verification method, the method comprising: obtaining several first operation records generated by the target chip during this operation process; wherein the first operation record is marked with the occurrence time point corresponding to the first operation record; from the several first operation records, select at least one first operation record that characterizes the operation abnormality of the target chip as the second operation record; based on the occurrence time point corresponding to each second operation record, determine the problem time point where the target chip has the operation abnormality, wherein the problem time point is used to indicate the generation time of the associated operation data that needs to be obtained during the re-operation of the target chip, and the associated operation data is used to perform abnormality analysis on the target chip.

[0005] Therefore, the second operation record is an operation record that characterizes the abnormal operation of the target chip. Therefore, the occurrence time point corresponding to the second operation record is the time point when the target chip has a problem and operates abnormally, that is, the problem time point when the target chip has the abnormal operation. Therefore, based on the occurrence time points marked by each second operation record, the problem time point when the target chip has the abnormal operation can be quickly and accurately determined.

[0006] Furthermore, users can locate specific problems on the chip based on the located problem time point to complete the verification of the chip. Since the problem time point when the chip has an abnormality is accurately and quickly located, users can locate the specific problem at the location where the chip has an operating abnormality without having to analyze the entire operating process of the chip to locate the specific problem, which shortens the chip verification cycle and improves the efficiency of chip verification.

[0007] Each first operation record includes at least one of log data and debug data.

[0008] Therefore, the specific data type of the first operation record can be flexibly set.

[0009] Among them, each first operation record includes log data, and the log data includes an event description of a log event; from a number of first operation records, at least one first operation record that characterizes the abnormal operation of the target chip is selected as the second operation record, including: analyzing the event description of each log event to determine whether each log event is an error event; in response to the log event being an error event, the first operation record corresponding to the log event is used as the second operation record.

[0010] Therefore, when the log event in the log data is an error event, it indicates that the target chip is abnormal at this moment and has problems, and when the log event in the log data is an error event, the event description of the log event will describe the error situation of the log event. Therefore, when the first operation record includes log data, by analyzing the event description of each log event, it is possible to determine whether each log event is an error event, so that when it is determined that the log event is an error event, the first operation record corresponding to the log event is determined to be an operation record that characterizes the abnormal operation of the target chip.

[0011] Among them, the event description of each log event is analyzed to determine whether each log event is an error event, including: analyzing whether the event description of each log event is an error code or an event error cause; in response to the event description of the log event being an error code and / or an event error cause, determining that the log event is an error event.

[0012] Therefore, when the event description of the log event is an error code or an event error reason, it indicates that the target chip is abnormal at this moment and there is a problem. Therefore, by analyzing the event description of each log event, it can be determined whether each log event is an error event.

[0013] Among them, each first operation record includes debug data; from a number of first operation records, at least one first operation record that characterizes the abnormal operation of the target chip is selected as the second operation record, including: analyzing each debug data to determine whether each debug data includes abnormal error information; in response to the debug data including abnormal error information, the first operation record corresponding to the debug data is used as the second operation record.

[0014] Therefore, when the chip runs abnormally, the abnormal conditions and error information generated during the operation will be captured and recorded, that is, the abnormal error information will be captured and recorded. The debug data is analyzed to determine whether there is abnormal error information captured and recorded in the debug data, and the abnormal error information can only be captured and recorded when the chip runs abnormally. Therefore, when there is abnormal error information captured and recorded in the debug data, it can be determined that the first operation record corresponding to the debug data is an operation record that characterizes the abnormal operation of the chip.

[0015] Among them, each first operation record includes log data and debug data; from a number of first operation records, at least one first operation record that characterizes the abnormal operation of the target chip is selected as the second operation record, including: for each first operation record, analyzing the log data and debug data in the first operation record to determine whether the log data and debug data in the first operation record characterize the abnormal operation of the target chip; in response to the log data and debug data in the first operation record both characterizing the abnormal operation of the target chip, using the first operation record as the second operation record.

[0016] Therefore, when the target chip operates abnormally at a certain operating time point, the operating data related to the target chip at that operating moment should all be abnormal. Therefore, when the log data and debug data in the first operating record (log data and debug data are different operating data at the same operating time point) are both abnormal, it can be sufficient to explain that the target chip is operating abnormally at that operating time point, that is, it can be sufficient to explain that the operating data generated at that operating time point, namely the first operating record, is an operating record that characterizes the abnormal operation of the target chip, thereby improving the accuracy of the determined operating record that characterizes the abnormal operation of the target chip, and the problem points determined subsequently based on this are more accurate, thereby improving the accuracy of chip verification.

[0017] Wherein, based on the occurrence time points corresponding to each second operation record, determining the problem time points at which the target chip has operation abnormalities, including: for the occurrence time points corresponding to each second operation record, obtaining a first time point before the occurrence time point and a second time point after the occurrence time point; wherein the time interval between the first time point and the occurrence time point meets the first interval requirement, and the time interval between the second time point and the occurrence time point meets the second interval requirement; taking the occurrence time points, the first time points and the second time points corresponding to each second operation record as the problem time points at which the target chip has operation abnormalities.

[0018] Therefore, the time range including the occurrence time point corresponding to the second operation record is used as the problem time point when the target chip has an operation abnormality, thereby improving the accuracy of the determined problem time point.

[0019] A counter is provided in the target chip, the occurrence time point is represented by the count value of the counter, and the counter is driven by a clock in the target chip to count.

[0020] Therefore, the count value of the counter may be set to represent the occurrence time point corresponding to the first operation record, and the representation of the occurrence time point corresponding to the first operation record is simpler.

[0021] Among them, after determining the problem time point at which the target chip has an operation abnormality based on the occurrence time points corresponding to each second operation record, the chip verification method includes: obtaining the associated operation data generated by re-running the target chip to the problem time point; and performing an abnormality analysis on the target chip based on the associated operation data.

[0022] Therefore, users can locate specific problems at the location where the chip operates abnormally without having to analyze the entire operation process of the chip to locate the specific problem, shortening the chip verification cycle and improving the efficiency of chip verification.

[0023] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a chip verification device, the chip verification method includes an acquisition module, a selection module and a determination module; the acquisition module is used to obtain a number of first operation records generated by the target chip during this operation process; wherein the first operation record is marked with the occurrence time point corresponding to the first operation record; the selection module is used to select at least one first operation record representing the abnormal operation of the target chip from the several first operation records as the second operation record; the determination module is used to determine the problem time point of the operation abnormality of the target chip based on the occurrence time point corresponding to each second operation record, wherein the problem time point is used to indicate the generation time of the associated operation data to be obtained during the re-operation of the target chip, and the associated operation data is used to perform abnormal analysis on the target chip.

[0024] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide an electronic device, the electronic device includes a processor and a memory, the memory stores program instructions, and the processor is used to execute the program instructions to implement the above chip verification method.

[0025] In order to solve the above technical problem, another technical solution adopted by the present application is: providing a computer-readable storage medium, which is used to store program instructions, and the program instructions can be executed to implement the above chip verification method.

[0026] In the above technical solution, the second operation record is an operation record that characterizes the abnormal operation of the target chip. Therefore, the occurrence time point corresponding to the second operation record is the time point when the target chip has a problem and operates abnormally, that is, the problem time point when the target chip has the abnormal operation. Therefore, based on the occurrence time points marked by each second operation record, the problem time point when the target chip has the abnormal operation can be quickly and accurately determined.

[0027] Furthermore, users can locate specific problems on the chip based on the located problem time point to complete the verification of the chip. Since the problem time point when the chip has an abnormality is accurately and quickly located, users can locate the specific problem at the location where the chip has an operating abnormality without having to analyze the entire operating process of the chip to locate the specific problem, which shortens the chip verification cycle and improves the efficiency of chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a flowchart of an embodiment of a chip verification method provided by the present application;

[0029] Figure 2 It is a structural schematic diagram of an embodiment of a chip verification device provided by the present application;

[0030] Figure 3 It is a structural schematic diagram of an embodiment of an electronic device provided by the present application;

[0031] Figure 4 It is a structural schematic diagram of an embodiment of a computer-readable storage medium provided by the present application. DETAILED DESCRIPTION

[0032] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0033] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0034] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of, for example, including at least one of A, B, and C, can mean including any one or more elements selected from the set consisting of A, B, and C.

[0035] See also Figure 1 , Figure 1 1 is a flow chart of an embodiment of a chip verification method provided by the present application. It should be noted that if there are substantially the same results, this embodiment does not necessarily Figure 1 The process sequence shown is limited. Figure 1 As shown, this embodiment includes:

[0036] Step S11: obtaining a plurality of first operation records generated by the target chip during the current operation process.

[0037] The method of this embodiment is used to quickly and accurately locate the problem time point of the target chip. The user locates the problem of the target chip based on the problem time point of the target chip to complete the verification of the target chip. That is, the method of this embodiment shortens the period of locating the problem time point of the chip and improves the efficiency of locating the problem time point of the chip, thereby shortening the period of chip verification and improving the efficiency of chip verification.

[0038] In this embodiment, a number of first operation records generated by the target chip during this operation process are obtained, wherein the first operation record is marked with the occurrence time point corresponding to the first operation record. By marking the occurrence time points corresponding to the number of first operation records generated by the target chip during this operation process, the occurrence time point corresponding to the first operation record that characterizes the abnormal operation of the target chip can be analyzed later, so that the abnormal problem time point in the entire operation process of the target chip can be determined, shortening the cycle of locating the chip problem time point and improving the efficiency of locating the chip problem time point. Furthermore, the user can locate the specific problem of the chip based on the located problem time point to complete the verification of the chip. Since the problem time point at which the chip has an abnormality is accurately and quickly located, the user can locate the specific problem at the location where the chip has an abnormal operation without analyzing the entire operation process of the chip to locate the specific problem, shortening the chip verification cycle and improving the efficiency of chip verification.

[0039] It should be noted that the occurrence time point corresponding to the first operation record is a time point relative to the start time of the chip operation, rather than an absolute time point (an absolute time point refers to a fixed time point that does not depend on other reference objects or conditions, such as 9:30 on May 5).

[0040] In one embodiment, the first operation records generated by the target chip during the current operation can be obtained from the cloud storage or the local storage. Of course, in other embodiments, the user can also control the operation of the target chip in real time to obtain the first operation records generated by the target chip during the current operation, which is not limited here.

[0041] In one embodiment, a counter is provided in the target chip, and the occurrence time point is represented by the count value of the counter, and the counter is driven by the clock in the target chip to count. After the target chip starts to run, the clock in the target chip keeps rotating, and when the clock rotates one circle or one cycle ends, a driving signal is generated and sent to the counter to drive the counter to increase by one unit; for example, the first operation record A is generated when the clock rotates the third circle or the third cycle after the target chip starts to run, and the count value of the counter is 3, and the count value 3 of the counter is used as the occurrence time point of the first operation record A.

[0042] In one embodiment, each first operation record includes at least one of log data and debug data. Log data, i.e., log data, is a data set used to record detailed information of various events and operations in the chip. It is usually used for debugging, monitoring, analysis and auditing purposes to help developers, system managers and other relevant personnel understand the operating status and performance of the chip. In the field of chip verification, log data also plays an important role, and can record the behavior of the chip under various conditions, including the values ​​of internal registers, the operations performed, and any exceptions or errors that occur. Debug data usually refers to data used to help locate and solve problems during the chip verification process. These data may include status, variable values, log entries, memory dumps, etc. They are crucial for developers or system administrators, etc., because they provide detailed information about the current status of the chip and possible problems.

[0043] Of course, in other implementations, each first operation record may also include other operation data, which is not specifically limited here.

[0044] Step S12: selecting at least one first operation record representing abnormal operation of the target chip from the plurality of first operation records as the second operation record.

[0045] In this embodiment, at least one first operation record characterizing the abnormal operation of the target chip is selected from a plurality of first operation records as the second operation record. At least one second operation record characterizing the abnormal operation of the target chip is selected from a plurality of first operation records generated by the target chip during this operation, and then based on the occurrence time point corresponding to the operation record characterizing the abnormal operation of the target chip, the problem time point at which the target chip has the abnormal operation is determined, thereby quickly and accurately determining the problem time point at which the target chip has the abnormal operation, shortening the chip verification cycle and improving the efficiency of chip verification.

[0046] In one embodiment, each first operation record includes log data, and the log data includes an event description of a log event. At this time, at least one first operation record that characterizes the abnormal operation of the target chip is selected from a number of first operation records as the second operation record. Specifically, the event description of each log event is analyzed to determine whether each log event is an error event; in response to the log event being an error event, the first operation record corresponding to the log event is used as the second operation record.

[0047] It should be noted that log data includes timestamp (recording the specific time when each log event occurs), event description (describing the specific event that occurred, such as function call, state change, error code, etc.), parameter value (recording the value of the parameter or variable related to the log event, which helps to understand the context when the log event occurs), verification status (indicating the progress or result of the current verification, such as pass, fail, skip, etc.) and error code information (if an error occurs, the error code and related error information should be recorded to help quickly locate the problem). Log events refer to event records generated by software or systems; for example, when we are using a certain software or operating system, the software or system will record various events in the background, such as user operations, system responses, errors, etc. These events are recorded as log events and saved in log files; if we encounter a software crash or system error, we can locate the problem by viewing these log events and understand the cause and process of the error. A log event includes a timestamp (recording the specific time when the event occurred, such as "2024-4-7 17:15:00"), an event description (describing the specific event that occurred, such as "the user tried to open file a" or "the application crashed due to insufficient system memory"), a process ID and a thread ID (identifying the process and thread where the event occurred), and an error message (if the event is an error event, the error code and related error information will be recorded, such as "error code E001: file not found").

[0048] That is to say, when the log event in the log data is an error event, it indicates that the target chip is abnormal at this moment and there is a problem. In addition, when the log event in the log data is an error event, the event description of the log event will describe the error situation of the log event, and the error code and related error information will be recorded in the error information record of the log event. Therefore, by analyzing the event description or error information record of each log event, it is possible to determine whether each log event is an error event, so that when it is determined that the log event is an error event, it is determined that the first operation record corresponding to the log event is an operation record that characterizes the abnormal operation of the target chip.

[0049] In a specific implementation, the event description of each log event is analyzed to determine whether each log event is an error event, specifically: analyzing whether the event description of each log event is an error code or an event error cause; in response to the event description of the log event being an error code and / or an event error cause, determining that the log event is an error event. That is, when the event description or error information record of the log event in the log data is an error code or an event error cause, it indicates that the log event is an error event, and the corresponding first operation record is an operation record that characterizes the abnormal operation of the target chip.

[0050] For example, the event description of log event A is analyzed to determine that the event description of log event A is "insufficient system memory causes application crash", and the event description of log event A describes the cause of the event error, so log event A is determined to be an error event. For another example, the error information record of log event B is analyzed to determine that the error information record of log event B is "error code E001: file not found", and the error information record of log event B is the error code and the corresponding error cause, so log event B is determined to be an error event.

[0051] In one embodiment, each first operation record includes debug data. At this time, at least one first operation record that characterizes the abnormal operation of the target chip is selected from a number of first operation records as the second operation record. Specifically, each debug data is analyzed to determine whether each debug data includes abnormal error information; in response to the debug data including abnormal error information, the first operation record corresponding to the debug data is used as the second operation record.

[0052] It should be noted that in chip development, debug data usually refers to data collected and analyzed during the debugging process, which helps identify and solve errors or problems. Debug data can include variable values, call lines, memory usage, thread status, log information, exceptions and errors (capturing and recording exceptions and error information generated when the program is running, which usually directly points to the problem) and performance data.

[0053] That is to say, when the chip runs abnormally, the abnormal conditions and error information generated during the operation will be captured and recorded, that is, the abnormal error information will be captured and recorded. The debug data is analyzed to determine whether there is abnormal error information captured and recorded in the debug data, and the abnormal error information can only be captured and recorded when the chip runs abnormally. Therefore, when there is abnormal error information captured and recorded in the debug data, it can be determined that the first operation record corresponding to the debug data is an operation record that characterizes the abnormal operation of the chip.

[0054] In one embodiment, each first operation record includes log data and debug data. At this time, at least one first operation record that characterizes abnormal operation of a target chip is selected from a number of first operation records as the second operation record. Specifically, for each first operation record, the log data and debug data in the first operation record are analyzed to determine whether the log data and debug data in the first operation record characterize abnormal operation of the target chip; in response to the log data and debug data in the first operation record both characterizing abnormal operation of the target chip, the first operation record is used as the second operation record.

[0055] When the target chip operates abnormally at a certain operating time point, the operating data related to the target chip at that operating moment should all be abnormal. Therefore, only when the log data and debug data in the first operating record (log data and debug data are different operating data at the same operating time point) are both abnormal, can it be sufficient to explain that the target chip is operating abnormally at that operating time point, that is, only when it is sufficient to explain that the operating data generated at that operating time point, namely the first operating record, is an operating record that characterizes the abnormal operation of the target chip, improves the accuracy of the determined operating record that characterizes the abnormal operation of the target chip, and the problem points determined subsequently based on this are more accurate, thereby improving the accuracy of chip verification.

[0056] Of course, in other embodiments, each first operation record includes log data and debug data, and at least one first operation record that characterizes the abnormal operation of the target chip is selected from several first operation records as the second operation record. It can also be: for each first operation record, the log data and debug data in the first operation record are analyzed to determine whether the log data and debug data in the first operation record characterize the abnormal operation of the target chip; in response to one of the log data and debug data in the first operation record characterizing the abnormal operation of the target chip, the first operation record is used as the second operation record.

[0057] Step S13: Based on the occurrence time points corresponding to the second operation records, determine the problem time point at which the target chip has an operation abnormality.

[0058] In this embodiment, based on the occurrence time points corresponding to each second operation record, the problem time point at which the target chip has an operation abnormality is determined, wherein the problem time point is used to indicate the generation time of the associated operation data to be obtained during the re-operation of the target chip, and the associated operation data is used to perform an abnormality analysis on the target chip. The second operation record is an operation record that characterizes the operation abnormality of the target chip, so the occurrence time point corresponding to the second operation record is the time point at which the target chip has a problem and operates abnormally, that is, the problem time point at which the target chip has an operation abnormality; therefore, based on the occurrence time points marked by each second operation record, the problem time point at which the target chip has an operation abnormality can be quickly and accurately determined. After determining the problem time point at which the target chip has an abnormal operation based on the occurrence time point corresponding to each second operation record, feedback is given to the user, and the user can learn the occurrence time point of the problem with the target chip based on the problem time point. The user subsequently re-operates the target chip and obtains the associated operation data generated by the target chip at the problem time point during the re-operation of the target chip (this associated operation data includes not only log data and debug data, but also other data. The acquisition of multiple data is conducive to the subsequent determination of specific problems by users), so as to facilitate the subsequent analysis of the target chip based on the associated operation data and locate the specific problem.

[0059] In a specific implementation, the time point at which the target chip has an abnormal operation is used as a trigger condition. Then, when the target chip is re-run, the trigger condition is met when the target chip runs to the time point of the problem. At this time, the associated operation data generated at the time point of the problem is captured, so as to facilitate the subsequent analysis of the target chip based on the associated operation data to locate the specific problem. The trigger condition is usually used to specify a condition or event. Once the condition or event is met or occurs, it will trigger a specific verification operation or data capture, which helps to accurately capture and record key events or states in complex chip behaviors, thereby effectively performing verification and debugging.

[0060] For example, a counter is set in the target chip, the occurrence time point is represented by the count value of the counter, and the counter is driven by the clock in the target chip to count: it is determined that the target chip has an operation abnormality when the counter value of the counter is 999, and the counter value of 999 is used as the trigger condition; the user re-runs the chip, the clock in the chip rotates, and the counter counts under the drive of the clock. When the counter counts to a counter value of 999, the trigger condition is met, indicating that the chip has been running for a period of time and has reached the problem time point. At this time, the associated operation data generated by the chip when the counter value is 999 is captured, so as to facilitate the subsequent analysis of the target chip based on the associated operation data and locate the specific problem.

[0061] In one embodiment, based on the occurrence time points corresponding to the second operation records, the problem time point at which the target chip has an operation abnormality is determined, specifically: the occurrence time points corresponding to the second operation records are used as the problem time points at which the target chip has an operation abnormality. In other words, the occurrence time points corresponding to the operation records that characterize the operation abnormality of the target chip are directly used as the problem time points at which the target chip has an operation abnormality.

[0062] In other embodiments, based on the occurrence time points corresponding to each second operation record, the problem time point at which the target chip has an operation abnormality is determined, specifically: for the occurrence time points corresponding to each second operation record, a first time point before the occurrence time point and a second time point after the occurrence time point are obtained, wherein the time interval between the first time point and the occurrence time point meets the first interval requirement, and the time interval between the second time point and the occurrence time point meets the second interval requirement; the occurrence time point, the first time point, and the second time point corresponding to each second operation record are used as the problem time point at which the target chip has an operation abnormality. In other words, the occurrence time point corresponding to the second operation record, the first time point before the occurrence time point and meeting the first interval requirement, and the second time point after the occurrence time point and meeting the second interval requirement are used as the problem time point at which the target chip has an operation abnormality, that is, a time range is used as the problem time point at which the target chip has an operation abnormality.

[0063] There is no limitation on the first spacing requirement and the second spacing requirement, and they can be set according to actual use needs.

[0064] See also Figure 2 , Figure 2It is a structural diagram of an embodiment of a chip verification device provided by the present application. The chip verification device 20 includes an acquisition module 21, a selection module 22 and a determination module 23; the acquisition module 21 is used to acquire a number of first operation records generated by the target chip during this operation process; wherein the first operation record is marked with an occurrence time point corresponding to the first operation record; the selection module 22 is used to select at least one first operation record representing the abnormal operation of the target chip from the first operation records as the second operation record; the determination module 23 is used to determine the problem time point of the abnormal operation of the target chip based on the occurrence time point corresponding to each second operation record, wherein the problem time point is used to indicate the generation time of the associated operation data to be acquired during the re-operation of the target chip, and the associated operation data is used to perform abnormal analysis on the target chip.

[0065] Each of the above-mentioned first operation records includes at least one of log data and debug data.

[0066] Among them, each of the above-mentioned first operation records includes log data, and the log data includes an event description of a log event; the selection module 22 is used to select at least one first operation record that characterizes the abnormal operation of the target chip from a number of first operation records as the second operation record, including: analyzing the event description of each log event to determine whether each log event is an error event; in response to the log event being an error event, using the first operation record corresponding to the log event as the second operation record.

[0067] Among them, the selection module 22 is used to analyze the event description of each log event to determine whether each log event is an error event, including: analyzing whether the event description of each log event is an error code or an event error cause; in response to the event description of the log event being an error code and / or an event error cause, determining that the log event is an error event.

[0068] Among them, each of the above-mentioned first operation records includes debug data; the selection module 22 is used to select at least one first operation record that characterizes the abnormal operation of the target chip from a number of first operation records as the second operation record, including: analyzing each debug data to determine whether each debug data includes abnormal error information; in response to the debug data including abnormal error information, using the first operation record corresponding to the debug data as the second operation record.

[0069] Among them, each of the above-mentioned first operation records includes log data and debug data; the selection module 22 is used to select at least one first operation record that characterizes the abnormal operation of the target chip from a number of first operation records as the second operation record, including: for each first operation record, analyzing the log data and debug data in the first operation record to determine whether the log data and debug data in the first operation record characterize the abnormal operation of the target chip; in response to the log data and debug data in the first operation record both characterizing the abnormal operation of the target chip, using the first operation record as the second operation record.

[0070] Among them, the determination module 23 is used to determine the time point when the target chip has an operation abnormality problem based on the occurrence time point corresponding to each second operation record, including: using the occurrence time point corresponding to each second operation record as the time point when the target chip has an operation abnormality problem.

[0071] Among them, the determination module 23 is used to determine the problem time point at which the target chip has an operation abnormality based on the occurrence time point corresponding to each second operation record, including: for the occurrence time point corresponding to each second operation record, obtain a first time point before the occurrence time point and a second time point after the occurrence time point; wherein the time interval between the first time point and the occurrence time point meets the first interval requirement, and the time interval between the second time point and the occurrence time point meets the second interval requirement; the occurrence time point, the first time point and the second time point corresponding to each second operation record are used as the problem time point at which the target chip has an operation abnormality.

[0072] Wherein, a counter is provided in the target chip, the occurrence time point is represented by the count value of the counter, and the counter is driven by a clock in the target chip to count.

[0073] Among them, after determining the problem time point at which the target chip has an operation abnormality based on the occurrence time points corresponding to each second operation record, the determination module 23 is also used to: obtain the associated operation data generated when the target chip re-operates to the problem time point; and perform an abnormality analysis on the target chip based on the associated operation data.

[0074] See also Figure 3 , Figure 3 3 is a schematic diagram of the structure of an embodiment of an electronic device provided by the present application. The electronic device 30 includes a memory 31 and a processor 32 coupled to each other, and the processor 32 is used to execute program instructions stored in the memory 31 to implement the steps of any of the above chip verification method embodiments. In a specific implementation scenario, the electronic device 30 may include but is not limited to: a microcomputer, a server, and in addition, the electronic device 30 may also include a mobile device such as a laptop computer and a tablet computer, which is not limited here.

[0075] Specifically, the processor 32 is used to control itself and the memory 31 to implement the steps of any of the above chip verification method embodiments. The processor 32 may also be referred to as a CPU (Central Processing Unit). The processor 32 may be an integrated circuit chip having signal processing capabilities. The processor 32 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. In addition, the processor 32 may be implemented by an integrated circuit chip.

[0076] See also Figure 4 , Figure 4 It is a structural diagram of an embodiment of a computer-readable storage medium provided by the present application. The computer-readable storage medium 40 of the embodiment of the present application stores a program instruction 41, and when the program instruction 41 is executed, it implements the method provided by any embodiment of the chip verification method of the present application and any non-conflicting combination. Among them, the program instruction 41 can form a program file and be stored in the above-mentioned computer-readable storage medium 40 in the form of a software product, so that a computer device (which can be a personal computer, a server, or a network device, etc.) executes all or part of the steps of each implementation method of the present application. The aforementioned computer-readable storage medium 40 includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes, or terminal devices such as computers, servers, mobile phones, and tablets.

[0077] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0078] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip verification method, characterized in that: The method comprises: Acquire a plurality of first operation records generated by the target chip during the current operation process; wherein the first operation records are marked with the occurrence time points corresponding to the first operation records; From the plurality of first operation records, select at least one first operation record indicating that the target chip is operating abnormally as a second operation record; Based on the occurrence time points corresponding to each of the second operation records, the problem time points at which the target chip has an operation abnormality are determined, wherein the problem time points are used to indicate the generation time of associated operation data that need to be obtained during the re-operation of the target chip, and the associated operation data are used to perform abnormality analysis on the target chip.

2. The method according to claim 1, characterized in that Each of the first operation records includes at least one of log data and debug data.

3. The method according to claim 2, characterized in that Each of the first operation records includes log data, and the log data includes an event description of a log event; and selecting at least one first operation record representing an abnormal operation of the target chip from the plurality of first operation records as the second operation record includes: Analyze the event description of each log event to determine whether each log event is an error event; In response to the log event being an error event, taking the first operation record corresponding to the log event as the second operation record.

4. The method according to claim 3, characterized in that The analyzing the event description of each log event to determine whether each log event is an error event includes: Analyze whether the event description of each log event is an error code or an event error cause; In response to the event description of the log event being an error code and / or an event error cause, the log event is determined to be an error event.

5. The method according to claim 2, characterized in that: Each of the first operation records includes debug data; and selecting at least one first operation record representing an abnormal operation of the target chip from the plurality of first operation records as the second operation record includes: Analyze each of the debug data to determine whether each of the debug data includes abnormal error information; In response to the debug data including abnormal error information, the first operation record corresponding to the debug data is used as the second operation record.

6. The method according to claim 2, characterized in that Each of the first operation records includes log data and debug data; The step of selecting at least one first operation record representing abnormal operation of the target chip from the plurality of first operation records as the second operation record comprises: For each of the first operation records, analyzing the log data and debug data in the first operation record to determine whether the log data and debug data in the first operation record indicate that the target chip is operating abnormally; In response to the fact that both the log data and the debug data in the first operation record indicate that the target chip operates abnormally, the first operation record is used as the second operation record.

7. The method according to claim 1, characterized in that The determining, based on the occurrence time points corresponding to the second operation records, the problem time point at which the target chip has an operation abnormality includes: For each occurrence time point corresponding to the second operation record, a first time point before the occurrence time point and a second time point after the occurrence time point are obtained; wherein the time interval between the first time point and the occurrence time point meets a first interval requirement, and the time interval between the second time point and the occurrence time point meets a second interval requirement; The occurrence time point, the first time point, and the second time point corresponding to each of the second operation records are used as the problem time point at which the target chip has an operation abnormality.

8. The method according to claim 1, characterized in that The target chip is provided with a counter, the occurrence time point is represented by a count value of the counter, and the counter is driven by a clock in the target chip to count.

9. The method according to claim 1, characterized in that: After determining the time point at which the target chip has an abnormal operation problem based on the time points corresponding to the second operation records, the method further includes: Acquire the associated operation data generated by re-operating the target chip to the problem time point; Based on the associated operation data, an abnormality analysis is performed on the target chip.

10. A chip verification device, characterized in that: The chip verification device comprises: An acquisition module, used for acquiring a plurality of first operation records generated by the target chip during the current operation process; wherein the first operation records are marked with the occurrence time points corresponding to the first operation records; A selection module, configured to select at least one first operation record representing abnormal operation of the target chip from the plurality of first operation records as a second operation record; A determination module is used to determine the problem time point at which the target chip has an operation abnormality based on the occurrence time point corresponding to each second operation record, wherein the problem time point is used to indicate the generation time of the associated operation data to be obtained during the re-operation of the target chip, and the associated operation data is used to perform abnormality analysis on the target chip.

11. An electronic device, characterized in that: The electronic device comprises a processor and a memory, the memory stores program instructions, and the processor is used to execute the program instructions to implement the chip verification method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program instructions, and the program instructions can be executed to implement the chip verification method as described in any one of claims 1-9.

Images