Simulation verification system based on DFI interface

Abstract

The invention relates to the technical field of chip verification, in particular to a simulation verification system based on a DFI interface, the system comprises a memory controller, a verification component and a memory model, the memory controller is connected with the verification component through the DFI interface, the memory controller is used for transmitting an operation command and first data through the DFI interface, the verification component is connected with the memory model, and the memory model is connected with the verification component. The verification component is used for checking the operation command and the first data, analyzing the operation command to obtain address information and calling the memory model to operate the first data, and the memory model is used for operating the first data according to the received operation command, address information and first data sent by the verification component. It can be known that the verification component and the memory model can be constructed based on the verification language compatible with the verification platform, so that initialization only needs to configure the memory controller through the bus, the initialization time of the simulation verification system is saved, a more flexible backdoor data loading mode is provided, and the simulation verification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a simulation verification system based on a DFI interface. Background Art

[0002] A chip simulation verification system usually includes a memory controller, a DRAM PHY simulation model and a DRAM simulation model. For the DRAM simulation model, since the DRAM simulation model is usually provided by a DRAM supplier, the DRAM simulation model often has a large number of DRAM functions. However, in the chip simulation verification scenario, most of the functions provided by the DRAM simulation model may not be needed, that is, the functions of the DRAM simulation model are redundant. In addition, the functions provided by the DRAM simulation model are usually determined by its supplier, and it is difficult for users to use the functions that are not open to the supplier.

[0003] Moreover, the DRAM PHY simulation model and the DRAM simulation model may be provided by different suppliers. Although the suppliers can ensure the compatibility between the DRAM PHY simulation model and the DRAM simulation model, they cannot ensure the compatibility between the DRAM PHY simulation model and the DRAM simulation model and the test platform respectively. Therefore, the DRAM PHY simulation model and the DRAM simulation model are often built based on the RTL code, which results in the initialization of the chip simulation verification system requiring the configuration, simulation or training of the memory controller, DRAM PHY simulation model and DRAM simulation model respectively, resulting in low initialization efficiency of the chip simulation verification system, and then low verification efficiency of the chip simulation verification system.

[0004] In addition, since the DRAM simulation model is provided by its supplier, the DRAM simulation model may not contain an open data interface, which means that the business data loaded into the DRAM simulation model must be loaded through the front door of the memory controller and DRAM PHY simulation model, which in turn makes the loading of business data time-consuming and also leads to low verification efficiency of the chip simulation verification system.

[0005] Therefore, how to improve the verification efficiency of the chip simulation verification system has become an urgent problem to be solved. Summary of the invention

[0006] In view of the above technical problems, the technical solution adopted by the present invention is: A simulation verification system based on a DFI interface, the simulation verification system comprising: a memory controller, a verification component and a memory model, wherein the memory controller is constructed based on an RTL code language, the verification component is constructed based on a first verification language, the memory model is constructed based on a second verification language, the simulation verification system is defined in a verification platform, and the verification platform is compatible with the first verification language and the second verification language.

[0007] The memory controller is connected to the verification component via a DFI interface, and the memory controller is used to transmit operation commands via the DFI interface.

[0008] The verification component is connected to the memory model, and is used to check the operation command, parse the operation command to obtain address information, and call the memory model to perform an operation according to the operation command and the address information, and return the operation result to the memory controller.

[0009] The memory model is used to perform an operation according to the received operation command and the address information sent by the verification component, and return the operation result to the verification component.

[0010] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, the simulation verification system based on the DFI interface provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects: The present invention provides a simulation verification system based on a DFI interface, the simulation verification system comprising: a memory controller, a verification component and a memory model, wherein the memory controller is constructed based on an RTL code language, the verification component is constructed based on a first verification language, the memory model is constructed based on a second verification language, the simulation verification system is defined in a verification platform, the verification platform is compatible with the first verification language and the second verification language, the memory controller is connected to the verification component through a DFI interface, the memory controller is connected to the verification component through the DFI interface, the memory controller is used to transmit an operation command through the DFI interface, the verification component is connected to the memory model, the verification component is used to check the operation command, parse the operation command to obtain address information, and call the memory model to perform an operation according to the operation command and the address information, and return the operation result to the memory controller, and the memory model is used to perform an operation according to the received operation command and the address information sent by the verification component, and return the operation result to the verification component.

[0011] It can be seen that the present invention replaces the DRAM PHY simulation model and DRAM simulation model in the prior art with a verification component and a memory model. The functions of the memory model are more suitable for the functions required for chip simulation verification, and the memory model function opening is more flexible. Moreover, the verification component and the memory model can be constructed based on a verification language compatible with the verification platform, so that the initialization of the simulation verification system only needs to configure the memory controller through the bus, which greatly saves the initialization time of the simulation verification system. The verification platform can directly access the verification component and the memory model for data transmission, providing a more flexible backdoor data loading method, thereby improving the simulation verification efficiency of the simulation verification system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of the architecture of a simulation verification system based on a DFI interface provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] This embodiment provides a simulation verification system based on the DFI interface. Figure 1 , is a schematic diagram of the architecture of a simulation verification system based on a DFI interface provided by an embodiment of the present invention, the simulation verification system comprises: a memory controller, a verification component and a memory model, wherein the memory controller is constructed based on an RTL code language, the verification component is constructed based on a first verification language, the memory model is constructed based on a second verification language, the simulation verification system is defined in a verification platform, and the verification platform is compatible with the first verification language and the second verification language; The memory controller is connected to the verification component via a DFI interface, and the memory controller is used to transmit an operation command via the DFI interface; The verification component is connected to the memory model, and is used to check the operation command, parse the operation command to obtain address information, and call the memory model to perform an operation according to the operation command and the address information, and return the operation result to the memory controller; The memory model is used to perform an operation according to the received operation command and the address information sent by the verification component, and return the operation result to the verification component.

[0016] The verification component checks the DFI (DDR PHY Interface) interface to obtain an operation command, and then parses the operation command to obtain address information corresponding to the operation command.

[0017] The operation command may refer to a write data command, a read data command, etc.

[0018] Specifically, when the operation command is a write data command, the memory controller is also used to transmit the first data through the DFI interface. The first data may refer to the data that needs to be written into the memory model. The verification component calls the memory model to perform a write operation according to the operation command and the address information obtained by parsing, and writes the first data into the memory model. When the operation command is a read data command, the verification component calls the memory model to perform a read operation according to the operation command and the address information obtained by parsing, and reads the data from the memory model.

[0019] In a specific implementation, the first verification language belongs to a first language set, the second verification language belongs to a second language set, the first language set includes at least UVM verification language and SV verification language, and the second language set includes at least UVM verification language, SV verification language and C language.

[0020] The first verification language and the second verification language may be the same, for example, both may be SV language (SystemVerilog), or they may be different, for example, the first verification language may be UVM verification language (Universal Verification Methodology), and the second verification language may be C language.

[0021] In a specific implementation, the initialization of the simulation verification system includes: Initialize and configure the memory controller.

[0022] Among them, the initialization configuration may refer to configuring the registers in the memory controller through the bus. In the initialization of the simulation verification system, since the verification components and memory models are constructed based on the verification language compatible with the verification platform, the initialization of the verification components and memory models only needs to be achieved by passing parameters to modify the variables.

[0023] Specifically, compared with the simulation verification system formed by the memory controller, the DRAM PHY simulation model and the DRAM simulation model in the prior art, the DRAM PHY simulation model also needs to configure the registers in the DRAM PHY simulation model through the bus, and the DRAM PHY simulation model also needs to perform simulation operations, such as completing the clock locking through the phase-locked loop, etc. The DRAM simulation model configures the registers in the DRAM simulation model through the bus, and the DRAM simulation model also needs to perform basic training. Experiments show that the average initialization time of the existing simulation verification system is more than ten times the average initialization time of the simulation verification system provided in this embodiment. Therefore, the initialization of the simulation verification system provided in this embodiment only needs to configure the memory controller through the bus, which greatly saves the initialization time of the simulation verification system and improves the simulation verification efficiency of the simulation verification system.

[0024] In a specific implementation, the verification component is further used to receive second data, and send the second data to the memory model for loading.

[0025] The second data may refer to business data that needs to be loaded into the memory model.

[0026] In a specific implementation, the memory model is further used to receive third data and load the third data into the memory model.

[0027] Among them, since the verification component and the memory model can be constructed by a verification language compatible with the verification platform, the verification platform can directly access the verification component or the memory model for data transmission, and directly load the business data in the memory model through the backdoor loading method, providing a more flexible backdoor data loading method. In the prior art, if the supplier of the DRAM simulation model does not provide a backdoor loading method, the data needs to be loaded through the front door, which will consume a lot of time. Even if the supplier of the DRAM simulation model provides a backdoor loading method, the data needs to be loaded strictly in the format provided by it, and the flexibility of the backdoor data loading is poor. Therefore, the simulation verification system provided in this embodiment saves the time of data loading, improves the flexibility of the backdoor data loading method, and thus improves the simulation verification efficiency of the simulation verification system.

[0028] In a specific implementation, the parsing the operation command to obtain the address information includes: Parsing the operation command to obtain position information, wherein the position information at least includes block information, row information, and column information; The address information is determined according to the location information.

[0029] In a specific implementation, the operation command includes at least a read command and a write command.

[0030] The operation command may refer to a command that complies with the DFI protocol specification, such as an act command, a write data command, a read data command, etc.

[0031] In a specific implementation, the verification component is further used to initialize the DFI interface and perform a handshake with the memory controller.

[0032] Among them, the verification component receives the first handshake information sent by the memory controller, sends the second handshake information to the memory controller to simulate DRAM PHY, and completes the handshake between the verification component and the memory controller. The first handshake information may refer to the setting of the dfi_init_start signal, and the second handshake information may refer to the setting of the dfi_init_complete signal.

[0033] It can be seen that in this embodiment, the DRAM PHY simulation model and the DRAM simulation model in the prior art are replaced by verification components and memory models. The functions of the memory model are more suitable for the functions required for chip simulation verification, and the memory model function opening is more flexible. Moreover, the verification components and the memory model can be constructed based on a verification language compatible with the verification platform, so that the initialization of the simulation verification system only needs to configure the memory controller through the bus, which greatly saves the initialization time of the simulation verification system. The verification platform can directly access the verification components and the memory model for data transmission, providing a more flexible backdoor data loading method, thereby improving the simulation verification efficiency of the simulation verification system.

[0034] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A simulation verification system based on a DFI interface, characterized in that: The simulation verification system includes: a memory controller, a verification component and a memory model, wherein the memory controller is constructed based on an RTL code language, the verification component is constructed based on a first verification language, the memory model is constructed based on a second verification language, the simulation verification system is defined in a verification platform, and the verification platform is compatible with the first verification language and the second verification language; The memory controller is connected to the verification component via a DFI interface, and the memory controller is used to transmit an operation command via the DFI interface; The verification component is connected to the memory model, and is used to check the operation command, parse the operation command to obtain address information, and call the memory model to perform an operation according to the operation command and the address information, and return the operation result to the memory controller; The memory model is used to perform an operation according to the received operation command and the address information sent by the verification component, and return the operation result to the verification component.

2. The simulation verification system based on the DFI interface according to claim 1, characterized in that: The first verification language belongs to a first language set, and the second verification language belongs to a second language set. The first language set includes at least UVM verification language and SV verification language, and the second language set includes at least UVM verification language, SV verification language and C language.

3. The simulation verification system based on the DFI interface according to claim 1, characterized in that: The initialization of the simulation verification system includes: Initialize and configure the memory controller.

4. The simulation verification system based on the DFI interface according to claim 1, characterized in that: The verification component is further used to receive second data, and send the second data to the memory model for loading.

5. The simulation verification system based on the DFI interface according to claim 1, characterized in that: The memory model is also used to receive third data and load the third data into the memory model.

6. The simulation verification system based on the DFI interface according to claim 1, characterized in that: The step of parsing the operation command to obtain address information includes: Parsing the operation command to obtain position information, wherein the position information at least includes block information, row information, and column information; The address information is determined according to the location information.

7. The simulation verification system based on the DFI interface according to claim 1, characterized in that: The operation command includes at least a read command and a write command.

8. The simulation verification system based on the DFI interface according to claim 1, characterized in that: The verification component is also used to initialize the DFI interface and perform a handshake with the memory controller.

Images