Communication asynchronization identification method and device, electronic equipment and vehicle

Abstract

The invention relates to the technical field of data processing, and provides a communication asynchronization identification method and device, electronic equipment and a vehicle. The method is applied to a first core and a second core in a system chip. The method comprises the following steps: when the first core performs communication, controlling the first core to send communication information to the second core; determining whether communication asynchronization exists between the first core and the second core or not by judging whether the first core receives feedback information fed back by the second core for the communication information or not within a preset duration; and in response to the situation that the first core does not receive the feedback information fed back by the second core within a preset duration, determining that communication asynchronization exists between the first core and the second core. Therefore, the problem of communication desynchrony between the first core and the second core can be quickly and accurately determined, so that the fault removal processing of the communication desynchrony can be carried out when the problem of communication desynchrony between the first core and the second core is identified.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a method, device, electronic equipment and vehicle for identifying communication asynchrony. Background Art

[0002] As vehicles become more intelligent, their computing power is gradually unable to meet the demand. More and more vehicles are using multi-core system on a chip (SOC). However, for multi-core chips, different cores may have asynchronous communication when working.

[0003] In view of this, how to determine whether different cores in a multi-core chip have communication asynchrony when working has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the purpose of the present disclosure is to propose a communication asynchrony identification method, device, electronic device and vehicle to solve the problem in the prior art that it is impossible to determine whether different cores in a multi-core chip have communication asynchrony when working.

[0005] Based on the above purpose, the first aspect of the present disclosure proposes a method for identifying communication asynchrony, which is applied to a first core and a second core in a system chip; the method comprises:

[0006] When the first core is communicating, controlling the first core to send communication information to the second core;

[0007] Determining whether there is communication asynchronism between the first core and the second core by judging whether the first core receives feedback information from the second core regarding the communication information within a preset time period;

[0008] In response to the first core not receiving the feedback information fed back by the second core within a preset time period, it is determined that communication asynchrony exists between the first core and the second core.

[0009] Based on the same inventive concept, the second aspect of the present disclosure provides a communication asynchronization identification device, the device comprising a first core and a second core in a system chip; the device comprises:

[0010] a sending module, configured to control the first core to send communication information to the second core when the first core is communicating;

[0011] a judgment module configured to determine whether there is communication asynchronism between the first core and the second core by judging whether the first core receives feedback information from the second core regarding the communication information within a preset time period;

[0012] The determination module is configured to determine that there is communication asynchronism between the first core and the second core in response to the first core not receiving the feedback information fed back by the second core within a preset time period.

[0013] Based on the same inventive concept, the third aspect of the present disclosure proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method as described above when executing the computer program.

[0014] Based on the same inventive concept, the fourth aspect of the present disclosure proposes a vehicle, which includes the communication asynchrony identification device described in the second aspect or the electronic device described in the third aspect.

[0015] From the above, it can be seen that the communication asynchrony identification method, device, electronic device and vehicle provided by the present disclosure. For the first core and the second core in the system chip, when the first core is communicating, the first core is controlled to send communication information to the second core. By judging whether the first core receives the feedback information fed back by the second core for the communication information within a preset time length, it can be judged whether the second core can timely feedback the feedback information for the communication information, thereby accurately judging whether there is communication asynchrony between the first core and the second core. When the first core does not receive the feedback information fed back by the second core within the preset time length, it means that the second core cannot feedback or cannot timely feedback the feedback information for the communication information, thereby quickly and accurately determining that there is a communication asynchrony problem between the first core and the second core, so as to perform communication asynchrony troubleshooting when it is identified that there is a communication asynchrony problem between the first core and the second core, thereby ensuring the communication synchronization between different cores in the system chip and ensuring the security of communication between different cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A flow chart of a method for identifying communication asynchrony according to an embodiment of the present disclosure;

[0018] Figure 2 It is a structural schematic diagram of a communication asynchrony identification device according to an embodiment of the present disclosure;

[0019] Figure 3 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Based on the description of background technology, the degree of intelligence of vehicles is getting higher and higher, and the computing power of vehicles is gradually unable to meet the demand. More and more vehicles use multi-core SOC chips, but the more cores there are in a multi-core chip, how to ensure that different cores can communicate and synchronize when working has always been a difficult problem in the industry.

[0023] As mentioned above, how to ensure the communication synchronization of different cores in a multi-core chip when they are working has become an important research issue.

[0024] Based on the above description, if Figure 1 As shown, the communication asynchrony identification method proposed in this embodiment is applied to the first core and the second core in the system chip; the method includes:

[0025] Step 101, when the first core is communicating, controlling the first core to send communication information to the second core.

[0026] In a specific implementation, the communication information includes a key. When the first core is communicating, the first core is controlled to send the key to the second core. Before the first core sends the key to the second core, the key is encrypted to obtain an encrypted key, and the encrypted key is sent to the second core.

[0027] The first core is a core that is sending information for communication, and the second core is a core that receives the sent key and gives feedback. There is at least one second core. When there are multiple second cores, the first core sends different keys to different second cores.

[0028] The first cores that communicate in different communication cycles may be different, and the second cores that receive and feedback the key may also be different. For example, the system chip includes core A, core B, core C, and core D. In the first communication cycle, core A communicates, core A is the first core, and cores B, core C, and core D are the second cores. In the second communication cycle, core C communicates, and cores A, core B, and core D are the second cores.

[0029] Step 102 , determining whether there is communication asynchronism between the first core and the second core by judging whether the first core receives feedback information from the second core regarding the communication information within a preset time period.

[0030] In a specific implementation, the feedback information includes a key. When the first core sends the key to the second core, timing starts. By determining whether the first core receives the key fed back by the second core within a preset time after the start of timing, it is determined whether there is communication asynchrony between the first core and the second core.

[0031] In addition, when the first core sends the encrypted key to the second core, the second core decrypts the encrypted key to obtain the decrypted key after receiving the encrypted key, and feeds the decrypted key back to the first core. By judging whether the first core receives the decrypted key fed back by the second core within a preset time period and whether the decrypted key meets the preset conditions, it is determined whether there is communication asynchrony between the first core and the second core.

[0032] For example, the preset condition is that the decrypted key is consistent with the initial key. When the first core receives the decrypted key fed back by the second core and the decrypted key is consistent with the initial key, it is determined that the communication between the first core and the second core is synchronized. When the first core does not receive the decrypted key fed back by the second core or the decrypted key is inconsistent with the initial key, it is determined that there is communication asynchrony between the first core and the second core.

[0033] Step 103 : In response to the first core not receiving the feedback information fed back by the second core within a preset time period, determining that communication asynchrony exists between the first core and the second core.

[0034] In a specific implementation, the feedback information includes a key. When the first core does not receive the key fed back by the second core within a preset time after sending the key to the second core, it is determined that there is communication asynchrony between the first core and the second core.

[0035] For example, the preset duration is 10ms. It is determined whether the key fed back by the second core is received within 10ms after the first core sends the key to the second core. If the first core does not receive the key fed back by the second core within 10ms after the first core sends the key to the second core, it is determined that there is communication asynchrony between the first core and the second core.

[0036] Through the above-mentioned embodiment, for the first core and the second core in the system chip, when the first core communicates, the first core is controlled to send communication information to the second core. By judging whether the first core receives the feedback information fed back by the second core for the communication information within the preset time length, it can be judged whether the second core can timely feed back the feedback information for the communication information, thereby accurately judging whether there is communication asynchrony between the first core and the second core. When the first core does not receive the feedback information fed back by the second core within the preset time length, it means that the second core cannot feed back or cannot timely feed back the feedback information for the communication information, thereby quickly and accurately determining that there is a communication asynchrony problem between the first core and the second core, so as to perform communication asynchrony troubleshooting when it is identified that there is a communication asynchrony problem between the first core and the second core, thereby ensuring the communication synchronization between different cores in the system chip and ensuring the security of communication between different cores.

[0037] In some embodiments, a flag bit corresponding to the second core is set in the first core; step 103 includes:

[0038] Step 1031: In response to the first core not receiving the feedback information fed back by the second core within a preset time period, controlling the state of the flag bit to remain in an initial state.

[0039] Step 1032: In response to the state of the flag bit remaining in the initial state, determining that communication asynchrony exists between the first core and the second core.

[0040] In a specific implementation, the feedback information includes a key. A flag is set in the memory corresponding to the first core. According to whether the first core receives the key fed back by the second core within a preset time, the state of the flag in the first core is controlled. According to the state of the flag, it is determined whether there is communication asynchronism between the first core and the second core.

[0041] Specifically, when the first core does not receive the key fed back by the second core within a preset time period, the state of the control flag remains in the initial state. When the state of the flag remains in the initial state, it is determined that there is communication asynchrony between the first core and the second core.

[0042] For example, maintaining the initial state means that the flag bit remains 0. When the first core does not receive the key fed back by the second core within a preset time period, the control flag bit remains 0. When the flag remains 0, it is determined that there is communication asynchronism between the first core and the second core.

[0043] In addition, when the key sent by the first core to the second core is an encrypted key, when the first core does not receive the decrypted key fed back by the second core within the preset time, or the decrypted key is inconsistent with the initial key, the state of the control flag remains in the initial state.

[0044] Through the above solution, when the first core does not receive the feedback information fed back by the second core within the preset time, the state of the control flag remains in the initial state. When the state of the flag remains in the initial state, it can quickly and accurately determine that there is communication asynchrony between the first core and the second core.

[0045] In some embodiments, there are multiple second cores; a flag bit corresponding to each second core is set in the first core; step 1032 includes:

[0046] Step 10321: In response to the state of the flag bit corresponding to any second core remaining in the initial state, it is determined that there is communication asynchrony between the first core and the plurality of second cores.

[0047] In a specific implementation, at least one flag bit is set in the first core, and each second core corresponds to a flag bit. For example, the system chip includes core A, core B, core C, and core D. When core A is the first core, a flag bit corresponding to core B, a flag bit corresponding to core C, and a flag bit corresponding to core D are set in core A.

[0048] When the state of the flag bit corresponding to any second core remains in the initial state, it is determined that there is communication asynchrony between the first core and the plurality of second cores, that is, there is communication asynchrony between the first core and the second cores whose flag bits are in the initial state.

[0049] Specifically, maintaining the initial state means that the flag bit remains 0. When flag bits corresponding to multiple second cores in the first core remain 0, it is determined that there is communication asynchrony between the first core and the second core whose flag bits remain 0.

[0050] For example, the system chip includes core A, core B, core C, and core D. When core A is the first core, when the flag bit corresponding to core B in core A remains 0, and the flag bit corresponding to core C and the flag bit corresponding to core D are both set to 1, it is determined that the communication between core A and core C and core D is synchronized, but the communication between core A and core B is asynchronous.

[0051] Through the above scheme, when there are multiple second cores, when the state of the flag bit corresponding to any second core remains in the initial state, it can be quickly determined that there is communication asynchrony between the first core and the second core whose flag bit is in the initial state. When there are multiple second cores, according to the state of the flag bit of each second core in the first core, it can be quickly and accurately determined whether there is communication asynchrony between each second core and the first core.

[0052] In some embodiments, a flag bit corresponding to the second core is set in the first core; and the method further includes:

[0053] Step 104: In response to the first core receiving the feedback information fed back by the second core within a preset time period, controlling the state of the flag bit to switch to a synchronization state.

[0054] Step 105 , in response to the state of the flag bit being switched to a synchronization state, determining that the communication between the first core and the second core is synchronized.

[0055] In a specific implementation, the feedback information includes a key. When the first core receives the key fed back by the second core within a preset time after sending the key to the second core, it is determined that the communication between the first core and the second core is synchronized. For example, the preset time is 10ms. Determine whether the key fed back by the second core is received within 10ms after the first core sends the key to the second core. When the first core receives the key fed back by the second core within 10ms after sending the key to the second core, it is determined that the communication between the first core and the second core is synchronized.

[0056] In a specific implementation, the feedback information includes a key. A flag is set in the memory corresponding to the first core. According to whether the first core receives the key fed back by the second core within a preset time, the state of the flag in the first core is controlled. According to the state of the flag, it is determined whether there is communication asynchronism between the first core and the second core.

[0057] Specifically, when the first core receives the key fed back by the second core within a preset time period, the state of the control flag is switched to the synchronization state. When the state of the flag is switched to the synchronization state, it is determined that the communication between the first core and the second core is synchronized.

[0058] For example, switching to the synchronization state means that the flag is set to 1. When the first core receives the key fed back by the second core within a preset time, the flag is set to 1. When the flag is set to 1, it is determined that the communication between the first core and the second core is synchronized.

[0059] In addition, when the key sent by the first core to the second core is an encrypted key, when the first core receives the decrypted key fed back by the second core within a preset time period, and the decrypted key is consistent with the initial key, the state of the control flag is switched to the synchronization state.

[0060] Through the above solution, when the first core receives the feedback information fed back by the second core within the preset time, the state of the control flag is switched to the synchronization state. When the state of the flag is switched to the synchronization state, the communication synchronization between the first core and the second core can be quickly and accurately determined.

[0061] In some embodiments, there are multiple second cores; a flag bit corresponding to each second core is set in the first core; step 105 includes:

[0062] Step 1051, in response to the state of the flag bit corresponding to each of the second cores being switched to a synchronous state, determining that the communication between the first core and the plurality of second cores is synchronous.

[0063] In a specific implementation, at least one flag bit is set in the first core, and each second core corresponds to a flag bit. For example, the system chip includes core A, core B, core C, and core D. When core A is the first core, a flag bit corresponding to core B, a flag bit corresponding to core C, and a flag bit corresponding to core D are set in core A.

[0064] When the state of the flag bit corresponding to each second core is switched to the synchronization state, it is determined that the first core and the plurality of second cores are all communicating synchronously.

[0065] Specifically, switching to the synchronization state means that the flag position is 1. When the flag positions corresponding to all the second cores in the first core are all set to 1, it is determined that the first core and all the second cores are in communication synchronization.

[0066] For example, the system chip includes core A, core B, core C and core D. When core A is the first core, when the flag bit corresponding to core B, the flag bit corresponding to core C and the flag bit corresponding to core D in core A are all set to 1, it is determined that the communication between core A and core B, core C and core D is synchronized.

[0067] Through the above scheme, when there are multiple second cores, when the state of the flag bit corresponding to each second core is switched to the synchronization state, it is possible to quickly determine whether the communication between the first core and the multiple second cores is synchronized. When there are multiple second cores, according to the state of the flag bit of each second core in the first core, it is possible to quickly and accurately determine whether there is communication asynchrony between each second core and the first core.

[0068] In some embodiments, after step 103, the method further includes:

[0069] Step 106 , in response to determining that there is communication asynchrony between the first core and the second core, recording a diagnostic fault code of communication asynchrony.

[0070] Step 107 , determining that there are second cores with which the first core has asynchronous communication, treating the second cores with which the first core has asynchronous communication as asynchronous second cores, and counting the number of the asynchronous second cores.

[0071] Step 108: determining a degree of communication asynchrony based on the number of the asynchronous second cores, and determining an adjustment method according to the degree of communication asynchrony.

[0072] Step 109: troubleshooting the communication asynchronism problem of the system chip according to the adjustment method.

[0073] In specific implementation, when there is communication asynchrony between the first core and the second core, the diagnostic fault code of the communication asynchrony is recorded. In this way, the cause of the communication asynchrony between the first core and the second core can be determined according to the diagnostic fault code, and the cause of the communication asynchrony can be troubleshooted.

[0074] Among them, the diagnostic trouble code (DTC) is a way to indicate a fault in the vehicle system. The diagnostic trouble code can reflect problems in multiple systems of the vehicle, wherein the system includes at least one of the following: power system, body system, chassis system and network data communication transmission system. The diagnostic trouble code is generated by the vehicle's electronic control unit (ECU) to indicate a fault or abnormality in the engine, transmission system or other systems. The diagnostic trouble code can help technicians quickly locate and solve the problem to ensure the safety and performance of the vehicle.

[0075] When there is communication asynchrony between the first core and the second core, the diagnostic fault code of the communication asynchrony is recorded, which is convenient for technicians to quickly identify the cause of the abnormality and eliminate the abnormality in time. In addition, the system chip is adjusted according to the degree of communication asynchrony between the first core and the second core, and the communication asynchrony abnormality between the first core and the second core in the system chip is eliminated in time.

[0076] Specifically, the number of asynchronous second cores that are asynchronous in communication with the first core is counted. The degree of communication asynchrony is determined based on the number of asynchronous second cores. When the degree of communication asynchrony is mild, the system chip is adjusted according to the first preset adjustment method to reduce the degree of inter-core communication asynchrony. When the degree of communication asynchrony is severe, the system chip is adjusted according to the second preset adjustment method to avoid inter-core communication asynchrony affecting the security of the system chip.

[0077] Through the above scheme, when there is communication asynchrony between the first core and the second core, by recording the diagnostic fault code of communication asynchrony, it is convenient for technicians to quickly identify the cause of the abnormality and eliminate the abnormality in time. The adjustment method is determined according to the degree of communication asynchrony between the first core and the second core, and the system chip is adjusted according to the adjustment method. In this way, the system chip can be adjusted according to the degree of communication asynchrony, the degree of communication asynchrony between the first core and the second core can be minimized, and the safety of the system chip can be avoided when the communication between the first core and the second core is seriously asynchrony.

[0078] In some embodiments, step 108 includes:

[0079] Step 1081, comparing the number of the asynchronous second cores with a preset number.

[0080] Step 1082, in response to the number of the asynchronous second cores being less than or equal to a preset number, determining that the communication asynchrony level is slightly asynchrony, and determining an adjustment method is to record the load rate of the asynchronous second cores at the current moment.

[0081] Step 1083, in response to the number of the asynchronous second cores being greater than a preset number, determining that the communication asynchrony level is severe asynchrony, and determining that the adjustment method is to control the system chip to reset.

[0082] In a specific implementation, when the number of second cores that are asynchronous in communication with the first core is less than or equal to a preset number, the degree of asynchronous communication between the first core and the second core is determined to be slightly asynchronous, the load rate of the asynchronous second core at the current moment is recorded, and the communication synchronization between the first core and the second core is maximized by reducing the load rate of the second core. The load rate is the ratio of the data transmitted per unit time to the number of cores of the central processing unit (CPU).

[0083] When the number of second cores that are not in communication synchronization with the first core is greater than a preset number, the degree of communication asynchrony between the first core and the second core is determined to be severe communication asynchrony, and the system chip is reset to avoid affecting the security of the system chip when the communication between the cores is severely asynchronized.

[0084] For example, the preset number is 1. When the number of the asynchronous second cores is 1, it is determined that the first core and the second core are slightly asynchronous, and the load rate of the asynchronous second core at the current moment is recorded. When the number of the asynchronous second cores is 2, it is determined that the first core and the second core are severely asynchronous, and the control system chip is reset.

[0085] Through the above scheme, when the degree of communication asynchrony between the first core and the second core is slightly asynchrony, the load rate of the asynchronous second core at the current moment is recorded, and the degree of communication asynchrony between the first core and the second core can be minimized by reducing the load rate of the second core. When the degree of communication asynchrony between the first core and the second core is severely asynchrony, the system chip is reset to avoid affecting the safety of the system chip when the communication between the first core and the second core is severely asynchrony.

[0086] In some embodiments, after step 1083, the method further includes:

[0087] Step 1083A, enable the safety backup function, and determine whether there are any abnormalities in the interface data and clock signal of the system chip.

[0088] Step 1083B, in response to determining that the interface data and clock signal of the system chip are abnormal, recording the diagnostic fault code of the signal abnormality, and controlling the system chip to reset.

[0089] Step 1083C: in response to determining that there is no abnormality in the interface data and the clock signal of the system chip, control the system chip to reset.

[0090] In a specific implementation, when the communication asynchronism between the first core and the second core is severely asynchronism, the control system chip is reset. Before the control system chip is reset, the safety backup function is enabled to implement safety information storage, ensure the basic functions of the system chip, and avoid data loss during the system chip reset process.

[0091] By sending a reset command to the system chip, the system chip is reset. When the control system chip is reset, it is determined whether there are abnormalities in the interface data and clock signal of the system chip. When there are abnormalities in the interface data and clock signal of the system chip, the system chip is reset after recording the diagnostic fault code of the signal abnormality, which is convenient for technicians to troubleshoot the system chip according to the diagnostic fault code of the signal abnormality. When there are no abnormalities in the interface data and clock signal of the system chip, the system chip is directly controlled to be reset. Among them, the interface data includes IO interface data. In addition, it can also be determined whether there is an abnormality in the erasable programmable read-only memory (Erasable Programmable ROM, referred to as EPROM).

[0092] Through the above solution, before the control system chip is reset, the safety backup function is enabled to avoid data loss during the system chip reset process. When the control system chip is reset, if the interface data and clock signal of the system chip are abnormal, the diagnostic fault code of the signal abnormality is recorded, which facilitates technicians to troubleshoot the system chip according to the diagnostic fault code of the signal abnormality.

[0093] Through the above-mentioned embodiment, for the first core and the second core in the system chip, when the first core communicates, the first core is controlled to send communication information to the second core. By judging whether the first core receives the feedback information fed back by the second core for the communication information within the preset time length, it can be judged whether the second core can timely feed back the feedback information for the communication information, thereby accurately judging whether there is communication asynchrony between the first core and the second core. When the first core does not receive the feedback information fed back by the second core within the preset time length, it means that the second core cannot feed back or cannot timely feed back the feedback information for the communication information, thereby quickly and accurately determining that there is a communication asynchrony problem between the first core and the second core, so as to perform communication asynchrony troubleshooting when it is identified that there is a communication asynchrony problem between the first core and the second core, thereby ensuring the communication synchronization between different cores in the system chip and ensuring the security of communication between different cores.

[0094] It should be noted that the embodiments of the present disclosure may be further described in the following manner:

[0095] Step 1: When the initial core (i.e., the first core) sends information, it synchronously sends different keys to other cores (i.e., the second core) and starts a 10ms timer T. After receiving the key, other cores decrypt it and return it to the sending core in the next first cycle.

[0096] Step 2: within T time, if the keys fed back by other cores meet the requirements after decryption, the flag positions corresponding to other cores in the memory corresponding to the initial core are set to 1.

[0097] Step 3: If the different flag bits reserved in the initial core memory are all set to 1 when time T arrives, it means that other cores have received the information, and the inter-core communication is synchronized.

[0098] Step 4: The initial core clears the flag in the memory and starts the communication sending task of the next cycle.

[0099] Step 5: Each core has a flag bit corresponding to other cores reserved in its memory for communication synchronization.

[0100] Step 6, when one flag bit in the initial core is not set within the T time, it means that the other unset cores are in the message delay process and the communication data is not synchronized. At this time, the diagnostic trouble code (DTC) of communication asynchrony is recorded, and the load rate (the ratio of the transmission data per unit time to the number of CPU cores) in the other unset cores at the corresponding time is recorded.

[0101] Step 7: If more than two flags in the initial core are not set within the T time, it means that there is a serious asynchrony problem in the communication between the initial core and other cores. The safety backup program (safety information storage to ensure basic functions) is started, and the SOC chip reset instruction is sent to ensure that the communication between the cores in the SOC chip can be synchronized. In addition, before the SOC chip is reset, it is determined whether there are abnormalities in the EPROM memory, IO interface, and clock signal. If there are abnormalities, the diagnostic fault code DTC of the signal abnormality is recorded to facilitate reading the fault problem of the system chip when replacing the chip.

[0102] Through the above embodiments, when communication asynchrony exists between different cores in a system chip, the cause of the communication asynchrony can be determined based on the diagnostic fault code of the communication asynchrony, and troubleshooting can be performed on the cause of the communication asynchrony, thereby ensuring communication synchronization between different cores in the system chip and guaranteeing the security of communication between different cores.

[0103] It should be noted that the method of the embodiment of the present disclosure can be performed by a single device, such as a computer or a server. The method of the present embodiment can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0104] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0105] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present disclosure also provides a communication asynchrony identification device.

[0106] refer to Figure 2 , the communication asynchrony identification device comprises a first core and a second core in a system chip; the device comprises:

[0107] The sending module 201 is configured to control the first core to send communication information to the second core when the first core is communicating;

[0108] The judgment module 202 is configured to determine whether there is communication asynchronism between the first core and the second core by judging whether the first core receives feedback information from the second core regarding the communication information within a preset time period;

[0109] The determination module 203 is configured to determine that there is communication asynchrony between the first core and the second core in response to the first core not receiving the feedback information fed back by the second core within a preset time period.

[0110] In some embodiments, a flag bit corresponding to the second core is set in the first core; the determination module 203 includes:

[0111] an initial state maintaining unit, configured to control the state of the flag bit to remain in an initial state in response to the first core not receiving the feedback information fed back by the second core within a preset time period;

[0112] The communication asynchrony determination unit is configured to determine that communication asynchrony exists between the first core and the second core in response to the state of the flag bit remaining in the initial state.

[0113] In some embodiments, the second core is multiple; a flag bit corresponding to each second core is set in the first core; and the communication asynchrony determination unit includes:

[0114] The communication asynchrony determination subunit is configured to determine that there is communication asynchrony between the first core and the plurality of second cores in response to the state of the flag bit corresponding to any second core remaining in the initial state.

[0115] In some embodiments, a flag bit corresponding to the second core is set in the first core; and the device further includes:

[0116] a synchronization state switching module, configured to control the state of the flag bit to switch to a synchronization state in response to the first core receiving the feedback information fed back by the second core within a preset time period;

[0117] The communication synchronization determination module is configured to determine whether the communication between the first core and the second core is synchronized in response to the state of the flag bit switching to the synchronization state.

[0118] In some embodiments, the apparatus further comprises:

[0119] a recording module configured to record a diagnostic fault code of communication asynchrony in response to determining that there is communication asynchrony between the first core and the second core;

[0120] a statistical module configured to determine that there are second cores with which the communication is not synchronized with the first core, regard the second cores with which the communication is not synchronized as asynchronous second cores, and count the number of the asynchronous second cores;

[0121] an adjustment mode determination module, configured to determine a degree of communication asynchrony based on the number of the asynchronous second cores, and determine an adjustment mode according to the degree of communication asynchrony;

[0122] The troubleshooting processing module is configured to perform troubleshooting processing for communication asynchronism on the system chip according to the adjustment method.

[0123] In some embodiments, the adjustment mode determination module includes:

[0124] A comparison processing unit, configured to compare the number of the asynchronous second cores with a preset number;

[0125] A first adjustment unit is configured to, in response to the number of the asynchronous second cores being less than or equal to a preset number, determine that the communication asynchronous degree is slightly asynchronous, and determine an adjustment method as recording a load rate of the asynchronous second core at a current moment;

[0126] The second adjustment unit is configured to, in response to the number of the asynchronous second cores being greater than a preset number, determine that the communication asynchrony degree is severe asynchrony, and determine that the adjustment method is to control the system chip to reset.

[0127] In some embodiments, when the determining adjustment method is to control the system chip to perform reset hysteresis, the fault elimination processing module includes:

[0128] an abnormality determination unit, configured to enable a safety backup function and determine whether the interface data and clock signal of the system chip are abnormal;

[0129] a first reset unit configured to, in response to determining that the interface data and clock signal of the system chip are abnormal, record a diagnostic fault code of the signal abnormality, and control the system chip to reset;

[0130] The second reset unit is configured to control the system chip to reset in response to determining that there is no abnormality in the interface data and the clock signal of the system chip.

[0131] For the convenience of description, the above device is described by dividing it into various modules according to its functions. Of course, when implementing the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0132] The device of the above embodiment is used to implement the corresponding communication asynchrony identification method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0133] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the communication asynchrony identification method described in any of the above embodiments is implemented.

[0134] Figure 3 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0135] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0136] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0137] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0138] The communication interface 1040 is used to connect a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB (Universal Serial Bus), network cable, etc.), or through a wireless mode (such as mobile network, WIFI (Wireless Fidelity), Bluetooth, etc.).

[0139] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0140] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0141] The electronic device of the above embodiment is used to implement the corresponding communication asynchrony identification method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0142] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the communication asynchrony identification method as described in any of the above embodiments.

[0143] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0144] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the communication asynchrony identification method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0145] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a vehicle, including the communication asynchrony identification device, or electronic device, or storage medium in the above-mentioned embodiments, and the vehicle equipment implements the communication asynchrony identification method described in any of the above embodiments.

[0146] The vehicle of the above-mentioned embodiment is used to implement the communication asynchrony identification method described in any of the above-mentioned embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0147] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0148] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present disclosure difficult to understand, the known power / ground connections to the integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present disclosure will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it is apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0149] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0150] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present disclosure. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for identifying communication asynchrony, characterized in that: The method is applied to a first core and a second core in a system chip; the method comprises: When the first core is communicating, controlling the first core to send communication information to the second core; Determining whether there is communication asynchronism between the first core and the second core by judging whether the first core receives feedback information from the second core regarding the communication information within a preset time period; In response to the first core not receiving the feedback information fed back by the second core within a preset time period, it is determined that communication asynchrony exists between the first core and the second core.

2. The method according to claim 1, characterized in that A flag bit corresponding to the second core is set in the first core; In response to the first core not receiving the feedback information fed back by the second core within a preset time period, determining that there is communication asynchrony between the first core and the second core includes: In response to the first core not receiving the feedback information fed back by the second core within a preset time period, controlling the state of the flag bit to remain in an initial state; In response to the state of the flag bit remaining in the initial state, it is determined that communication asynchrony exists between the first core and the second core.

3. The method according to claim 2, characterized in that There are multiple second cores; a flag bit corresponding to each second core is set in the first core; In response to the state of the flag bit being maintained in the initial state, determining that there is communication asynchronism between the first core and the second core includes: In response to the state of the flag bit corresponding to any second core being maintained in the initial state, it is determined that communication asynchrony exists between the first core and the plurality of second cores.

4. The method according to claim 1, characterized in that: A flag bit corresponding to the second core is set in the first core; The method further comprises: In response to the first core receiving the feedback information fed back by the second core within a preset time period, controlling the state of the flag bit to switch to a synchronization state; In response to the state of the flag bit being switched to a synchronization state, it is determined that the communication between the first core and the second core is synchronized.

5. The method according to claim 1, characterized in that The method further comprises: In response to determining that there is a communication asynchrony between the first core and the second core, recording a diagnostic trouble code for a communication asynchrony; determining a second core with which communication is not synchronized with the first core, treating the second core with which communication is not synchronized as an asynchronous second core, and counting the number of the asynchronous second cores; Determining a degree of communication asynchrony based on the number of the asynchronous second cores, and determining an adjustment method according to the degree of communication asynchrony; The system chip is troubleshooted for communication asynchronism according to the adjustment method.

6. The method according to claim 5, characterized in that The determining the degree of communication asynchrony based on the number of the asynchronous second cores, and determining the adjustment method according to the degree of communication asynchrony, includes: Comparing the number of the asynchronous second cores with a preset number; In response to the number of the asynchronous second cores being less than or equal to a preset number, determining that the communication asynchronous degree is slightly asynchronous, and determining that the adjustment method is to record the load rate of the asynchronous second core at the current moment; In response to the number of the asynchronous second cores being greater than a preset number, the communication asynchrony level is determined to be severe asynchrony, and the adjustment method is determined to be controlling the system chip to reset.

7. The method according to claim 6, characterized in that After determining that the adjustment method is to control the system chip to reset, the method further includes: Enable the safety backup function and determine whether the interface data and clock signal of the system chip are abnormal; In response to determining that the interface data and clock signal of the system chip are abnormal, recording a diagnostic fault code of the signal abnormality, and controlling the system chip to reset; In response to determining that there is no abnormality in the interface data and the clock signal of the system chip, the system chip is controlled to be reset.

8. A communication asynchrony identification device, characterized in that: The device includes a first core and a second core in a system chip; the device includes: a sending module, configured to control the first core to send communication information to the second core when the first core is communicating; a judgment module configured to determine whether there is communication asynchronism between the first core and the second core by judging whether the first core receives feedback information from the second core regarding the communication information within a preset time period; The determination module is configured to determine that there is communication asynchrony between the first core and the second core in response to the first core not receiving the feedback information fed back by the second core within a preset time period.

9. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and running on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A vehicle, characterized in that: It includes the communication asynchrony identification device as described in claim 8 or the electronic device as described in claim 9.

Images