Processing system

Abstract

The invention provides a neuron logic gate metal oxide semiconductor vLGMOS circuit which can simulate the'integrating and exciting 'behaviors of neurons in a biological neural network system and can be manufactured together with a plurality of digital operation circuits by utilizing an industrial CMOS logic process technology. The processing system comprises an analog vLGMOS circuit, a converter circuit and a digital processing circuit, can optimize the power and cost of various applications, and can be manufactured into an integrated circuit chip by the same CMOS logic process technology. Meanwhile, the simulation vLGMOS circuit is inspired by a biological neural network system and can be simulated, designed and manufactured into an integrated circuit chip so as to be applied to the field of biomedicine.

Description

Technical Field

[0001] The present invention relates to a neuron metal oxide semiconductor field effect transistor (vMOSFET) circuit to simulate a biological neuron circuit for analog signal processing. In particular, because the neuron circuit can be designed and manufactured using industry standard complementary metal oxide semiconductor (CMOS) logic process technology, an optimized high processing efficiency information processing system including analog neuron circuits and digital operation circuits can be implemented using an integrated circuit (IC) chip. Background Art

[0002] FIG1(a) is a schematic diagram showing a conventional neuron MOSFET device according to the public document of Shibata et al. (“An intelligent MOS transistor featuring gate-level weighted sum and threshold operations”, International Electron Devices meeting (IEDM) 1991, p. 99). FIG1(b) shows the equivalent floating gate capacitance of the conventional neuron MOSFET device of FIG1(a). The voltage potential of the neuron MOSFET device 100 is The calculation is as follows: And, C t =C 1 +…+C n ;in, represents the voltage potential of the conductive floating gate 110, (C 1 ,C 2 ,...,C n ) represents the capacitance of the input gate 120 relative to the conductive floating gate 110 and (V 1 ,V 2 ...,V n ) represents the applied voltage value of the input gate 120.

[0003] As shown in the above equation, the voltage potential of the conductive floating gate 110 is obtained by multiplying each input voltage by the weight of the respective coupling capacitance value. The neuron MOSFET device 100 is turned on by a voltage greater than the device threshold voltage. Because biological neurons are activated or turned on by a gradient voltage potential (similar to the floating gate voltage potential of the neuron MOSFET device 100) greater than the neuron threshold voltage (about tens of millivolts), the neuron MOSFET device (herein referred to as the vMOS device by the inventor) can simulate the electrical activation (integrate-and-fire) behavior of a neuron; wherein the neuron threshold voltage is obtained by the product of the neurotransmitter signal (similar to the multiple input voltage signals of the neuron MOSFET device 100) applied to multiple post-synapses (similar to the multiple input gates 120 of the neuron MOSFET device 100) and the respective synaptic strength (similar to the multiple input gate coupling capacitance values ​​of the neuron MOSFET device 100).

[0004] According to the neuron excitation model of "integrate and fire", a neuron with multiple postsynapses (signal receptors) can have "any strong" postsynapses, strong enough to excite, or have "all weak" postsynapses, strong enough to excite. From the mathematical concept of logic gates, the former can be regarded as an "OR" gate function because "any strong" input can be turned on (to excite); the latter can be regarded as an "AND" gate function because "all weak" inputs can be turned on (to excite). By analogy, a neuron applies its "integrate and fire" function to "analogously and logically" analyze input neural signals from multiple postsynaptic inputs with various synaptic connection strengths. Analogically, according to the circuit configuration, the vMOS circuit (including a circuit network formed by multiple vMOS devices with different capacitive coupling strengths (weights) to perform the above-mentioned "integration and excitation" function) "analogically and logically" analyzes multiple input analog voltage signals related to the output analog voltage signal.

[0005] FIG2(a) is a schematic diagram of a conventional vMOS circuit. FIG2(b) is a schematic diagram of an external control signal voltage (V A ,V B ,V C ) and the input gate voltage (I 1 ,I 2) between different logic functions. The vMOS circuit 200 includes a two-bit digital-to-analog converter (D / A converter) 210 and a neuron circuit 220; the neuron circuit 220 includes a vMOS inverter 221 with four input terminals and a traditional inverter 222. In the above-mentioned public document, Shibata further applied the vMOS device 100 in the vMOS circuit 200, as shown in FIG2(a), by changing the circuit amplifier reference voltage of the vMOS inverter 221 with four input terminals and the fixed circuit input coupling capacitance ratio (8:4:2:1), to demonstrate the "variable" logic gate functions of the digital logic gate in FIG2(b), such as AND, OR and XOR gates. The above demonstration indicates that different reference voltages (V A ,V B ,V C ), input voltage (V 1 ,V 2 ,V 3 ,V 4 ) and coupling strength, will change the logical functionality of the circuit. Similarly, the excitation behavior of neurons is mainly controlled by the strength of the input neurotransmitter signal from the post-synaptic connection. According to the mechanism of neural plasticity, by frequently stimulating specific locations of the biological neural network system during training exercises, the synaptic strength of a neuron entity can be changed or new synapses can be formed to change the logical analysis of the neuron. However, because the input / output analog voltage signals of the vMOS circuit are inaccurate and susceptible to environmental interference, the vMOS circuit is not suitable for replacing the basic logic circuits (AND, OR and NOT) used in digital computing circuits, where the input / output digital voltage signals of the circuit are represented by a series of voltage signals to represent the accurate voltage state, and the digital high voltage V DD Represents the value 1, while the digital low voltage V SS represents a value of 0. Furthermore, in addition to the analog nature of the input / output voltage signals of the vMOS circuit, it is not economical to use the existing vMOS circuit design as a combinational logic gate circuit (a combination of AND, OR, and NOT gates) for the following two reasons: (1) the vMOS circuit 200 has more transistors and larger transistors, such as the amplifier transistor of FIG. 2(a), which occupies a larger silicon area than a conventional logic gate circuit, resulting in a higher IC chip cost; (2) the double-gate process of the existing vMOS device and circuit requires an additional floating gate processing step (floating gate processing module), resulting in a higher chip process cost. Summary of the invention

[0006] The present application provides a processing system to optimize the power and cost of various applications, and can be manufactured into an integrated circuit chip using the same CMOS logic process technology, thereby solving the problems existing in the prior art.

[0007] In order to solve the above technical problems, this application provides the following technical solutions:

[0008] The present application provides a processing system for receiving a plurality of input analog voltages and generating one or more digital output values, comprising:

[0009] an analog circuit comprising at least one metal oxide semiconductor (MOS) circuit, each MOS circuit comprising a first single-layer gate neuron MOS device having a plurality of input gates, wherein each MOS circuit is used to model one of a sigmoid function and an inverse sigmoid function to generate an output analog voltage in response to one or more of the plurality of input analog voltages applied to the plurality of input gates;

[0010] a conversion circuit coupled to the analog circuit and comprising one or more analog-to-digital converters ADC, each ADC performing analog-to-digital conversion on a corresponding output analog voltage according to its own resolution to generate a digital value; and

[0011] a digital processor for performing digital processing operations on one or more digital values ​​from the conversion circuit to generate the one or more digital output values;

[0012] The analog circuit, the conversion circuit and the digital processor are manufactured using industrial standard complementary metal oxide semiconductor (CMOS) logic process technology to form one or more integrated circuit chips.

[0013] By using this application, the power and cost of various applications can be optimized, and the same CMOS logic process technology can be used to manufacture integrated circuit chips. At the same time, the above-mentioned analog vLGMOS circuit is inspired by the biological neural network system and can be simulated, designed and manufactured into an integrated circuit chip for application in the biomedical field. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1( a ) is a schematic diagram showing a conventional double-layer gate neuron MOS (νMOS) device according to the public document of Shibata et al. (“An intelligent MOS transistor featuring gate-level weighted sum and threshold operations”, International Electron Devices meeting (IEDM) 1991, p. 99).

[0015] FIG. 1( b ) shows the equivalent floating gate capacitance value of the conventional double-layer gate neuron MOSFET device in FIG. 1( a ).

[0016] FIG. 2( a ) is a schematic diagram showing a conventional vMOS circuit according to a publication by Shibata et al. (“An intelligent MOS transistor featuring gate-level weighted sum and threshold operations”).

[0017] Figure 2(b) shows the external control signal voltage (V A ,V B ,V C ) and the input gate voltage (I 1 ,I 2 )’s simulated logic functions.

[0018] FIG. 3( a ) is a cross-sectional view of a conventional double-gate vMOS device according to the νMOS device of FIG. 1( a ).

[0019] FIG. 3( b ) shows a cross-sectional view of a single-gate vLGMOS device of the present invention.

[0020] FIG. 3( c ) shows a corresponding equivalent circuit diagram of the conventional double-gate νMOS device 30A of FIG. 3( a ).

[0021] FIG3( d ) shows a corresponding equivalent circuit diagram of the single-gate vLGMOS device 30B of FIG3( b ).

[0022] Figure 4 1 is a circuit diagram showing an inhibition type N-type νLG NMOS device and a diode-connected NMOSFET device load to generate a reverse S-shaped voltage function according to the present invention.

[0023] Figure 5 show Figure 4 A diagram of the relationship between floating gate voltage and output voltage for a reverse S-shaped voltage transfer function produced by a circuit arrangement.

[0024] Figure 6 1 is a circuit diagram showing a suppression type P-type νLGPMOS device and a diode-connected NMOSFET device load to generate a reverse S-type voltage function according to the present invention.

[0025] Figure 7 show Figure 6 A diagram of the relationship between floating gate voltage and output voltage for a reverse S-shaped voltage transfer function produced by a circuit arrangement.

[0026] Figure 8 FIG. 1 is a circuit diagram showing a suppression-type complementary νLGCMOS circuit for generating an inverse S-shaped voltage function according to the present invention.

[0027] Fig. 9 show Figure 8 A diagram of the relationship between floating gate voltage and output voltage for a reverse S-shaped voltage transfer function produced by a circuit arrangement.

[0028] Fig.10 FIG. 4 is a schematic diagram showing an excited complementary vLGCMOS circuit for generating an S-shaped voltage function according to an embodiment of the present invention.

[0029] Fig.11 show Fig.10 A graph of the floating gate voltage versus output voltage of an S-shaped voltage transfer function produced by a circuit arrangement.

[0030] Fig.12 The circuit diagram of a processing system according to an embodiment of the present invention is shown. The processing system has an ADC circuit for connecting the output of the analog vLGMOS circuit to the input of the digital processing circuit.

[0031] Fig.13 FIG. 1 is a top view of a suppression-type complementary vLGCMOS circuit with four input gates fabricated using CMOS logic process technology according to an embodiment of the present invention.

[0032] Fig.14 FIG. 1 is a top view of an excitatory complementary vLGCMOS circuit with four input gates fabricated using CMOS logic process technology according to an embodiment of the present invention.

[0033] [Explanation of symbols]

[0034] 30A, 100Ω Double-layer Gate Neuron MOSFET Device

[0035] 30B Single-layer gate neuron MOS device

[0036] 110, 340, 414, 614, 816, 1016, 1316, 1416 Conductive floating gate

[0037] 120, 35(1), 35(2), …, 35(n) Input gate

[0038] 200 vMOS circuit

[0039] 210 Digital to Analog Converter

[0040] 220 Neuronal Circuits

[0041] 221 νMOS Inverter with Four Inputs

[0042] 222 Traditional inverter

[0043] 300 P-type substrate

[0044] 310 Source region

[0045] 320 Drain region

[0046] 330 P-type channel area

[0047] 331 Gate dielectric layer

[0048] 341 Coupling dielectric layer

[0049] 360 Field Isolation Dielectric

[0050] 370 N-type semiconductor input gate

[0051] 400 Suppression type νLGNMOS circuit

[0052] 410 Single-gate N-type vLGNMOS device

[0053] 420, 620 load elements

[0054] 411 Source of single-gate N-type νLGNMOS device 410

[0055] 412, 814, 1322, 1422 P-type substrate electrode

[0056] 413 Drain of single-gate N-type vLGNMOS device 410

[0057] 415(1), ..., 415(n), 615(1), ..., 615(n) Input gate electrode

[0058] 817(1), ..., 817(n), 1011(1), ..., 1011(n), 1021 Input gate electrode

[0059] 1317(1), 1317(2), 1317(3), 1317(4) Input gate electrode

[0060] 1417(1), 1417(2), 1417(3), 1417(4) Input gate electrode

[0061] Nodes 421, 422, 611, 621, 622, 815, 1012, 1022, 1435, 1445

[0062] 600 Suppression type vLGPMOS circuit

[0063] 610 Single-gate P-type νLGNMOS device

[0064] 611 Source of single-gate P-type νLGPMOS device 610

[0065] 612, 812, 1312, 1412 N-type well electrode

[0066] 613 Drain of single-gate P-type νLGPMOS device 610

[0067] 800, 1300 Suppression Complementary νLGCMOS Circuit

[0068] 810, 1310 Single-gate P-type νLGPMOS device

[0069] 811 Source of single-gate P-type νLGPMOS device 810

[0070] 813 Source of single-gate N-type vLGNMOS device 820

[0071] 815N Drain of single-gate N-type νLGNMOS device 820

[0072] 815P Drain of single-gate P-type vLGPMOS device 810

[0073] 820, 1320 Single-gate N-type νLGNMOS device

[0074] 850 Floating Gate Inverter Device

[0075] 1000, 1400 Excitation type νLGCMOS circuit

[0076] 1010 Single-Gate νLGCMOS Device

[0077] 1020, 1440 CMOS Inverter Device

[0078] 1200 Processing System

[0079] 1201 Input Node

[0080] 1202, 1203 output nodes

[0081] 1204 Digital Output Node

[0082] 1210 Analog vLGMOS Circuit Department

[0083] 1220 Digital Processing Circuit

[0084] 1221 Digital input

[0085] 1222 Digital output

[0086] 1230 Analog to Digital Converter Circuit Section

[0087] 1210 Analog vLGMOS Circuit Department

[0088] 1220 digital processing circuit

[0089] 1311, 1411 single-gate P-type vLGPMOS device source

[0090] 1321, 1421 Source of single-gate N-type vLGNMOS device

[0091] 1330 Floating Gate Inverter Device

[0092] 1430vLGCMOS Inverter DETAILED DESCRIPTION

[0093] The following detailed description of the vLGMOS circuit layout manufactured with CMOS logic process technology is for example only and not for limitation. It should be understood that other embodiments may be used, and that component changes may be made for different CMOS devices manufactured with different generations of CMOS logic process technology (e.g., planar components, Fin Field Effect Transistor components, and Gate all around components, etc.), all of which should fall within the scope of the claims of the present invention. It should be further understood that the phraseology and terminology used in this specification are for illustration only and not for limitation. Those familiar with the art should understand that the embodiments of the methods and schematic diagrams in this specification are for example only and not for limitation. Those familiar with the art who understand the spirit of the present invention due to the disclosure of this specification may use other embodiments, all of which should fall within the scope of the claims of the present invention.

[0094] From the perspective of information processing, analog vMOS circuits can "analogically and logically" analyze multiple input analog information related to output analog information without going through multiple computational steps, similar to the information processing of biological neural systems, which is a single-step feed-forward mechanism well known in the industry. In contrast, digital computing processors that analyze input information rely on multiple computational steps executed by a set of program instructions (algorithms). The power consumption of information extraction performed by analog vMOS circuits is believed to be much lower than the multiple computational steps performed simultaneously by digital circuits driven by a high-frequency clock, especially high-dimensional multi-input and multi-output information processors. In order to develop an efficient information processor with better power consumption, a vMOS circuit is urgently needed to process multiple input signal fields generated by multiple sensor arrays to represent a set of concise information, and the concise information is represented by a set of digital data (bit symbols), so that the number of computational processing steps for the final information extraction generated by the digital processor can be significantly reduced. To this end, the vMOS circuit should be designed to first analyze the input analog signal field, then filter out the unnecessary analog signals and noise, so as to generate a set of concise digital data of the expected information from the sensor array field, thereby minimizing the number of subsequent digital processing operations. The significant reduction in digital processing operations can not only save overall processing power, but also save the huge memory space of the random access memory (RAM) in the digital operation processor.

[0095] On the other hand, because the dual-gate process of existing vMOS devices and circuits (developed specifically for floating gate non-volatile memories (such as EEPROM, NOR-type flash memories, and NAND-type flash memories)) is incompatible with the single-gate CMOS logic process developed specifically for digital circuit manufacturing, the incompatible process is one reason that hinders the idea of ​​"merging vMOS circuit processors and digital circuit processors to pursue the best value of information processor efficiency." The ability to use the same CMOS logic process to manufacture IC chips to merge digital circuits and νMOS circuits not only provides a method for building efficient information processors for various applications, but also reduces the overall chip manufacturing cost. The present application discloses an innovative single-gate νLG (neuron logic gate) MOS device that is manufactured using industry-standard CMOS logic process technology for neuron circuit design. Therefore, circuit design tools, such as device SPICE models and circuit simulators developed for industry-standard CMOS logic process technology, can be used to simulate and emulate the νLGMOS circuit of the present invention. At the same time, the industrial standard CMOS logic process technology of the wafer manufacturing plant is used to design and manufacture IC chip processors that can include analog νLGMOS processor circuits and digital processor circuits, achieving optimized power and cost to meet various applications. At the same time, the analog circuit processor built by the νLGMOS-like circuit system architecture of the present invention, inspired by the biological neural circuit system architecture of "from sensing to high-level consciousness (neural feedforward system)", together with the biological memory / biological decision-making system (neural feedback loop), can be explored, simulated, manufactured and developed into a physical IC chip for application in the biomedical field.

[0096] In one aspect of the present invention, a fruitful application of analog processors (built with vLGMOS circuits) is demonstrated, where the inventors use neuron logic gate N-type metal oxide semiconductor (vLGNMOS) circuits, neuron logic gate P-type metal oxide semiconductor (vLGPMOS) circuits, and neuron logic gate complementary metal oxide semiconductor (vLGCMOS) circuits to generate sigmoidal voltage functions, which are the basic activation functions for neural network simulations in computational neuroscience. The activation functions are introduced as neural activation behaviors in neural network simulations, particularly for use in training neural networks with multiple inputs and multiple layers, and the trained neural networks are deep neural networks (DNNs) in the field of machine learning of artificial neural network algorithms well known in the industry. In fact, Cybenko has mathematically proved the approximation function theorem: a multilayer feedforward network with hidden layers and a sigmoidal activation function is a universal function approximator (Cybenko, G (1989). "approximation by superpositions of a sigmoidal function". Mathematics of Control, Signals, and Systems. 2 (4): pp. 303-314). This public document indicates that any given function can be approximated by a neural circuit network with an sigmoidal activation function. Because the numerical value of the sigmoidal function in the neural network simulation is generated by digital calculations, most of the computing resources need to be provided to the numerical sigmoidal function of the neural network simulation. The number of bits used in the neural network simulation has always been a trade-off between numerical accuracy and computing resources. When simulating the entire neural network, adding one bit for the numerical accuracy of the sigmoidal function will exponentially increase the burden of digital computing resources. Therefore, in an IC chip, using the vLGMOS circuit of the present invention to implement an S-shaped voltage function to generate a function value can significantly reduce the burden of digital computing resources during neural network simulation.

[0097] In another aspect of the present invention, the neural network model simulation data analysis must include a re-normalization process for computing binary values, wherein the re-normalization process of the digital processor consumes a large amount of computing resources. Because the analog voltage signals on all nodes of the vLGMOS circuit of the present invention must be limited to the high voltage rail V a and low voltage rail V STherefore, the output voltage signal generated by the vLGMOS circuit of the present invention will be divided into multiple voltage levels to meet the desired bit accuracy, so that when the subsequent neural network simulation data analysis is applied, the S-type function value generated by the vLGMOS circuit no longer needs to be re-normalized.

[0098] In another aspect of the present invention, one or more analog-to-digital converter circuits (ADCs) are used to convert the voltage level of the output analog voltage signal generated by the vLGMOS circuit into a plurality of digital voltage signals of bit symbols, wherein the bit symbols are composed of a series of digital high voltages V DD (representing a value of 1) and a digital low voltage V SS (representing the value 0) is used for digital operations.

[0099] In another aspect of the present invention, the bit symbol representation of the output analog voltage signals generated at the multiple output nodes of the vLGMOS circuit can be regarded as the response voltage state under the given state of the multiple input voltage signals within a sampling time.

[0100] The relevant terms mentioned throughout the specification and claims are defined as follows, unless otherwise specifically stated in this specification. The term "double-layer gate neuron MOS device" refers to a neuron MOS device having multiple input gates and a floating gate located above a substrate, such as Figure 1(a) and Figure 3(a). The term "single-layer gate neuron MOS device" refers to a neuron MOS device having a floating gate located above a substrate and multiple input gates embedded in the substrate, such as Figure 3(b). The above-mentioned neuron MOS device is a floating gate device, which uses multiple input gates to control the voltage on the floating gate to control the on / off state of the floating gate device. By using the above-mentioned multiple input gates, the above-mentioned neuron MOS device operates very similar to a biological neuron.

[0101] The conventional double-gate N-type vMOS device shown in FIG. 1( a ) is disclosed by Shibata et al., and uses a double-gate process to manufacture one input gate 120 and another floating gate 110. The main idea of ​​converting the double-gate (multiple input gates and one floating gate) vMOS device 30A into a single-gate vLGMOS device 30B is to replace the N-type polysilicon input gate with an N-type semiconductor silicon input gate embedded in a P-type semiconductor silicon substrate, where the P-type semiconductor silicon substrate is a typical starting silicon substrate in CMOS logic process technology. FIG. 3( a ) and FIG. 3( b ) are schematic diagrams of a double-gate N-type vMOS device 30A and a single-gate N-type vLGMOS device 30B, respectively, where the highly doped N-type (N +) semiconductor forms a source region 310 and a drain region 320 in a P-type substrate 300, and a P-type channel region 330 located below a conductive floating gate 340 is formed with a gate capacitance value C NM The n input gates (35(1), 35(2), ..., 35(n)) in the double-gate vMOS device 30A and the single-gate vLGMOS device 30B are separated by a gate dielectric layer 331 having a capacitance value (C 1 ,C 2 ,...,C n ) is coupled to the conductive floating gate 340 by a coupling dielectric layer 341. In the N-type vLGMOS device 30B of FIG3(b), the N-type semiconductor input gates (35(1), 35(2), ..., 35(n)) embedded in the P-type substrate 300 are electrically insulated from each other by “surrounding the side with a field isolation dielectric 360 and forming an N / P junction at the bottom 370 through the N-type semiconductor and the P-type substrate”. FIG3(c) and FIG3(d) are schematic diagrams showing the equivalent circuit topology of the double-gate N-type vMOS device 30A and the single-gate N-type vLGMOS device 30B, respectively.

[0102] In order to be compatible with CMOS logic circuits, the present invention utilizes a single-gate N-type vLGMOS device and a pull-up loading element, a single-gate P-type vLGMOS device and a pull-down loading element, and a single-gate complementary vLGCMOS device to establish different vLGMOS circuits to generate an inverted S-shaped voltage function. The inverted S-shaped voltage function is regarded as an inhibitory excitation function corresponding to the inhibitory excitation behavior of neurons, while the S-shaped voltage function used for neural network simulation corresponds to the excitatory excitation function of the excitatory excitation behavior of neurons. The inverted S-shaped voltage function can be converted into an S-shaped voltage function by inverting the output voltage of the inverted S-shaped voltage function through a CMOS inverter.

[0103] Figure 4 In the embodiment, the suppression type vLGNMOS circuit 400 includes a single-gate N-type vLGNMOS device 410 and a load element 420 connected in series, which are biased at a high voltage rail V a and low voltage rail V S The source 411 and the P-type substrate electrode 412 of the single-gate N-type vLGNMOS device 410 are connected to the ground potential V S(=0), and the drain 413 of the single-gate N-type vLGNMOS device 410 is connected to the node of the load element 420 to form an output node 422, while the other node 421 of the load element 420 is biased to the high voltage rail V a The coupling capacitance C between the floating gate 414 and the MOS device 410 is NM , and the coupling capacitance values ​​between the floating gate 414 and the n input gate electrodes (415(1), ..., 415(n)) are (C S1 , …, C Sn ). The voltage potential V of the floating gate 414 f The calculation is as follows:

[0104] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C NM / C T )V S (=0),

[0105] Among them, (V S1 , …, V Sn ) represents the voltage applied to the n input gates, and the total coupling capacitance C of the channel region and the input gate electrodes (415(1), ..., 415(n)) relative to the floating gate 414 T =C s1 +…+C sn +C NM According to the floating gate voltage V of the N-type νLGNMOS device 410 connected in series with the load element 420 f And the voltage transfer function V O =f(V f ) can obtain the output voltage V on node 413 or 422 O When the floating gate voltage V f Greater than the threshold voltage V of the vLGNMOS device th0 When the N-type νLGNMOS device 410 is turned on, the output voltage V O To ground voltage V S . Output voltage V O Between high voltage rail V a and ground voltage V S For example, Figure 5 The threshold voltage V of the N-type νLGNMOS device 410 is shown th0 (curve 500), V th1 (curve 501) and V th2The floating gate voltage V f The output voltage V O The voltage transfer function V O =f(V f ), where V th0 <V th1 <V th2 , the load element 420 is implemented using a diode-connected N-type MOSFET device and V lth It is noted that the load element 420 includes, but is not limited to, a resistor, a diode-connected MOSFET device, or a biased MOSFET device, for allowing current to flow through the N-type νLGNMOS device 410 to increase the output voltage potential V O From high voltage (V a -V lth ) is pulled down to the ground voltage V S The voltage transfer function of the suppression type vLGNMOS circuit 400 with the pull-up diode-connected MOSFET device load element 420 is an inverse voltage transfer function with input voltage variation, which is calculated as follows:

[0106] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C NM / C T )V S (=0).

[0107] Furthermore, because the floating gate 414 of the N-type vLGNMOS device 410 is electrically insulated from the external electrode, storing charges in the isolated floating gate 414 of the N-type vLGNMOS device 410 will cause the voltage transfer function curves (500, 501, 502) to move in parallel, as shown in FIG. Figure 5 According to the charge conservation law of the floating gate, the rightward shift voltage ΔV of the negatively charged electrons (curves 501, 502) from the intrinsic voltage transfer function curve 500 (no charge in the floating gate 414) is calculated as follows: ΔV = -q / (C s1 +…+C sn ), where q represents the amount of charge stored in the floating gate 414, and (C s1 +…+C sn) is the total coupling capacitance of the input gate electrodes (415(1), ..., 415(n)) relative to the floating gate 414. The right-shift voltage ΔV is a function bias variable of the inverse S-shaped function.

[0108] Figure 6 In the embodiment, the suppression type vLGPMOS circuit 600 includes a single-gate P-type vLGNMOS device 610 and a load element 620 connected in series, which are biased at a high voltage rail V a and low voltage rail V S The source 611 and the N-type well electrode 612 of the single-gate P-type vLGPMOS device 610 are biased to the high voltage rail V a , and the drain 613 of the single-gate P-type vLGPMOS device 610 is connected to the node 622 of the load element 620 to form an output node 613, and the other node 621 of the load element 620 is connected to the ground potential V S The coupling capacitance C between the floating gate 614 and the vLGNMOS device 610 is PM , and the coupling capacitance values ​​between the floating gate 614 and the n input gate electrodes (615(1), ..., 615(n)) are (C S1 , …, C Sn ). The voltage potential V of the floating gate 614 f The calculation is as follows:

[0109] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C PM / C T )V a =(C s1 / C T )(V s1 -V a )+…+(C sn / C T )(V sn -V a )+V a ,

[0110] Among them, (V S1 , …, V Sn ) is the voltage applied to the n input gates, and the total coupling capacitance C of the channel region and the input gate electrodes (615(1), ..., 615(n)) relative to the floating gate 614 is T =C s1 +…+C sn +C PM.

[0111] According to the floating gate voltage V of the P-type vLGPMOS device 610 connected in series with the load element 610 f And the voltage transfer function V O =f(V f ), the output voltage V on node 613 or 622 can be obtained O When the floating gate voltage V f Less than the voltage (V a -V th ), the P-type vLGPMOS device 610 is turned on to pull up the output voltage V O , from the threshold voltage V of the diode-connected N-type MOSFET device lth Pull up to high voltage rail V a , where V th is the threshold voltage of the P-type νLGPMOS device 610. Output voltage V O is between the high voltage rail V a and ground voltage V S For example, Figure 7 The threshold voltage V of the P-type vLGPMOS device 610 is shown th0 (curve 700), V th1 (curve 701) and V th2 The floating gate voltage V f The output voltage V O The voltage transfer function V O =f(V f ), where V th0 <V th1 <V th2 , the load element 620 is implemented using an N-type MOSFET device in a diode connection configuration, and V lth It is noted that the load element 620 includes, but is not limited to, a resistor, a diode-connected MOSFET device, or a biased MOSFET device, which allows current to flow through the P-type νLGPMOS device 610 to increase the output voltage potential V O From the critical voltage V lth Pull up to high voltage rail V a The voltage transfer function of the suppression type vLGPMOS circuit 600 with a pull-down diode-connected MOSFET device load element is an inverse voltage transfer function with an input voltage variable, and the input voltage variable is calculated as follows:

[0112] V f =(C s1 / C T )V s1+…+(C sn / C T )V sn +(C PM / C T )V a

[0113] =(C s1 / C T )(V s1 -V a )+…+(C sn / C T )(V sn -V a )+V a .

[0114] Furthermore, because the floating gate 614 of the P-type vLGPMOS device 610 is electrically insulated from the external electrode, storing charges in the isolated floating gate 614 of the P-type vLGPMOS device 610 will cause the voltage transfer function curves (700, 701, 702) to move in parallel, as shown in FIG. Figure 7 According to the charge conservation law of the floating gate, the voltage ΔV that the negatively charged electrons (curves 701, 702) move to the right from the intrinsic voltage transfer function curve 700 (no charge in the floating gate 614) is calculated as follows: ΔV = -q / (C s1 +…+C sn ), where q represents the amount of charge stored in the floating gate 614, and (C s1 +…+C sn ) is the total coupling capacitance of the input gate electrodes (615(1), ..., 615(n)) relative to the floating gate 614. The right-shift voltage ΔV is a function bias variable of the inverse S-shaped function.

[0115] Figure 8 In the embodiment, the suppression type vLGCMOS circuit 800 includes a floating gate inverter device 850, including a single-gate P-type vLGPMOS device 810 and a single-gate N-type vLGNMOS device 820 connected in series. The source 811 and the N-type well electrode 812 of the single-gate P-type vLGPMOS device 810 are biased to the high voltage rail V a , and the source 813 and the P-type substrate electrode 814 of the single-gate N-type vLGNMOS device 820 are connected to the ground potential V S The drain 815P of the single-gate P-type vLGPMOS device 810 and the drain 815N of the single-gate N-type vLGNMOS device 820 are connected to form a node 815 to generate an output voltage V O The conductive floating gate 816 and the floating gate inverter device 850 form a capacitive coupling having a PMOS capacitance value C PM and NMOS capacitance CNM , the conductive floating gate 816 and the input gate electrode (817(1), ..., 817(n)) form a capacitive coupling having a capacitance value (C s1 , ..., C sn ). The voltage potential V of the floating gate 816 f The calculation is as follows:

[0116] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C PM / C T )V a +(C NM / C T )V S (=0),

[0117] Among them, (V S1 , …, V Sn ) is the voltage applied to the n input gates, and the total coupling capacitance C of the two channel regions and the input gate electrodes (817(1), ..., 817(n)) relative to the floating gate 816 is T =C s1 +…+C sn +C PM +C NM .

[0118] According to the floating gate voltage V f With the voltage conversion function V O =f(V f ), the output voltage V on node 815 can be obtained O The characteristic curve of the voltage transfer function (curve 900) of the vLGCMOS inverter device 850 is an inverted S-shaped voltage function, such as Fig. 9 At the same time, because the floating gate 816 of the vLGCMOS inverter device 850 is electrically insulated from the external electrode, if charges are stored in the floating gate 816 of the P-type vLGCMOS inverter device 850, the voltage transfer function curves (901, 902, 903) will move in parallel, as shown in FIG. Fig. 9 According to the charge conservation law of the floating gate, the voltage amount ΔV shifted to the right from the intrinsic voltage transfer function curve 900 (no charge in the floating gate 816) is calculated as follows: ΔV = -q / (C s1 +…+C sn ), where q represents the amount of charge stored in the floating gate 816, and (C s1 +…+Csn ) is the total coupling capacitance value of the input gate electrodes (817(1), ..., 817(n)) relative to the floating gate 816. Fig. 9 In FIG. 8 , because electrons (negative charge) are stored in the floating gate 816 , the voltage transfer function curve shifts from the no-charge curve 900 to the right to the curves ( 901 , 902 , 903 ), where 0<ΔV 1 <ΔV 2 <ΔV 3 Corresponding to 0<-q 1 <-q 2 <-q 3 The inverse S-shaped function generated by the suppression-type νLGCMOS circuit 800 is the voltage transfer function of the floating gate inverter device 850 with input voltage variation:

[0119] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C PM / C T )V a +(C NM / C T )V S (=0),

[0120] And voltage bias: ΔV = -q / (C s1 +…+C sn ).

[0121] The above two voltage variables (V f , ΔV) is the function variable of the inverse sigmoid function.

[0122] In order to convert the inhibitory S-shaped voltage function into an excitatory S-shaped function, a CMOS inverter device is added to invert all output voltage signals. For example, Fig.10 The display-excited vLGCMOS circuit 1000 includes a single-gate vLGCMOS device 1010 and a CMOS inverter device 1020. The floating gate 1016 forms a capacitive coupling with the vLGCMOS device 1010 with a PMOS capacitance C PM and NMOS capacitance C NM , and the floating gate 1016 and the input gate electrode (1011(1), ..., 1011(n)) form a capacitive coupling with a capacitance value (C s1 , ..., C sn). The output node 1012 of the vLGCMOS device 1010 is connected to the input gate 1021 of the CMOS inverter device 1020. Therefore, the excited S-shaped voltage function generated by the excited vLGCMOS circuit 1000 is as follows: Fig.11 As shown, where V th0 (Curve 1100)<V th1 (Curve 1101)<V th2 (curve 1102). The voltage potential V of the floating gate 1016 f It is obtained based on the function input voltage variable and is calculated as follows:

[0123] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C PM / C T )V a +(C NM / C T )V S (=0),

[0124] And voltage bias: ΔV = -q / (C s1 +…+C sn ), where q represents the amount of charge stored in the floating gate 1016, and (C s1 +…+C sn ) is the total coupling capacitance of the input gate electrodes (1011(1), ..., 1011(n)) relative to the floating gate 1016. The above two voltage variables (V f , ΔV) is the function variable of the S-shaped voltage function used in the neural network simulation.

[0125] Fig.12 A schematic diagram of a processing system with a vLGMOS circuit for optimizing processing efficiency is shown. The processing system 1200 includes an analog vLGMOS circuit portion 1210, an analog-to-digital converter (ADC) circuit portion 1230, a plurality of digital input terminals 1221, a digital processing circuit 1220, and a plurality of digital output terminals 1222, and can be manufactured into an IC chip using industry standard CMOS logic process technology; wherein the analog vLGMOS circuit portion 1210 includes at least one vLGMOS circuit 400 / 600 / 800 / 1000. A plurality of analog voltage signals (V ia1 , ..., V ian) is fed to the input node 1201 of the analog vLGMOS circuit portion 1210 to generate a plurality of output analog voltage signals (V oa1 , ..., V oam ), wherein n and m>=1. Then, the ADC circuit unit 1230 includes at least one ADC, which converts the analog voltage signal (V oa1 , ..., V oam ) is converted into a plurality of bit symbols having a plurality of digital voltage signals. Then, the plurality of digital voltage signals of the bit symbols are converted into a plurality of bit symbols by a plurality of strings of digital high voltage V DD (representing a value of 1) and a digital low voltage V SS (representing a value of 0) and fed to the digital input terminal 1221. The digital processing circuit 1220 includes a digital processor and a program memory (not shown). The program memory stores a plurality of instructions / program codes for the digital processor to execute, so that the digital processor is configured to perform digital operations on the digital data input from the digital input terminal 1221 and output the digital data after the operation to the digital output terminal 1222 on the output node 1202. The above-mentioned digital processor includes, but is not limited to, a general-purpose processor, a special-purpose processor, or both of the above-mentioned processors.

[0126] Fig.13 A top view of a suppression-type complementary vLGCMOS circuit 800 with four input gates fabricated in CMOS logic process technology is shown. The suppression-type complementary vLGCMOS circuit 1300 includes a single-gate P-type vLGPMOS device 1310 and a single-gate N-type vLGNMOS device 1320. The source 1311 and the N-type well electrode 1312 of the single-gate P-type vLGPMOS device 1310 are biased to a high voltage rail V a , and the source 1321 and the P-type substrate electrode 1322 of the single-gate N-type vLGNMOS device 1320 are connected to the ground potential V S The drains of the single-gate P-type vLGPMOS device 1310 and the single-gate N-type vLGNMOS device 1320 are connected to form a node 1315 through a metal / contact to generate an output voltage V O The conductive floating gate 1316 extends from the region of the vLGPMOS device 1310 and the vLGNMOS device 1320 to the input electrode region, and forms a capacitive coupling with the floating gate inverter device 1330 with a PMOS capacitance value C PM and NMOS capacitance C NM, and the electrically floating gate 1316 forms a capacitive coupling with a plurality of input gates (1317(1), 1317(2), 1317(3), 1317(4)) having an input electrode capacitance value (C 1 , C 2 , C 3 , C 4 ). The voltage potential V of the floating gate 1316 f The calculation is as follows:

[0127] V f =(C 1 / C T )V 1 +(C 2 / C T )V 2 +(C 3 / C T )V 3 +(C 4 / C T )V 4 +(C PM / C T )V a +(C NM / C T )V S (=0),

[0128] Among them, (V 1 , V 2 , V 3 , V 4 ) is the voltage applied to the four input gates, and the total coupling capacitance C of the two channel regions and the input gate electrodes (1317(1), ..., 1317(4)) relative to the floating gate 1316 is T =C 1 +C 2 +C 3 +C 4 +C PM +C NM .

[0129] Please note that by ignoring the parasitic capacitances, the floating gate region 1316 and the PMOS region (PA), the NMOS region (NA), and the input electrode region (A 1 , A 2 , A 3 , A 4 ) area overlap ratio, the capacitance ratio can be roughly calculated.

[0130] Fig.14A top view of an excitatory complementary vLGCMOS circuit 1000 fabricated in CMOS logic process technology and having four input gates is shown. The excitatory complementary vLGCMOS circuit 1400 includes a single-gate vLGCMOS inverter 1430 and a CMOS inverter 1440. The single-gate vLGCMOS inverter 1430 includes a single-gate P-type vLGPMOS device 1410 and a single-gate N-type vLGNMOS device 1420 connected in series. The CMOS inverter 1440 includes an input gate 1446, a source electrode 1441 of the PMOS, and a source electrode 1442 of the NMOS, wherein the source electrode 1441 of the PMOS and the source electrode 1442 of the NMOS are biased to a high voltage V a and ground potential V S The output node 1435 of the vLGCMOS inverter 1430 is connected to the input gate 1446 of the conventional CMOS inverter 1440 to invert the output voltage signal from the vLGCMOS inverter 1430 into an output voltage signal V on the output node 1445. O The conductive floating gate 1416 extends from the region of the vLGPMOS device 1410 and the vLGNMOS device 1420 to the input electrode region, and forms a capacitive coupling with the floating gate inverter device 1430 with a PMOS capacitance value C PM and NMOS capacitance C NM , and the electrically floating gate 1416 forms a capacitive coupling with a plurality of input gates (1417(1), 1417(2), 1417(3), 1417(4)) having an input electrode capacitance value (C 1 , C 2 , C 3 , C 4 ). The voltage potential V of the floating gate 1416 f The calculation is as follows:

[0131] V f =(C 1 / C T )V 1 +(C 2 / C T )V 2 +(C 3 / C T )V 3 +(C 4 / C T )V 4 +(C PM / C T )V a

[0132] +(C NM / C T )V S(=0),

[0133] Among them, (V 1 , V 2 , V 3 , V 4 ) is the voltage applied to the four input gates, and the total coupling capacitance C of the two channel regions and the input gate electrodes (1417(1), ..., 1417(4)) relative to the floating gate 1416 is T =C 1 +C 2 +C 3 +C 4 +C PM +C NM .

[0134] Please note that by ignoring the parasitic capacitance, the floating gate region and the PMOS region (PA), NMOS region (NA), and input electrode region (A 1 ,A 2 ,A 3 ,A 4 ) area overlap ratio, the capacitance ratio can be roughly calculated.

[0135] The preferred embodiments provided above are only used to illustrate the present invention, and are not intended to limit the present invention to a specific type or exemplary embodiment. Therefore, this specification should be regarded as illustrative rather than restrictive. The preferred embodiments provided above are intended to effectively illustrate the gist of the present invention and its best mode of implementation, so that those familiar with the art can understand the various embodiments and various changes of the present invention to adapt to specific uses or implementation purposes. The scope of the present invention is defined by the claims and their equivalents, in which all terms are intended to have the broadest reasonable meaning unless otherwise specifically indicated. Therefore, "the present invention" and similar terms do not limit the scope of the claims to a specific embodiment, and any reference to a specific preferred embodiment of the present invention does not mean to limit the present invention, and no such limitation will be inferred. The present invention is defined only by the scope and spirit of the claims. The abstract of the present invention is provided in accordance with the requirements of the law so that searchers can quickly confirm the subject matter of this technical disclosure from any patent approved by this specification, and is not used to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the present invention. It should be understood that various modifications or changes can be made by the industry, all of which should fall within the scope of the present invention defined by the claims. Furthermore, all elements and components in this specification are not intended to be dedicated to the public, regardless of whether the claims list these elements and components.

Claims

1. A processing system for receiving a plurality of input analog voltages and generating one or more digital output values, characterized in that: include: an analog circuit comprising at least one metal oxide semiconductor (MOS) circuit, each MOS circuit comprising a first single-layer gate neuron MOS device having a plurality of input gates, wherein each MOS circuit is used to model one of a sigmoid function and an inverse sigmoid function to generate an output analog voltage in response to one or more of the plurality of input analog voltages applied to the plurality of input gates; a conversion circuit coupled to the analog circuit and comprising one or more analog-to-digital converters ADC, each ADC performing analog-to-digital conversion on a corresponding output analog voltage according to its own resolution to generate a digital value; as well as a digital processor for performing digital processing operations on one or more digital values ​​from the conversion circuit to generate the one or more digital output values; The analog circuit, the conversion circuit and the digital processor are manufactured using industrial standard complementary metal oxide semiconductor (CMOS) logic process technology to form one or more integrated circuit chips.

2. The system of claim 1, wherein: The range of the output analog voltage is limited by two different operating voltages carried by an operating voltage terminal and a ground voltage terminal, and the operating voltage terminal and the ground voltage terminal are coupled to the analog circuit.

3. The system of claim 1, wherein: One of the at least one MOS circuit is used to model the inverse sigmoid function and comprises: a load element; and The first single-layer gate neuron MOS device is connected in series with the load element through an output node, and generates the output analog voltage at the output node.

4. The system of claim 3, wherein: The inverse sigmoid function is equivalent to the output analog voltage at the output node being a function of a voltage potential on a floating gate of the first single-layer gate neuron MOS device in one of the at least one MOS circuit.

5. The system of claim 4, wherein: The voltage potential on the floating gate is related to the one or more voltages of the multiple input analog voltages, the two different operating voltages of the analog circuit, and the multiple input gates and multiple capacitance values ​​of a channel region relative to the floating gate in the first single-layer gate neuron MOS device.

6. The system of claim 1, wherein: One of the at least one MOS circuit is used to model the inverse sigmoid function and comprises: The first single-layer gate neuron MOS device; and A second single-layer gate neuron MOS device, wherein the first single-layer gate neuron MOS device and the second single-layer gate neuron MOS device are connected in series to form a single-layer gate neuron CMOS device, comprising the multiple input gates, a floating gate, a first channel region and a second channel region.

7. The system of claim 6, wherein: The inverse S-shaped function of one of the at least one MOS circuit is equivalent to the output analog voltage on an output node of the first single-layer gate neuron CMOS device being a function of a voltage potential on the floating gate.

8. The system of claim 7, wherein: The voltage potential on the floating gate is related to the one or more voltages of the multiple input analog voltages, two different operating voltages of the analog circuit, and multiple capacitance values ​​of the multiple input gates, the first channel region and the second channel region relative to the floating gate.

9. The system of claim 1, wherein: One of the at least one MOS circuit is used to model the S-shaped function and comprises: The first single-layer gate neuron MOS device; a second single-layer gate neuron MOS device, wherein the first single-layer gate neuron MOS device and the second single-layer gate neuron MOS device are connected in series to form a single-layer gate neuron CMOS device; and A CMOS inverter, wherein an input node of the CMOS inverter is connected to an output node of the single-layer gate neuron CMOS device, and an output node of the CMOS inverter generates the output analog voltage.

10. The system of claim 9, wherein: The single-layer gate neuron CMOS device includes multiple input gates, a floating gate, a first channel region and a second channel region, wherein the S-shaped function of at least one of the MOS circuits is equivalent to the output analog voltage on the output node of the CMOS inverter being a function of a voltage potential on the floating gate, and wherein the voltage potential on the floating gate is related to one or more voltages of the multiple input analog voltages, two different operating voltages of the analog circuit, and multiple capacitance values ​​of the multiple input gates, the first channel region and the second channel region relative to the floating gate.

11. The system of claim 1, wherein: The first single-layer gate neuron MOS device is formed in a substrate with a first conductivity type and comprises: a source region having a second conductivity type and formed in the substrate; a drain region having the second conductivity type and formed in the substrate; a channel region between the source region and the drain region; The plurality of input gates have the second conductivity type and are formed in the substrate; and A floating gate is disposed above the channel region and the plurality of input gates and is insulated from the channel region and the plurality of input gates.

12. The system of claim 11, wherein: For one of the at least one MOS circuit, The rightward shift of a current voltage transfer curve relative to an intrinsic voltage transfer curve depends on the amount of charge stored in the floating gate and the total capacitance of the plurality of input gates relative to the floating gate; wherein the current voltage transfer curve is equivalent to one of the S-shaped function and the reverse S-shaped function; and The intrinsic voltage transfer curve corresponds to the fact that no electrons are stored in the floating gate of the first single-layer gate neuron MOS device included in one of the at least one MOS circuits.

13. The system of claim 1, wherein: The analog circuit is simulated and manufactured into the one or more integrated circuit chips for application in the biomedical field.

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