Distributed capacitance detection method and system for power equipment

Abstract

The invention belongs to the technical field of electrical parameter simulation calculation of power equipment, and discloses a distributed capacitance detection method and system for the power equipment, and the method comprises the steps: calculating the distributed capacitance of any winding in a pre-established geometric model of the power equipment, the method specifically comprises the following steps: calculating an internal shielding range, an edge shielding range and an end shielding range of any winding; dividing any winding into a plurality of winding partitions by taking a cake as a unit; according to the internal shielding range, the edge shielding range and the end shielding range, respectively carrying out finite element simulation on the plurality of winding partitions to obtain distributed capacitance of each winding partition; combining the distributed capacitance of each winding zone to obtain the distributed capacitance of any winding in the pre-established geometric model of the power equipment; and combining the distributed capacitance of all windings in the geometric model of the power equipment to obtain the distributed capacitance of the power equipment. According to the invention, large-scale main distributed capacitance with controllable relative errors can be obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of electrical parameter simulation calculation of power equipment, and in particular relates to a distributed capacitance detection method and system for power equipment. Background Art

[0002] For power equipment with windings, such as transformers and reactors, the distributed capacitance parameters are the main factors affecting their overvoltage performance and need to be considered in the equipment design stage. Therefore, obtaining a large number of main distributed capacitance parameters with small errors will be a key prerequisite for establishing a fine model of the overvoltage simulation circuit. However, due to the excessive number of winding turns of high-voltage power equipment and the limitation of computer memory, the calculation of the distributed capacitance of the windings in the design process is currently mostly done by using analytical methods or finite element methods to calculate the local model of the winding (usually a 2-cake winding) to obtain the inter-turn distributed capacitance and the inter-cake distributed capacitance. The winding is regarded as a whole and then divided by the number of winding cakes to obtain the inter-winding distributed capacitance and the outer side of the winding to the ground distributed capacitance. The analytical method does not consider the edge effect of the distributed capacitance, and the finite element simulation method is relatively more accurate. However, the related finite element calculation scheme currently used has large errors in the distributed capacitance parameters obtained, and the errors are uncontrollable. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the purpose of the present invention is to provide a distributed capacitance detection method and system for power equipment. The present invention can solve the problem that the prior art cannot detect large-scale distributed capacitance terminals (usually the capacitance terminals are on the order of 10 3 And above) to perform a finite element simulation calculation to obtain all the main distributed capacitances (involving inter-turn distributed capacitance, inter-cake distributed capacitance, inter-winding distributed capacitance, and outer side of winding distributed capacitance to ground) to obtain large-scale main distributed capacitance with controllable relative error.

[0004] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0005] A distributed capacitance detection method for electric power equipment, comprising:

[0006] Calculate the distributed capacitance of any winding in a pre-built geometric model of a power plant, including:

[0007] Calculating the inner shielding range, the edge shielding range and the end shielding range of any one of the windings;

[0008] Divide any one of the windings into a plurality of winding partitions based on the unit of cake;

[0009] According to the internal shielding range, the edge shielding range and the end shielding range, finite element simulation is performed on the plurality of winding partitions to obtain the distributed capacitance of each winding partition;

[0010] Combining the distributed capacitances of each winding to obtain the distributed capacitance of any winding in the pre-established geometric model of the power equipment;

[0011] The distributed capacitance of all windings in the geometric model of the power equipment is combined to obtain the distributed capacitance of the power equipment.

[0012] The present invention also provides a distributed capacitance detection system for electric power equipment, which is used to implement the above method, comprising:

[0013] Winding distributed capacitance calculation module: used to calculate the distributed capacitance of any winding in the pre-established geometric model of the power equipment, including:

[0014] Shielding range calculation module: used to calculate the internal shielding range, edge shielding range and end shielding range of any one of the windings;

[0015] Winding partitioning module: used to divide any one winding into a plurality of winding partitions in units of pancakes;

[0016] Winding partition distributed capacitance calculation module: used to perform finite element simulation on the plurality of winding partitions according to the internal shielding range, the edge shielding range and the end shielding range, so as to obtain the distributed capacitance of each winding partition;

[0017] A first combining module: used for combining the distributed capacitances of each winding to obtain the distributed capacitance of any winding in the pre-established geometric model of the power equipment;

[0018] The second combination module is used to combine the distributed capacitances of all windings in the geometric model of the power equipment to obtain the distributed capacitance of the power equipment.

[0019] The present invention has the following beneficial effects:

[0020] The present invention uses the finite element solution domain simulation condition setting and parameter iteration scheme to achieve electric field equivalence, and then divides the winding into sections and performs multiple finite element simulations of the overall model to obtain the large-scale main distributed capacitance of the winding with controllable relative error (usually the capacitance end is on the order of 10 3 And above, involving the method of inter-turn distributed capacitance, inter-cake distributed capacitance, inter-winding distributed capacitance, and distributed capacitance of the outer side of the winding to the ground), solves the problem of memory limitation and error control in large-scale distributed capacitance calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The overall flow chart of the method of the present invention; Figure 2 A flowchart of selecting shielding parameters in an embodiment of the present invention; Figure 3A flow chart for setting simulation conditions for the current winding partition solution domain in an embodiment of the present invention; Figure 4 In the embodiment of the present invention, Bp range Relative error control selection flow chart; Figure 5 A flow chart for setting simulation conditions for the current winding edge solution domain in an embodiment of the present invention; Figure 6 A flow chart for setting simulation conditions for solving domains of adjacent winding edges in an embodiment of the present invention; Figure 7 Bbp in the embodiment of the present invention range Relative error control selection flow chart; Figure 8 L(R)Bp in the embodiment of the present invention num Relative error control selection flow chart; Fig. 9 Flowchart of other types of winding processing methods; Fig.10 This is a flow chart of electrostatic field scanning calculation in an embodiment of the present invention; Fig.11 A diagram showing the winding types in an embodiment of the present invention; Fig.12 A winding zoning diagram in an embodiment of the present invention; Fig.13 This is a Btest cake test winding zoning selection diagram in an embodiment of the present invention; Fig.14 A diagram showing the setting of simulation conditions for the current winding partition solution domain in an embodiment of the present invention; Fig.15 A diagram showing the current winding edge solution domain simulation condition setting in an embodiment of the present invention; Fig.16 In the embodiment of the present invention, By start Value map; Fig.17 A diagram showing the setting of simulation conditions for solving the domain of adjacent winding edges in an embodiment of the present invention; Fig.18 A diagram showing the setting of simulation conditions for the solution domain when the current winding is a Class 3 winding in an embodiment of the present invention; Fig.19 This is a diagram for setting simulation conditions for the solution domain when the edge winding is a Class 3 winding in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Reference Figure 1-Figure 10 The distributed capacitance detection method for electric power equipment of the present invention comprises the following steps:

[0024] Step 1, establishing a geometric model of the power equipment, selecting a winding from the windings as the current winding, and selecting a first test winding partition from the current winding; in this step, different operations are performed according to different winding types, and the first test winding partition is selected to iteratively adjust the internal shielding range and the edge shielding range;

[0025] Step 2: in the geometric model, all winding terminals in the middle of the first test winding partition are set as the first test winding partition scanning terminal, and the current winding partition solution domain simulation condition is set according to the first test winding partition scanning terminal to obtain the first simulation condition; in this step, it is necessary to select the internal shielding range according to the capacitance iteration error between the scanning terminal in the middle of the test cake and the remaining scanning terminals in the test cake and the capacitance terminals of the adjacent cakes;

[0026] Step 3, iteratively adjust the initially preset internal shielding range of the current winding under the first simulation condition, perform electrostatic field scanning calculation on the first test winding partition, and obtain the internal shielding range of the current winding; in this step, the selection of the internal shielding range is used to ensure the equivalence of the electric field in the winding partition, and to ensure that the calculation results of the distributed capacitance between turns and between cakes within the partition are reasonable.

[0027] Step 4, according to the current winding partition solution domain simulation condition and the internal shielding range of the current winding, the current winding edge solution domain simulation condition and the adjacent winding edge solution domain simulation condition are set in the geometric model to obtain the second simulation condition; in this step, it is necessary to select the edge shielding range according to the capacitance iteration error between the scanning terminal of the edge of the test cake and the capacitance terminal between the adjacent windings and the capacitance terminal of the grounding part;

[0028] Step 5, iteratively adjusting the initially preset edge shielding range under the second simulation condition, performing electrostatic field scanning calculation on the first test winding partition, and obtaining the edge shielding range of the current winding; in this step, the edge shielding range is selected to ensure that the electric field between the current winding and the adjacent windings and the outer side of the winding to the ground is equivalent, and the calculation results of the distributed capacitance between the turns at the edge of the partition, between the cakes, between the windings, and the outer side of the partition to the ground are reasonable;

[0029] Step 6, selecting the two outermost cakes at one end and the two outermost cakes at the other end from the current winding as the second test winding partition, setting all winding terminals in the second winding partition as the second test winding partition scanning terminals, and setting the first simulation condition of the second test winding partition within the internal shielding range according to the internal shielding range and the edge shielding range; setting the second simulation condition of the second test winding partition within the edge shielding range according to the edge shielding range; and obtaining the third simulation condition;

[0030] Step 7, iteratively adjusting the preset initial end shielding range under the third simulation condition, performing electrostatic field scanning calculation on the geometric model of the power equipment, and obtaining the end shielding range of the current winding; in this step, the selection of the end shielding range is used to ensure that when the winding partition is at the end, the electric field between the current winding and the adjacent windings and the outer side of the winding are equivalent to the ground, and to ensure that when the winding partition is at the end, the calculation results of the distributed capacitance between the turns at the edge of the partition, between the cakes, between the windings, and the outer side of the partition to the ground are reasonable;

[0031] Step 8, in the geometric model, the current winding of the electric power equipment is divided into a plurality of winding partitions in units of cakes, and finite element simulations are sequentially performed on the winding partitions of all the current windings according to the internal shielding range, the edge shielding range, and the end shielding range to obtain the distributed capacitance of the current winding;

[0032] Step 9, sequentially selecting one winding from all windings of the power equipment in the geometric model as the current winding, completing the above steps, and obtaining the distributed capacitance of the power equipment.

[0033] In the above solution of the present invention, the specific process of establishing the geometric model of the power equipment, determining the winding type, selecting a winding from the windings as the current winding, and selecting the first test winding partition from the current winding includes:

[0034] Establishing a geometric model of the power equipment; defining material properties in the geometric model, setting the dielectric constants of metal materials to 1, that is, when no special settings are made for the metal area, it is regarded as air for calculation; setting the conductor area of ​​the grounding component of the power equipment to a capacitor terminal;

[0035] defining material properties in the geometric model and setting a grounding component conductor region of the power device as a capacitor terminal;

[0036] Determine the winding type; Fig.11 As shown, the winding with only one coil in a single phase is a Class 1 winding; the non-voltage-regulating winding with two coils connected in parallel and the middle outlet is a Class 2 winding; the voltage-regulating winding with two coils connected in parallel and the middle outlet is a Class 3 winding; the winding with a screen wire is classified according to the above principles, and the screen wire can be regarded as a working wire and treated in the same way as follows;

[0037] Unless otherwise specified, the upper and lower coils of the Class 2 winding are combined into one coil and treated as a Class 1 winding for subsequent processing; unless otherwise specified, the Class 3 winding is treated as two Class 1 windings for subsequent processing; the following windings are defaulted to Class 1 windings;

[0038] like Fig.13 As shown, select B, which is in the middle of the interval between the current winding and the adjacent windings on both sides.test Pie and B test The upper and lower pies of the cake are the first test winding partitions; all winding cake numbers increase from 1 from top to bottom;

[0039] like Fig. 9 and Fig.19 As shown, when the adjacent windings are Class 3 windings, the upper / lower windings of the adjacent windings are regarded as two adjacent Class 1 windings on the same side, and two first test winding partitions are selected according to the different middle positions of the opposite intervals between the current winding and the two adjacent Class 1 windings on the same side, and subsequent internal shielding ranges and edge shielding ranges are iteratively adjusted to obtain two internal shielding ranges and two edge shielding ranges, and the larger value of the two internal shielding ranges and the two edge shielding ranges is selected as the final value of the internal shielding range and the edge shielding range of the current winding.

[0040] In the above solution of the present invention, all winding terminals in the middle of the first test winding partition are set as scanning terminals in the geometric model, and the simulation conditions of the current winding partition solution domain are set according to the scanning terminals to obtain the first simulation conditions, such as Figure 3 As shown, the specific process includes:

[0041] The winding terminals in the middle of the first test winding partition are all set as scanning terminals, i.e. Bs start To Bs end Pie (the symbol marked as start in the lower right corner is the pie number of the upper end of the partition, and the symbol marked as end is the pie number of the lower end of the first test winding partition. The same applies to all the following labels). Fig.14 As shown;

[0042] The first test winding is divided into upper and lower Bs start -1 and Bs end +1 All winding terminals are set as capacitor terminals, i.e. Bc start With Bc end Pie, we can see that it has the following relationship:

[0043] Bc start =Bs start -1

[0044] Bc end =Bs end +1

[0045] If there is no pie that meets the above relationship requirements, there is no need to set the capacitor terminal; however, when calculating the relevant pie number later, the Bc involved start , Bc end Still follow the above formula to get the value, such as Fig.14 As shown;

[0046] The first test winding partition Bcstart -1 to Bc start -Bp range , next Bc end +1 to Bc end +Bp range The left and right edge winding terminals are set as capacitor terminals, and the remaining winding terminals are set as shielding terminals, that is, Bp start To Bp end Pie, we can see that it has the following relationship:

[0047] B start =Bc start -Bp range

[0048] B end =Bc end +Bp range

[0049] If there is no pie that meets the above relationship requirements, it is not necessary to set the capacitor terminal and the shielding terminal; however, when calculating the relevant pie number, the Bp involved start , Bp end Still follow the above formula to get the value, such as Fig.14 As shown; among them, Bp range The shielding range of the current winding. When each winding is set for the first time, Bp range =1, and the value is selected through relative error control later.

[0050] In the above solution of the present invention, the initially preset internal shielding range is iteratively adjusted under the first simulation condition, and the electrostatic field scanning calculation is performed on the first test winding partition to obtain the internal shielding range of the current winding, such as Fig.14 As shown, the specific process includes:

[0051] Fine meshing is performed on the scanning terminal, capacitor terminal, shielding terminal area and nearby areas (the nearby areas can be set according to specific circumstances and are not specifically limited in the present invention), and coarse meshing is performed on the remaining areas; all scanning terminals are set to 1V and the remaining terminals are set to 0V in turn to perform electrostatic field calculation. This step is referred to as electrostatic field scanning calculation below. Fig.10 As shown;

[0052] When the current winding is the upper / lower winding in the three types of windings, before each electrostatic field scanning calculation, the cake closest to the current winding in the lower / upper winding is set as a capacitor terminal, and the next closest cake is set as a shielding terminal; at the same time, before each electrostatic field scanning calculation, the outermost winding non-charged terminal of the cake whose center y coordinate in the left / right adjacent winding is within the range of [SY[SBn], XY[1]] is set as a capacitor terminal, and the second outer winding non-charged terminal is set as a shielding terminal; S(X)Y[n] is the y coordinate of the nth cake of the upper / lower winding in the three types of windings, and S(X)Bn is the total number of cakes in the upper / lower winding, such as Fig. 9 , Fig.18 As shown;

[0053] Extract B test The first two orders of magnitude of inter-turn and inter-pancake terminal charges in the calculation results of the terminal electrostatic field scanned in the middle of the pancake are taken as the first terminal charges; Explanation: the inter-turn capacitance is the capacitance between the conductor and other conductors in the same pancake; the inter-pancake capacitance is the capacitance between the conductor and the conductors in the upper and lower adjacent pancakes.

[0054] Iteratively adjust Bp range , until the relative error between the first terminal charge of the current iteration and the first terminal charge of the previous iteration meets the preset first error requirement: increase the internal shielding range according to the preset first step length; the first step length is an integer; under the condition of the increased internal shielding range, perform electrostatic field scanning calculation on the first test winding partition to obtain the first terminal charge of the current iteration; calculate the first difference between the first terminal charge of the current iteration and the first terminal charge of the previous iteration, and if the first difference meets the preset first error requirement, end the iteration;

[0055] The internal shielding range of the current iteration is used as the internal shielding range of the current winding.

[0056] In the above scheme of the present invention, according to the current winding partition solution domain simulation condition and the internal shielding range, the current winding edge solution domain simulation condition and the adjacent winding edge solution domain simulation condition are set in the geometric model to obtain the second simulation condition, and the second simulation condition is obtained by referring to Figure 5 , Figure 6 , the above process is as follows:

[0057] Shield the start and end numbers of the current winding edge Bbp start , Bbp end Value: Bbp start =Bp start -Bbp range , Bbp end =Bp end +Bbp range ;Bbp range The current winding edge shielding range, each winding is set for the first time Bbp range=1, and the value is selected through relative error control later;

[0058] Set the solution domain simulation conditions for the current winding edge: Bbp start ≥2, that is, when there is a winding edge setting cake above the current winding partition, Bbp start To Bp start -1 The outermost winding terminal of the cake is set as a capacitor terminal, and the second outer winding terminal is set as a shielding terminal; Bp end ≤Bn-1, that is, when there is a winding edge setting cake below the current winding partition, Bp end +1 to Bp end The outermost winding terminal of the cake is set as the capacitor terminal, and the second outer winding terminal is set as the shielding terminal; Bn is the total number of winding cakes at present, such as Fig.15 As shown;

[0059] According to the current winding edge shielding range Bbp range Corresponding to the upper and lower boundaries of the required shielding range y coordinates By start 、By end The shielding start and end numbers of the left and right adjacent winding edges are L(R)Bbp start 、L(R)Bbp end Take values, where the symbol with the first letter L(R) represents the left / right adjacent winding related parameters, and the same applies to all the following symbols. If there is no adjacent winding on one side, the related symbols and steps are skipped). In this step, the edge shielding range setting of the adjacent winding is selected according to the edge shielding range setting of the current winding. The selection principle is to select the two cakes in the adjacent winding when the Y coordinate range just covers all the edge shielding terminals of the current winding as the start and end cakes of the edge shielding range setting of the adjacent winding;

[0060] (i) According to the winding partition and Bbp range Size start 、By end Value:

[0061] Bb start ≥1,By start The value is the current winding Bbp start The y coordinate of the middle of the pie;

[0062] Bb start <1,By start Value is By 1 +(1-Bbp start )*(By 1 -By 2 ), By 1 is the y coordinate of the middle of the first cake of the current winding, By 2 is the y coordinate of the middle of the second cake of the current winding;

[0063] Bb end ≤Bn,By end The value is the current winding Bbp end The y coordinate of the middle of the cake, Bn is the total number of cakes in the current winding;

[0064] Bb end >Bn,By end Value is By Bn +(Bbp end -Bn))*(By Bn -By Bn-1 ), By Bn is the y coordinate of the middle of the Bnth cake of the current winding, By Bn-1 is the y coordinate of the middle of the Bn-1th cake of the current winding;

[0065] Explanation: When the edge shielding range exceeds the number of winding cakes, the coordinates are padded with 1, 2 or Bn, Bn-1 cake spacing multiples, such as Fig.16 As shown;

[0066] (ii) According to the relative position of the current winding and the adjacent winding and By start 、By end Size is L(R)Bbp start 、L(R)Bbp end Select the L(R)Bbp whose corresponding pie y coordinate satisfies the following conditions start 、L(R)Bbp end Pie number:

[0067] If L(R)Y[n]-Bystart≥0, where n∈[1, L(R)Bn], then L(R)n=max{L(R)n|L(R)Y[n]-Bystart>0}, L(R)Bystart=L(R)Y[n]; otherwise, L(R)Bystart=L(R)Y[1]. Explanation: If there is a pie on Bystart in the left / right adjacent winding, then the pie closest to Bystart is taken; if not, the pie number is 1.

[0068] If there exists L(R)Y[n]-Byend≤0, where L(R)n∈[1, L(R)Bn], then L(R)n=min{L(R)n|L(R)Y[n]-Byend<0}, L(R)Byend=L(R)Y[n]; otherwise, L(R)Byend=L(R)Y[L(R)Bn]. Explanation: If there is a pie under Byend in the left / right adjacent winding, then the pie closest to Byend is taken; if not, the pie number is L(R)Bn.

[0069] L(R)Y[n] is the y coordinate of the nth cake of the left / right adjacent winding, and L(R)Bn is the total number of cakes of the left / right adjacent winding;

[0070] Set the solution domain simulation conditions for the adjacent winding edges: L(R)Bp start to L(R)Bp end The outermost winding terminal of the left / right adjacent winding of the pie facing the current winding is set as the capacitor terminal, and the second outermost winding terminal is set as the shielding terminal; if there is no L(R)Y[n]-By start ≥0, where n∈[1, L(R)Bn], i.e. the y coordinates of the left / right adjacent windings are all less than By start , then the left / right L(R)Bp num (Number of left / right end shield windings, each winding is set up for the first time L(R)Bp num =1, and then select the value through relative error control) The first winding terminal of the adjacent winding is set as the capacitor terminal, and the second winding non-charged terminal is set as the shielding terminal; if there is no L(R)Y[n]-By end ≤0, where L(R)n∈[1, L(R)Bn], i.e. the y coordinates of the left / right adjacent windings are both greater than By end , then the left / right L(R)Bsp num The last winding terminal of the adjacent winding is set as a capacitor terminal, and the non-charged terminal of the next last winding is set as a shielding terminal. Fig.17 As shown;

[0071] When the adjacent winding edge solution domain simulation condition setting area overlaps with the simulation condition setting area before the electrostatic field scanning calculation when the current winding is an upper / lower winding in the three types of windings, the adjacent winding edge solution domain simulation condition setting in the overlapping area is skipped;

[0072] When the adjacent windings are Class 3 windings, the upper / lower windings of the adjacent windings are regarded as two adjacent Class 1 windings on the same side. When setting the current winding edge solution domain simulation conditions and the adjacent winding edge solution domain simulation conditions, the two adjacent Class 1 windings on the same side sequentially perform the current winding edge and adjacent winding edge solution domain simulation conditions settings, such as Fig. 9 , Fig.19 shown.

[0073] In the above solution of the present invention, iteratively adjusting the initially preset edge shielding range under the second simulation condition, performing electrostatic field scanning calculation on the second test winding partitions, and obtaining the edge shielding range of the current winding includes:

[0074] Performing electrostatic field scanning calculation on the first test winding partition;

[0075] Extract Btest The first two orders of magnitude of the terminal charges of the winding edges (left and right edges, first and last pancakes) in the calculation results of the terminal electrostatic field of the left / right edge of the pancake are used as the second terminal charges (when the current winding is an edge winding, the terminal charges of the grounded part also need to be extracted);

[0076] Iteratively adjust Bbp range , until the relative error between the second terminal charge of the current iteration and the second terminal charge of the previous iteration meets the preset second error requirement: increase the edge shielding range according to a preset second step length; the second step length is an integer; under the condition of the increased edge shielding range, perform electrostatic field scanning calculation on the second test winding partition to obtain the second terminal charge of the current iteration; calculate the second difference between the second terminal charge of the current iteration and the second terminal charge of the previous iteration, and if the second difference meets the preset second error requirement, end the iteration;

[0077] The edge shielding range of the current iteration is used as the edge shielding range of the current winding.

[0078] In the above scheme of the present invention, the two outermost cakes at one end and the two outermost cakes at the other end are selected from the current winding as the second test winding partition, and all winding terminals of the outermost cakes at both ends of the second winding partition are set as scanning terminals. According to the internal shielding range and the edge shielding range, the first simulation condition and the second simulation condition are set in sequence to obtain the third simulation condition, such as Fig.17 As shown, the specific process includes:

[0079] According to the internal shielding range, setting a first simulation condition in which the second test winding is partitioned within the internal shielding range;

[0080] According to the edge shielding range, a second simulation condition is set in which the second test winding is partitioned within the edge shielding range.

[0081] In the above solution of the present invention, the preset initial end shielding range is iteratively adjusted under the third simulation condition, and the electrostatic field scanning calculation is performed to obtain the end shielding range of the current winding, such as Figure 8 As shown, the specific process includes:

[0082] Perform electrostatic field scanning calculation on the second test winding partition;

[0083] Extracting the grounding terminal charge from the terminal electrostatic field calculation result of the two side ends of the current winding as the third terminal charge;

[0084] Iterative adjustment of L(R)Bp num, until the relative error between the third terminal charge of the current iteration and the previous iteration meets the preset third error requirement: increase the end shielding range according to the preset third step length; the third step length is an integer; if L(R)Bp num If the structural limit has been reached, the iteration is terminated; under the condition of the increased end shielding range, the electrostatic field scanning calculation is performed on the second test winding partition to obtain the third terminal charge of the current iteration; the third difference between the third terminal charge of the current iteration and the third terminal charge of the previous iteration is calculated, and if the third difference meets the preset third error requirement, the iteration is terminated;

[0085] The end shielding range of the current iteration is used as the edge shielding range of the current winding.

[0086] In the above solution of the present invention, the current winding of the power equipment is divided into a plurality of winding partitions in units of cakes in the geometric model, and the winding partitions of all the current windings are sequentially subjected to finite element simulation according to the internal shielding range, the edge shielding range and the end shielding range to obtain the distributed capacitance of the current winding, including:

[0087] The current winding is divided into n multi-cake calculation partitions A from top to bottom with cake as the basic unit. 1 , A 2 ,……,A n , until all the pies of the current winding are divided; that is, Bn A1 +Bn A2 +……+Bn An =Bn;Bn A1 , Bn A2 , ..., Bn An The total number of pies corresponding to each partition; the number of pies in each winding partition shall not exceed the maximum number of pies that the computing device can calculate at one time; (such as Fig.12 (shown)

[0088] According to the internal shielding range, setting a first simulation condition for each of the winding partitions within the internal shielding range;

[0089] According to the edge shielding range and the end shielding range, setting a second simulation condition for partitioning each winding into the edge shielding range;

[0090] According to the simulation conditions within the internal shielding range and the simulation conditions within the edge shielding range and the end shielding range, electrostatic field scanning calculations are performed on all the winding partitions in turn to obtain the current distributed capacitance.

[0091] Example

[0092] The distributed capacitance detection method for electric power equipment in this embodiment comprises the following steps:

[0093] 【1】Clarify the relative error requirements of distributed capacitance parameters;

[0094] 【2】Establish a geometric model of power equipment, define material properties, and set the dielectric constants of all metal materials to 1. That is, when no special settings are made for metal areas, they are considered to be air for calculation;

[0095] 【3】Determine the type of each winding: a single-phase winding with only one coil is a Class 1 winding; a single-phase winding with two coils connected in parallel and a non-voltage-regulating winding with a middle outlet is a Class 2 winding; a single-phase winding with two coils connected in parallel and a middle outlet is a Class 3 winding; for windings with screen wires, the winding types are classified according to the above principles, and the screen wires can be regarded as working wires and treated in the same way as follows;

[0096] 【4】First, the technical solution is explained for the case where all windings are Class 1;

[0097] 【5】All winding numbers are incremented from 1 from top to bottom;

[0098] 【6】Select B in the middle of the interval between the current winding and the adjacent windings on both sides. test Pie and B test The upper and lower cakes of the cake are the test winding partitions, and the solution domain simulation conditions are set and the finite element simulation is iterated to confirm the parameters required for electric field equivalence;

[0099] 【7】According to the different simulation conditions of the solution domain, the conductor area of ​​the coil and the grounding component (hereinafter referred to as the terminal) can be divided into the following four types:

[0100] 【8】1) No charge terminal: There is no free charge distribution, and all terminals are defaulted to no charge terminals;

[0101] 【9】2) Scan terminal: The potential is initially set to 0 V and is set to 1 V in subsequent scan calculations. There is free charge distribution and subsequent terminal charge extraction.

[0102]

[10] 3) Capacitor terminal: The potential is set to 0 V, there is free charge distribution, and its distributed capacitance is considered, and terminal charge extraction is performed later;

[0103]

[11] 4) Shielded terminal: The potential is set to 0 V, there is free charge distribution, its distributed capacitance is not considered, and the terminal capacitance extraction is not performed subsequently;

[0104]

[12] Set the grounding component terminal to a capacitor terminal;

[0105]

[13] Set the simulation conditions for the solution domain of the current winding partition to achieve the equivalence of the electric field in the winding partition and ensure that the calculation results of the distributed capacitance between turns and between disks within the partition are reasonable:

[0106]

[14] 1) All winding terminals in the middle of the partition are set as scanning terminals, i.e. Bs start To Bs end Pie (the symbol marked as start in the lower right corner is the pie number at the upper end of the scan terminal in the partition, and the symbol marked as end is the pie number at the lower end of the scan terminal in the partition, and the same applies to all the following labels);

[0107]

[15] 2) Partition upper and lower Bs start -1.Bs end +1 All winding terminals are set as capacitor terminals, i.e. Bc start With Bc end Cake, we can see that there is the following relationship: Bc start =Bs start -1, Bc end =Bs end +1;

[0108]

[16] 3) Partition Bc start -1 to Bc start -Bp range , next Bc end +1 to Bc end +Bp range (When each winding is first set up, Bp range =1, and the value is selected later through relative error control) The left and right edge winding terminals are set as capacitor terminals, and the remaining winding terminals in the pancake are set as shielding terminals, that is, Bp start To Bp end Pie, we can see that there is the following relationship: Bp start =Bc start -Bp range , Bp end =Bc end +Bp range ;

[0109]

[17] For the current winding internal shielding range Bp range Make relative error control selection:

[0110]

[18] 1) According to the simulation condition setting of the solution domain, mesh generation is performed, and all scanning terminals are set to 1V in turn to perform electrostatic field calculation (hereinafter referred to as electrostatic field scanning calculation);

[0111]

[19] 2) Extract B test The inter-turn and inter-pancake terminal charges in the calculation results of the electrostatic field of the scanning terminal in the middle of the pancake;

[0112]

[20] 3) Increase Bp range , Bp range =Bp range +k (k is a positive integer);

[0113]

[21] 4) Repeat

[13] to

[20] , compare the charges extracted twice before and after, if the relative errors of the terminal charges of the first two orders of magnitude in the current iteration compared with the previous iteration meet the requirements, then end the iteration and take the Bp used in the current iteration simulation range is the final value;

[0114]

[22] Set the simulation conditions of the solution domain for the edge of the current winding and the edge of the adjacent winding to achieve the equivalence of the electric field between the current winding and the adjacent winding and the outer side of the winding to the ground, and ensure that the calculation results of the distributed capacitance between turns, between cakes, between windings, and outside the partition to the ground are reasonable:

[0115]

[23] 1) is the start and end number of the current winding edge shield Bbp start , Bbp end Value:

[0116]

[24] Bbp start =Bp start -Bbp range ;

[0117]

[25] Bbp end =Bp end +Bbp range ;

[0118]

[26] Bbp range The current winding edge shielding range, each winding is set for the first time Bbp range =1, and the value is selected through relative error control later;

[0119]

[27] 2) Set the simulation conditions for the solution domain of the current winding edge:

[0120]

[28] Bp start ≥2, that is, when there is a winding edge setting cake above the current winding partition, Bbp start To Bp start -1 The outermost winding terminal of the cake is set as a capacitor terminal, and the second outer winding terminal is set as a shielding terminal;

[0121]

[29] Bp end ≤Bn-1, that is, when there is a winding edge setting cake below the current winding partition, Bp end +1 to Bp end The outermost winding terminal of the cake is set as the capacitor terminal, and the second outer winding terminal is set as the shielding terminal; Bn is the total number of winding cakes at present;

[0122]

[30] 3) According to the current winding edge shielding range Bbp range Corresponding to the upper and lower boundaries of the required shielding range y coordinates By start 、By end The shielding start and end numbers of the left and right adjacent winding edges are L(R)Bbp start 、L(R)Bbp end Value:

[0123]

[31] (i) According to the winding partition and Bbp range Size start 、By end Value:

[0124]

[32] Bbp start ≥1,By start The value is the current winding Bbp start The y coordinate of the middle of the pie;

[0125] Bb start <1,By start Value is By 1 +(1-Bbp start )*(By 1 -By 2 ), By 1 is the y coordinate of the middle of the first cake of the current winding, By 2 is the y coordinate of the middle of the second cake of the current winding;

[0126]

[33] Bbp end ≤Bn,By end The value is the current winding Bbp end The y coordinate of the middle of the cake, Bn is the total number of cakes in the current winding;

[0127] Bb end >Bn,By end Value is By Bn +(Bbp end -Bn))*(By Bn -By Bn-1 ), By Bn is the y coordinate of the middle of the Bnth cake of the current winding, By Bn-1 is the y coordinate of the middle of the Bn-1th cake of the current winding;

[0128]

[34] (ii) According to the relative position of the current winding and the adjacent winding and By start 、By end Size is L(R)Bbp start 、L(R)Bbp end Select the L(R)Bbp whose corresponding pie y coordinate satisfies the following conditionsstart 、L(R)Bbp end Pie number:

[0129]

[35] If there exists L(R)Y[n]-By start ≥0, where n∈[1,L(R)Bn], then L(R)n=max{L(R)n|L(R)Y[n]-By start >0},L(R)By start =L(R)Y[n]; otherwise, take L(R)By start =L(R)Y[1].

[0130]

[36] If there exists L(R)Y[n]-By end ≤0, where L(R)n∈[1,L(R)Bn], then L(R)n=min{L(R)n|L(R)Y[n]-By end <0},L(R)By end =L(R)Y[n]; otherwise, take L(R)By end =L(R)Y[L(R)Bn].

[0131]

[37] L(R)Y[n] is the y coordinate of the nth coil of the left / right adjacent winding, and L(R)Bn is the total number of coils of the left / right adjacent winding;

[0132]

[38] 4) Set the simulation conditions for the solution domain of adjacent winding edges:

[0133]

[39] (i) L(R)Bp start to L(R)Bp end The outermost winding terminal of the left / right adjacent winding of the pie facing the current winding is set as a capacitor terminal, and the second outermost winding terminal is set as a shielding terminal;

[0134]

[40] (ii) If there is no L(R)Y[n]-By start ≥0, where n∈[1,L(R)Bn], then the left / right L(R)Bp num (Number of left / right end shield windings, each winding is set up for the first time L(R)Bp num =1, and the value is selected later through relative error control) The first winding terminal of the adjacent winding is set as a capacitor terminal, and the non-charged terminal of the second winding is set as a shielding terminal;

[0135]

[41] (iii) If there is no L(R)Y[n]-By end ≤0, where L(R)n∈[1, L(R)Bn], i.e. the y coordinates of the left / right adjacent windings are both greater than By end , then the left / right L(R)Bsp numThe last winding terminal of each adjacent winding is set as a capacitor terminal, and the non-charged terminal of the next last winding is set as a shielding terminal;

[0136]

[42] Bbp for the current winding edge shielding range range Select the relative error control to ensure that the calculation results of the distributed capacitance between turns, between cakes, and between windings at the edge of the partition meet the relative error requirements:

[0137]

[43] 1) Electrostatic field scanning calculation;

[0138]

[44] 2) Extract the B test The terminal charge of the winding edge (left and right edges, first and last pancakes) in the calculation results of the electrostatic field of the left / right edge scanning terminal. When the current winding is an edge winding, the terminal charge of the grounded part needs to be extracted;

[0139]

[45] 3) Increase Bbp range , Bbp range =Bbp range +k (k is a positive integer);

[0140]

[46] 4) Repeat

[22] to

[45] , compare the extracted charges twice before and after, if the relative error of the terminal charge of the first two orders of magnitude in the current iteration compared with the previous iteration meets the requirements, then end the iteration and take the Bbp used in the current iteration simulation range is the final value;

[0141]

[47] Select the two outermost cakes at one end and the two outermost cakes at the other end from the current winding as the test winding partitions, set all the winding terminals of the outermost cakes at both ends as scanning terminals, set the solution domain simulation conditions, and iterate the finite element simulation to confirm the parameters L(R)Bp required for electric field equivalence num ;

[0142]

[48] Repeat

[12] -

[16] ,

[22] -

[41] to establish the corresponding finite element model;

[0143]

[49] When the shielding range of adjacent winding ends is L(R)Bp num Select the relative error control to ensure that the calculation of the distributed capacitance to the ground outside the partition meets the relative error requirements:

[0144]

[50] 1) Electrostatic field scanning calculation;

[0145]

[51] 2) Extract the terminal charge of the grounded part from the electrostatic field calculation results of the first and last pancake scanning terminals;

[0146]

[52] 3) If L(R)Bp num If the structural limit has been reached, this step will not be performed, otherwise increase L(R)Bp num, L(R)Bp num =L(R)Bp num +k (k is a positive integer);

[0147]

[53] 4) Repeat

[38] -

[41] ,

[50] -

[52] , compare the charges extracted twice before and after, if the relative errors of the terminal charges of the first two orders of magnitude in the current iteration compared with the previous iteration meet the requirements, then end the iteration and take the L(R)Bp used in the current iteration simulation num is the final value;

[0148]

[54] All parameters required for electric field equivalence are determined, the winding is partitioned, and finite element simulation is performed on all winding partitions in turn to obtain the main distributed capacitance of the winding:

[0149]

[55] The current calculation winding (hereinafter referred to as the current winding) is divided into n multi-pie calculation partitions A from top to bottom with pie as the basic unit 1 , A 2 ,……,A n , until all the cakes of the current winding are divided; the number of cakes in each winding partition does not exceed the maximum number of cakes that the computing device can calculate at one time;

[0150]

[56] Bn A1 +Bn A2 +……+Bn An =Bn;

[0151]

[57] Bn A1 , Bn A2 , ..., Bn An The total number of pies corresponding to each partition;

[0152]

[58] Repeat

[12] -

[16] ,

[22] -

[41] to establish corresponding finite element models for different partitions of the current winding, and perform electrostatic field scanning calculations on all of them;

[0153]

[59] Repeat 【5】-

[58] for different windings to complete the distributed capacitance partition calculation;

[0154]

[60] Special treatment is performed when the power equipment structure has Class 2 windings or Class 3 windings:

[0155]

[61] 1) When the current winding or the adjacent winding has Class 2 windings, first merge the upper and lower coils into one coil and process it as Class 1 winding for subsequent processing;

[0156]

[62] 2) When there are Class 3 windings in the current winding and the adjacent winding, the Class 3 windings are regarded as two Class 1 windings, and special settings are made for the winding terminals according to the calculation conditions:

[0157]

[63] (i) When the current winding is the upper / lower winding among the three types of windings, before the scanning calculation, the pancake closest to the current winding in the lower / upper winding is set as a capacitor terminal, and the second closest pancake is set as a shielding terminal; at the same time, before the electrostatic field scanning calculation, the outermost winding non-charged terminal of the pancake whose center y coordinate is within [SY[SBn], XY[1]] in the left / right adjacent winding is set as a capacitor terminal, and the second outermost winding non-charged terminal is set as a shielding terminal (when the adjacent winding edge solution domain simulation condition setting overlaps with the terminal setting area set in this step, the adjacent winding edge solution domain simulation condition setting in the overlapping area is skipped);

[0158]

[64] S(X)Y[n] is the y coordinate of the nth cake of the upper / lower winding in the three types of windings, and S(X)Bn is the total number of cakes of the upper / lower winding;

[0159]

[65] (ii) When the adjacent windings are of Class 3, the upper / lower windings are selected for shielding parameter relative error control in turn, and the larger value of the two results of the same type of parameter is selected as the final value; subsequently, when setting the solution domain simulation conditions for the edge of the current winding and the edge of the adjacent winding, the two windings are set in turn;

[0160]

[66] Finally, the distributed capacitance value is extracted:

[0161]

[67] In the equivalent electric field of the winding, the potential of the scanning terminal is set to 1V during the scanning calculation, and the potential of other terminals is set to 0V.

[0162]

[68] C=Q / U

[0163]

[69] It can be seen that there is no distributed capacitance between other terminals, and the charge value on other terminals is the distributed capacitance value between the scanning terminal and other terminals;

[0164]

[70] By extracting the other terminal charge values ​​in the scan calculation results, all the main distributed capacitance values ​​that meet the relative error requirements can be obtained.

[0165] The present invention also provides a system for implementing the detection method provided in the above embodiment, comprising:

[0166] Winding distributed capacitance calculation module: used to calculate the distributed capacitance of any winding in the pre-established geometric model of the power equipment, including:

[0167] Shielding range calculation module: used to calculate the internal shielding range, edge shielding range and end shielding range of any one of the windings;

[0168] Winding partitioning module: used to divide any one winding into a plurality of winding partitions in units of pancakes;

[0169] Winding partition distributed capacitance calculation module: used to perform finite element simulation on the plurality of winding partitions according to the internal shielding range, the edge shielding range and the end shielding range, so as to obtain the distributed capacitance of each winding partition;

[0170] A first combining module: used for combining the distributed capacitances of each winding to obtain the distributed capacitance of any winding in the pre-established geometric model of the power equipment;

[0171] The second combination module is used to combine the distributed capacitances of all windings in the geometric model of the power equipment to obtain the distributed capacitance of the power equipment.

[0172] It can be seen from the above solution of the present invention that the present invention solves the problem in the prior art that large-scale distributed capacitor terminals (usually capacitor terminals with an order of magnitude of 10 3 And above) to obtain all the main distributed capacitance (involving inter-turn distributed capacitance, inter-cake distributed capacitance, inter-winding distributed capacitance, and outer side of winding to ground distributed capacitance) to obtain large-scale main distributed capacitance with controllable relative error. Using the large-scale main distributed capacitance partition calculation method of winding, the winding can be divided into multiple parts for multiple overall model finite element simulation calculations to obtain all the main distributed capacitance values ​​that meet the relative error requirements.

Claims

1. A distributed capacitance detection method for power equipment, characterized in that: include: Calculate the distributed capacitance of any winding in a pre-built geometric model of a power plant, including: Calculating the inner shielding range, the edge shielding range and the end shielding range of any one of the windings; Divide any one of the windings into a plurality of winding partitions based on the unit of cake; According to the internal shielding range, the edge shielding range and the end shielding range, finite element simulation is performed on the plurality of winding partitions to obtain the distributed capacitance of each winding partition; Combining the distributed capacitances of each winding to obtain the distributed capacitance of any winding in the pre-established geometric model of the power equipment; The distributed capacitance of all windings in the geometric model of the power equipment is combined to obtain the distributed capacitance of the power equipment.

2. A distributed capacitance detection method for electric power equipment according to claim 1, characterized in that: The process of calculating the inner shielding range, the edge shielding range and the end shielding range of any one of the windings includes: Selecting a first test winding partition from the current winding; In the geometric model of the power equipment, all winding terminals in the middle of the first test winding partition are set as the first test winding partition scanning terminals, and the solution domain simulation conditions of the current winding partition are set according to the first test winding partition scanning terminals to obtain the first simulation conditions; Iteratively adjusting the initially preset internal shielding range of the current winding under the first simulation condition, performing electrostatic field scanning calculation on the first test winding partitions, and obtaining the internal shielding range of the current winding; According to the first simulation condition and the internal shielding range of the current winding, the current winding edge solution domain simulation condition and the adjacent winding edge solution domain simulation condition are set in the geometric model of the power equipment to obtain the second simulation condition; Iteratively adjust the initially preset edge shielding range of the current winding under the second simulation condition, perform electrostatic field scanning calculation on the first test winding partition, and obtain the edge shielding range of the current winding; Selecting a second test winding partition from the current winding; In the geometric model of the electric power equipment, all the winding terminals of the outermost cakes of both side ends of the current winding in the second winding partition are set as the second test winding partition scanning terminals, and the first simulation condition of the second test winding partition within the internal shielding range is set according to the second test winding scanning terminal and the internal shielding range of the current winding, and the second simulation condition of the second test winding partition within the edge shielding range is set according to the first simulation condition and the edge shielding range of the current winding, so as to obtain the third simulation condition; Under the third simulation condition, the preset initial end shielding range of the current winding is iteratively adjusted, and the electrostatic field scanning calculation is performed on the geometric model of the power equipment to obtain the end shielding range of the current winding.

3. A distributed capacitance detection method for electric power equipment according to claim 2, characterized in that: For Class 2 windings, the upper and lower coils of the Class 2 windings are combined into one coil and used as Class 1 windings; For Class 3 windings, the Class 3 windings are considered as two Class 1 windings; For a Class 1 winding, select the current winding and three pieces of the middle positions of the adjacent windings on both sides of the winding as the first test winding partition; when the adjacent winding is a Class 3 winding, the upper winding and the lower winding of the adjacent winding are regarded as two adjacent Class 1 windings on the same side, select the current winding and the middle positions of different opposite intervals of the adjacent Class 1 windings on both sides of the winding, and select two first test winding partitions; For Class 1 windings, select the two outermost discs at one end of the current winding and the two outermost discs at the other end as the second test winding partition; The Class 1 winding is a single-phase winding with only one coil, the Class 2 winding is a single-phase non-voltage-regulating winding with two coils connected in parallel up and down and a wire coming out of the middle; the Class 3 winding is a single-phase voltage-regulating winding with two coils connected in parallel up and down and a wire coming out of the middle; For a Class 1 winding, when the adjacent winding is a Class 3 winding, in the process of calculating the internal shielding range and the edge shielding range, two internal shielding ranges and two edge shielding ranges are obtained, and the larger value of the two internal shielding ranges and the two edge shielding ranges is selected as the final value of the internal shielding range and the edge shielding range of the current winding.

4. A distributed capacitance detection method for electric power equipment according to claim 3, characterized in that: The pie numbers in the winding increase from 1 from the top to the bottom; The process of setting the solution domain simulation condition of the current winding partition according to the first test winding partition scanning terminal and obtaining the first simulation condition includes: Set all winding terminals in the first test winding zone as scanning terminals; Divide the first test winding into upper and lower Bs start -1 Creampie and Bs end +1 All winding terminals are set as capacitor terminals, among which, the upper Bs start -1 pie is recorded as Bc start Cake, next Bs end +1 pie is recorded as Bc end Pie, then there is the following relationship: Bc start =Bs start -1 Bc end =Bs end +1 If there is no cake that meets the above relationship requirements, no capacitor terminal is set; among them, Bs start Pie is the number of the topmost pie in the first test winding partition, Bs end Pie is the number of the lowest pie of the winding in the first test winding partition; The first test winding partition Bc start -1 to Bc start -Bp range , next Bc end +1 to Bc end +Bp range The left and right edge winding terminals are set as capacitor terminals, and the remaining winding terminals are set as shield terminals. start To Bp end Pie, then there is the following relationship: Bp start =Bc start -Bp range Bp end =Bc end +Bp range If there is no cake that meets the above relationship requirements, it is not necessary to set the capacitor terminal and the shielding terminal; among them, Bp range The shielding range of the current winding. When each winding is set for the first time, Bp range =1, and the value is selected through relative error control later.

5. A distributed capacitance detection method for electric power equipment according to claim 4, characterized in that: The process of iteratively adjusting the initially preset internal shielding range of the current winding under the first simulation condition, performing electrostatic field scanning calculation on the first test winding partition, and obtaining the internal shielding range of the current winding includes: Fine meshing is performed on the scanning terminal, capacitor terminal, shielding terminal area and adjacent areas, and coarse meshing is performed on the remaining areas; all scanning terminals are set to 1V and the remaining terminals are set to 0V for electrostatic field calculation; When the current winding is the upper and lower windings among the three types of windings, before each electrostatic field scanning calculation, the cake closest to the current winding in the lower and upper windings is set as a capacitor terminal, and the next closest cake is set as a shielding terminal; before each electrostatic field scanning calculation, the cakes with the y coordinates of the centers of the cakes in the left and right adjacent windings within the range of the y coordinates of the centers of the last cakes of the upper winding among the three types of windings to the y coordinates of the centers of the first cakes of the lower winding among the three types of windings, the outermost winding non-charged terminal is set as a capacitor terminal, and the second outer winding non-charged terminal is set as a shielding terminal; Extract the first two orders of magnitude of inter-turn and inter-pancake terminal charges from the calculation results of the electrostatic field of the middle scanning terminal of the current winding and the adjacent windings on both sides in the middle of the interval facing each other as the first terminal charge; Iteratively adjust Bp range , until the relative error between the first terminal charge of the current iteration and the first terminal charge of the previous iteration meets the preset first error requirement: increase the internal shielding range according to the preset first step length; the first step length is an integer; under the condition of the increased internal shielding range, perform electrostatic field scanning calculation on the first test winding partition to obtain the first terminal charge of the current iteration; calculate the first difference between the first terminal charge of the current iteration and the first terminal charge of the previous iteration, if the first difference meets the preset first error requirement, end the iteration, otherwise continue the iteration; The internal shielding range of the current iteration is used as the internal shielding range of the current winding.

6. A distributed capacitance detection method for electric power equipment according to claim 4, characterized in that: According to the first simulation condition and the internal shielding range of the current winding, the current winding edge solution domain simulation condition and the adjacent winding edge solution domain simulation condition are set in the geometric model of the power equipment, and the process of obtaining the second simulation condition includes: Shield the start and end numbers of the current winding edge Bbp start , Bbp end Value: Let Bbp start =Bp start -Bbp range , Bbp end =Bp end +Bbp range , among which, Bbp range The current winding edge shielding range, each winding is set for the first time Bbp range =1, and the value is selected through relative error control later; Set the simulation conditions for the solution domain of the current winding edge: when Bbp start ≥2, when there is a winding edge setting cake above the current winding partition, Bbp start To Bp start -1 The outermost winding terminal of the cake is set as a capacitor terminal, and the second outer winding terminal is set as a shielding terminal; Bp end ≤Bn-1, when there is a winding edge setting cake under the current winding partition, Bp end +1 to Bp end The outermost winding terminal of the cake is set as the capacitor terminal, and the second outer winding terminal is set as the shielding terminal; Bn is the total number of winding cakes at present; According to the current winding edge shielding range Bbp range Corresponding to the upper and lower boundaries of the required shielding range y coordinates By start 、By end The shielding start and end numbers of the left and right adjacent winding edges are L(R)Bbp start 、L(R)Bbp end The value includes: (i) According to the winding partition and Bbp range Size start 、By end Value: Bb start ≥1,By start The value is the current winding Bbp start The y coordinate of the middle of the pie; Bb start <1,By start The value is By1+(1-Bbp start )*(By1-By2), By1 is the y coordinate of the middle of the first cake of the current winding, By2 is the y coordinate of the middle of the second cake of the current winding; Bb end ≤Bn,By end The value is the current winding Bbp end The y coordinate of the middle of the cake, Bn is the total number of cakes in the current winding; Bb end >Bn,By end Value is By Bn +(Bbp end -Bn))*(By Bn -By Bn-1 ), By Bn is the y coordinate of the middle of the Bnth cake of the current winding, By Bn-1 is the y coordinate of the middle of the Bn-1th cake of the current winding; (ii) According to the relative position of the current winding and the adjacent winding and By start 、By end Size is L(R)Bbp start 、L(R)Bbp end Select the value and select the L(R)Bbp whose corresponding pie y coordinate satisfies the following conditions start 、L(R)Bbp end Pie number: If there are adjacent windings on the left and right sides, start The pie on the top is L(R)Bbp. start The left and right adjacent winding distance By start The pie number of the nearest pie; if it does not exist, take L(R)Bbp start is 1; If there are adjacent windings on the left and right sides, end下 pie, then take L(R)Bbp end The left and right adjacent winding distance By end The pie number of the nearest pie; if it does not exist, take L(R)Bbp start L(R)Bn is the total number of adjacent windings on the left and right. The simulation conditions for the solution domain are set for the edges of adjacent windings: L(R)Bp start to L(R)Bp end The outermost winding terminal of the adjacent windings on the left and right sides of the pie facing the current winding is set as a capacitor terminal, and the second outermost winding terminal is set as a shielding terminal; if there is no L(R)Y[n]-By start ≥0, where n∈[1, L(R)Bn], i.e. the y coordinates of the left / right adjacent windings are all less than By start , then the left and right L(R)Bp num The first winding terminal of the adjacent winding is set as a capacitor terminal, and the second winding non-charged terminal is set as a shielding terminal; if there is no L(R)Y[n]-By end ≤0, where L(R)n∈[1, L(R)Bn], i.e. the y coordinates of the left / right adjacent windings are both greater than By end , then the left / right L(R)Bsp num The last winding terminal of each adjacent winding is set as a capacitor terminal, and the non-charged terminal of the next last winding is set as a shielding terminal; When the adjacent winding edge solution domain simulation condition setting area overlaps with the simulation condition setting area before the electrostatic field scanning calculation when the current winding is an upper / lower winding in the three types of windings, the adjacent winding edge solution domain simulation condition setting in the overlapping area is skipped; When the adjacent windings are Class 3 windings, the upper and lower windings of the adjacent windings are regarded as two adjacent Class 1 windings on the same side. When setting the current winding edge solution domain simulation conditions and the adjacent winding edge solution domain simulation conditions, the two adjacent Class 1 windings on the same side sequentially set the current winding edge and adjacent winding edge solution domain simulation conditions.

7. A distributed capacitance detection method for electric power equipment according to claim 6, characterized in that: The process of iteratively adjusting the initially preset edge shielding range of the current winding under the second simulation condition, performing electrostatic field scanning calculation on the first test winding partition, and obtaining the edge shielding range of the current winding includes: Perform electrostatic field scanning calculation on the first test winding partition; Extract B test The first two orders of magnitude of the winding edge terminal and the grounded part terminal charge in the electrostatic field calculation results of the left and right edges of the cake are used as the second terminal charge; Iteratively adjust Bbp range , until the relative error between the second terminal charge of the current iteration and the second terminal charge of the previous iteration meets the preset second error requirement: increase the edge shielding range according to a preset second step length; the second step length is an integer; under the condition of the increased edge shielding range, perform electrostatic field scanning calculation on the second test winding partition to obtain the second terminal charge of the current iteration; calculate the second difference between the second terminal charge of the current iteration and the second terminal charge of the previous iteration, and if the second difference meets the preset second error requirement, end the iteration; The edge shielding range of the current iteration is used as the edge shielding range of the current winding.

8. A distributed capacitance detection method for electric power equipment according to claim 6, characterized in that: The process of iteratively adjusting the preset initial end shielding range of the current winding under the third simulation condition, performing electrostatic field scanning calculation on the geometric model of the power equipment, and obtaining the end shielding range of the current winding includes: Perform electrostatic field scanning calculation on the second test winding partition; Extracting the grounded terminal charge from the terminal electrostatic field calculation result of the two side ends of the current winding as the third terminal charge; Iterative adjustment of L(R)Bp num , until the relative error between the third terminal charge of the current iteration and the previous iteration meets the preset third error requirement: increase the end shielding range according to the preset third step length; the third step length is an integer; if L(R)Bp num If the structural limit has been reached, the iteration is terminated; under the condition of the increased end shielding range, the electrostatic field scanning calculation is performed on the second test winding partition to obtain the third terminal charge of the current iteration; the third difference between the third terminal charge of the current iteration and the third terminal charge of the previous iteration is calculated, and if the third difference meets the preset third error requirement, the iteration is terminated; The end shielding range of the current iteration is used as the edge shielding range of the current winding.

9. A distributed capacitance detection method for electric power equipment according to claim 6, characterized in that: According to the internal shielding range, the edge shielding range and the end shielding range, the finite element simulation is performed on the plurality of winding zones respectively to obtain the distributed capacitance of each winding zone, which includes: The current winding is divided into n multi-cake calculation partitions A1, A2, ..., A from top to bottom with cake as the basic unit. n , until all the pies of the current winding are divided; that is, Bn A1 +Bn A2 +……+Bn An =Bn;Bn A1 , Bn A2 , ..., Bn An The total number of pies corresponding to each partition; the number of pies in each winding partition shall not exceed the maximum number of pies that the computing device can calculate at one time; According to the internal shielding range, setting a first simulation condition for each of the winding partitions within the internal shielding range; According to the edge shielding range and the end shielding range, setting a second simulation condition for partitioning each winding into the edge shielding range; According to the simulation conditions within the internal shielding range and the simulation conditions within the edge shielding range and the end shielding range, electrostatic field scanning calculations are performed on all the winding partitions in turn to obtain the distributed capacitance of the current winding.

10. A distributed capacitance detection system for electric power equipment, used to implement the distributed capacitance detection method for electric power equipment according to any one of claims 1 to 9, characterized in that: include: Winding distributed capacitance calculation module: used to calculate the distributed capacitance of any winding in the pre-established geometric model of the power equipment, including: Shielding range calculation module: used to calculate the internal shielding range, edge shielding range and end shielding range of any one of the windings; Winding partitioning module: used to divide any one winding into a plurality of winding partitions in units of pancakes; Winding partition distributed capacitance calculation module: used to perform finite element simulation on the plurality of winding partitions according to the internal shielding range, the edge shielding range and the end shielding range, so as to obtain the distributed capacitance of each winding partition; A first combining module: used for combining the distributed capacitances of each winding to obtain the distributed capacitance of any winding in the pre-established geometric model of the power equipment; The second combination module is used to combine the distributed capacitances of all windings in the geometric model of the power equipment to obtain the distributed capacitance of the power equipment.

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