A power amplifier design method, a power amplifier

Abstract

This invention relates to a power amplifier design method and a power amplifier. The power amplifier design method includes the following steps: performing load pull simulation on the target power amplifier to obtain the input and output impedances of the transistors; designing a bias circuit; designing an input matching network and an output matching network based on the input and output impedances of the transistors; optimizing the input and output matching networks using small-signal S-parameter simulation to obtain optimized input and output matching networks; and substituting the optimized input and output matching networks into the input and output terminals of the transistors to obtain the circuit structure of the target power amplifier. This invention obtains ideal large-signal simulation results for the power amplifier simply by optimizing the input and output matching networks using small-signal S-parameters, greatly improving the design efficiency of the power amplifier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a power amplifier design method and a power amplifier. Background Technology

[0002] In recent years, GaN HEMT-based MMIC technology has developed rapidly and is widely used in active phased array radar components. In active phased array radar, the power amplifier is a fundamental component. With technological advancements, the requirements for the power and efficiency of power amplifiers are constantly increasing. Therefore, developing microwave RF power amplifiers with high output power and high efficiency has become one of the core technologies in modern microwave circuit design.

[0003] ADS software provides a powerful tool for RF and microwave circuit design. Currently, using ADS software for harmonic balance simulation optimization in MMIC chip design has replaced manual design and calculation work, greatly improving chip design efficiency. However, as power amplifier chip area continues to increase, output power continues to rise, and frequency bands gradually widen, the time required for harmonic balance simulation will continue to increase. Therefore, the method of optimizing power amplifier chip performance through harmonic balance simulation is no longer sufficient to meet design requirements, and a more time-saving power amplifier design optimization method is urgently needed. Summary of the Invention

[0004] Based on this, and addressing the problem that current methods for optimizing power amplifier chip performance through harmonic balance simulation are insufficient to meet design requirements, the present invention aims to provide a power amplifier design method and a power amplifier. This power amplifier design method extracts the optimal input and output impedance of the transistor through LoadPull simulation, and then optimizes the optimal input and output matching network of the transistor through small-signal S-parameter simulation, thus eliminating the need for harmonic balance simulation optimization and improving design efficiency.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] This invention provides a power amplifier design method, which includes the following steps:

[0007] S1. Perform Load Pull simulation on the target power amplifier to obtain the optimal input impedance and optimal output impedance of the transistor;

[0008] S2. Design the bias circuit;

[0009] S3. Design the input matching network and the output matching network according to the optimal input impedance and optimal output impedance of the transistor, respectively;

[0010] S4. Optimize the input matching network and output matching network using small-signal S-parameter simulation to obtain the optimized input matching network and optimized output matching network;

[0011] S5. The optimized input matching network and the optimized output matching network are respectively fed into the input and output terminals of the transistor to obtain the circuit structure of the target power amplifier.

[0012] Preferably, in step S1, the target frequency of the target power amplifier is the Ku band, the transistor is a 0.15μm GaN HEMT field-effect transistor, and the DC operating point of the transistor is V. ds =28V、V gs =-2.4V.

[0013] Preferably, in step S2, the design of the bias circuit includes the following steps: according to the DC operating point requirements of the transistor, the D terminal of the transistor is connected to a 28V power supply, the G terminal is connected to a -2.4V power supply, an ideal DC blocking capacitor (DC_Block) is added between the DC and AC paths of the transistor to block the DC power supply network, and an ideal choke inductor (DC_Feed) is added to the DC path of the transistor to obtain the bias circuit.

[0014] Preferably, in step S3, the input matching network and output matching network are designed using DA_SmithChartMatch in ADS software.

[0015] Preferably, in step S3, the design of the input matching network and the output matching network based on the optimal input impedance and optimal output impedance of the transistor obtained in step S1 includes: setting the load impedance of the input matching circuit to the optimal input impedance of the transistor obtained in step S1, and setting the source impedance of the output matching circuit to the optimal output impedance of the transistor obtained in step S1, thereby obtaining the input matching network and the output matching network.

[0016] Preferably, in step S4, the optimization of the input matching network and output matching network designed in step S3 using small-signal S-parameter simulation includes:

[0017] The impedance in the Term component is set to the optimal input impedance and optimal output impedance of the transistor, resulting in the transistor input impedance Term component and transistor output impedance Term component with impedance varying with frequency. The transistor input impedance Term component and transistor output impedance Term component are used to optimize the input matching network and output matching network obtained in step S3, respectively, to obtain the optimized input matching network and optimized output matching network.

[0018] Preferably, in step S5, after obtaining the circuit structure of the target power amplifier, the design method further includes: performing simulation verification on the target power amplifier.

[0019] The present invention provides a power amplifier designed using the power amplifier design method described above.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] This invention extracts the optimal input and output impedances of transistors through LoadPull simulation, and then obtains the optimal input and output matching networks of transistors through small-signal S-parameter simulation optimization. This eliminates the need for harmonic balance simulation optimization and allows for the acquisition of ideal large-signal simulation results for power amplifiers simply by optimizing the input and output matching networks through small-signal S-parameters, greatly improving the design efficiency of power amplifiers. Attached Figure Description

[0022] Figure 1 This is a flowchart of the power amplifier design method in an embodiment of the present invention;

[0023] Figure 2 These are the optimal input and load impedance points for the transistors at each frequency point in the embodiments of the present invention;

[0024] Figure 3 This is a schematic diagram of the bias circuit in an embodiment of the present invention;

[0025] Figure 4 This is the input matching circle chart in this embodiment of the invention;

[0026] Figure 5 This is the output matching circle chart in the embodiments of the present invention;

[0027] Figure 6 This is a schematic diagram showing the transistor input / output impedance Term component configuration in an embodiment of the present invention.

[0028] Figure 7 This is a schematic diagram of the input matching network optimization principle in an embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of the output matching network optimization principle in an embodiment of the present invention;

[0030] Figure 9 This is a circuit diagram of the power amplifier in an embodiment of the present invention;

[0031] Figure 10 for Figure 9 Simulated saturated output power and efficiency curves;

[0032] Figure 11This is a graph showing the saturated output power and efficiency obtained through harmonic balance simulation in an embodiment of the present invention. Detailed Implementation

[0033] To facilitate understanding of the present invention, a more comprehensive description will be given below with reference to specific embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of the present invention.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0035] This embodiment addresses the problem that current methods for optimizing power amplifier chip performance through harmonic balance simulation are insufficient to meet design requirements. This embodiment provides a power amplifier design method.

[0036] Reference Figure 1 The purpose of this invention is to provide a power amplifier design method comprising the following steps:

[0037] S1. Perform a load pull simulation on the target power amplifier to obtain the optimal input impedance and optimal output impedance of the transistor.

[0038] The power amplifier designed in this embodiment targets the Ku band frequency and uses 0.15µm GaN HEMT field-effect transistors with a DC operating point of V. ds =28V、V gs =-2.4V. Using Load Pull simulation in ADS software, the optimal input and load impedance points of the transistors at each frequency were obtained after considering both maximum power and maximum efficiency, such as... Figure 2 As shown.

[0039] The simulation results show that the input impedance and output impedance of the transistor at various frequencies in the 14-18GHz band are shown in Table 1.

[0040] Table 1 Input and output impedances of transistors at various frequencies

[0041] Input impedance (Ohm) Output impedance (Ohm) 14GHz 2.98-j*4.82 25.612-j*44.793 15GHz 2.85-j*4.25 24.050-j*42.061 16GHz 2.73-j*3.69 22.492-j*39.547 17GHz 2.52-j*3.14 18.342-j*37.790 18GHz 2.45-j*2.65 17.013-j*35.741

[0042] S2. Design the bias circuit.

[0043] Based on the transistor's DC operating point requirements, the drain (D) terminal of the transistor model is connected to a 28V power supply, and the gate (G) terminal is connected to a -2.4V power supply. Simultaneously, an ideal DC-blocking capacitor (DC_Block) is added between the transistor's DC and AC paths to block the DC power supply network. An ideal choke inductor (DC_Feed) is added to the transistor's DC path to prevent high-frequency signals from entering the DC power supply network and affecting signal transmission. This results in... Figure 3 The bias circuit shown.

[0044] S3. Design the input matching network and output matching network according to the optimal input impedance and optimal output impedance of the transistor, respectively.

[0045] The input matching network and output matching network are designed using DA_SmithChartMatch in ADS software.

[0046] Taking matching at 16GHz as an example: To match the conjugate impedance of the optimal source impedance to 50 Ohms, the load impedance of the input matching circuit is set to the transistor's input impedance of 2.73 - j * 3.69 Ohms, resulting in the following... Figure 4 The input matching circle diagram is shown below; similarly, to match the conjugate impedance of the optimal load impedance to 50 Ohms, the source impedance of the output matching circuit is set to the transistor's output impedance of 22.492 - j * 39.547 Ohms, resulting in the following... Figure 5 The output matching circle chart is shown.

[0047] S4. Optimize the input matching network and output matching network using small-signal S-parameter simulation to obtain the optimized input matching network and optimized output matching network.

[0048] First, set the impedance in the Term component to the optimal input and output impedances of the transistor. By using the DAC control and an MDF file containing the input and output impedances, different impedance values ​​can be assigned to different frequency points. Finally, set the Z value in the Term component to a reference to the DAC. This will give you the transistor input impedance Term component and the transistor output impedance Term component, whose settings are as follows: Figure 6 As shown.

[0049] Substitute the input matching network obtained in step S3 into... Figure 7 The diagram shows the principle of input matching network optimization. The optimization targets are set as "dB(S(1,1)<-25", "dB(S(2,2)<-25", "dB(S(2,1)>-0.02", resulting in an optimized output matching network. Similarly, the output matching network obtained in step S3 is substituted into the following... Figure 8The diagram shows the principle of output matching network optimization. The optimization targets are set as "dB(S(1,1)<-25", "dB(S(2,2)<-25", "dB(S(2,1)>-0.02", resulting in the optimized output matching network.

[0050] S5. Substitute the optimized input matching network and the optimized output matching network into the input and output terminals of the transistor, respectively, to obtain the circuit structure of the target power amplifier.

[0051] By substituting the optimized input matching network and the optimized output matching network into the input and output terminals of the transistor, respectively, we can obtain the following results: Figure 9 The circuit schematic of the power amplifier with input and output matching networks optimized for small-signal S-parameters is shown below. Its simulation results are as follows: Figure 10 As shown.

[0052] Traditional methods for optimizing large-signal simulation results of power amplifiers require setting the harmonic balance simulation results as the optimization target. For comparison, the input matching network and output matching network generated by the Smith chart tool in step S3 are added to the input and output terminals of the transistor, respectively. Combined with harmonic balance simulation, the results can be obtained... Figure 11 The curves showing saturated output power and efficiency are shown.

[0053] Depend on Figure 11 As the curves show, the matching network generated using the Smith chart tool only achieves good matching results at the 16GHz frequency point; the efficiency at other frequency points does not reach the ideal level. Further optimization is needed to achieve high efficiency at all frequency points within the band. Figure 10 and Figure 11 The simulation results show that the power amplifier designed in this embodiment achieves a 0.5 dB increase in typical output power in the 14-18 GHz frequency band, with a maximum efficiency improvement of 13%. The simulation results demonstrate that the power amplifier designed in this embodiment does not require harmonic balance simulation optimization; a more ideal saturated output power and efficiency can be obtained simply through small-signal S-parameter simulation of the matching network. Compared to the small-signal S-parameter simulation in this embodiment, traditional harmonic balance simulation requires more time, and the simulation speed decreases as the power amplifier size and bandwidth increase. Therefore, optimizing the input and output networks through small-signal S-parameter simulation can reduce the simulation time.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A power amplifier design method, characterized in that, It includes the following steps: S1. Perform Load Pull simulation on the target power amplifier to obtain the optimal input impedance and optimal output impedance of the transistor; S2. Design the bias circuit; S3. Design the input matching network and the output matching network according to the optimal input impedance and the optimal output impedance of the transistor respectively; set the load impedance of the input matching circuit to the optimal input impedance of the transistor obtained in step S1, and set the source impedance of the output matching circuit to the optimal output impedance of the transistor obtained in step S1 to obtain the input matching network and the output matching network. S4. Optimize the input matching network and output matching network using small-signal S-parameter simulation to obtain the optimized input matching network and optimized output matching network; The impedance in the Term component is set to the optimal input impedance and optimal output impedance of the transistor to obtain the transistor input impedance Term component and transistor output impedance Term component with impedance changing with frequency. The transistor input impedance Term component and transistor output impedance Term component are used to optimize the input matching network and output matching network obtained in step S3, respectively, to obtain the optimized input matching network and optimized output matching network. S5. The optimized input matching network and the optimized output matching network are respectively fed into the input and output terminals of the transistor to obtain the circuit structure of the target power amplifier.

2. The power amplifier design method according to claim 1, characterized in that, In step S1, the target frequency of the target power amplifier is the Ku band, the transistor is a 0.15μm GaN HEMT field-effect transistor, and the DC operating point of the transistor is V. ds =28V、V gs =-2.4V.

3. The power amplifier design method according to claim 2, characterized in that, In step S2, the design of the bias circuit includes the following steps: according to the DC operating point requirements of the transistor, connect the D terminal of the transistor to a 28V power supply and the G terminal to a -2.4V power supply; add a DC_Block ideal DC blocking capacitor between the DC and AC paths of the transistor to block the DC power supply network; and add a DC_Feed ideal choke inductor to the DC path of the transistor to obtain the bias circuit.

4. The power amplifier design method according to claim 1, characterized in that, In step S3, the input matching network and output matching network are designed using DA_SmithChartMatch in the ADS software.

5. The power amplifier design method according to claim 1, characterized in that, In step S5, after obtaining the circuit structure of the target power amplifier, the design method further includes: performing simulation verification on the target power amplifier.

6. A power amplifier, characterized in that, It is designed using the power amplifier design method as described in any one of claims 1-5.

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