Display panel, driving method thereof and display device

Abstract

The application relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device. The display panel comprises a gate driving circuit, a compensation circuit, a compensation signal line and two power signal lines. The gate driving circuit is connected with the two power signal lines respectively, and is used for outputting a gate driving signal according to two power signals provided by the two power signal lines respectively. The compensation circuit is connected with the compensation signal line and a target power signal line respectively, and is used for selecting to turn on a pass between the compensation signal line and the target power signal line. The target power signal line is one of the two power signal lines, and the absolute value of a compensation signal provided by the compensation signal line is greater than the absolute value of a target power signal provided by the target power signal line. The application can output a flat and burr-free gate driving signal, so as to improve the display effect.

Description

Display panel, driving method thereof, and display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, its driving method, and a display device. Background Technology

[0002] The display panel includes a gate drive circuit to provide gate drive signals to the pixel circuits, controlling the pixel circuits to drive line by line. In existing technology, the gate drive signals output by the gate drive circuit exhibit abnormal waveforms, causing malfunctions in the pixel circuits and consequently resulting in poor display quality. Summary of the Invention

[0003] Therefore, it is necessary to provide a display panel, its driving method, and a display device that can output a flat, burr-free gate driving signal to improve the display effect, in order to address the above-mentioned technical problems.

[0004] In a first aspect, embodiments of this application provide a display panel, including a gate driving circuit, a compensation circuit, a compensation signal line, and two power signal lines, wherein...

[0005] The gate driving circuit is connected to the two power signal lines respectively, and the gate driving circuit is used to output a gate driving signal according to the two power signals provided by the two power signal lines respectively.

[0006] The compensation circuit is connected to the compensation signal line and the target power signal line respectively. The compensation circuit is used to select and conduct the path between the compensation signal line and the target power signal line. The target power signal line is one of the two power signal lines. The absolute value of the compensation signal provided by the compensation signal line is greater than the absolute value of the target power signal provided by the target power signal line.

[0007] In one embodiment, the two power signal lines include a first power signal line and a second power signal line, wherein a first power signal provided by the first power signal line is greater than a second power signal provided by the second power signal line, and the gate driving circuit is used to connect to the target transistor of the pixel circuit.

[0008] The target transistor is an N-type transistor, and the target power signal line is the first power signal line; or...

[0009] The target transistor is a P-type transistor, and the target power signal line is the second power signal line.

[0010] In one embodiment, the display panel further includes a first control signal line, and the compensation circuit includes at least one first compensation module, the first compensation module including a storage unit, a first gating unit, and a second gating unit, wherein...

[0011] In the same first compensation module, the first gating unit is connected to the first control signal line, the compensation signal line, and the first end of the storage unit respectively. The first gating unit receives the first control signal provided by the first control signal line. The first gating unit is used to select and connect the path between the compensation signal line and the first end of the storage unit.

[0012] The second end of the storage unit receives a reference signal;

[0013] In the same first compensation module, the second gating unit is connected to the first end of the storage unit, the target power signal line, and the output end of the gate drive circuit, respectively. The second gating unit receives the gate drive signal and is used to select and conduct the path between the first end of the storage unit and the target power signal line.

[0014] In one embodiment, the effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal.

[0015] In one embodiment, the first end of the storage unit is used to store the compensation signal when the first gating unit is in the on state;

[0016] The second gating unit responds to a valid pulse of the gate drive signal by applying the compensation signal stored at the first end of the memory cell to the target power signal line.

[0017] In one embodiment, the gate driving circuit is used to connect to the pixel circuit, the display panel further includes two pixel power signal lines and an initialization signal line, the pixel circuit is connected to the two pixel power signal lines and the initialization signal line respectively, and the second end of the storage unit is connected to any one of the two pixel power signal lines and the initialization signal line.

[0018] In one embodiment, the display panel further includes at least one of a ground signal line and an external power signal line, and the second end of the storage unit is connected to either the ground signal line or the external power signal line.

[0019] In one embodiment, the first gating unit includes a first transistor, the first terminal of the first transistor is connected to the compensation signal line, the second terminal of the first transistor is connected to the first end of the memory cell of the same first compensation module, and the gate of the first transistor is connected to the first control signal line.

[0020] In one embodiment, the first transistor includes a P-type transistor or an N-type transistor.

[0021] In one embodiment, the second gating unit includes a second transistor, the first terminal of the second transistor is connected to the first terminal of the storage cell of the same first compensation module, the second terminal of the second transistor is connected to the target power signal line, and the gate of the second transistor is connected to the output terminal of the gate driving circuit.

[0022] In one embodiment, the gate driving circuit is used to connect to a target transistor of the pixel circuit, the second transistor being of the same type as the target transistor.

[0023] In one embodiment, the storage unit includes a capacitor, the first terminal of which is connected to the first gating unit and the second gating unit of the same first compensation module, respectively, and the second terminal of which is used to receive the reference signal.

[0024] In one embodiment, the gate driving circuit includes a plurality of cascaded gate driving units, and the compensation circuit includes a plurality of first compensation modules, wherein the output terminal of the i-th gate driving unit is connected to the second gating unit of the i-th first compensation module, i≥1.

[0025] In one embodiment, the second gating unit of the i-th first compensation module responds to the effective pulse of the gate drive signal output by the i-th gate drive unit and applies the compensation signal stored at the first end of the storage unit of the i-th first compensation module to the target power signal line.

[0026] In one embodiment, the gate driving units are arranged in columns, and the first compensation module is arranged in columns.

[0027] In one embodiment, the i-th first compensation module is arranged in the same row as the i-th stage gate drive unit.

[0028] In one embodiment, the i-th first compensation module is arranged in the same row as the (i+1)-th stage gate drive unit.

[0029] In one embodiment, the display panel further includes a second control signal line, and the compensation circuit includes at least one second compensation module. The second compensation module includes a third gating unit, which is connected to the second control signal line, the compensation signal line, and the target power signal line respectively. The third gating unit receives a second control signal provided by the second control signal line and is used to select and connect the path between the compensation signal line and the target power signal line.

[0030] In one embodiment, the third gating unit applies the compensation signal to the target power signal line in response to a valid pulse of the second control signal; wherein the start time of at least one valid pulse of the second control signal is the same as the start time of a valid pulse of the gate drive signal.

[0031] In one embodiment, the gate driving circuit is further configured with a clock signal line, the gate driving circuit is connected to the clock signal line, and the gate driving circuit is used to output the gate driving signal according to the two power supply signals and the clock signal provided by the clock signal line, wherein the frequency of the second control signal is the same as the frequency of the clock signal.

[0032] In one embodiment, the gate driving circuit includes a plurality of cascaded gate driving units, and the compensation circuit includes a plurality of second compensation modules, wherein the number of the gate driving units is greater than or equal to the number of the second compensation modules.

[0033] In one embodiment, the gate driving units are arranged in columns, and the second compensation module is arranged in columns.

[0034] In one embodiment, the second compensation module is arranged in the same row as at least a portion of the gate drive unit.

[0035] In one embodiment, the number of rows of the gate drive units between any two adjacent second compensation modules is the same.

[0036] In one embodiment, at least a portion of the effective pulse start time of the second control signal is the same as the effective pulse start time of at least a portion of the gate drive signal output by the gate drive unit.

[0037] In one embodiment, the third gating unit includes a third transistor, the first terminal of which is connected to the compensation signal line, the second terminal of which is connected to the target power signal line, and the gate of which is connected to the second control signal line.

[0038] In one embodiment, the third transistor includes a P-type transistor or an N-type transistor.

[0039] Secondly, embodiments of this application provide a driving method for a display panel, applied to the display panel described above, the driving method for the display panel including:

[0040] The compensation module of the control gate drive circuit selects the path between the compensation signal line and the target power signal line.

[0041] Thirdly, embodiments of this application provide a display device, including the display panel as described above.

[0042] The display panel, driving method, and display device provided in this application embodiment can connect the compensation signal line and the target power signal line through a compensation circuit to apply a compensation signal to the target power signal line. This compensates for the charge demand on the target power signal line when the gate driving circuit outputs an effective gate driving signal pulse, thereby improving the glitches caused by the target power signal line's inability to meet the charge demand. In other words, in related technologies, glitches are generated on the target power signal line because the charge demand cannot be met when the gate driving circuit outputs an effective gate driving signal pulse. In this case, the display panel provided in this application embodiment applies a compensation signal to the target power signal line when the gate driving circuit outputs an effective gate driving signal pulse, which is equivalent to generating glitches in the opposite direction. The two reverse glitches cancel each other out, thereby obtaining a flat and glitch-free target power signal waveform, and thus a flat and glitch-free gate driving signal waveform, which helps to improve the display effect of the display panel. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 is a waveform diagram of a gate drive signal with glitches;

[0045] Figure 2 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0046] Figure 3 is a second schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0047] Figure 4 is a third schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0048] Figure 5 is a fourth structural schematic diagram of a display panel provided in an embodiment of this application;

[0049] Figure 6 is a fifth schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0050] Figure 7 is one of the waveform diagrams of a gate drive signal provided in an embodiment of this application;

[0051] Figure 8 is a second waveform diagram of a gate drive signal provided in an embodiment of this application;

[0052] Figure 9 is a sixth schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0053] Figure 10 is a seventh structural schematic diagram of a display panel provided in an embodiment of this application;

[0054] Figure 11 is a third waveform diagram of a gate drive signal provided in an embodiment of this application;

[0055] Figure 12 is a fourth waveform diagram of a gate drive signal provided in an embodiment of this application;

[0056] Figure 13 is a flowchart illustrating the driving method for a display panel provided in an embodiment of this application;

[0057] Figure 14 is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0058] Explanation of reference numerals in the attached figures:

[0059] 1-Display panel, 10-Gate driving circuit, 20-Compensation circuit, 210-First compensation module, 220-Second compensation module, 1000-Display device. Detailed Implementation

[0060] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0062] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0063] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on said other layer or substrate, or there may be intermediate layers. Furthermore, it is understood that when a layer is referred to as "between" two layers, the layer may be the only layer between said two layers, or there may be one or more intermediate layers. Additionally, the same reference numerals always denote the same elements.

[0064] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0065] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are only used to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions, unless the singular form has a distinctly different meaning in the context.

[0066] When a phrase such as “at least one of…” follows a list of elements, it modifies the entire list of elements, not individual elements within that list. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. As used in the application documents, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0067] Electronic or electrical devices and / or any other related devices or components (e.g., display devices including a display panel and a display panel driver, wherein the display panel driver further includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and a transmit driver) according to embodiments of the concepts described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Additionally, various components of these devices may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of these devices may be processes or threads running on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. Computer program instructions are stored in memory, which may be implemented in a computing device using standard storage devices such as random access memory (RAM). Computer program instructions may also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present application.

[0068] While exemplary embodiments of the display module and the display device including the display module have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that the display module and the display device including the display module, constructed according to the principles of this application, may be implemented in ways other than those specifically described herein. This application is also defined in the claims and their equivalents.

[0069] The display panel incorporates a gate-in-panel (GIP) circuit, which outputs a periodic gate drive signal, Gout, to drive the pixel circuitry within the panel. The GIP circuit requires at least two power supply signals, VGH and VGL, to support its gate drive signal output. The gate drive signal level transitions periodically between high and low. At the instant of this transition, the GIP circuit experiences a momentary charge demand. Because the GIP circuit's ability to withstand instantaneous current is insufficient, the power supply signals VGH or VGL cannot meet this demand, resulting in periodic glitches in VGH or VGL. Consequently, the gate drive signal Gout output by the GIP circuit based on VGH and VGL will also exhibit periodic glitches. Figure 1 illustrates the output waveform of a gate drive signal with periodic glitches. Using the gate drive signal shown in Figure 1 to drive the pixel circuitry of the display panel may affect the display's performance.

[0070] To address the aforementioned technical problems, this application provides a display panel, its driving method, and a display device. By compensating the power supply signal with a compensation signal, the glitches caused by the instantaneous charge demand generated by the gate driving signal can be offset, thereby improving the output waveform of the gate driving signal and enhancing the display effect.

[0071] Figure 2 is a schematic diagram of the structure of a display panel provided in an embodiment of this application, and Figure 3 is a schematic diagram of the structure of another display panel provided in an embodiment of this application. Referring to Figures 2 and 3, in one embodiment, a display panel is provided, which includes a gate driving circuit 10, a compensation circuit 20, a compensation signal line, and two power signal lines. The compensation signal line is used to provide a compensation signal VH or VL. The two power signal lines are used to provide different power signals. For example, the two power signal lines include a first power signal line and a second power signal line, wherein the first power signal line is used to provide a first power signal VGH, and the second power signal line is used to provide a second power signal VGL, and the first power signal VGH is different from the second power signal VGL. For ease of description, in this embodiment of the application, the first power signal VGH is a high-level signal, and the second power signal VGL is a low-level signal, as an example.

[0072] The gate drive circuit 10 is connected to two power signal lines. The gate drive circuit 10 outputs a gate drive signal based on the two power signals provided by the two power signal lines. The compensation circuit 20 is connected to a compensation signal line and a target power signal line. The compensation circuit 20 selects the path between the compensation signal line and the target power signal line. The target power signal line is one of the two power signal lines, and the absolute value of the compensation signal is greater than the absolute value of the target power signal provided by the target power signal line. For example, if the target power signal line is the first power signal line, then the target power signal VH is greater than the first power signal VGH. As another example, if the target power signal line is the second power signal line, then the target power signal VL is less than the second power signal VGL.

[0073] In applications, the compensation circuit 20 can be used to connect the compensation signal line and the target power signal line to apply the compensation signal VH or VL to the target power signal line, thereby compensating for the charge demand of the target power signal line through the compensation signal VH. In applications, a momentary charge demand is generated at the start of the effective pulse of the gate drive signal output by the gate drive circuit 10. Accordingly, the compensation circuit 20 can be controlled to connect the compensation signal line and the target power signal line to apply the compensation signal VH or VL to the target power signal line to cancel the glitches generated by the output gate drive signal. The effective levels of the target power signal and the gate drive signal are the same. The effective level of the gate drive signal includes a high level or a low level. As shown in Figure 2, when the effective level of the gate drive signal is high, the target power signal is also high, and the target power signal line is the first power signal line. As shown in Figure 3, when the effective level of the gate drive signal is low, the target power signal is also low, and the target power signal line is the second power signal line.

[0074] The aforementioned display panel can connect the compensation signal line and the target power signal line through the compensation circuit 20, so as to apply the compensation signal VH or VL to the target power signal line. This compensates for the charge demand generated by the effective pulse of the gate drive signal output by the gate drive circuit 10 on the target power signal line, thereby improving the glitches caused by the target power signal line's inability to meet the charge demand. In other words, in related technologies, the target power signal line generates glitches because it cannot meet the instantaneous charge demand of the gate drive signal output by the gate drive circuit 10. In this regard, the display panel provided in this application applies the compensation signal VH or VL to the target power signal line when the gate drive circuit 10 outputs the effective pulse of the gate drive signal, which is equivalent to generating glitches in the opposite direction. The two reverse glitches cancel each other out, resulting in a flat and glitch-free target power signal waveform. This, in turn, results in a flat and glitch-free gate drive signal waveform, which helps to improve the display effect of the display panel. The display effect is significantly improved, especially in application scenarios such as frequency conversion direct cut and multi-frequency partitioning, and the waveform debugging window is also reduced.

[0075] Referring to Figures 2 and 3, in one embodiment, the two power signal lines include a first power signal line and a second power signal line. The first power signal line provides a first power signal VGH, which is greater than the second power signal line provides a second power signal VGL. The gate driving circuit 10 is used to connect to the target transistor of the pixel circuit. Specifically, the output terminal of the gate driving circuit 10 is used to connect to the gate of the target transistor of the pixel circuit.

[0076] For example, as shown in Figure 2, the target transistor is an N-type transistor. The gate of the N-type transistor turns on in response to a high-level signal. That is, the effective level of the gate drive signal is high, so the target power supply signal is a high-level signal, the target power supply signal line is the first power supply signal line, and the compensation signal VH is greater than the first power supply signal VGH.

[0077] In the application, the compensation circuit 20 can be used to connect the compensation signal line and the first power signal line, and a high-level compensation signal VH can be applied to the first power signal line. The compensation signal VH is greater than the first power signal VGH. In this way, the compensation signal VH compensates for the charge demand on the first power signal line when the gate drive signal outputs a valid high level. That is, the gate drive signal outputting a high level will cause the first power signal VGH to generate a downward glitch. The compensation signal VH provided in this embodiment can cause the first power signal VGH to generate an upward glitch. The two reverse glitches cancel each other out, thereby obtaining a flat and glitch-free first power signal VGH waveform and gate drive signal waveform.

[0078] Another example, as shown in Figure 3, is that the target transistor is a P-type transistor. The gate of the P-type transistor turns on in response to a low-level signal. That is, the effective level of the gate drive signal is low, so the target power supply signal is a low-level signal, the target power supply signal line is the second power supply signal line, and the compensation signal VL is less than the second power supply signal VGL.

[0079] In the application, the compensation circuit 20 can compensate the signal line and the first power signal line, and apply a low-level compensation signal VL to the second power signal line. The compensation signal VL is less than the second power signal VGL. In this way, the compensation signal VL compensates for the charge demand on the second power signal line when the gate drive signal outputs a valid low level. That is, the low level output of the gate drive signal will cause the second power signal VGL to generate an upward glitch. The compensation signal VL provided in this embodiment can cause the second power signal VGL to generate a downward glitch. The two reverse glitches cancel each other out, thereby obtaining a flat and glitch-free second power signal VGL waveform and gate drive signal waveform.

[0080] Figure 4 is a schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 5 is a schematic diagram of the structure of another display panel provided in an embodiment of this application; Figure 6 is a schematic diagram of the structure of yet another display panel provided in an embodiment of this application; Figure 7 is a waveform diagram of a gate driving signal provided in an embodiment of this application; and Figure 8 is a waveform diagram of another gate driving signal provided in an embodiment of this application. Referring to Figures 4 to 8, in one embodiment, the display panel further includes a first control signal line, which is used to provide a first control signal Reset. The compensation circuit 20 includes at least one first compensation module 210. The first compensation module 210 includes a storage unit, a first gating unit, and a second gating unit.

[0081] In the same first compensation module 210, a first gating unit is connected to the first control signal line, the compensation signal line, and the first end of the storage unit. The first gating unit receives the first control signal Reset provided by the first control signal line. The first gating unit is used to select the path between the compensation signal line and the first end of the storage unit.

[0082] The second terminal of the memory cell is used to receive a reference signal Vx. The reference signal Vx is a DC signal with a fixed level, used to stabilize the potential at the second terminal of the memory cell.

[0083] In the same first compensation module 210, the second gating unit is connected to the first terminal of the memory cell, the target power signal line, and the output terminal of the gate drive circuit 10, respectively. The second gating unit receives the gate drive signal output by the gate drive circuit 10. The second gating unit is used to select and conduct the path between the first terminal of the memory cell and the target power signal line.

[0084] For example, the first terminal of the memory cell can be used to store the compensation signal VH or VL when the first gating unit is in the on state. The second gating unit is used to turn on the path between the first terminal of the memory cell and the target power signal line in response to a valid pulse of the gate drive signal, so as to apply the compensation signal VH or VL to the target power signal line.

[0085] The gate drive circuit 10 described above controls the first gating unit to select the path between the compensation signal line and the first end of the storage cell through the first control signal Reset, and controls the second gating unit to select the path between the first end of the storage cell and the target signal line through the gate drive signal. When the first gating unit selects the path between the compensation signal line and the first end of the storage cell, the compensation signal VH or VL is stored at the first end of the storage cell. When the second gating unit responds to the effective level of the gate drive signal, the path between the first end of the storage cell and the target signal line is selected, so that the compensation signal VH or VL stored at the first end of the storage cell is applied to the target power signal line. In this way, the compensation signal VH or VL compensates for the charge demand generated when the gate drive signal output by the gate drive circuit 10 is at the effective level, and a flat and glitch-free gate drive signal waveform can be obtained, as shown in Figures 7 and 8, which helps to improve the display effect.

[0086] Referring to Figures 7 and 8, in one embodiment, the effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal; that is, the effective pulse start time of the first control signal is earlier than the effective pulse start time of the gate drive signal, and the effective pulses of the first control signal and the gate drive signal do not overlap. When the gate drive circuit 10 includes multiple cascaded gate drive units GIPu, the effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal output by each gate drive unit GIPu.

[0087] In the application, the first gating unit is turned on in response to the effective pulse of the first control signal output, causing the first terminal of the storage unit of each first compensation module 210 to store the compensation signal. Based on this, the second gating unit is turned on in response to the effective pulse of the gate drive signal output by the gate drive circuit 10, and applies the compensation signal stored at the first terminal of the storage unit to the target power signal line, thereby compensating for the instantaneous charge demand generated by the output gate drive signal through the compensation signal, so as to obtain a flatter gate drive signal and thus improve the display effect of the display panel.

[0088] Referring to Figures 4 through 8, in one embodiment, the gate driving circuit 10 is used to connect to the pixel circuit. Specifically, the output terminal of the gate driving circuit 10 is used to connect to the gate of the target transistor of the pixel circuit. The display panel also includes two pixel power signal lines and an initialization signal line. The pixel circuit is connected to the two pixel power signal lines and the initialization signal line respectively. The two pixel power signal lines are used to provide two different power signals ELVDD and ELVSS to the pixel circuit respectively. The initialization signal line is used to provide an initialization signal VREF to the pixel circuit. The second terminal of the memory cell is connected to either the two pixel power signal lines or the initialization signal line. That is, either the two pixel power signal lines or the initialization signal line can be selected to provide a reference signal Vx to the second terminal of the memory cell. In this way, the signal lines in the display panel can be reused, which can reduce costs and area.

[0089] Referring to Figures 4 through 8, in one embodiment, the display panel further includes at least one of a ground signal line and an external power signal line. The ground signal line provides a ground signal GND. The external power signal line provides an external power signal. The second terminal of the memory cell is connected to either the ground signal line or the external power signal line. That is, either the ground signal line or the external power signal line can be selected to provide a reference signal Vx to the second terminal of the memory cell. Thus, the potential of the second terminal of the memory cell can be stabilized by additionally designing the ground signal line or the external power signal line.

[0090] Please continue referring to Figures 4 to 8. In one embodiment, the first gating unit includes a first transistor T1. The first terminal of the first transistor T1 is connected to the compensation signal line, the second terminal of the first transistor T1 is connected to the first end of the storage cell of the same first compensation module 210, and the gate of the first transistor T1 is connected to the first control signal line. The first transistor T1 is used to select and turn on the path between the compensation signal line and the first end of the storage cell in response to the first control signal Reset provided by the first control signal line. Based on this, by controlling the first transistor T1 through the first control signal Reset, the on / off state of the path between the compensation signal line and the first end of the storage cell can be effectively controlled, and when the first transistor T1 is in the on state, the first end of the storage cell can store the compensation signal VH or VL provided by the compensation signal line.

[0091] Please continue referring to Figures 4 through 8. In one embodiment, the first transistor T1 includes an N-type transistor or a P-type transistor. For example, as shown in Figures 4 and 6, if the first transistor T1 includes an N-type transistor, then the first transistor T1 turns on in response to a high-level first control signal Reset, and turns off in response to a low-level first control signal Reset. As another example, as shown in Figure 5, if the first transistor T1 includes a P-type transistor, then the first transistor T1 turns on in response to a low-level first control signal Reset, and turns off in response to a high-level first control signal Reset. In practical applications, the type of the first transistor T1 can be arbitrarily chosen, and the corresponding first control signal line can be configured; no limitation is made here.

[0092] Please refer to Figures 4 through 8. In one embodiment, the second gating unit includes a second transistor T2. The first terminal of the second transistor T2 is connected to the first end of the storage cell of the same first compensation module 210, the second terminal of the second transistor T2 is connected to the target power signal line, and the gate of the second transistor T2 is connected to the output terminal of the gate driving circuit 10. The second transistor T2 is used to select and conduct the path between the first end of the storage cell and the target power signal line in response to the gate driving signal output by the gate driving circuit 10. Specifically, the second transistor T2 is used to conduct the path between the first end of the storage cell and the target power signal line in response to the effective pulse of the gate driving signal. Based on this, by controlling the second transistor T2 through the gate driving signal, the on / off state of the path between the first end of the storage cell and the target power signal line can be effectively controlled. When the second transistor T2 is in the conducting state, the compensation signal VH or VL stored at the first end of the storage cell can be applied to the target power signal line to compensate for the charge demand generated when the gate driving signal outputs an effective level, thereby obtaining a flat and glitch-free gate driving signal waveform, which helps to improve the display effect.

[0093] Referring to Figures 4 through 8, in one embodiment, the gate driving circuit 10 is used to connect to the target transistor of the pixel circuit. Specifically, the output terminal of the gate driving circuit 10 is used to connect to the gate of the target transistor of the pixel circuit. The second transistor T2 is of the same type as the target transistor. For example, as shown in Figures 4 and 6, if the target transistor is an N-type transistor, then the second transistor T2 is an N-type transistor. In this case, the effective level of the gate driving signal is high, the target power signal line is the first power signal line, and the compensation signal VH is greater than the first power signal VGH. As another example, as shown in Figure 5, if the target transistor is a P-type transistor, then the second transistor T2 is a P-type transistor. In this case, the effective level of the gate driving signal is low, the target power signal line is the second power signal line, and the compensation signal VL is less than the second power signal VGL. In practical applications, the second transistor T2 of the same type can be selected according to the type of the target transistor in the pixel circuit driven by the gate driving circuit 10, thereby achieving effective control of the second transistor T2 by the gate driving signal.

[0094] Please refer to Figures 4 through 8. In one embodiment, the storage unit includes a capacitor C. The first terminal of capacitor C is connected to both the first gating unit and the second gating unit of the same first compensation module 210. The second terminal of capacitor C is used to receive a reference signal Vx. The first terminal of capacitor C is used to store compensation signals VH or VL when the first gating unit is in the on state, thereby preserving charge through the first terminal of capacitor C. Based on this, when the second gating unit is in the on state, charge is released to the target power signal line through the first terminal of capacitor C, thereby achieving charge compensation for the target power signal line to obtain a flat, glitch-free gate drive signal waveform.

[0095] Please refer to Figures 4 through 8. The gate drive circuit 10 includes multiple cascaded gate drive units GIPu. The compensation circuit 20 includes multiple first compensation modules 210. The number of gate drive units and first compensation modules 210 can be set according to actual needs and is not limited here. For example, the number of gate drive units GIPu is the same as the number of first compensation modules 210.

[0096] The output terminal of the i-th level gate driving unit GIPu is connected to the second gating unit of the i-th first compensation module 210. Where i ≥ 1. The output terminals of different levels of gate driving units GIPu are connected to different first gating units. For example, when the second gating unit includes a second transistor T2, the output terminal of the i-th level gate driving unit is connected to the gate of the second transistor T2 of the i-th first compensation module 210. For instance, in the display panel shown in Figures 4 and 5, the output terminal of the first level gate driving unit GIPu is connected to the gate of the first second transistor T2 in the same row, the output terminal of the second level gate driving unit GIPu is connected to the gate of the second second transistor T2 in the same row, and so on up to the last level gate driving unit GIPu. Similarly, in the display panel shown in Figure 6, the output terminal of the first level gate driving unit GIPu is connected to the gate of the first second transistor T2 in the second row, the output terminal of the second level gate driving unit GIPu is connected to the gate of the second second transistor T2 in the third row, and so on up to the last level gate driving unit GIPu.

[0097] The second gating unit of the i-th first compensation module 210 is used to select and connect the path between the first terminal of the memory cell of the i-th first compensation module 210 and the target power signal line in response to the gate drive signal output by the i-th gate drive unit GIPu. That is, the second gating unit of the i-th first compensation module 210 is controlled by the gate drive signal output by the i-th gate drive unit GIPu, thereby controlling the on / off state between the first terminal of the memory cell of the i-th first compensation module 210 and the target power signal line.

[0098] Please continue to refer to Figures 4 to 8. In one embodiment, the second gating unit of the i-th first compensation module 210 responds to the effective pulse of the gate drive signal output by the i-th gate drive unit GIPu and applies the compensation signal stored at the first end of the storage unit of the i-th first compensation module 210 to the target power signal line.

[0099] In the application, before each gate drive unit GIPu outputs a valid pulse of the gate drive signal, each first compensation module 210 is turned on in response to a valid pulse of the first control signal Reset provided by the first control signal line, so that the first terminal of each memory cell stores the compensation signal. Based on this, the second gating unit of the i-th first compensation module 210, in response to a valid pulse of the gate drive signal output by the i-th stage gate drive unit GIPu, applies the compensation signal stored at the first terminal of the memory cell of the i-th first compensation module 210 to the target power signal line. It can be understood that the gate driving unit GIPu outputs gate driving signals step by step starting from the first stage. Therefore, starting from the second gating unit of the first compensation module 210, it sequentially responds to the effective pulses of the gate driving signals output by the corresponding level of the gate driving unit GIPu, and is turned on one by one in a time-division manner until the second gating unit of the last first compensation module 210. When each level of the gate driving unit GIPu outputs an effective pulse of the gate driving signal, the corresponding first compensation module 210 applies a compensation signal to the target power line to avoid glitches in the effective pulses of the gate driving signals output by each level of the gate driving unit GIPu. This allows each level of the gate driving unit GIPu to output flat and glitch-free gate driving signals, thereby improving the display effect of the display panel.

[0100] Please refer to Figures 4 through 6. In one embodiment, the gate driving units GIPu and the first compensation module 210 are arranged in columns. That is, the gate driving units GIPu and the first compensation module 210 are arranged along the column direction of the pixel circuit. This regular arrangement of the gate driving units GIPu and the first compensation module 210 helps to shorten signal traces, reduce the occupied area, and achieve a narrow bezel. For example, the first compensation module 210 is positioned close to the gate driving unit GIPu. This further reduces the traces between the gate driving unit GIPu and the first compensation module 210, reduces the delay caused by signal transmission, improves the timeliness of the compensation signal in compensating the target power signal, obtains a flatter gate driving signal, and improves the display effect of the display panel.

[0101] Please continue referring to Figures 4 and 5. In one embodiment, the i-th first compensation module 210 is arranged in the same row as the i-th gate driving unit GIPu. For example, as shown in Figure 5, the first compensation module 210 and the gate driving unit GIPu are arranged in columns, and the first first compensation module 210 is arranged in the same row as the first-stage gate driving unit GIPu, the second first compensation module 210 is arranged in the same row as the second-stage gate driving unit GIPu, and so on until the last row.

[0102] It is understood that the second gating unit of the i-th first compensation module 210 is connected to the output terminal of the i-th gate driving unit GIPu. Therefore, by setting the i-th first compensation module 210 and the i-th gate driving unit GIPu in the same row, the signal trace between the i-th gate driving unit GIPu and the i-th first compensation module 210 can be shortened, the delay caused by signal transmission can be reduced, the timeliness of the compensation signal to compensate the target power signal can be improved, so as to obtain a flatter gate driving signal and improve the display effect of the display panel.

[0103] Please refer to Figure 6. In one embodiment, the i-th first compensation module 210 is arranged in the same row as the (i+1)-th level gate driving unit. Specifically, the first-level gate driving unit GIPu and the last first compensation module 210 are arranged separately. In other words, the first row only has the first-level gate driving unit GIPu, the last row only has the last first compensation module 210, and the second row to the penultimate row each have one first compensation module 210 and one first-level gate driving unit GIPu. For example, as shown in Figure 6, the first compensation module 210 and the gate driving unit GIPu are arranged in columns, with the first-level gate driving unit GIPu arranged separately. The first first compensation module 210 is arranged in the same row as the second-level gate driving unit GIPu, the second first compensation module 210 is arranged in the same row as the third-level gate driving unit GIPu, and so on until the penultimate first compensation module 210 is arranged in the same row as the last level gate driving unit GIPu, and the last first compensation module 210 is arranged separately.

[0104] It is understandable that the i-th first compensation module 210 is close to the (i+1)-th level gate driving unit GIPu. Therefore, by setting the i-th first compensation module 210 and the (i+1)-th level gate driving unit GIPu in the same row, the signal trace between the i-th level gate driving unit GIPu and the i-th first compensation module 210 can be shortened, the delay caused by signal transmission can be reduced, and the timeliness of the compensation signal in compensating the target power signal can be improved, so as to obtain a flatter gate driving signal and improve the display effect of the display panel.

[0105] Figure 9 is a schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 10 is a schematic diagram of the structure of another display panel provided in an embodiment of this application; Figure 11 is a waveform diagram of a gate driving signal provided in an embodiment of this application; and Figure 12 is a waveform diagram of another gate driving signal provided in an embodiment of this application. Referring to Figures 9 to 12, in one embodiment, the display panel further includes a second control signal line, which is used to provide a second control signal SYNC. The compensation circuit 2020 includes at least one second compensation module 220. The number of second compensation modules 220 can be 1, 2, 3, or any other value greater than 3, and can be set according to requirements, without limitation here.

[0106] The second compensation module 220 includes a third gating unit, which is connected to the second control signal line, the compensation signal line, and the target power signal line respectively. The third gating unit receives the second control signal SYNC provided by the second control signal line and is used to select the path between the compensation signal line and the target power signal line.

[0107] For example, the third gating unit responds to a valid pulse of the second control signal and applies a compensation signal to the target power signal line. The start time of at least one valid pulse of the second control signal is the same as the start time of a valid pulse of the gate drive signal. For instance, the second control signal includes multiple valid pulses, and the gate drive circuit 10 includes multiple gate drive units GIPu, with the start times of some valid pulses of the second control signal corresponding to the start times of valid pulses of the gate drive signals output by each gate drive unit GIPu.

[0108] In the application, at the start of the effective pulse of the gate drive signal output by the gate drive circuit 10, the third gating unit begins to conduct in response to the effective pulse of the second control signal, applying the compensation signal VH or VL to the target power signal line. That is, when the gate drive signal output by the gate drive circuit 10 is at an effective level, the third gating unit is controlled by the second control signal SYNC to conduct the path between the compensation signal line and the target power signal line, applying the compensation signal VH or VL to the target power signal line. This compensates for the charge demand on the target power signal line when the gate drive signal output by the gate drive circuit 10 is at an effective level, improving the glitches caused by the target power signal line's inability to meet the charge demand. A flat, glitch-free waveform can be obtained, as shown in Figures 11 and 12, which helps improve the display effect of the display panel.

[0109] Please continue referring to Figures 9 to 12. In one embodiment, the gate driving circuit 10 is further configured with a clock signal line. The gate driving circuit 10 is connected to the clock signal line and is used to output a gate driving signal based on two power supply signals and a clock signal provided by the clock signal line. The frequency of the second control signal SYNC is less than or equal to the frequency of the clock signal. For example, the frequency of the second control signal SYNC is the same as the frequency of the clock signal. That is, when the gate driving signal outputs an effective level, the level of the second control signal SYNC is synchronously adjusted to meet the requirement that, when the gate driving circuit 10 outputs an effective level gate driving signal, the second control signal SYNC controls the third gating unit to conduct the path between the compensation signal line and the target power supply signal line.

[0110] Please refer to Figures 9 to 12. In one embodiment, the third gating unit includes a third transistor T3. The first terminal of the third transistor T3 is connected to the compensation signal line, the second terminal of the third transistor T3 is connected to the target power signal line, and the gate of the third transistor T3 is connected to the second control signal line. The third transistor T3 is used to select the path between the compensation signal line and the target power signal line in response to the second control signal SYNC provided by the second control signal line. That is, the second compensation module 220 is a 1TOC structure, which further reduces the number of transistors and capacitors C, which is beneficial to achieving the design requirements of a narrow bezel. The gate drive circuit 10 controls the third transistor T3 through the second control signal SYNC, which can effectively control the on / off state of the path between the compensation signal line and the target power signal line. When the third transistor T3 is in the on state, the compensation signal VH or VL can be applied to the target power signal line to compensate for the charge demand generated when the gate drive signal outputs an effective level, thereby obtaining a flat and glitch-free gate drive signal waveform, which helps to improve the display effect. Because the third transistor T3 has a significant impedance, the compensation signal line and the target power signal line are not short-circuited, but rather charge is injected into the target power signal line.

[0111] Please continue referring to Figures 9 through 12. In one embodiment, the third transistor T3 includes an N-type transistor or a P-type transistor. For example, as shown in Figures 9 and 11, if the third transistor T3 includes an N-type transistor, then the third transistor T3 turns on in response to a high-level second control signal SYNC, and turns off in response to a low-level second control signal SYNC. As another example, as shown in Figures 10 and 12, if the third transistor T3 includes a P-type transistor, then the third transistor T3 turns on in response to a low-level second control signal SYNC, and turns off in response to a high-level second control signal SYNC. In practical applications, the type of the third transistor T3 can be arbitrarily selected, and the corresponding second control signal line can be configured; no limitation is made here.

[0112] In one embodiment, the gate driving circuit 10 includes multiple cascaded gate driving units GIPu, and the compensation circuit 20 includes multiple second compensation modules 220, wherein the number of gate driving units GIPu is greater than or equal to the number of second compensation modules 220. The number of second compensation modules 220 is greater than or equal to 1, and the number of gate driving units GIPu can be determined based on factors such as the number of rows of the pixel circuit and the driving method, and is not specifically limited here. It can be understood that the second compensation module 220 selects the path between the compensation signal line and the target power line according to the second control signal. Therefore, by controlling the timing of the second control signal, reverse compensation of the target power signal can be achieved to obtain a relatively flat gate driving signal. It is not necessary to set a second compensation module 220 for each gate driving unit GIPu, which can reduce the number of second compensation modules 220 and reduce the occupied area.

[0113] In one embodiment, the gate driving units GIPu and the second compensation module 220 are arranged in columns. That is, the gate driving units GIPu and the second compensation module 220 are arranged along the column direction of the pixel circuit, respectively. This regular arrangement of the gate driving units GIPu and the second compensation module 220 helps to shorten signal traces, reduce the occupied area, and achieve a narrow bezel. For example, the second compensation module 220 is positioned close to the gate driving unit GIPu. This further reduces the traces between the gate driving unit GIPu and the second compensation module 220, reduces delays caused by signal transmission, improves the timeliness of the compensation signal in compensating the target power signal, obtains a flatter gate driving signal, and improves the display effect of the display panel.

[0114] In one embodiment, the second compensation module 220 is arranged parallel to at least a portion of the gate driving units (GIPu). For example, when the number of second compensation modules 220 and gate driving units (GIPu) is the same, the i-th stage second compensation module 220 can be arranged parallel to the i-th stage gate driving unit (GIPu), where i ≥ 1. Alternatively, when the number of second compensation modules 220 is less than the number of gate driving units (GIPu), one second compensation module 220 is arranged parallel to one gate driving unit (GIPu), and the gate driving units (GIPu) arranged parallel to different second compensation modules 220 are different. Thus, by arranging the second compensation modules 220 parallel to at least a portion of the gate driving units (GIPu), the second compensation modules 220 and gate driving units (GIPu) can be regularly arranged, which helps reduce the wiring between the gate driving units (GIPu) and the second compensation modules 220, thereby reducing the delay caused by signal transmission, improving the timeliness of the compensation signal in compensating the target power signal, obtaining a flatter gate driving signal, and improving the display effect of the display panel.

[0115] In one embodiment, the number of rows of gate driving units GIPu between any two adjacent second compensation modules 220 is the same. The number of rows of gate driving units GIPu between any two adjacent second compensation modules 220 can be 1, 2, 3, or any other value greater than 3, and is not limited here. For example, in the display panel shown in Figures 9 and 10, the number of rows of gate driving units GIPu between any two adjacent second compensation modules 220 is 1. The first second compensation module 220 is arranged in the same row as the first-level gate driving unit GIPu, the second second compensation module 220 is arranged in the same row as the third-level gate driving unit GIPu, the third second compensation module 220 is arranged in the same row as the fifth-level gate driving unit GIPu, and so on. Thus, a second compensation module 220 is set for each of the one or more adjacent gate drive units GIPu. This helps to apply the compensation signal to the target power signal line in a timely manner at the start of the effective pulse of the gate drive signal output by the gate drive unit GIPu, so as to obtain a flatter and glitch-free gate drive signal waveform and improve the display effect of the display panel.

[0116] In one embodiment, as shown in Figures 11 and 12, the start time of at least a portion of the effective pulses of the second control signal is the same as the start time of the effective pulses of the gate drive signals output by at least a portion of the gate drive units GIPu. For example, the start time of a portion of the effective pulses of the second control signal is the same as the start time of the effective pulses of the gate drive signals output by each gate drive unit GIPu.

[0117] In the application, at the start of the effective pulse of the gate drive signal output by each gate drive unit GIPu, the third gating unit in the second compensation module 220 begins to respond to the effective pulse of the second control signal, conducts the path between the compensation signal line and the target power signal line, and performs charge compensation on the target power signal line with the compensation signal VH or VL, so that each gate drive unit GIPu can obtain a flat and waveformless gate drive signal waveform, and can reduce cost and footprint.

[0118] Based on the same inventive concept, this application further provides a driving method for a display panel, which can be applied to the aforementioned display panel. Referring to Figures 2 to 12, the driving method for a display panel provided in this application embodiment may include: controlling the compensation circuit 20 of the display panel, and selecting the path between the compensation signal line and the target power signal line.

[0119] The aforementioned driving method for the display panel can select and connect the path between the compensation signal line and the target power signal line by controlling the compensation circuit 20. When the compensation circuit 20 connects the compensation signal line and the target power signal line, a compensation signal VH or VL is applied to the target power signal line. This compensates for the charge demand generated by the effective gate drive signal pulse output by the gate drive circuit 10, thus improving the glitches caused by the target power signal line's inability to meet the charge demand. In other words, in related technologies, glitches are generated on the target power signal line because the target power signal line cannot meet the charge demand when the gate drive circuit 10 outputs an effective gate drive signal level. In this application, when the gate drive circuit 10 outputs an effective gate drive signal level, a compensation signal VH or VL is applied to the target power signal line, which is equivalent to generating glitches in the opposite direction. The two reverse glitches cancel each other out, resulting in a flat, glitch-free target power signal waveform. This, in turn, results in a flat, glitch-free gate drive signal waveform, which helps improve the display effect of the display panel.

[0120] In one embodiment, the difference between the absolute value of the compensation signal VH or VL and the absolute value of the target power signal is obtained through simulation. Specifically, this is the difference between the compensation signal VH and the first power signal VGH (VH-VGH), and the difference between the second power signal VGL and the compensation signal VL (VL-VGL). Specifically, the voltage difference VH-VGH or VL-VGL between the absolute value of the compensation signal and the absolute value of the target power signal can be adjusted through layout load and post-simulation. The layout load can be understood as the pixel circuit connected to the gate drive circuit 10. After sample production, the voltage difference VH-VGH or VL-VGL between the absolute value of the compensation signal and the absolute value of the target power signal can be optimized again. Thus, the compensation signal VH or VL can be optimized through simulation to obtain a flat, glitch-free gate drive signal waveform.

[0121] Figure 13 is a schematic flowchart of the driving method of the gate driving circuit 10 provided in an embodiment of this application. Referring to Figures 4 to 8 and Figure 13, in one embodiment, the gate driving circuit 10 is configured with a first control signal line, and the compensation circuit 20 includes at least one first compensation module 210. The first compensation module 210 includes a storage unit, a first gating unit, and a second gating unit. Based on the display panel provided as shown in Figures 4 to 6, and as shown in Figure 13, the above steps, controlling the compensation circuit 20 of the display panel to select and connect the path between the compensation signal line and the target power signal line, may include the following steps S1301 to S1303.

[0122] S1301: Control the first control signal line to output a valid pulse of the first control signal Reset, so as to open the path between the compensation signal line and the target power signal line through the first gating unit.

[0123] S1302: The compensation signal is stored in the storage unit, and the invalid pulse of the first control signal Reset is output by the first control signal line to disconnect the path between the compensation signal line and the target power signal line through the first gating unit.

[0124] S1303: In response to the effective pulse of the gate drive signal output by the gate drive circuit 10 through the second gating unit, the path between the compensation signal line and the target power supply signal line is turned on.

[0125] In this configuration, the end time of the effective pulse of the first control signal Reset is earlier than the start time of the effective pulse of the gate drive signal. In application, the effective pulse of the first control signal Reset can be output through the first control signal line, causing the first gating unit to turn on in response to the effective pulse of the first control signal Reset, thereby opening the path between the compensation signal line and the target power signal line, allowing the first terminal of the memory cell to store the compensation signal VH or VL. When the compensation signal VH or VL is stored at the potential of the first terminal of the memory cell, an invalid pulse of the first control signal Reset can be output through the first control signal line, causing the first gating unit to turn off in response to the effective pulse of the first control signal Reset, thereby breaking the path between the compensation signal line and the target power signal line, allowing the first terminal of the memory cell to latch the compensation signal VH or VL. When the gate drive signal outputs an effective pulse, the first gating unit remains in a state where the path between the compensation signal line and the target power signal line is disconnected. The second gating unit is turned on in response to the effective pulse of the gate drive signal output by the gate drive circuit 10, thereby turning on the path between the compensation signal line and the target power signal line. This allows the compensation signal VH or VL stored at the first end of the storage unit to be applied to the target power signal line. As a result, the compensation signal VH or VL compensates for the charge demand generated by the effective level of the gate drive signal output by the gate drive circuit 10, thereby obtaining a flat and glitch-free signal output waveform.

[0126] For example, the display panel provided in Figures 4 and 6 includes a first compensation module 210 with 2T1C, and the first transistor T1 and the second transistor T2 are NTFTs. Before each frame scan begins, the first control signal Reset is set to a high level, and the corresponding first transistor T1 is turned on. At this time, the second transistor T2 is turned off, and the first terminal of capacitor C is charged to the VH potential. Then the first control signal Reset becomes low level, and the first transistor T1 and the second transistor T2 are turned off respectively, and the charge is locked in capacitor C. The next line-by-line scan begins. Whenever the gate drive signal output by the gate drive circuit 10 becomes high level, the corresponding second transistor T2 is turned on. The charge in capacitor C rushes into the first power signal line instantaneously, causing it to generate an upward spike. Consequently, the gate drive signal also has an upward spike. The charge in capacitor C satisfies the large charge demand at the instant the gate drive signal becomes high level. The upward spike and the downward spike generated by the gate drive signal becoming high level cancel each other out, thereby obtaining a smooth and spike-free waveform as shown in Figure 7.

[0127] Another example is the display panel shown in Figure 5, which includes a first compensation module 210 with 2T1C transistors, and where the first transistor T1 and the second transistor T2 are PTFTs. Before each frame scan begins, the first control signal Reset is set to a low level, and the corresponding first transistor T1 is turned on. At this time, the second transistor T2 is turned off, and the first terminal of capacitor C is charged to the VL potential. Then, the first control signal Reset becomes a high level, and the first transistor T1 and the second transistor T2 are turned off respectively, and the charge is locked in capacitor C. The next step, line-by-line scanning, begins. Whenever the gate drive signal output by the gate drive circuit 10 becomes a low level, the corresponding second transistor T2 is turned on. The charge in capacitor C rushes into the second power supply signal line instantaneously, causing it to generate a downward spike. Consequently, the gate drive signal also has a downward spike. The charge in capacitor C satisfies the large charge demand at the instant the gate drive signal becomes a low level. The downward spike and the upward spike generated by the gate drive signal becoming a low level cancel each other out, thereby obtaining a smooth and spike-free waveform as shown in Figure 8.

[0128] In one embodiment, the duration for which the first control signal Reset turns on the first gating unit is obtained based on simulation. Specifically, the turn-on duration of the first gating unit can be adjusted through layout load and post-simulation. The turn-on duration of the first gating unit can be optimized again after sample production. Thus, the turn-on duration of the first gating unit can be optimized through simulation, ensuring that the storage potential at the first terminal of the memory cell is the potential of the compensation signal VH or VL, guaranteeing the storage time of the memory cell, thereby obtaining a flat, glitch-free gate drive signal waveform.

[0129] Please continue referring to Figures 9 to 12. In one embodiment, the display panel includes a second control signal line, and the compensation circuit 20 includes at least one second compensation module 220, which includes a third gating unit. Based on the display panel provided in Figures 9 and 10, the above steps, controlling the compensation circuit 20 of the display panel to select and connect the path between the compensation signal line and the target power signal line, may include: controlling the second control signal line to output a valid pulse of the second control signal SYNC to connect the path between the compensation signal line and the target power signal line through the third gating unit. The start time of at least one valid pulse of the second control signal SYNC is the same as the start time of the valid pulse of the gate drive signal output by the gate drive circuit 10.

[0130] For example, the display panel shown in Figure 9 includes a second compensation module 220 with a 1T0C, and the third transistor T3 is an NTFT. At the rising edge of the gate drive signal output, the second control signal SYNC outputs a short-duration high-level pulse, the third transistor T3 is turned on, and the compensation signal VH is applied to the first power supply signal VGH, causing the first power supply signal VGH to have a periodic upward spike, which cancels out the downward spike generated by the effective high level of the gate drive signal output, resulting in a smooth, spike-free waveform as shown in Figure 11.

[0131] Another example is the display panel shown in Figure 10, which includes a second compensation module 220 with a 1T0C and a third transistor T3 that is a PTFT. At the moment of the falling edge of the gate drive signal output, the second control signal SYNC outputs a short-duration low-level pulse, the third transistor T3 is turned on, and the compensation signal VL is applied to the second power supply signal VGL, causing the second power supply signal VGL to have a periodic downward glitch, which cancels out the upward glitch generated by the effective low level of the gate drive signal output, resulting in a smooth, glitch-free waveform as shown in Figure 12.

[0132] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0133] Based on the same inventive concept, this application also provides a display device. Figure 14 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Referring to Figure 14, in one embodiment, the display device 1000 includes the display panel 1 in the above embodiment. It is understood that the display device 1000 in the embodiments of this application can be any product or component with display function, such as an OLED display device, a QLED display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a wearable device, or an IoT device, and the embodiments disclosed in this application do not limit this.

[0134] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0135] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0136] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a gate driving circuit, a compensation circuit, a compensation signal line, and two power signal lines. The gate driving circuit is connected to both power signal lines and outputs a gate driving signal based on two power signals provided by the two power signal lines. The compensation circuit is connected to both the compensation signal line and a target power signal line and is used to selectively conduct the path between the compensation signal line and the target power signal line. The target power signal line is one of the two power signal lines, and the absolute value of the compensation signal provided by the compensation signal line is greater than the absolute value of the target power signal provided by the target power signal line. The display panel also includes a first control signal line. The compensation circuit includes at least one first compensation module, which includes a storage unit, a first gating unit, and a second gating unit. Within the same first compensation module, the first gating unit is connected to the first end of the first control signal line, the compensation signal line, and the storage unit. The first control signal is received from the first control signal line, and the first gating unit is used to select and conduct the path between the compensation signal line and the first end of the storage unit; the second end of the storage unit receives a reference signal; in the same first compensation module, the second gating unit is connected to the first end of the storage unit, the target power signal line, and the output end of the gate drive circuit, respectively, and the second gating unit receives the gate drive signal and is used to select and conduct the path between the first end of the storage unit and the target power signal line; or, the display panel further includes a second control signal line, the compensation circuit includes at least one second compensation module, the second compensation module includes a third gating unit, the third gating unit is connected to the second control signal line, the compensation signal line, and the target power signal line, respectively, the third gating unit receives the second control signal provided by the second control signal line, and the third gating unit is used to select and conduct the path between the compensation signal line and the target power signal line.

2. The display panel according to claim 1, characterized in that, The two power signal lines include a first power signal line and a second power signal line. The first power signal line provides a first power signal that is greater than the second power signal line provides a second power signal. The gate driving circuit is used to connect to the target transistor of the pixel circuit. The target transistor is an N-type transistor and the target power signal line is the first power signal line; or, the target transistor is a P-type transistor and the target power signal line is the second power signal line.

3. The display panel according to claim 1, characterized in that, The effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal.

4. The display panel according to claim 1, characterized in that, The first terminal of the storage unit is used to store the compensation signal when the first gating unit is in the on state; the second gating unit, in response to a valid pulse of the gate drive signal, applies the compensation signal stored at the first terminal of the storage unit to the target power signal line.

5. The display panel according to claim 1, characterized in that, The gate driving circuit is used to connect to the pixel circuit. The display panel also includes two pixel power signal lines and an initialization signal line. The pixel circuit is connected to the two pixel power signal lines and the initialization signal line respectively. The second end of the storage unit is connected to any one of the two pixel power signal lines and the initialization signal line.

6. The display panel according to claim 1, characterized in that, The display panel further includes at least one of a ground signal line and an external power signal line, and the second end of the storage unit is connected to either the ground signal line or the external power signal line.

7. The display panel according to claim 1, characterized in that, The first selection unit includes a first transistor, the first terminal of the first transistor is connected to the compensation signal line, the second terminal of the first transistor is connected to the first end of the memory cell of the same first compensation module, and the gate of the first transistor is connected to the first control signal line.

8. The display panel according to claim 7, characterized in that, The first transistor includes a P-type transistor or an N-type transistor.

9. The display panel according to claim 1, characterized in that, The second selection unit includes a second transistor, the first terminal of the second transistor is connected to the first terminal of the storage cell of the same first compensation module, the second terminal of the second transistor is connected to the target power signal line, and the gate of the second transistor is connected to the output terminal of the gate driving circuit.

10. The display panel according to claim 9, characterized in that, The gate driving circuit is used to connect to the target transistor of the pixel circuit, and the second transistor is of the same type as the target transistor.

11. The display panel according to claim 1, characterized in that, The storage unit includes a capacitor, the first terminal of which is connected to the first gating unit and the second gating unit of the same first compensation module, respectively, and the second terminal of which is used to receive the reference signal.

12. The display panel according to claim 1, characterized in that, The gate driving circuit includes multiple cascaded gate driving units, and the compensation circuit includes multiple first compensation modules, wherein the output terminal of the i-th gate driving unit is connected to the second gating unit of the i-th first compensation module, i≥1.

13. The display panel according to claim 12, characterized in that, In response to a valid pulse of the gate drive signal output by the i-th gate drive unit, the second gating unit of the i-th first compensation module applies the compensation signal stored at the first terminal of the storage unit of the i-th first compensation module to the target power signal line.

14. The display panel according to claim 12, characterized in that, The gate driving units are arranged in columns, and the first compensation module is arranged in columns.

15. The display panel according to claim 12, characterized in that, The i-th first compensation module is arranged in the same row as the i-th stage gate drive unit.

16. The display panel according to claim 12, characterized in that, The i-th first compensation module is arranged in the same row as the (i+1)-th stage gate drive unit.

17. The display panel according to claim 1, characterized in that, The third gating unit responds to a valid pulse of the second control signal by applying the compensation signal to the target power supply signal line; wherein the start time of at least one valid pulse of the second control signal is the same as the start time of the valid pulse of the gate drive signal.

18. The display panel according to claim 1, characterized in that, The gate driving circuit is further configured with a clock signal line, and the gate driving circuit is connected to the clock signal line. The gate driving circuit is used to output the gate driving signal according to the two power supply signals and the clock signal provided by the clock signal line. The frequency of the second control signal is the same as the frequency of the clock signal.

19. The display panel according to claim 1, characterized in that, The gate driving circuit includes multiple cascaded gate driving units, and the compensation circuit includes multiple second compensation modules, wherein the number of gate driving units is greater than or equal to the number of second compensation modules.

20. The display panel according to claim 19, characterized in that, The gate driving units are arranged in columns, and the second compensation module is arranged in columns.

21. The display panel according to claim 19, characterized in that, The second compensation module is arranged in the same row as at least a portion of the gate drive unit.

22. The display panel according to claim 19, characterized in that, The number of rows of the gate driving units between any two adjacent second compensation modules is the same.

23. The display panel according to claim 19, characterized in that, The effective pulse start time of at least a portion of the second control signal is the same as the effective pulse start time of at least a portion of the gate drive signal output by the gate drive unit.

24. The display panel according to claim 1, characterized in that, The third gating unit includes a third transistor, the first terminal of which is connected to the compensation signal line, the second terminal of which is connected to the target power signal line, and the gate of which is connected to the second control signal line.

25. The display panel according to claim 24, characterized in that, The third transistor includes a P-type transistor or an N-type transistor.

26. A driving method for a display panel, characterized in that, The method for driving the display panel as described in any one of claims 1-25 includes: controlling a compensation module of a gate driving circuit to select and connect a path between a compensation signal line and a target power signal line.

27. A display device, characterized in that, Includes the display panel as described in any one of claims 1-25.

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