Method and device for writing data into memory

Abstract

This application discloses a method and apparatus for writing data to a memory, belonging to the field of memory technology. The method comprises: receiving a write instruction from a controller instructing the memory to write data of a specified length to the memory; and writing the data of the specified length to a storage medium of the memory based on the write instruction. Because the write instruction can specify the length of the data to be written, the number of write instructions required to write data of a specified length can be reduced, thereby reducing the overhead of the write instructions.

Description

[0001] This application is a divisional application. The application number of the original application is 202210191660.7, and the original application date is February 28, 2022. The entire content of the original application is incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a method and device for writing data into a memory. Background Art

[0003] In the field of storage technology, when a controller writes data to a storage medium of a memory, the controller needs to send a write instruction and the data to be written to the memory to instruct the memory to write the data to be written to the storage medium of the memory.

[0004] Generally, the write instructions sent by the controller to the same memory can indicate that the length of the data to be written is the same and is a fixed value.

[0005] However, when the same data (such as 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by one write instruction, the controller needs to send multiple write instructions and data, resulting in a large overhead for writing data. Summary of the Invention

[0006] This application provides a method and apparatus for writing data into a memory. This application reduces the overhead of write instructions. The technical solutions provided by this application are as follows:

[0007] In a first aspect, the present application provides a method for writing data to a memory, the method comprising: the memory receives a write instruction from a controller instructing the memory to write data of a specified length to the memory; and the memory writes the data of the specified length to a storage medium of the memory based on the write instruction.

[0008] In the data writing method of the memory provided in the present application, the memory receives a write instruction from a controller to write data of a specified length to the memory, and the memory writes the data of the specified length to the storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when data of a specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. In addition, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0009] In one implementation, since the memory includes multiple memory arrays, data access processes between the multiple memory arrays do not affect each other, and writing data to the memory arrays is achieved by controlling the bit lines and word lines of the memory arrays. Furthermore, each bit line corresponds to an address range, with different bit lines corresponding to different address ranges. The addresses corresponding to multiple bit lines connected to the same memory array constitute a segment of the address range of the memory array. Each word line corresponds to an address range, with different word lines corresponding to different address ranges. The addresses corresponding to multiple word lines connected to the same memory array constitute a segment of the address range of the memory array. Furthermore, each memory array corresponds to an address range, with different memory arrays corresponding to different address ranges. The addresses corresponding to multiple memory arrays in the same memory array constitute a segment of the address range of the memory. Therefore, the specified length is reflected by any one or more of the following: the total number of bit lines with consecutive addresses that need to be controlled for writing data based on a write instruction, the total number of word lines with consecutive addresses that need to be controlled for writing data based on a write instruction, and the total number of memory arrays with consecutive addresses to which data is written based on a write instruction.

[0010] In one implementation, bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when a memory is subjected to a bit line scan. Typically, the plurality of bit lines with consecutive addresses are sequentially deployed on a memory array. Similarly, word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when a memory is subjected to a word line scan. Furthermore, the plurality of word lines with consecutive addresses are typically sequentially deployed on a memory array. Memory arrays with consecutive addresses may be a plurality of memory arrays to which data is sequentially written when data needs to be sequentially written to the plurality of memory arrays in the memory. Furthermore, the plurality of memory arrays with consecutive addresses are typically sequentially deployed on a memory array.

[0011] In a possible implementation scenario, the write instruction further indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is the current value of the current signal used to execute the write operation indicated by the write instruction that does not indicate a current value.

[0012] By using a write instruction to instruct the current value of the current signal used to perform a write operation to be less than a reference value, the power consumption of the write operation can be reduced. Furthermore, due to the low power consumption of the write operation, for a memory including multiple memory arrays, the controller can concurrently access instructions to the multiple memory arrays of the memory based on the memory's power consumption, thereby flexibly allocating bandwidth and power consumption among the multiple memory arrays, thereby meeting the needs of more applications.

[0013] In another possible implementation scenario, the write instruction further indicates that data of a specified length can be written in one or more time periods according to the power consumption of the memory.

[0014] When a write instruction indicates that data of a specified length can be written in multiple time periods according to the power consumption of the memory, the memory can select to write part of the data of the specified length in each of the multiple time periods according to the overall power consumption of the memory, so as to achieve the purpose of reducing the overall power consumption of the memory.

[0015] In another possible implementation scenario, the write instruction further indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

[0016] When the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, by not performing the write operation on the storage address, the operation time of the write operation indicated by the write instruction can be effectively reduced, thereby achieving fast writing to the memory, and shortening the instruction interval corresponding to the write instruction, so that other data can be written using the saved time, reducing the write latency of the memory and improving the write bandwidth of the memory.

[0017] Furthermore, the data of the specified length may include multiple identical data. For example, when the data is represented by binary values, the data of the specified length is data consisting of multiple binary values 1, or the data of the specified length is data consisting of multiple binary values 0.

[0018] At this time, by specifying the length in the write instruction, it is possible to send one write instruction to indicate the writing of data of the specified length. Compared with the write instructions in the related art that indicate the same and fixed length of the data to be written, there is no need to send multiple write instructions to indicate writing, thereby reducing the number of write instructions that need to be sent.

[0019] In a second aspect, the present application provides a data writing device for a memory, which includes: a receiving module for receiving a write instruction from a controller instructing to write data of a specified length to the memory; and an access module for writing data of a specified length to the storage medium of the memory based on the write instruction.

[0020] Optionally, the memory includes multiple storage arrays, and data access processes between the multiple storage arrays do not affect each other. Writing data to the storage array is achieved by controlling the bit lines and word lines connected to the storage array. The specified length is reflected by any one or more of the following: the total number of bit lines with consecutive addresses that need to be controlled for writing data based on a write instruction, the total number of word lines with consecutive addresses that need to be controlled for writing data based on a write instruction, and the total number of storage arrays with consecutive addresses to which data is written based on a write instruction.

[0021] Optionally, the write instruction further indicates that the current value of the current signal used to perform the write operation indicated by the write instruction is smaller than a reference value, and the reference value is the current value of the current signal used to perform the write operation indicated by the write instruction without indicating a current value.

[0022] Optionally, the write instruction further indicates that data of a specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

[0023] Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data the write instruction indicates to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data the write instruction indicates to be written to the storage address, no write operation is performed on the storage address.

[0024] Optionally, the data of the specified length is data consisting of multiple binary values 1, or the data of the specified length is data consisting of multiple binary values 0.

[0025] In a third aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores program instructions, and the processor runs the program instructions to execute the method provided in the first aspect of the present application and any possible implementation thereof.

[0026] In a fourth aspect, the present application provides a computer-readable storage medium, which is a non-volatile computer-readable storage medium, and the computer-readable storage medium includes program instructions. When the program instructions are executed on a computer device, the computer device executes the method provided in the first aspect of the present application and any possible implementation thereof.

[0027] In a fifth aspect, the present application provides a computer program product comprising instructions, which, when run on a computer, enables the computer to execute the method provided in the first aspect of the present application and any possible implementation thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of an application scenario involving a method for writing data into a memory provided in an embodiment of the present application;

[0029] Figure 2 This is a schematic diagram of transmitting a write instruction and data to be written provided by an embodiment of the present application;

[0030] Figure 3 This is another schematic diagram of transmitting a write instruction and data to be written provided by an embodiment of the present application;

[0031] Figure 4 This is a schematic diagram of the structure of a memory provided by an embodiment of the present application;

[0032] Figure 5 This is a schematic diagram of the structure of a storage component provided in an embodiment of the present application;

[0033] Figure 6 is a schematic diagram of a storage array provided in an embodiment of the present application;

[0034] Figure 7 This is a flow chart of a method for writing data into a memory provided by an embodiment of the present application;

[0035] Figure 8 1 is a schematic structural diagram of a data writing device for a memory provided in an embodiment of the present application;

[0036] Figure 9 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0038] Currently, in the field of storage technology, when a controller writes data to a storage medium of a memory, the controller needs to send a write instruction and data to be written to the memory to instruct the storage medium of the memory to write the data to be written. In addition, the length of the data to be written that can be indicated by the write instruction sent by the controller to the same memory is the same and is a fixed value. Therefore, when the same data (for example, 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by one write instruction, the controller needs to send multiple write instructions and data, resulting in a large overhead for writing data. In addition, since the improvement of the memory write bandwidth (especially the write bandwidth of continuous writing to the same storage array) is restricted by the instruction interval (time write to write, tW2W), when a large number of instructions need to be sent, the execution interval that needs to be waited is long, resulting in the write bandwidth of the memory being affected. Among them, the memory includes one or more storage arrays (banks), and the data access processes between the multiple storage arrays do not affect each other.

[0039] An embodiment of the present application provides a method for writing data to a memory. The method includes: the memory receives a write instruction from a controller instructing the memory to write data of a specified length, and the memory writes data of the specified length to the storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when data of a specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0040] Figure 1 Schematic diagram of the structure of the implementation environment involved in the method for writing data into the memory provided in the embodiment of the present application. Figure 1 As shown, the implementation environment includes: a processor 01 and a storage system 02. Optionally, the storage system 02 can be a memory chip. In addition, the storage system 02 includes a controller 021 and a memory 022. A communication connection is established between the processor 01 and the controller 021, and a communication connection is established between the controller 021 and the memory 022. The processor 01 is used to indicate a write request to the controller 021, that is, to notify the controller 021 of the logical address of the data to be written. The controller 021 is used to determine the physical address for writing the data to be written according to the instruction of the processor 01, and to send a write instruction to the memory 022 according to the physical address and the data to be written. The memory 022 is used to write the data to be written to the corresponding physical address according to the write instruction.

[0041] Optionally, the processor 01 may be a hardware chip, which may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. Alternatively, the processor 01 may be a general-purpose processor, such as a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.

[0042] The memory 022 may be a non-volatile memory (NVM) such as a phase change memory (PCM), a spin transfer torque memory (STT-RAM), or a resistive random-access memory (RRAM). The embodiment of the present application is described by taking the memory 022 as a phase change memory as an example. Phase change memory is a new type of non-volatile semiconductor memory based on sulfur compounds. The memory 022 includes a plurality of memory cells. The storage medium of each memory cell is implemented using a phase change material, which utilizes the difference in electrical properties between the crystalline and amorphous states of the phase change material to store 0 / 1 bit information. Among them, the high-resistance amorphous state is defined as the write 0 state (i.e., the RESET (0) state), and the low-resistance crystalline state is defined as the write 1 state (i.e., the SET (1) state, also known as the erase 1 state). The write 0 state is obtained by performing a write operation on the memory cell. The write operation is achieved by applying a high-amplitude and narrow-width electric pulse to the memory cell. Under the action of this electric pulse, the temperature of the phase change material is rapidly raised to above the melting temperature and then suddenly cooled. Since the microscopic atoms of the phase change material do not have sufficient time to crystallize during this process, the phase change material remains in a high-resistance amorphous state. The erased state is obtained by performing an erase operation on the memory cell. The erase operation is achieved by applying an electric pulse with a lower amplitude than the write operation electric pulse but a relatively longer duration to the memory cell. Under the action of this electric pulse, the temperature of the phase change material is raised to above the crystallization temperature and below the melting temperature. During this process, the phase change material can be transformed into a low-resistance state through a thermally induced crystallization process. The read operation of the phase change memory 022 is achieved by applying an electric pulse with a lower amplitude than both the write operation electric pulse and the erase operation electric pulse to the memory cell. Under the action of this electric pulse, the resistance value information of the phase change material is sensed by the read circuit in the form of current or voltage, thereby achieving a read operation on the memory cell. Among them, since both the write operation and the erase operation write data to the memory cell, the write operation in the embodiment of the present application does not distinguish between a write operation and an erase operation.

[0043] In an embodiment of the present application, the memory 022 can be used as a memory for temporarily storing data required for the operation of the processor 01. Accordingly, the controller 021 can be a memory controller. And an application scenario of the data writing method of the memory 022 provided in the embodiment of the present application can be: the processor 01 generates operation data during operation, and the operation data needs to be stored in the memory. In this application scenario, the collaborative process between the processor 01, the controller 021 and the memory includes: the processor 01 indicates to the controller 021 that the operation data needs to be stored, the controller 021 obtains the operation data, and determines the storage address for storing the operation data in the storage space of the memory, and then sends a write instruction and operation data to the memory according to the operation data and the storage address, and the memory stores the operation data at the corresponding storage address according to the write instruction.

[0044] Among them, the write instruction and the data to be written can be sent through different ports. For example, when it is necessary to send the write instruction and the operation data to the memory, such as Figure 2 and Figure 3 As shown, port 1 can be used to send a write instruction to the memory, and port 2 can be used to send operation data to the memory. In addition, the write instruction can include the write instruction itself for indicating the write operation and the storage address for storing the data to be written. In one implementation, the write instruction itself and the storage address can be sent to the memory through the same port. For example, Figure 2 As shown, the write instruction itself and the storage address can be sent to the memory using port 1. Alternatively, the write instruction itself and the storage address can be sent to the memory through different ports. For example, Figure 3 As shown, port 1 can be used to send the write instruction itself to the memory, and port 3 can be used to send the storage address to the memory.

[0045] In one possible implementation, Figure 4 As shown, the memory 022 includes: a storage component 0221, a drive circuit 0222, a control component 0223, and an input / output (I / O) port 0224. The implementation process of the data writing method of the memory 022 provided in the embodiment of the present application can be implemented through the collaboration of the control component 0223, the drive circuit 0222, the storage component 0221, and the I / O port 0224. Among them, the control component 0223 is used to determine the control parameters required to perform the access operation indicated by the write instruction, and instruct the drive circuit 0222 to provide a drive signal to the storage component 0221 according to the control parameters. The storage component 0221 is used to write data under the drive signal.

[0046] like Figure 5As shown, the storage component 0221 includes one or more storage arrays (banks) 0221a, and the data access processes between the multiple storage arrays 0221a do not affect each other, that is, each storage array 0221a can accept read and write instructions independently or in parallel and complete the corresponding operations. Each storage array 0221a includes multiple storage cells a1. Each storage cell a1 is connected to a word line (word line, WL) and a bit line (bit line, BL), and at least one of the word lines and bit lines connected to different storage cells a1 is different. The read and write operations on different storage cells a1 can be achieved by applying electrical signals to the word lines and bit lines connected to the corresponding storage cells a1. And when at least one of the word lines and bit lines to which the electrical signals are applied during the read and write operations is different, the storage cells a1 affected by the read and write operations are different. For example, as Figure 6 As shown, memory array 0221a is crisscrossed with multiple bit lines BL and word lines WL. The word lines WL are arranged sequentially along the columns, with each word line WL extending along the rows. Each memory cell a1 is connected to a bit line BL and a word line WL, respectively. Different memory cells a1 are connected to at least one different word line WL or bit line BL.

[0047] In one possible implementation, Figure 6 As shown, the memory cell a1 includes a variable resistor R and a gating device T connected in series. The variable resistor R is used as a storage medium of the memory cell a1 for storing information. In addition, the material used to make the variable resistor R includes a phase change material. One end of the variable resistor R is connected to the bit line BL, the other end of the variable resistor R is connected to the first port of the gating device T, and the word line WL is connected to the second port of the gating device T. The voltage difference between the word line WL and the bit line BL determines the opening and closing of the loop between the bit line and the word line. When the voltage difference between the word line WL and the bit line BL is greater than a specific threshold voltage, the loop between the two is opened. When the loop between the bit line and the word line is opened, the electrical signal applied to the bit line BL can be transmitted to the variable resistor R, and the data writing and reading of the variable resistor R can be realized under the control of the electrical signal.

[0048] It should be understood that the above content is an illustrative description of the application scenarios of the data writing method for the memory provided in the embodiment of the present application, and does not constitute a limitation on the application scenarios of the event analysis method. Ordinary technicians in this field know that as business needs change, its application scenarios can be adjusted according to application needs, and the embodiments of the present application do not list them one by one.

[0049] Below Figure 1 Taking the application scenario shown in the figure as an example, the implementation process of the data writing method of the memory provided by the embodiment of the present application is described. Figure 7As shown, the implementation process of the data writing method of the memory may include the following steps:

[0050] Step 701: The memory receives a write instruction from a controller instructing the memory to write data of a specified length into the memory.

[0051] According to the aforementioned content, the storage system includes a controller and a memory, and the controller is configured to send write instructions to the memory. For example, when the memory is used as a memory, the processor is configured to instruct the controller that computation data needs to be stored. After obtaining the computation data, the controller can determine a storage address within the memory space for storing the computation data. The controller then sends the write instruction and the computation data to the memory based on the computation data and the storage address, so that the memory stores the computation data at the corresponding storage address according to the write instruction.

[0052] Because the memory includes multiple memory arrays, the data access processes between the multiple memory arrays do not affect each other. Writing data to the memory arrays is achieved by controlling the bit lines and word lines of the memory arrays. Furthermore, each bit line corresponds to an address range, with different bit lines corresponding to different address ranges. The addresses corresponding to multiple bit lines connected to the same memory array constitute a segment of the address range of the memory array. Each word line corresponds to an address range, with different word lines corresponding to different address ranges. The addresses corresponding to multiple word lines connected to the same memory array constitute a segment of the address range of the memory array. Furthermore, each memory array corresponds to an address range, with different memory arrays corresponding to different address ranges. The addresses corresponding to multiple memory arrays in the same memory array constitute a segment of the address range of the memory. Therefore, the specified length can be reflected by any one or more of the following: the total number of bit lines with consecutive addresses that need to be controlled for writing data based on a write instruction, the total number of word lines with consecutive addresses that need to be controlled for writing data based on a write instruction, and the total number of memory arrays with consecutive addresses to which data is written based on a write instruction.

[0053] In one implementation, the bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when the memory is subjected to bit line scanning. Typically, the plurality of bit lines with consecutive addresses are sequentially deployed on the memory array. Furthermore, for every two adjacent bit lines, the first address of the latter bit line may be equal to the maximum address of the previous bit line + 1. For example, Figure 6 As shown, the bit lines BL(1), BL(2) and BL(3) on the memory array are continuously arranged bit lines, and when the memory is subjected to bit line scanning, electrical signals are applied to the bit lines BL(1), BL(2) and BL(3) in sequence, so the bit lines BL(1), BL(2) and BL(3) are bit lines with continuous addresses.

[0054] In one implementation, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is scanned. Typically, the plurality of word lines with consecutive addresses are sequentially deployed on the memory array. Furthermore, for every two adjacent word lines, the first address of the latter word line may be equal to the maximum address of the previous word line + 1. For example, Figure 6 As shown, word line WL(1), word line WL(2) and word line WL(3) on the memory array are word lines arranged continuously, and when the memory is word line scanned, electrical signals are applied to word line WL(1), word line WL(2) and word line WL(3) in sequence, so word line WL(1), word line WL(2) and word line WL(3) are word lines with continuous addresses.

[0055] In one implementation, the storage arrays with consecutive addresses can be multiple storage arrays to which data is written sequentially when data needs to be written sequentially to multiple storage arrays in the memory. Typically, multiple storage arrays with consecutive addresses are deployed sequentially on the memory. Furthermore, for every two storage arrays with adjacent logical addresses, the first address of the latter storage array can be equal to the maximum address of the previous storage array + 1. For example, Figure 5 As shown, the storage component 0221 includes multiple storage arrays 0221a arranged in sequence, and when data is continuously written to the multiple storage arrays 0221a in the storage component 0221, data is written to the storage array 0221a(1) and the storage array 0221a(2) in sequence, so the storage array 0221a(1) and the storage array 0221a(2) are storage arrays with consecutive addresses.

[0056] In an embodiment of the present application, data of a specified length may include multiple identical data. For example, when the data is represented by a binary value, the data of the specified length may be data consisting of multiple binary values 1, or the data of the specified length may be data consisting of multiple binary values 0. In this case, by specifying the length in the write instruction, it is possible to instruct the writing of the data of the specified length by sending a single write instruction. Compared to the write instructions in the related art that indicate the length of the data to be written is the same and is a fixed value, there is no need to send multiple write instructions to instruct the writing, thereby reducing the number of write instructions that need to be sent.

[0057] In one implementation, the write instruction may further indicate that the current value of the current signal used to perform the write operation indicated by the write instruction is less than a reference value. The reference value is the current value of the current signal used to perform the write operation indicated by the write instruction without indicating a current value. Because performing a write operation on a memory cell requires applying a current pulse signal to the bit line connected to the memory cell and applying a gate enable voltage signal to the word line connected to the memory cell, the electrical properties of the storage medium of the memory cell are changed under the action of the signals, thereby facilitating the storage of information through the changed electrical properties. Therefore, when the write instruction does not indicate a current value, the current value of the current pulse signal applied to the bit lines connected to all memory cells in the same memory array can be the same, and this current value can be the reference value. When the current value of the current signal used to perform the write operation indicated by the write instruction is less than the reference value, it is equivalent to the write instruction instructing the write operation to be performed using a smaller current or a transient operating current. In one implementation, performing a write operation using a smaller current or a transient operating current can be achieved by reducing the number of bits being written at the same time.

[0058] By using a write instruction to instruct the current value of the current signal used to perform a write operation to be less than a reference value, the power consumption of the write operation can be reduced. Furthermore, due to the low power consumption of this write operation, for a memory including multiple storage arrays, the controller can concurrently access instructions to the multiple storage arrays of the memory based on the power consumption of the memory, thereby flexibly allocating bandwidth and power consumption among the multiple storage arrays, thereby meeting more application requirements. Because this write instruction instructs the use of a smaller current or transient operating current to perform a write operation, the power consumption of the write operation can be reduced, and this write instruction can also be referred to as a low-power write instruction.

[0059] In another possible implementation, the write instruction may further indicate that data of a specified length may be written in one or more time periods based on the memory's power consumption. The memory's power consumption includes the sum of the power consumption of multiple storage arrays within the memory. When the write instruction indicates that data of a specified length may be written in multiple time periods based on the memory's power consumption, the memory may select, based on the overall power consumption of the memory, to write a portion of the data of the specified length in each of the multiple time periods, thereby reducing the overall power consumption of the memory. Since writing data in accordance with the instructions of this write instruction can also reduce the memory's power consumption, this write instruction may also be referred to as a low-power write instruction.

[0060] In another possible implementation, the write instruction may further indicate that: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, a write operation is not performed on the storage address. For example, assuming that the data stored at a certain storage address is all 1, and the write instruction indicates that when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, a write operation is not performed on the storage address. Then, when the write operation indicated by the write instruction is executed, when the data to be written to the bit of the storage address is 0, the data stored in the bit needs to be refreshed to 0; when the data to be written to the bit of the storage address is 1, no operation is performed on the bit. Since no operation needs to be performed on the bit at this time, fast writing to the memory can be achieved.

[0061] When the data stored at a storage address is the same as the data to be written to the storage address as instructed by a write instruction, by not performing a write operation on the storage address, the operation time of the write operation instructed by the write instruction can be effectively reduced, thereby achieving fast write to the memory. This can shorten the instruction interval corresponding to the write instruction, so that other data can be written using the saved time, reducing the write latency of the memory and improving the write bandwidth of the memory. Because this write instruction can reduce the operation time of executing the write operation, it can be called a fast write instruction.

[0062] Corresponding to the fast write instruction, a possible application scenario may be: before performing a write operation on a continuous address of the memory, the controller instructs the memory to pre-write all the continuous addresses to a uniform value, so that when the memory performs a write operation according to a subsequent write instruction received, it only needs to operate on the bits that are different from the data stored in the continuous address and the data indicated by the write instruction. For example, during the idle period of a certain storage array of the memory, the controller can control the memory to write all the bits of the continuous address of the specified length of the storage array to a uniform value by indicating a write instruction or a low-power write instruction to write data of a specified length, so that when the controller receives an urgent data write request, it can use a fast write instruction to perform a write operation in the continuous address. The uniform value can be set according to the performance of the memory. For example, when the memory writes 0 quickly and writes 1 slowly, the uniform value can be 1.

[0063] In addition, the write instruction can also directly specify the data to be written, such as specifying to write a binary value 1 or 0. By instructing the write instruction to write a binary value 1 of a specified length or a binary value 0 of a specified length, it is not necessary to transmit the data to be written through the data bus, which can reduce the power consumption of data transmission. At this time, the write instruction can also be called a write 1 instruction or a write 0 instruction, or it can also be called an instruction to write a specified length of 0 or an instruction to write a specified length of 1. Similarly, the above-mentioned low-power write instruction can also be called a low-power write 1 instruction or a low-power write 0 instruction, or it can also be called a low-power write instruction of a specified length of 0 or a low-power write instruction of a specified length of 1. The above-mentioned fast write instruction can also be called a fast write 1 instruction or a fast write 0 instruction, or it can also be called a fast write instruction of a specified length of 0 or a fast write instruction of a specified length of 1.

[0064] Step 702: The memory writes data of a specified length to a storage medium of the memory based on a write instruction.

[0065] After receiving the write instruction from the controller, the memory executes the write operation according to the write instruction, writing the data to be written to the storage medium of the memory. Furthermore, when the content of the write operation instruction varies, the implementation method of executing the write operation varies slightly. The following describes the implementation methods of executing the corresponding write operations in various situations for various implementation methods of the write instruction in step 701.

[0066] In the first case, when the specified length of the write instruction is reflected based on the total number of consecutive bit lines of the address that need to be controlled by the write instruction to write data, the memory can find the first storage address indicated by the write instruction according to the hierarchy of the storage array, word line and bit line according to the write instruction, and then perform the write operation on the first storage address, and then add one to the address of the bit line to find the second storage address indicated by the write instruction, and then perform the write operation on the second storage address, and so on, traverse and perform the write operation according to the hierarchy of the bit line, word line and storage array until the write operation indicated by the write instruction is completed.

[0067] In the second case, when the specified length of the write instruction is reflected based on the total number of consecutive word lines of addresses that need to be controlled by the write instruction to write data, the memory can find the first storage address indicated by the write instruction according to the levels of the storage array, word line and bit line according to the write instruction, and then perform the write operation on the first storage address, and then add one to the address of the word line to find the second storage address indicated by the write instruction, and then perform the write operation on the second storage address, and so on, traverse and perform the write operation according to the levels of word line, bit line and storage array until the write operation indicated by the write instruction is completed.

[0068] In the third case, when the specified length of the write instruction is based on the total number of consecutive memory array addresses that need to be controlled by the write instruction to write data, the memory, in the process of executing the write operation indicated by the write instruction, can find the first memory address indicated by the write instruction according to the write instruction in sequence through the levels of the memory array, bit line, and word line, and then perform the write operation on the first memory address, and then increase the address of the memory array by one to find the second memory address indicated by the write instruction, and then perform the write operation on the second memory address, and so on, traversing and performing the write operation according to the levels of the memory array, bit line, and word line until the write operation indicated by the write instruction is completed. For example, Figure 5 The arrow b1 in FIG. 1 is the direction in which the storage address of the storage array 0021a increases. Figure 6 The arrow b2 in FIG. 1 is a direction in which the bit line BL on the memory array 0221a is scanned, that is, a direction in which the storage address of the bit line BL increases. Figure 6 The arrow b3 in FIG. 1 is a scanning direction for the word line WL on the memory array 0221 a , that is, a direction in which the storage address of the word line WL increases. The memory array, the bit line, and the word line can be traversed in this order.

[0069] In the fourth case, when the data of the specified length in the write instruction includes multiple identical data, the memory can directly refresh the bits of the storage address of the specified length indicated by the write instruction to the identical data according to the write instruction during the process of executing the write operation indicated by the write instruction.

[0070] In the fifth case, when the write instruction also indicates that the current value of the current signal used to perform the write operation indicated by the write instruction is less than the reference value, the memory can apply a current pulse signal to the bit line connected to the storage unit indicated by the write instruction during the process of executing the write operation indicated by the write instruction, and the current value of the current pulse signal is less than the reference value, and apply a selection enable voltage signal to the word line connected to the storage unit to complete the write operation indicated by the write instruction.

[0071] In the sixth case, when the write instruction also indicates that data of a specified length can be written in one or more time periods according to the power consumption of the memory, the memory can predict the overall power consumption of the memory during the process of executing the write operation indicated by the write instruction, and write the data indicated by the write instruction in one or more time periods when the overall power consumption of the memory is lower, thereby achieving the purpose of reducing the overall power consumption of the memory.

[0072] In the seventh case, when the write instruction is the above-mentioned fast write instruction, during the process of executing the write operation indicated by the write instruction, for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, the memory may perform the write operation on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, the memory may not perform the write operation on the storage address.

[0073] It should be noted that in the actual application of the memory, the write instruction can be a combination of part or all of the above-mentioned multiple implementation methods. When the write instruction is a combination of the above-mentioned multiple implementation methods, when the memory performs a write operation, it can perform the write operation based on the combination of the write instruction implementation methods and comprehensively use the above-mentioned situations corresponding to the write instruction implementation methods. The implementation process will not be repeated here.

[0074] Step 703: The memory feeds back a write response to the write instruction to the controller.

[0075] After the memory responds to a write command, it can provide a write response to the write command to the controller, thereby providing feedback to the controller on whether the write operation indicated by the write command has been completed. It should be noted that the memory can also not provide a write response to the controller. In this case, the controller can determine the execution result of the write command through other means. For example, a command delay can be defined. If the controller does not receive feedback from the memory within a specified period of time after sending the write command, it determines that the write operation has not been completed.

[0076] In summary, in the data writing method of the memory provided in the embodiment of the present application, the memory receives a write instruction from the controller to write data of a specified length to the memory, and the memory writes data of the specified length to the storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when data of a specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0077] It should be noted that the order of the steps in the method for writing data to a memory provided in the embodiments of the present application can be adjusted appropriately, and the number of steps can be increased or decreased accordingly. Any person skilled in the art who can easily conceive of a modified method within the technical scope disclosed in this application should be included in the scope of protection of this application, and therefore will not be described in detail.

[0078] The embodiment of the present application also provides a device for writing data into a memory. Figure 8 As shown, the data writing device 80 of the memory includes:

[0079] The receiving module 801 is configured to receive a write instruction from a controller instructing the controller to write data of a specified length into a memory.

[0080] The access module 802 is configured to write data of a specified length to a storage medium of the memory based on a write instruction.

[0081] Optionally, the memory includes multiple storage arrays, and data access processes between the multiple storage arrays do not affect each other. Writing data to the storage array is achieved by controlling the bit lines and word lines connected to the storage array. The specified length is reflected by any one or more of the following: the total number of bit lines with consecutive addresses that need to be controlled for writing data based on a write instruction, the total number of word lines with consecutive addresses that need to be controlled for writing data based on a write instruction, and the total number of storage arrays with consecutive addresses to which data is written based on a write instruction.

[0082] Optionally, the write instruction further indicates that the current value of the current signal used to perform the write operation indicated by the write instruction is smaller than a reference value, and the reference value is the current value of the current signal used to perform the write operation indicated by the write instruction without indicating a current value.

[0083] Optionally, the write instruction further indicates that data of a specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

[0084] Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data the write instruction indicates to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data the write instruction indicates to be written to the storage address, no write operation is performed on the storage address.

[0085] Optionally, the data of the specified length is data consisting of multiple binary values 1, or the data of the specified length is data consisting of multiple binary values 0.

[0086] In summary, in the data writing device of the memory provided in the embodiment of the present application, the receiving module receives a write instruction from the controller to write data of a specified length to the memory, and the writing module writes data of the specified length to the storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when data of a specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. In addition, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0087] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding contents in the aforementioned method embodiments and will not be repeated here.

[0088] An embodiment of the present application provides a computer device. Figure 1 The storage system shown can be deployed in the computing device. The computing device includes a memory and a processor, wherein the memory stores program instructions, and the processor executes the program instructions to execute the method for writing data to the memory provided in the present application or execute any step of the method for writing data to the memory provided in the present application.

[0089] Figure 9 Schematic diagram of the structure of a computer device 90 provided in an embodiment of the present application. Figure 9 As shown, the computer device 90 includes a memory 901, a processor 902, a communication interface 903, and a bus 904. The memory 901, the processor 902, and the communication interface 903 are communicatively connected to each other via the bus 904. Furthermore, the computer device 90 may include multiple processors 902, so that the functions of the above-mentioned different functional modules can be implemented by different processors.

[0090] The memory 901 can be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 901 can store executable code sequences. When the executable code stored in the memory 901 is executed by the processor 902, the processor 902 and the communication interface 903 are used to execute the data writing method for the memory provided in the embodiment of the present application. The memory 901 can also include software modules and data required for other running processes such as the operating system.

[0091] The processor 902 may be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits.

[0092] The processor 902 may also be an integrated circuit chip with signal processing capabilities. During implementation, some or all of the functions of the memory data writing method of the present application may be performed by hardware integrated logic circuits or software instructions in the processor 902. The aforementioned processor 902 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application may be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or the like. The storage medium is located in the memory 901, and the processor 902 reads the information in the memory 901 and completes the data writing method of the memory in the embodiment of the present application in combination with its hardware.

[0093] The communication interface 903 uses a transceiver module, such as, but not limited to, a transceiver, to enable communication between the computer device 90 and other devices or a communication network. For example, the communication interface 903 can be any one or a combination of the following devices: a network interface (such as an Ethernet interface), a wireless network card, or other device with network access capabilities.

[0094] The bus 904 may include a path for transmitting information between various components of the computer device 90 (eg, the memory 901 , the processor 902 , and the communication interface 903 ).

[0095] It should be noted that, when the computer device is a client, the computer device further includes a display screen, which is used to display a graphical user interface of the program development platform.

[0096] The descriptions of the processes corresponding to the above figures have different focuses. For parts that are not described in detail in a certain process, please refer to the relevant descriptions of other processes.

[0097] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product providing a program development platform includes one or more computer instructions, and when these computer program instructions are loaded and executed on a computer device, all or part of the process or function of the method for writing data to a memory provided in the embodiments of the present application is implemented.

[0098] The computer device may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium stores computer program instructions that provide a platform for program development.

[0099] An embodiment of the present application also provides a computer-readable storage medium, which is a non-volatile computer-readable storage medium. The computer-readable storage medium includes program instructions. When the program instructions are executed on a computer device, the computer device executes the data writing method for the memory provided in the embodiment of the present application.

[0100] An embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method for writing data into a memory provided in an embodiment of the present application.

[0101] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0102] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, storage, and display, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the resistance value information involved in this application was obtained with full authorization.

[0103] In the embodiments of the present application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "plurality" refers to two or more, unless otherwise expressly limited.

[0104] In this application, the term "and / or" simply describes an association between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0105] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the concepts and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for writing data into a memory, characterized in that: The method comprises: The memory receives a write instruction from the controller instructing the memory to write data of a specified length and a specified type, wherein the specified type indicates that the data is composed of a plurality of binary values 1, or the specified type indicates that the data is composed of a plurality of binary values 0; The memory writes the data of the specified length and the specified type to the storage medium of the memory based on the write instruction.

2. The method according to claim 1, characterized in that The memory includes multiple storage arrays, and data access processes between the multiple storage arrays do not affect each other. Writing data to the storage arrays is achieved by controlling the bit lines and word lines connected to the storage arrays. The specified length is reflected by any one or more of the following: the total number of bit lines with consecutive addresses that need to be controlled for writing data based on the write instruction, the total number of word lines with consecutive addresses that need to be controlled for writing data based on the write instruction, and the total number of storage arrays with consecutive addresses to which data is written based on the write instruction.

3. The method according to claim 1 or 2, characterized in that The write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, where the reference value is a current value of a current signal used to perform a write operation indicated by a write instruction that does not indicate a current value.

4. The method according to claim 1 or 2, characterized in that The write instruction further indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

5. The method according to claim 3, characterized in that The write instruction further indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

6. The method according to any one of claims 1, 2 and 5, characterized in that: The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

7. The method according to claim 3, characterized in that The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

8. The method according to claim 4, characterized in that The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

9. A data writing device for a memory, characterized in that: The device comprises: a receiving module, configured to receive a write instruction from a controller instructing the memory to write data of a specified length and a specified type, wherein the specified type indicates that the data is composed of a plurality of binary values 1, or the specified type indicates that the data is composed of a plurality of binary values 0; An access module is configured to write the data of the specified length and the specified type to the storage medium of the memory based on the write instruction.

10. The device according to claim 9, characterized in that The memory includes multiple storage arrays, and data access processes between the multiple storage arrays do not affect each other. Writing data to the storage arrays is achieved by controlling the bit lines and word lines connected to the storage arrays. The specified length is reflected by any one or more of the following: the total number of bit lines with consecutive addresses that need to be controlled for writing data based on the write instruction, the total number of word lines with consecutive addresses that need to be controlled for writing data based on the write instruction, and the total number of storage arrays with consecutive addresses to which data is written based on the write instruction.

11. The device according to claim 9 or 10, characterized in that The write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, where the reference value is a current value of a current signal used to perform a write operation indicated by a write instruction that does not indicate a current value.

12. The device according to claim 9 or 10, characterized in that The write instruction further indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

13. The device according to claim 11, characterized in that The write instruction further indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

14. The device according to any one of claims 9, 10 and 13, characterized in that: The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

15. The device according to claim 11, characterized in that The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

16. The device according to claim 12, characterized in that The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

17. A method for writing data into a memory, characterized in that: The method comprises: The controller generates a write instruction, the write instruction including an instruction to write data of a specified length and an instruction to write data of a specified type, the specified type indicating that the data is data consisting of a plurality of binary values 1, or the specified type indicating that the data is data consisting of a plurality of binary values 0; The controller sends the write instruction to the memory to instruct the memory to write the data of the specified length and the specified type into the storage medium of the memory.

18. The method according to claim 17, characterized in that The memory includes multiple storage arrays, and the data access processes between the multiple storage arrays do not affect each other. The memory writes data to the storage array by controlling the bit lines and word lines connected to the storage array. The specified length is reflected by any one or more of the following: the total number of address-contiguous bit lines that the memory needs to control to write data based on the write instruction, the total number of address-contiguous word lines that the memory needs to control to write data based on the write instruction, and the total number of address-contiguous storage arrays to which data is written based on the write instruction.

19. The method according to claim 17 or 18, characterized in that The write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, where the reference value is a current value of a current signal used to perform a write operation indicated by a write instruction that does not indicate a current value.

20. The method according to claim 17 or 18, characterized in that The write instruction further indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

21. The method according to claim 19, wherein The write instruction further indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

22. The method according to any one of claims 17, 18 and 21, characterized in that: The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

23. The method according to claim 19, wherein The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

24. The method according to claim 20, characterized in that The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored at the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

25. A controller connected to a memory, characterized in that The controller is configured to execute the method according to any one of claims 17 to 24.

26. A storage system, characterized in that: The method comprises a memory and a controller, wherein the memory is used to execute the method according to any one of claims 1 to 8, and the controller is used to execute the method according to any one of claims 17 to 24.

27. A computer-readable storage medium, characterized in that The method comprises program instructions, which, when executed on a computer device, cause the computer device to execute the method according to any one of claims 1 to 8 or the method according to any one of claims 17 to 24.

28. A computer program product, characterized in that When the computer program product is run on a computer, the computer is enabled to perform the method according to any one of claims 1 to 8 or the method according to any one of claims 17 to 24.

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