Memory access method and device

Abstract

The invention discloses a memory access method and device, and belongs to the technical field of memories. The method comprises the steps that the memory receives an access instruction of a controller indicating to access a specified address of the memory, the access instruction carries a configuration value of a control parameter, and the control parameter is used for influencing an access result of the specified address; the memory performs an access operation indicated by the access instruction based on the configuration value. The access instruction carries the configuration value of the control parameter, and the control parameter is used for influencing the access result of the specified address, so that the control parameter can be optimized through the configuration value, the access result of the memory is influenced, and the performance optimization of the memory is facilitated.

Description

[0001] This application is a divisional application. The application number of the original application is 202210191674.9, and the original application date is February 28, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of memory technology, and in particular to a memory access method and device. Background Art

[0003] The memory usually includes multiple memory cells. Each memory cell is connected to a word line (WL) and a bit line (BL), and at least one of the word lines and bit lines connected to different memory cells is different. The read and write operations on different memory cells can be achieved by applying electrical signals to the word lines and bit lines connected to the corresponding memory cells.

[0004] Typically, the parameters of the electrical signals applied to the word lines and bit lines are all default values ​​set by the memory manufacturer, which is not conducive to the performance optimization of the memory. Summary of the invention

[0005] The present application provides a method and device for accessing a memory. The present application can influence the access result of the memory by optimizing the control parameters through the configuration value, which is beneficial to the performance optimization of the memory. The technical solution provided by the present application is as follows:

[0006] In a first aspect, the present application provides a method for accessing a memory, which includes: a memory receiving controller instructs an access instruction to access a specified address of the memory, the access instruction carries a configuration value of a control parameter, and the control parameter is used to affect the access result of the specified address; the memory executes the access operation indicated by the access instruction based on the configuration value.

[0007] In the memory access method provided in the present application, the memory receives an access instruction from a controller to access a specified address of the memory, and performs the access operation indicated by the access instruction based on the configuration value. Since the access instruction carries the configuration value of the control parameter, the control parameter is used to affect the access result of the specified address, and the control parameter can be optimized through the configuration value, such as optimizing the control parameter according to the drift of the storage characteristics of the storage unit, thereby affecting the access result of the memory, which is beneficial to the performance optimization of the memory, such as improving the operation success rate of the memory.

[0008] Optionally, the control parameter is used to indicate the pulse used to perform the access operation. That is, the control parameter can indicate the characteristics of the pulse used to perform the access operation. For example, the control parameter is used to indicate: the width and / or height of a rectangular wave pulse, or the total number of steps of a step wave pulse, the height and / or width of a single step.

[0009] By carrying the configuration value of the control parameter for indicating the pulse in the access instruction, the control parameter can be optimized through the configuration value, such as optimizing the control parameter according to the drift of the storage characteristic of the storage unit, thereby affecting the access result of the memory, which is beneficial to the performance optimization of the memory.

[0010] And / or, the control parameter is used to indicate an additional function used in performing the access operation. That is, the control parameter can indicate whether to use an additional function in performing the access operation, and what additional function to use. Optionally, the additional function includes any one or more of the following: a write pre-read function, a write path compensation function, a write temperature compensation function, a voltage write 0 function, a read path compensation function, a read temperature compensation function, a multiple read XOR function, and a read word line voltage zero bias function.

[0011] The write path compensation function means that according to the length of the write path of the write operation, the amplitude of the current pulse signal applied to the bit line connected to the storage unit is adjusted so that the writing results are the same when the same content is written to different storage units. Similarly, the read path can also be compensated in the process of reading data from the memory, that is, the read path compensation function is turned on to ensure the accuracy of the read data.

[0012] The write temperature compensation function is mainly used for memories whose access results are affected by temperature, such as phase change memories. When the current overall temperature of the memory affects the accuracy of the access results to the memory, the overall temperature of the memory needs to be compensated. Similarly, the overall temperature of the memory can also be compensated during the process of reading data from the memory, that is, the read temperature compensation function is turned on to ensure the accuracy of the read data.

[0013] The voltage write 0 function means that when 0 needs to be written into a memory cell, a voltage pulse signal is applied to the bit line connected to the memory cell.

[0014] The multiple read XOR function means that after the memory receives a read instruction, it continuously performs two read processes on the storage address indicated by the read instruction, and the read voltages used in the two read processes are different. When the results of the two reads are XORed to 1, it is determined that the data stored in the current storage address is unreliable. When the results of the two reads are XORed to 0, it is determined that the data stored in the current storage address is reliable.

[0015] The zero bias function of the read word line voltage means that for any memory array, after receiving an access instruction that carries only the bit line address but not the word line address, the voltage applied to the word lines connected to all the memory cells in the memory array can be biased to 0 level or near 0 level, and then a read operation is performed on this basis. When the read current value of the bit line indicated by the bit line address is higher than a certain threshold value, it can be determined that the bit line has a leakage fault.

[0016] As an implementable manner, the access instruction may carry a parameter set, which may include: configuration values ​​of one or more control parameters. When the parameter set does not carry the names of one or more control parameters, the memory and the controller may pre-agree which control parameter configuration values ​​are carried in the access instruction, and the position of the carried control parameter configuration values ​​in the access instruction. Alternatively, the parameter set may include: one or more control parameters and their configuration values. At this time, the memory and the controller may pre-agree on the correspondence between the control parameters and their identifiers. When the memory receives the access instruction, it may determine the control parameters and their configuration values ​​carried by it according to the identifiers in the parameter set. Optionally, the configuration value may be expressed in absolute or relative terms. When the configuration value is expressed in relative terms, the memory and the controller may pre-agree on the reference value of each control parameter. After the memory receives the access instruction, it may obtain the absolute value of the configuration value according to the relative value and the reference value in the access instruction.

[0017] In addition, the access instruction may carry an instruction prefix. The instruction prefix is ​​used to indicate the type of the access instruction. The types of access instructions include read instructions and / or write instructions. Alternatively, the types of access instructions may be further subdivided. For example, the types of access instructions may include: read instructions and / or write instructions that use absolute values ​​to represent configuration values, read instructions and / or write instructions that use relative values ​​to represent configuration values, and read instructions and / or write instructions that carry control parameters indicating additional functions used in the access operation. Furthermore, the memory and the controller may pre-agree on the correspondence between the type of the access instruction and its identifier. When the memory receives the access instruction, the type of the access instruction may be determined based on the identifier of the type of the access instruction.

[0018] In a second aspect, a memory access device is provided, which includes: a receiving module, used to receive an access instruction from a controller to access a specified address of the memory, the access instruction carries a configuration value of a control parameter, and the control parameter is used to affect the access result of the specified address; an access module, used to execute the access operation indicated by the access instruction based on the configuration value.

[0019] Optionally, the control parameter is used to indicate a pulse and / or additional function to be used for performing the access operation.

[0020] Optionally, the control parameter is used to indicate: the width and / or height of a rectangular wave pulse, or the total number of steps of a step wave pulse, the height and / or width of a single step.

[0021] Optionally, the additional functions include any one or more of the following: write pre-read function, write path compensation function, write temperature compensation function, voltage write 0 function, read path compensation function, read temperature compensation function, multiple read XOR function, and read word line voltage zero bias function.

[0022] Optionally, the access instruction carries a parameter set, and the parameter set includes: configuration values ​​of one or more control parameters, or one or more control parameters and their configuration values.

[0023] Optionally, the configuration value is expressed as an absolute value or a relative value.

[0024] Optionally, the access instruction carries an instruction prefix, and the instruction prefix is ​​used to indicate the type of the access instruction, and the type of the access instruction includes a read instruction and / or a write instruction.

[0025] Optionally, the access instruction carries an instruction prefix, which is used to indicate the type of the access instruction, and the types of access instructions include: read instructions and / or write instructions that use absolute values ​​to represent configuration values, read instructions and / or write instructions that use relative values ​​to represent configuration values, and read instructions and / or write instructions that carry control parameters indicating additional functions used by the access operation.

[0026] In a third aspect, the present application provides a computer device including a memory and a processor, wherein the memory stores program instructions, and the processor runs the program instructions to execute the method provided in the first aspect of the present application and any possible implementation thereof.

[0027] In a fourth aspect, the present application provides a computer-readable storage medium, which is a non-volatile computer-readable storage medium, and the computer-readable storage medium includes program instructions. When the program instructions are executed on a computer device, the computer device executes the method provided in the first aspect of the present application and any possible implementation thereof.

[0028] In a fifth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method provided in the first aspect of the present application and any possible implementation thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of an application scenario involved in a memory access method provided in an embodiment of the present application;

[0030] Figure 2 It is a schematic diagram of transmitting a write instruction and data to be written provided by an embodiment of the present application;

[0031] Figure 3 It is a schematic diagram of another method of transmitting a write instruction and data to be written provided in an embodiment of the present application;

[0032] Figure 4 is a schematic diagram of the structure of a memory provided by an embodiment of the present application;

[0033] Figure 5is a structural diagram of a storage component provided in an embodiment of the present application;

[0034] Figure 6 is a schematic diagram of a storage array provided in an embodiment of the present application;

[0035] Figure 7 is a flow chart of a method for accessing a memory provided in an embodiment of the present application;

[0036] Figure 8 is a schematic diagram of a rectangular wave pulse provided in an embodiment of the present application;

[0037] Fig. 9 is a schematic diagram of a step wave pulse provided in an embodiment of the present application;

[0038] Fig.10 is a schematic diagram of another step wave pulse provided in an embodiment of the present application;

[0039] Fig.11 It is a schematic diagram of sending an access instruction using a clock signal provided by an embodiment of the present application;

[0040] Fig.12 It is a structural diagram of a memory access device provided in an embodiment of the present application;

[0041] Fig.13 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0043] At present, in the field of memory technology, a memory generally includes a plurality of memory cells. Each memory cell is connected to a word line and a bit line, and at least one of the word lines and bit lines connected to different memory cells is different. The read and write operations on different memory cells can be achieved by applying electrical signals to the word lines and bit lines connected to the corresponding memory cells. However, since the parameters of the electrical signals applied on the word lines and bit lines are all default values ​​set by the memory manufacturer, it is not conducive to the performance optimization of the memory.

[0044] An embodiment of the present application provides a method for accessing a memory. The method includes: the memory receives an access instruction from a controller indicating access to a specified address of the memory, and performs the access operation indicated by the access instruction based on a configuration value. The access instruction carries a configuration value of a control parameter, and the control parameter is used to affect the access result of the specified address. In this method, since the access instruction carries the configuration value of the control parameter, the access result of the memory can be affected by the configuration value, which is beneficial to the performance optimization of the memory.

[0045] Figure 1 Schematic diagram of the structure of the implementation environment involved in the memory access method provided in the embodiment of the present application. Figure 1 As shown, the implementation environment includes: a processor 01 and a storage system 02. Optionally, the storage system 02 can be a storage chip. In addition, the storage system 02 includes a controller 021 and a memory 022. A communication connection is established between the processor 01 and the controller 021, and a communication connection is established between the controller 021 and the memory 022. The processor 01 is used to indicate the access requirement to the controller 021. That is, when the access requirement is a requirement to read data, the processor 01 notifies the controller 021 of the logical address of the data to be read that needs to be read, and when the access requirement is a requirement to write data, the processor 01 notifies the controller 021 of the logical address of the data to be written that needs to be written. The controller 021 is used to determine the physical address that needs to be accessed, such as the physical address of the data to be read or the physical address of the data to be written, according to the instruction of the processor 01, and send an access instruction to the memory 022 according to the physical address. The memory 022 is used to access the memory 022 according to the access instruction, such as reading the data to be read in the corresponding physical address, or writing the data to be written to the corresponding physical address.

[0046] Optionally, the processor 01 may be a hardware chip, which may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. Alternatively, the processor 01 may be a general-purpose processor, such as a central processing unit (CPU), a network processor (NP), or a combination of a CPU and a NP.

[0047] The memory 022 may be a non-volatile memory (NVM) such as a phase change memory (PCM), a spin transfer torque memory (shared transistor technology random access memory, STT-RAM), or a resistive random-access memory (RRAM). The embodiment of the present application is described by taking the memory 022 as a phase change memory as an example. Phase change memory is a new type of non-volatile semiconductor memory based on sulfur compounds. The memory 022 includes a plurality of memory cells. The storage medium of each memory cell is implemented by a phase change material, which utilizes the difference in electrical properties between the crystalline and amorphous states of the phase change material to store 0 / 1 bit information. Among them, the high-resistance amorphous state is defined as a write 0 state (i.e., RESET (0) state), and the low-resistance crystalline state is defined as a write 1 state (i.e., SET (1) state, also called erase 1 state). The write 0 state is obtained by performing a write operation on the memory cell. The write operation is achieved by applying a high-amplitude and narrow-width electrical pulse to the memory cell. Under the action of this electric pulse, the temperature of the phase change material is rapidly raised to above the melting temperature and then suddenly cooled. Since the microscopic atoms of the phase change material do not have sufficient time to crystallize in this process, the phase change material remains in a high-resistance amorphous state. The erase state is obtained by performing an erase operation on the storage unit. The erase operation is achieved by applying an electric pulse with a lower amplitude than the electric pulse of the write operation but a relatively long duration to the storage unit. Under the action of this electric pulse, the temperature of the phase change material is raised to above the crystallization temperature and below the melting temperature, and the phase change material can be transformed into a low-resistance state through a thermal crystallization process in this process. The read operation of the phase change memory 022 is achieved by applying an electric pulse with a lower amplitude than the electric pulse of the write operation and the electric pulse of the erase operation to the storage unit. Under the action of this electric pulse, the resistance information of the phase change material is sensed by the read circuit in the form of current or voltage, thereby realizing the read operation of the storage unit. Among them, since both the write operation and the erase operation write data to the storage unit, the write operation in the embodiment of the present application does not distinguish between a write operation and an erase operation.

[0048] In an embodiment of the present application, the memory 022 can be used as a memory for temporarily storing data required for the operation of the processor 01. Correspondingly, the controller 021 can be a memory controller. And an application scenario of the access method of the memory 022 provided in the embodiment of the present application can be: the processor 01 generates operation data during operation, and the operation data needs to be stored in the memory, and the processor 01 needs to read the memory data required for the operation from the memory during operation. In the scenario of writing data to the memory, the collaborative process between the processor 01, the controller 021 and the memory includes: the processor 01 indicates to the controller 021 that the operation data needs to be stored, the controller 021 obtains the operation data, and determines the storage address for storing the operation data in the storage space of the memory, and then sends a write instruction and operation data to the memory according to the operation data and the storage address, and the memory stores the operation data at the corresponding storage address according to the write instruction. In the scenario of reading memory data from the memory, the collaborative process between the processor 01, the controller 021 and the memory includes: the processor 01 indicates to the controller 021 the logical address of the memory data to be read, the controller 021 determines the storage address for storing the memory data in the storage space of the memory, and then sends a read instruction to the memory according to the storage address, and the memory reads the memory data from the corresponding storage address according to the read instruction.

[0049] When data needs to be written to the memory, the write instruction and the data to be written can be sent through different ports. For example, when a write instruction and operation data need to be sent to the memory, Figure 2 and Figure 3 As shown, port 1 can be used to send a write instruction to the memory, and port 2 can be used to send operation data to the memory. In addition, the write instruction can include the write instruction itself for indicating the write operation and the storage address for storing the data to be written. In an implementable manner, the write instruction itself and the storage address can be sent to the memory through the same port. For example, Figure 2 As shown, the write instruction itself and the storage address can be sent to the memory using port 1. Alternatively, the write instruction itself and the storage address can be sent to the memory via different ports. For example, Figure 3 As shown, port 1 can be used to send the write instruction itself to the memory, and port 3 can be used to send the storage address to the memory. Similarly, when data needs to be read from the memory, the read instruction can include the read instruction itself for indicating the read operation and the storage address for storing the data to be read. In an implementable manner, the read instruction itself and the storage address can be sent to the memory through the same port. Alternatively, the read instruction itself and the storage address can be sent to the memory through different ports.

[0050] In one possible implementation, Figure 4As shown, the memory 022 includes: a storage component 0221, a driving circuit 0222, a control component 0223 and an input / output (I / O) port 0224. The implementation process of the access method of the memory 022 provided in the embodiment of the present application can be implemented in collaboration with the control component 0223, the driving circuit 0222, the storage component 0221 and the I / O port 0224. Among them, the control component 0223 is used to determine the control parameters required for the access operation indicated by the access instruction, and instruct the driving circuit 0222 to provide a driving signal to the storage component 0221 according to the control parameters. The storage component 0221 is used to read and write data under the drive of the driving signal.

[0051] like Figure 5 As shown, the storage component 0221 includes one or more storage arrays (banks) 0221a, and the data access processes between the multiple storage arrays 0221a do not affect each other, that is, each storage array 0221a can accept read and write instructions independently or in parallel and complete the corresponding operations. Each storage array 0221a includes multiple storage cells a1. Each storage cell a1 is connected to a word line (word line, WL) and a bit line (bit line, BL), and at least one of the word lines and bit lines connected to different storage cells a1 is different. The read and write operations on different storage cells a1 can be achieved by applying electrical signals to the word lines and bit lines connected to the corresponding storage cells a1. And when at least one of the word lines and bit lines to which the electrical signals are applied during the read and write operations is different, the storage cells a1 acted upon by the read and write operations are different. For example, as Figure 6 As shown, a plurality of bit lines BL and a plurality of word lines WL are arranged in a crisscross pattern on the memory array 0221a. The plurality of word lines WL are arranged in sequence along the column direction, and each word line WL extends in the row direction. The plurality of bit lines BL are arranged in sequence along the row direction, and each bit line BL extends in the column direction. Each memory cell a1 is connected to a bit line BL and a word line WL, respectively, and at least one of the word lines WL and the bit lines BL connected to different memory cells a1 is different.

[0052] In one possible implementation, Figure 6As shown, the memory cell a1 includes a variable resistor R and a gating device T connected in series. The variable resistor R is used as a storage medium of the memory cell a1 for storing information. In addition, the material used to make the variable resistor R includes a phase change material. One end of the variable resistor R is connected to the bit line BL, the other end of the variable resistor R is connected to the first port of the gating device T, and the word line WL is connected to the second port of the gating device T. The voltage difference between the word line WL and the bit line BL determines the opening and closing of the loop between the bit line and the word line, such as when the voltage difference between the word line WL and the bit line BL is greater than a specific threshold voltage, the loop between the two is opened. When the loop between the bit line and the word line is opened, the electrical signal applied to the bit line BL can be transmitted to the variable resistor R, and the data writing and reading of the variable resistor R can be realized under the control of the electrical signal.

[0053] It should be understood that the above content is an illustrative description of the application scenarios of the memory access method provided in the embodiment of the present application, and does not constitute a limitation on the application scenarios of the event analysis method. A person of ordinary skill in the art will know that as business needs change, its application scenarios can be adjusted according to application needs, and the embodiments of the present application do not list them one by one.

[0054] Below Figure 1 Taking the application scenario shown in FIG. 1 as an example, the implementation process of the memory access method provided in the embodiment of the present application is described. Figure 7 As shown, the implementation process of the memory access method may include the following steps:

[0055] Step 701: A memory receives an access instruction from a controller to access a specified address of the memory. The access instruction carries a configuration value of a control parameter, and the control parameter is used to affect the access result of the specified address.

[0056] According to the foregoing, the storage system includes a controller and a memory, the controller is used to send an access instruction to the memory, and the memory is used to perform an access operation in the memory according to the access instruction. The access instruction can be a read instruction or a write instruction. Accordingly, the access operation can be a read operation or a write operation. The access result can be the content read from the memory by executing the read operation, or the content written in the memory by executing the write operation.

[0057] Optionally, the control parameter is used to indicate the pulse used to perform the access operation. That is, the control parameter may indicate the characteristics of the pulse used to perform the access operation. For one access operation, the pulse used to perform the access operation may be a rectangular wave pulse or a step wave pulse. Figure 8 As shown, the characteristics of the rectangular wave pulse can be represented by the width W1 and / or height H1 of the rectangular wave pulse. Fig. 9 and Fig.10As shown, the characteristics of the step wave pulse can be represented by the total number of steps of the step wave pulse, the height H2 and / or the width W2 of a single step. By carrying the configuration value of the control parameter for indicating the pulse through the access instruction, the control parameter can be optimized through the configuration value, such as optimizing the control parameter according to the drift of the storage characteristic of the storage unit, thereby affecting the access result of the memory, which is beneficial to the performance optimization of the memory.

[0058] And / or, the control parameter is used to indicate the additional function used to perform the access operation. That is, the control parameter can indicate whether to use the additional function to perform the access operation, and what additional function to use. Optionally, the additional function may include any one or more of the following: write pre-read function, write path compensation function, write temperature compensation function, voltage write 0 function, read path compensation function, read temperature compensation function, multiple read XOR function, and read word line voltage zero bias function. Each function is described below:

[0059] The write pre-read function means: before executing a write operation according to a write instruction (such as before a write pulse occurs), pre-read the data stored in the storage address indicated by the write instruction, and determine whether the stored data and the data to be written indicated by the write instruction are the same. When the stored data and the data to be written are the same, the write operation indicated by the write instruction is not executed. When the stored data and the data to be written are different, the write operation indicated by the write instruction is executed. When it is determined through the write pre-read function that the write operation indicated by the write instruction does not need to be executed, the total number of storage units that need to perform the actual write operation can be reduced, and the power consumption of the memory can be effectively reduced.

[0060] Furthermore, since the read operation can be realized by applying an electric pulse to the storage cell so that the resistance of the storage cell is sensed in the form of voltage, different read voltage thresholds can be set for the read process to affect the result of the pre-reading, thereby achieving different operation effects. For example, when the set read voltage is higher than the voltage threshold corresponding to the unreliable 0, the unreliable 0 stored in the storage cell will be read as 1, so in addition to the original storage cell storing 1, the storage cell storing unreliable 0 also needs to be refreshed; when the set read voltage is lower than the voltage threshold corresponding to the unreliable 1, the unreliable 1 stored in the storage cell will be read as 0, so in addition to the original storage cell storing 0, the storage cell storing unreliable 1 also needs to be refreshed. In this way, the unreliable data stored in the storage cell can be refreshed to reliable data, and the subsequent reading errors caused by the threshold voltage drift of the unreliable data can be prevented, thereby improving the reliability of the memory. Among them, the voltage threshold corresponding to the reliable 1 is lower than the voltage threshold corresponding to the unreliable 1, the voltage threshold corresponding to the unreliable 1 is lower than the voltage threshold corresponding to the unreliable 0, and the voltage threshold corresponding to the unreliable 0 is lower than the voltage threshold corresponding to the reliable 0.

[0061] The write path compensation function refers to: adjusting the amplitude of the current pulse signal applied to the bit line connected to the storage unit according to the length of the write path of the write operation, so that the write results when the same content is written to different storage units are the same. The write operation is implemented by applying an electrical signal to the word line and the bit line connected to the storage unit, and both the word line and the bit line have a loop, which is the write path for performing the write operation. When the storage units indicated by the write instruction are different, the length of the write path corresponding to the write operation indicated by the write instruction is different, and accordingly, the parasitic resistance on the write path is different. At this time, if the electrical signal is applied to the word line and the bit line according to the same standard, even if the same content is written to different storage units, the write results will be different. Therefore, by turning on the write path compensation function during the write process, this situation can be avoided. In one achievable method, the implementation method of the write path compensation function includes: when performing a write operation on a storage unit with a shorter write path, applying a current pulse signal with a smaller amplitude to the bit line; when performing a write operation on a storage unit with a longer write path, applying a current pulse signal with a larger amplitude to the bit line. Similarly, the read path may be compensated in the process of reading data from the memory, that is, the read path compensation function may be enabled to ensure the accuracy of the read data.

[0062] The write temperature compensation function is mainly aimed at memories whose access results will be affected by temperature, such as phase change memories. When the current overall temperature of the memory affects the accuracy of the access results to the memory, the overall temperature of the memory needs to be compensated. For example, for phase change memory, temperature will affect the crystallization state of the phase change memory, and the crystallization state will affect the access results of the phase change memory. Therefore, when the overall temperature of the phase change memory affects the accuracy of access to it, it is necessary to adjust the overall temperature of the phase change memory, that is, to compensate for the overall temperature of the phase change memory. Similarly, the overall temperature of the memory can also be compensated in the process of reading data from the memory, that is, the read temperature compensation function is turned on to ensure the accuracy of the read data.

[0063] The voltage write 0 function means that when it is necessary to write 0 to the memory cell, a voltage pulse signal is applied to the bit line connected to the memory cell. Since the voltage pulse signal is more powerful and easier to operate, if a voltage pulse signal is applied to the bit line during the data writing process, the success rate of writing data to the memory cell is higher. However, since the power consumption requirements of applying a voltage pulse signal are higher, usually the write operation is to apply a current pulse signal to the bit line. Therefore, in scenarios where the write success rate needs to be improved, you can choose to turn on the voltage write 0 function. Similarly, in some scenarios, the function of writing 1 to the memory cell can also be achieved by applying a voltage pulse signal to the bit line.

[0064] The multiple read XOR function means that after the memory receives the read instruction, it continuously performs two read processes on the storage address indicated by the read instruction, and the read voltages used in the two read processes are different. When the results of the two reads are XORed to 1, it is determined that the data stored at the current storage address is unreliable. When the results of the two reads are XORed to 0, it is determined that the data stored at the current storage address is reliable. In one implementable method, for the read voltages used in the two read processes, one read voltage is higher than the voltage threshold corresponding to unreliable 0 and lower than the voltage threshold corresponding to reliable 0, and the other read voltage is lower than the voltage threshold corresponding to unreliable 1 but higher than the voltage threshold corresponding to reliable 1. By turning on the multiple read XOR function, data with higher reliability can be read out, thereby improving the reliability of the read process. It should be noted that the read voltages used in the two read processes can be adjusted according to application requirements to achieve the purpose of on-demand monitoring of the reliability of the memory.

[0065] The zero bias function of the read word line voltage means that for any storage array, after receiving an access instruction that only carries the bit line address but not the word line address, the voltage applied to the word lines connected to all storage cells in the storage array can be biased to 0 level or near 0 level, and then a read operation is performed on this basis. When the read current value of the bit line indicated by the bit line address is higher than a certain threshold, it can be determined that the bit line has a leakage fault. At this time, since all the word lines on the bit line are not selected, the read circuit actually reads the leakage current on the selected bit line. Therefore, the read value can be used to evaluate whether there is a leakage fault on this bit line. It should be noted that when implementing the zero bias function of the read word line voltage, the amplitude of the voltage applied to the word line and the bit line and the read delay when reading data can also be adjusted according to application requirements to achieve flexible monitoring of leakage and other conditions of the storage array, evaluate the health status of the memory, and thus improve the reliability of the storage array.

[0066] As an implementable manner, the access instruction may carry a parameter set, which may include: one or more configuration values ​​of control parameters. When the parameter set does not carry the name of one or more control parameters, the memory and the controller may pre-agreed which configuration values ​​of control parameters are carried in the access instruction, and the position of the configuration values ​​of the carried control parameters in the access instruction. For example, the memory and the controller may pre-agreed: the control parameters carried in the access instruction are the width and height of the rectangular wave pulse, and the p1 to p2 bits of the access instruction carry the configuration value of the width of the rectangular wave pulse, and the p3 to p4 bits of the access instruction carry the configuration value of the height of the rectangular wave pulse. Alternatively, the parameter set may include: one or more control parameters and their configuration values. At this time, the memory and the controller may pre-agreed the corresponding relationship between the control parameters and their identifiers, and when the memory receives the access instruction, it may determine the control parameters and their configuration values ​​carried by it according to the identifier in the parameter set. It should be noted that the control parameters included in the parameter set may be adjusted according to application requirements. Moreover, the number of bits occupied by the control parameters and their configuration values ​​in the access instruction may be adjusted according to application requirements, and the number of bits occupied by different control parameters and their configuration values ​​in the same access instruction may be the same or different. For example, the configuration value of each control parameter in the access instruction may occupy 2 bits, or the configuration value of one control parameter in the access instruction may occupy 2 bits and the configuration value of another control parameter may occupy 3 bits.

[0067] Optionally, the configuration value may be expressed as an absolute value, or may be expressed as a relative value. When the configuration value is expressed as a relative value, the memory and the controller may pre-agreed on a reference value for each control parameter, and after receiving the access instruction, the memory may obtain the absolute value of the configuration value according to the relative value and the reference value in the access instruction.

[0068] In addition, the access instruction may carry an instruction prefix. The instruction prefix is ​​used to indicate the type of the access instruction. The types of access instructions include read instructions and / or write instructions. Alternatively, the types of access instructions may be further subdivided. For example, the types of access instructions may include: read instructions and / or write instructions that use absolute values ​​to represent configuration values, read instructions and / or write instructions that use relative values ​​to represent configuration values, and read instructions and / or write instructions that carry control parameters indicating additional functions used in the access operation. In addition, the memory and the controller may pre-agree on the correspondence between the type of access instruction and its identifier. When the memory receives the access instruction, the type of the access instruction may be determined based on the identifier of the type of the access instruction. By way of example, the correspondence between the type of access instruction and its identifier may be as shown in Table 1.

[0069] Table 1

[0070] Type identifier of access instruction Type of access instruction 0000 Read instructions that use absolute values ​​to represent configuration values 0001 Write instructions that use relative values ​​to represent configuration values 0010 Read instructions that use absolute values ​​to represent configuration values 0011 Write instructions that use relative values ​​to represent configuration values 0100 Read instruction indicating additional functions 0101 Write instruction indicating additional functions 0110 General read instruction 0111 General write instructions 1XXX Other instructions

[0071] For the access instruction in the embodiment of the present application, it can include the access instruction itself for indicating the access operation and the storage address to be accessed. In one implementable manner, the access instruction itself and the storage address can be sent to the memory through different ports. At this time, the content of the access instruction can include an instruction prefix and a parameter set arranged in sequence. Alternatively, the access instruction itself and the storage address can be sent to the memory through the same port. At this time, the content of the access instruction can include an instruction prefix, a storage address and a parameter set arranged in sequence. Among them, the number of bits occupied by each part of the content in the access instruction can be set according to application requirements. For example, the number of bits occupied by the instruction prefix can be set according to the size of the instruction set, such as four bits. For another example, the number of bits occupied by the storage address can be set according to the actual capacity of the memory.

[0072] In addition, if Fig.11 As shown, when a clock signal is used to send an access instruction, considering the width M of the access instruction and the total number of ports K of the storage address, the access instruction needs to contain at least M / K (when M can divide K) or [M / K]+1 (when M cannot divide K) instruction beats. And when the total length of the actual content of the access instruction is less than an integer multiple of the instruction beat, it is necessary to add 0 after the actual content of the access instruction, so that the total length of the access instruction after adding 0 is equal to an integer multiple of the instruction beat. Among them, one instruction beat is one clock cycle or half a clock cycle, Fig.11 The diagram shows that one instruction beat is one clock cycle. [x] represents the rounding operation performed on x.

[0073] Step 702: The memory executes the access operation indicated by the access instruction based on the configuration value.

[0074] After receiving the access instruction sent by the controller, the memory can perform the access operation according to the access instruction. In addition, when the access instruction carries a configuration value of the control parameter, the memory can intervene in the access operation according to the configuration value. For example, when the control parameter carried by the access instruction is used to indicate a pulse used to perform the access operation, the pulse indicated by the configuration value can be applied to the storage unit. When the control parameter carried by the access instruction is used to indicate an additional function used to perform the access operation, the corresponding additional function can be enabled. Among them, the above step 701 describes the implementation method of the additional function, which will not be repeated here.

[0075] Step 703: The memory feeds back an access response to the access instruction to the controller.

[0076] After the memory executes the access operation indicated by the access instruction, it can feed back an access response to the access instruction to the controller to feedback whether the access operation is completed. It should be noted that the memory may not feed back the access response to the controller, in which case the controller can determine the execution result of the access instruction in other ways. For example, an instruction delay can be defined, and when the controller does not receive feedback from the memory within a specified time period after sending a write instruction, it is determined that the access operation is not completed.

[0077] In summary, in the memory access method provided in the embodiment of the present application, the memory receives an access instruction instructing the controller to access the specified address of the memory, and executes the access operation indicated by the access instruction based on the configuration value. Since the access instruction carries the configuration value of the control parameter, the control parameter is used to affect the access result of the specified address, and the control parameter can be optimized through the configuration value, such as optimizing the control parameter according to the drift of the storage characteristics of the storage unit, thereby affecting the access result of the memory, which is beneficial to the performance optimization of the memory, such as improving the operation success rate of the memory.

[0078] It should be noted that the order of steps of the memory access method provided in the embodiment of the present application can be appropriately adjusted, and the steps can be increased or decreased accordingly according to the situation. Any technician familiar with the technical field can easily think of a change within the technical scope disclosed in this application, and all of them should be included in the protection scope of this application, so they will not be repeated here.

[0079] The present application also provides a memory access device. Fig.12 As shown, the memory access device 120 includes:

[0080] The receiving module 1201 is used to receive an access instruction from a controller to access a specified address of a memory, the access instruction carries a configuration value of a control parameter, and the control parameter is used to affect the access result of the specified address.

[0081] The access module 1202 is used to execute the access operation indicated by the access instruction based on the configuration value.

[0082] Optionally, the control parameter is used to indicate a pulse and / or additional function to be used for performing the access operation.

[0083] Optionally, the control parameter is used to indicate: the width and / or height of a rectangular wave pulse, or the total number of steps of a step wave pulse, the height and / or width of a single step.

[0084] Optionally, the additional functions include any one or more of the following: write pre-read function, write path compensation function, write temperature compensation function, voltage write 0 function, read path compensation function, read temperature compensation function, multiple read XOR function, and read word line voltage zero bias function.

[0085] Optionally, the access instruction carries a parameter set, and the parameter set includes: configuration values ​​of one or more control parameters, or one or more control parameters and their configuration values.

[0086] Optionally, the configuration value is expressed as an absolute value or a relative value.

[0087] Optionally, the access instruction carries an instruction prefix, and the instruction prefix is ​​used to indicate the type of the access instruction, and the type of the access instruction includes a read instruction and / or a write instruction.

[0088] Optionally, the access instruction carries an instruction prefix, which is used to indicate the type of the access instruction, and the types of access instructions include: read instructions and / or write instructions that use absolute values ​​to represent configuration values, read instructions and / or write instructions that use relative values ​​to represent configuration values, and read instructions and / or write instructions that carry control parameters indicating additional functions used by the access operation.

[0089] In summary, in the memory access device provided in the embodiment of the present application, the receiving module receives the access instruction instructing the controller to access the specified address of the memory, and the access module performs the access operation indicated by the access instruction based on the configuration value. Since the access instruction carries the configuration value of the control parameter, the control parameter is used to affect the access result of the specified address, and the control parameter can be optimized through the configuration value, such as optimizing the control parameter according to the drift of the storage characteristics of the storage unit, thereby affecting the access result of the memory, which is beneficial to the performance optimization of the memory, such as improving the operation success rate of the memory.

[0090] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding contents in the aforementioned method embodiments and will not be repeated here.

[0091] An embodiment of the present application provides a computer device. Figure 1 The storage system shown can be deployed in the computing device. The computing device includes a memory and a processor, the memory stores program instructions, and the processor runs the program instructions to execute the memory access method provided in the present application or execute any step of the memory access method provided in the present application.

[0092] Fig.13 1 is a schematic diagram of the structure of a computer device 130 provided in an embodiment of the present application. Fig.13As shown, the computer device 130 includes a memory 1301, a processor 1302, a communication interface 1303 and a bus 1304. The memory 1301, the processor 1302 and the communication interface 1303 are connected to each other through the bus 1304. In addition, the computer device 130 may include multiple processors 1302, so that the functions of the above-mentioned different functional modules can be realized through different processors.

[0093] The memory 1301 may be a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 1301 may store executable code sequences. When the executable code stored in the memory 1301 is executed by the processor 1302, the processor 1302 and the communication interface 1303 are used to execute the memory access method provided in the embodiment of the present application. The memory 1301 may also include software modules and data required for other running processes such as an operating system.

[0094] The processor 1302 may be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits.

[0095] The processor 1302 may also be an integrated circuit chip with signal processing capabilities. In the implementation process, some or all of the functions of the memory access method of the present application may be completed by hardware integrated logic circuits or software instructions in the processor 1302. The above-mentioned processor 1302 may also be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware decoding processor, or may be executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 1301, and the processor 1302 reads the information in the memory 1301 and completes the memory access method of the embodiment of the present application in combination with its hardware.

[0096] The communication interface 1303 uses a transceiver module such as, but not limited to, a transceiver to implement communication between the computer device 130 and other devices or a communication network. For example, the communication interface 1303 can be any one or any combination of the following devices: a network interface (such as an Ethernet interface), a wireless network card, and other devices with network access functions.

[0097] The bus 1304 may include a path for transmitting information between various components of the computer device 130 (eg, the memory 1301 , the processor 1302 , and the communication interface 1303 ).

[0098] It should be noted that, when the computer device is a client, the computer device also includes a display screen, which is used to display a graphical user interface of the program development platform.

[0099] The descriptions of the processes corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process, please refer to the relevant descriptions of other processes.

[0100] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product providing a program development platform includes one or more computer instructions, and when these computer program instructions are loaded and executed on a computer device, the process or function of the memory access method provided in the embodiment of the present application is implemented in whole or in part.

[0101] The computer device may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium stores computer program instructions that provide a program development platform.

[0102] An embodiment of the present application also provides a computer-readable storage medium, which is a non-volatile computer-readable storage medium. The computer-readable storage medium includes program instructions. When the program instructions are executed on a computer device, the computer device executes a method for accessing a memory as provided in an embodiment of the present application.

[0103] The embodiment of the present application also provides a computer program product including instructions. When the computer program product is executed on a computer, the computer executes the memory access method provided by the embodiment of the present application.

[0104] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0105] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the resistance value information involved in this application is obtained with full authorization.

[0106] In the embodiments of the present application, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise expressly defined.

[0107] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0108] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the concept and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for accessing a memory, characterized in that: The method comprises: The memory receives an access instruction from the controller instructing access to a specified address of the memory, wherein the access instruction carries a configuration value of a control parameter; The memory determines, based on the configuration value of the control parameter, an operation mode corresponding to the configuration value, wherein the operation mode is an operation mode for executing an access operation of the access instruction; The memory performs the access operation in the operation mode.

2. The method according to claim 1, characterized in that The control parameters include pulses and / or additional functions used to perform the access operation.

3. The method according to claim 2, characterized in that The pulse used to perform the access operation includes a rectangular wave pulse, and the configuration value includes the width and / or height of the rectangular wave pulse; or, the pulse used to perform the access operation includes a step wave pulse, and the configuration value includes the total number of steps of the step wave pulse, the height and / or width of a single step.

4. The method according to claim 2 or 3, characterized in that: The additional functions include any one or more of the following: write pre-read function, write path compensation function, write temperature compensation function, voltage write 0 function, read path compensation function, read temperature compensation function, multiple read XOR function, and read word line voltage zero bias function.

5. The method according to any one of claims 1 to 4, characterized in that: The configuration value of the control parameter carried by the access instruction is a set of control parameter values, and the set of control parameter values ​​includes: one or more configuration values ​​of the control parameters, or one or more control parameters and their configuration values.

6. The method according to any one of claims 1 to 5, characterized in that: The configuration value is expressed as an absolute value or a relative value.

7. The method according to any one of claims 1 to 6, characterized in that: The access instruction carries an instruction prefix, and the instruction prefix is ​​used to indicate the type of the access instruction, and the type of the access instruction includes a read instruction and / or a write instruction.

8. The method according to any one of claims 1 to 6, characterized in that: The access instruction carries an instruction prefix, which is used to indicate the type of the access instruction. The types of the access instruction include: read instructions and / or write instructions that use absolute values ​​to represent the configuration value, read instructions and / or write instructions that use relative values ​​to represent the configuration value, and read instructions and / or write instructions that carry control parameters indicating additional functions used by the access operation.

9. A memory access device, characterized in that: The device comprises: A receiving module, used for receiving an access instruction from a controller instructing to access a specified address of a memory, wherein the access instruction carries a configuration value of a control parameter; The access module is used to determine the operation mode corresponding to the configuration value based on the configuration value of the control parameter, wherein the operation mode is the operation mode of executing the access operation of the access instruction, and execute the access operation in the operation mode.

10. The device according to claim 9, characterized in that The control parameters include pulses and / or additional functions used to perform the access operation.

11. The device according to claim 10, characterized in that The pulse used to perform the access operation includes the width and / or height of a rectangular wave pulse, or the pulse used to perform the access operation includes a step wave pulse, and the configuration value includes the total number of steps of the step wave pulse, the height and / or width of a single step.

12. The device according to claim 10 or 11, characterized in that The additional functions include any one or more of the following: write pre-read function, write path compensation function, write temperature compensation function, voltage write 0 function, read path compensation function, read temperature compensation function, multiple read XOR function, and read word line voltage zero bias function.

13. The device according to any one of claims 9 to 12, characterized in that: The configuration value of the control parameter carried by the access instruction is a set of control parameter values, and the set of control parameter values ​​includes: one or more configuration values ​​of the control parameters, or one or more control parameters and their configuration values.

14. The device according to any one of claims 9 to 13, characterized in that: The configuration value is expressed as an absolute value or a relative value.

15. The device according to any one of claims 9 to 14, characterized in that: The access instruction carries an instruction prefix, and the instruction prefix is ​​used to indicate the type of the access instruction, and the type of the access instruction includes a read instruction and / or a write instruction.

16. The device according to any one of claims 9 to 14, characterized in that: The access instruction carries an instruction prefix, which is used to indicate the type of the access instruction. The types of the access instruction include: read instructions and / or write instructions that use absolute values ​​to represent the configuration value, read instructions and / or write instructions that use relative values ​​to represent the configuration value, and read instructions and / or write instructions that carry control parameters indicating additional functions used by the access operation.

17. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores program instructions, and the processor runs the program instructions to execute the method according to any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that: The method comprises program instructions, and when the program instructions are executed on a computer device, the computer device is caused to execute the method according to any one of claims 1 to 8.

19. A computer program product, characterized in that When the computer program product is executed on a computer, the computer is enabled to execute the method according to any one of claims 1 to 8.

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