Memory device and operation method thereof

Abstract

The invention discloses a memory device and an operation method thereof. The memory device includes: a plurality of first memory cells each having a first terminal coupled to a first node and a second terminal coupled to a corresponding first bit line of a plurality of first bit lines; a plurality of second memory cells each having a first terminal coupled to a second node and a second terminal coupled to a corresponding second bit line in the plurality of second bit lines; and a driver circuit coupled between the first node and the second node and configured to generate a second voltage at the second node in response to a first voltage at the first node when a memory operation is performed on one of the plurality of first memory cells. The first voltage and the second voltage have different polarities.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a memory device and an operating method thereof, and more particularly to a memory device with a recovery mechanism and an operating method thereof. Background Art

[0002] Ferroelectric random access memory (FeRAM) uses a device structure similar to volatile memory, but achieves non-volatility by utilizing ferroelectric capacitors as storage elements. FeRAM devices can then demonstrate superior performance when compared to both volatile and non-volatile memory devices. Some FeRAM implementations achieve this by dividing the sensing window of a single storage structure multiple times, thereby creating distinct memory states. Summary of the invention

[0003] In some embodiments, a memory device is provided, which includes a plurality of first memory cells, a plurality of second memory cells, and a driver circuit. Each of these first memory cells has a first terminal coupled to a first node and a second terminal coupled to a corresponding first bit line among a plurality of first bit lines. Each of these second memory cells has a first terminal coupled to a second node and a second terminal coupled to a corresponding second bit line among a plurality of second bit lines. The driver circuit is coupled between the first node and the second node and is used to generate a second voltage at the second node in response to a first voltage at the first node when a memory operation is performed on one of these first memory cells, and the first voltage and the second voltage have different polarities.

[0004] In some embodiments, a method for operating a memory device is provided, comprising the following steps: performing a plurality of cycle operations of a first polarity on a first memory cell to restore a first portion of the first memory cell to a first condition, and simultaneously performing a plurality of cycle operations of a second polarity on a first portion of a second memory cell until the first portion of the second memory cell changes to the first condition, the first polarity and the second polarity being different from each other.

[0005] In some embodiments, a memory device is provided, which includes a first memory cell, a driver circuit, a second memory cell, and a control circuit. The first memory cell has a first terminal coupled to a plate wiring and a second terminal coupled to a first bit line. The second memory cell has a first terminal coupled to a second terminal of the driver circuit and a second terminal coupled to a second bit line. The control circuit is used to control a first voltage on the plate wiring to perform a memory operation on a first portion of the first memory cell. The driver circuit is used to generate a second voltage at its second terminal in response to the first voltage to perform a recovery operation on the first portion of the second memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of one embodiment of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a schematic diagram of a memory device according to some embodiments;

[0008] Figure 1B For example, according to some embodiments, Figure 1A a schematic diagram of a portion of a memory device;

[0009] Figure 2 FIG. 1 illustrates a method for performing a multi-layered structure according to some embodiments of the present invention. Figure 1A a portion of a memory device;

[0010] Figure 3 According to some embodiments, Figure 1A to Figure 2 The switching polarization value of the memory cell in the r -V) characteristics;

[0011] Figure 4 FIG. 1 illustrates a method for performing a multi-layered structure according to some embodiments of the present invention. Figure 1A a portion of a ferroelectric capacitor;

[0012] Figure 5 is a diagram illustrating an asymmetric field cycling recovery (AFCR) operation of a memory cell according to some embodiments;

[0013] Figure 6 For illustration Figure 5 A diagram describing the operation of

[0014] 7A to 7C For example, according to some embodiments, Figure 5 to Figure 6 The switching polarization value (Δ2P r)

[0015] FIG. 8A to FIG. 8B According to some embodiments, Figures 1A to 7C The read current-time characteristics, read voltage characteristics and polarity-voltage (PV) characteristics of the Pos.AmL state portion of the memory cell;

[0016] FIG. 9A to FIG. 9B According to some embodiments, Figures 1A to 7C The read current-time characteristics, read voltage characteristics and polarity-voltage (PV) characteristics of the Neg.AmL state part of the memory cell in the embodiment of the present invention are shown in FIG.

[0017]

Explanation of symbols

[0018] 10: Memory Device

[0019] 11: Memory unit

[0020] 12: Memory unit

[0021] 40: Ferroelectric capacitor

[0022] 41~42: Metal electrode

[0023] 43:Resistance pattern

[0024] 44: Interface layer

[0025] 45: Interface layer

[0026] 100:Memory array

[0027] 102:Substrate

[0028] 104: Bottom electrode

[0029] 106: variable resistor pattern

[0030] 108: Top electrode

[0031] 112: Select component

[0032] 120: Sensing circuit

[0033] 125: Column address selection circuit

[0034] 130: row address selection circuit

[0035] 135: Input / output circuit

[0036] 140: Driver circuit

[0037] 141: Inverting Amplifier

[0038] 150: Control circuit

[0039] 301: Positive polarity asymmetric small loop

[0040] 302: Negative polarity asymmetric small loop

[0041] 701~708: Curve

[0042] 801: Hysteresis loop

[0043] 802: Hysteresis loop

[0044] 811~818: Path

[0045] 821: Significant switching current

[0046] 822: Non-switching current

[0047] 823: Non-switching current

[0048] 824: Switching current

[0049] 825: Switching current

[0050] 826: Non-switching current

[0051] 827: Non-switching current

[0052] 828: Significant switching current

[0053] BL0~BLn: bit line

[0054] C FE2 :Ferroelectric Capacitors

[0055] C FE1 :Ferroelectric Capacitors

[0056] CBL: Conductive Blind Connection

[0057] CPL: Conductive wiring

[0058] CWL: Conductive Wiring

[0059] NFE1: Node

[0060] NFE2: Node

[0061] P1~P4: Location

[0062] P81~P87: Polarization state

[0063] PLB: Plate wiring

[0064] PL: Plate wiring

[0065] R1~R2: Resistors

[0066] VN1: Voltage

[0067] VN2: Voltage

[0068] VP1: Voltage

[0069] VP2: Voltage

[0070] VPL1: Voltage

[0071] VPL2: Voltage

[0072] VR: Reverse Voltage

[0073] WL0~WLm: word line DETAILED DESCRIPTION

[0074] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify an embodiment of the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, an embodiment of the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0075] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of an embodiment of the present disclosure or the scope and meaning of any exemplified term. Likewise, an embodiment of the present disclosure is not limited to the various embodiments given in this specification.

[0076] Although the terms "first," "second," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly a second component may be referred to as a first component without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0077] As used herein, the terms "comprising," "including," "having," "containing," "involving," and the like should be construed as open ended, ie, meaning including, but not limited to, including.

[0078] As used herein, "approximately," "about," "roughly," or "substantially" shall generally refer to any approximation or range of a given value, wherein the value or range varies according to the various technologies to which the value is related, and its scope shall be understood in the broadest sense as understood by a person familiar with an embodiment of the present disclosure to cover all such modifications and similar structures. In some embodiments, it shall generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The quantities given herein are approximate, thereby meaning that the terms "roughly," "about," "approximately," or "substantially" may be inferred without explicit statement, or mean other approximate values.

[0079] View now Figure 1A . Figure 1A 1 is a schematic diagram of a memory device 10 according to some embodiments. For illustration, memory array 100 includes memory cells 11 and 12 arranged in rows and columns. Memory cells 11 and 12 can be programmed to store different states. Each of memory cells 11 and 12 can be programmed to store two states labeled as state 0 and state 1. In some embodiments, each of memory cells 11 and 12 is used to store more than two logical states (e.g., three or more values). Figure 1A In the embodiment of the present invention, each of the memory cells 11 includes a ferroelectric capacitor C FE1 , and can be referred to as a ferroelectric memory cell. Each of the memory cells 12 includes a ferroelectric capacitor C FE2 , and can be called a ferroelectric memory cell. Ferroelectric capacitor C FE1 and ferroelectric capacitor C FE2 Having ferroelectric dielectric material. Ferroelectric capacitor C FE1 and ferroelectric capacitor C FE2 The different levels of dipoles in represent different logic states. In some embodiments, the ferroelectric capacitor C FE1 and ferroelectric capacitor C FE2 Some of the ferroelectric materials store a first charge (or a first portion of the charge) associated with the dielectric and a second charge (or a second portion of the charge) associated with the polarity. Ferroelectric materials have nonlinear polarization properties.

[0080] Memory operations such as read operations and write operations are performed on the memory cells 11 and 12 by activating or selecting an appropriate one of the word lines WL0 to WLm and one of the bit lines BL0 to BLn. Activating or selecting a word line or a bit line includes applying a voltage to the respective wiring. The word lines WL0 to WLm and the bit lines BL0 to BLn are made of a conductive material. For example, the word lines WL0 to WLm and the bit lines BL0 to BLn may be made of a metal (such as copper, aluminum, gold, tungsten, etc.), a metal alloy, other conductive materials, or the like. According to Figure 1AIn an example of, each column of memory cells 11 to 12 is connected to one of word lines WL0 to WLm. Each of memory cells 11 has a first terminal coupled to a corresponding bit line of bit lines BL0 to BLk, and a second terminal coupled to plate wiring PL at node NFE1. Each of memory cells 12 has a first terminal coupled to a corresponding bit line of bit lines BL0 to BLn, and a second terminal coupled to plate wiring PLB at node NFE2. By activating a word line such as WL0, a bit line such as BL0, and plate wiring PL (e.g., applying voltage to word line WL0, plate wiring PL, or bit line BL0), a memory cell such as 11 is accessed at its intersection.

[0081] Accessing memory cells 11-12 may include a read operation or a write operation to memory cells 11-12. The intersection of a word line and a bit line is referred to as the address of the memory cell. In some instances, the read operation may include sensing a plurality of levels from a ferroelectric memory. These operations include sensing polarization charge from a memory cell by causing the polarization charge to be received in a sense amplifier and activating the sense amplifier. In some instances, the read operation includes sensing a plurality of levels from a ferroelectric memory based at least in part on the polarity of the dielectric charge and polarization charge from the memory cell. In some instances, the read operation may be performed based at least in part on the polarity of the dielectric charge and polarization charge from the memory cell. In some instances, this read operation may include: accessing a unit to determine the polarity of the dielectric charge at a first time, storing the determined dielectric charge polarity, accessing a unit (i.e., the same or different unit) to determine the polarization charge from the memory cell, and then initiating one or more other actions based on the read as described in various aspects of an embodiment of the present disclosure. In some embodiments, read operations of different charge-related information may be performed simultaneously, in overlapping intervals, consecutively, in consecutive intervals, or in parallel.

[0082] In some embodiments, the logic storage device of the memory cell, for example, a ferroelectric capacitor C FE1 or C FE2 The memory cells 11 to 12 are isolated from the bit lines by a selection element 112. In some embodiments, the selection element 112 comprises a transistor having a gate terminal coupled to the corresponding word line, a source / drain terminal coupled to the cell bottom of the ferroelectric capacitor, and a drain / source terminal coupled to the cell plate of the ferroelectric capacitor.

[0083] In some embodiments, the word line controls the selection element 112. For example, activating a word line such as WL0 causes the ferroelectric capacitor of the memory cell 11, such as C FE1The electrical connection or circuit between the corresponding bit line is then accessed to read or write the memory cell 11.

[0084] Access to memory cells 11-12 is controlled via column address selection circuitry 125 and row address selection circuitry 130. In some embodiments, column address selection circuitry 125 receives a column address from control circuitry 150 and activates the appropriate bit line. Similarly, row address selection circuitry 130 receives a row address from control circuitry 150 and activates the appropriate word line based on the received row address. For example, by enabling word line WL0 and bit line BL0, memory cell 11 can be accessed at its intersection.

[0085] After access, the memory cells 11-12 can be read or sensed by the sensing circuit 120 to determine the stored state of the memory cells 11-12. For example, after accessing one of the memory cells 11-12, the ferroelectric capacitors of these memory cells 11-12 discharge the charge (e.g., polarization charge) to their corresponding bit lines. In some embodiments, the ferroelectric capacitors C FE1 The discharge can be based on bias or by applying a voltage VPL1 to the ferroelectric capacitor C via the plate connection PL. FE1 . Make the ferroelectric capacitor C FE2 The discharge can be based on the bias voltage or by applying a voltage VPL2 to the ferroelectric capacitor C via the plate connection PLB. FE2 .

[0086] like Figure 1A As shown in FIG. 1 , the memory device 10 includes a driver circuit 140 having an input terminal coupled to a node NFE1 and an output terminal coupled to a node NFE2. In some embodiments, when a memory operation, such as a read operation or a write operation, is performed on one of the memory cells 11 to 12, the driver circuit 140 is used to generate a voltage VPL2 at a node NFE2 in response to a voltage VPL1 at n1. The voltage VPL1 and the voltage VPL2 have different polarities. For example, according to some embodiments, the voltage VPL1 has a positive voltage value, and the voltage VPL2 has a negative voltage value. In another embodiment, the voltage VPL2 has a positive voltage value, and the voltage VPL1 has a negative voltage value. In some embodiments, the voltage VPL1 and the voltage VPL2 have the same absolute value.

[0087] In some embodiments, the driver circuit 140 includes an inverting amplifier 141 and resistors R1 to R2. Figure 1B For illustration, the inverting amplifier 141 has a resistor R1 coupled to the plate wiring PL to Figure 1AThe output terminal of the inverting amplifier 141 is at a node NFE1 in the circuit, which receives the voltage VPL1 and also has a positive input terminal coupled to the ground. Figure 1A The resistor R1 is coupled to the board wiring PLB at the node NFE2. Figure 1A The resistor R2 is coupled between the negative input terminal and the node NFE1. Figure 1A The node NFE2 is coupled between the negative input terminal of the inverting amplifier 141 and the node NFE2.

[0088] The discharge induces a change in the voltage of the corresponding bit line, and the sensing circuit 120 compares the voltage change to a reference voltage (not shown) to determine the stored state of the memory cell. For example, when the bit line has a higher voltage than the reference voltage, the sensing circuit 120 determines that the stored state in the memory cell is about a first predetermined logic value. In some embodiments, this first value may include state 1, or may be another value - including other logic values ​​associated with multi-level sensing that enables storage of more than two values ​​(e.g., 3 states per cell or 1.5 bits per cell). In some embodiments, predetermined encoded logic values ​​can be mapped to memory cell states so as to be written to and read from the memory cell, as described with reference to an embodiment of the present disclosure.

[0089] In some embodiments, the sensing circuit 120 includes various transistors or amplifiers to detect and amplify the signal difference, which may be referred to as latching. The detected logic state of the memory cell may then be output via the column address selection circuit 125 and the input / output circuit 135.

[0090] Memory cells 11-12 can be set or written by activating the associated word lines and bit lines. As discussed above, activating the word lines electrically connects the corresponding columns of memory cells 11-12 to their respective bit lines. By controlling the associated bit lines while activating the word lines, one of the memory cells 11-12 is written—that is, a state can be stored in the memory cell. Column address selection circuit 125 receives the data to be written to memory cells 11-12, for example, via input / output circuit 135.

[0091] View now Figure 2 . Figure 2 FIG. 1 illustrates a method for performing a multi-layered structure according to some embodiments of the present invention. Figure 1A In some embodiments, the ferroelectric capacitors C in the memory cells 11 and 12 are FE1 and C FE2 Therefore, the memory unit 11 refers to Figure 2 It is given as an example for illustrative purposes.

[0092] The memory cell 11 includes a substrate 102, a bottom electrode 104 as the cell bottom, a variable resistance pattern 106, and a top electrode 108 as the cell plate, which are sequentially stacked. The bottom electrode 104, the variable resistance pattern 106, and the top electrode 108 constitute a ferroelectric capacitor C for storing memory data. FE1 . The bottom electrode 104 and the top electrode 108 are formed of, for example, a conductive material, such as a metal, an alloy, a compound of a metal, or a stack of metals, alloys, compounds of alloys. Examples of the bottom electrode 104 and the top electrode 108 include suitable conductive materials, such as TaN, TiN, W, Pt, Mo, Ta, Ti, metal silicides, the like, and / or combinations thereof. The bottom electrode 104 and the top electrode 108 may be a single-layer structure, or a multi-layer structure including a plurality of stacked layers of metals and / or metal-containing compounds. In some embodiments, the bottom electrode 104 and the top electrode 108 each have a thickness in the range of about 1 nm to about 1000 nm.

[0093] In some embodiments, the variable resistor pattern 106 is a ferroelectric layer. In some embodiments, the variable resistor pattern 106 may include HfZrO2 (HZO), HAO (HfO2 doped with aluminum), HSO (HfO2 doped with silicon), lead zirconate titanate (PZT), strontium bismuth tantalit (SBT), and aluminum scandium nitride (AlScN). In some embodiments, the variable resistor pattern 106 has Hf 1-x Zr x O2 composition, wherein x is in the range of about 0.5 to 1, and thus may have ferroelectric properties exhibiting a single hysteresis loop. In some embodiments, the variable resistance pattern 106 has a thickness in the range of about 0.1 nm to about 50 nm, such as about 10 nm. In use and operation, when the memory cell 11 is selected to be programmed, a voltage VPL1 having a certain voltage value may be applied to the memory cell 11 to change the polarization state of the variable resistance pattern 106 of the memory cell 11. When the voltage VPL1 is removed, the variable resistance pattern 106 may exhibit polarization. In a read operation of the memory cell 11, the voltage VPL1 having a certain voltage value is used to detect the state of the variable resistance pattern 106.

[0094] The memory device 10 further includes: Figure 1A The conductive connection CBL of the corresponding bit line in Figure 1A The conductive wiring CWL corresponding to the word line in the , and the conductive wiring CPL can serve as the plate wiring PL.

[0095] The configuration of the memory cell 12 is similar to that of the memory cell 11. Specifically, the ferroelectric capacitor C in the memory cell 12 FE2 The unit plate is coupled to the plate wiring PLB, and the unit bottom is coupled to the corresponding bit line. Repeated description is omitted here.

[0096] Figure 3 According to some embodiments, Figure 1A to Figure 2 The switching polarization value of the memory cell 11 or 12 in the r In some embodiments, by performing multiple cycle operations of two different polarities on the memory cells 11 to 12 via the control circuit 150 of the control voltage VPL1, polarization is established in the ferroelectric capacitors in the memory cells 11 to 12, which indicates the state of the data stored in the memory cells 11 to 12.

[0097] For example, if Figure 3 As shown in the positive polarity asymmetric minor loop (Pos.AmL) 301 in FIG. 1 , as the voltage VPL1 applied to the unit plate of the ferroelectric capacitor cycles from the voltage VP1 to the voltage VP2, the ferroelectric capacitor, such as C FE1 , the switching polarization value (Δ2P r ) is extended and reaches half of the full switching polarization value. In some embodiments, half of the full switching polarization value refers to sufficient dipole switching response polarization induced by the reversal field, where the dipole is generated by the "B" atom surrounded by "A" atoms in the variable resistance pattern 106 of the ferroelectric capacitor, moving from position P1 to P2 as shown in the schematic diagram. 1-x Zr x In the embodiment of the variable resistance pattern 106 of O2, the "A" atom represents Hf (Zr) and the "B" atom represents oxygen. In some embodiments, the full (saturated) switching polarization value refers to the polarization of the dipole formed as the "B" atom moves from position P2 to position P4, which can be measured in the main loop of the cycle of the voltage VPL1 from the positive voltage VP1 to the negative voltage VP1.

[0098] In some embodiments, voltage VP1 is referred to as a positive saturation voltage and has a positive voltage value. Voltage VP2 is referred to as a reverse voltage VR and has a negative voltage value. The absolute value of voltage VP1 is greater than the absolute value of voltage VP2. In some embodiments, voltage VP1 is about +3V and corresponds to an electric field of +3MV / cm, and voltage VP2 is about -1V and corresponds to an electric field of -1MV / cm.

[0099] According to another example, Figure 3As shown in the negative polarity asymmetric minor loop (Neg.AmL) 302 in FIG. 1 , as the voltage applied to the unit plate of the ferroelectric capacitor cycles from voltage VN1 to voltage VN2, the switching polarization value (Δ2P r ) is extended and reaches half of the full switching polarization value. In some embodiments, sufficient dipole switching response polarization is induced by a reverse field, wherein the generation of a dipole is illustrated by a schematic diagram of a "B" atom surrounded by "A" atoms in the variable resistance pattern 106 of the ferroelectric capacitor moving from position P1 to position P4.

[0100] In some embodiments, voltage VN1 is referred to as a negative saturation voltage and has a negative voltage value. Voltage VN2 is referred to as a reverse voltage VR and has a positive voltage value. The absolute value of voltage VN1 is greater than the absolute value of voltage VN2. In some embodiments, voltage VN1 is approximately -3V and corresponds to an electric field of -3MV / cm, and voltage VN2 is approximately +1V and corresponds to an electric field of +1MV / cm.

[0101] Figure 3 The configuration is given for illustrative purposes. Various implementations are within the contemplated scope of an embodiment of the present disclosure. For example, in some embodiments, the voltages VP1, VP2, VN1, and VN2 depend on the composition Hf. 1-x Zr x Factor x in O2.

[0102] In some embodiments, positive asymmetric small loops and negative asymmetric small loops exhibit no disturbance readout and are more than 10 4 Seconds and extrapolated to 10 years of stable data retention for multi-bit NVM.

[0103] In some embodiments, the positive asymmetric small loop and the negative asymmetric small loop are independent of each other. For example, in some embodiments, when the ferroelectric capacitor cycles with a positive asymmetric small loop to obtain half of the complete switching polarization value generated by polarizing the first portion of the structure in the ferroelectric capacitor (hereinafter referred to as the positive (Pos.) AmL state portion), the second portion of the structure in the ferroelectric capacitor (hereinafter referred to as the negative (Neg.) AmL state portion) remains non-polarized or unchanged until the ferroelectric capacitor cycles with a negative asymmetric small loop. Therefore, after cycling the Pos.AmL state portion of the ferroelectric capacitor a sufficient number of times with a positive asymmetric small loop, a Δ2P appears in the Pos.AmL state portion of the ferroelectric capacitor. r -V characteristics of the significant degradation or fatigue; and the remaining Neg.AmL state of the ferroelectric capacitor partially shows Δ2P r -Non-significant distortion of the V characteristic.

[0104] In addition, opposite polarity cycling (called asymmetric field cycling recovery (AFCR)) can provide a solution mechanism for recovery. Figure 4 In the embodiment of the ferroelectric capacitor 40 shown in FIG. 1 , the ferroelectric capacitor 40 is associated with, for example, a Figure 1A to Figure 2 The ferroelectric capacitor C FE1 or C FE2 The ferroelectric capacitor 40 includes metal electrodes 41 and 42 and a resistor pattern 43 inserted between the metal electrodes. An interface layer 44 is formed between the metal electrode 41 and the resistor pattern 43 , and an interface layer 45 is formed between the metal electrode 42 and the resistor pattern 43 .

[0105] Figure 4 Part (A) illustrates the Pos.AmL state portion in the ferroelectric capacitor 40. For illustration, an asymmetric polarization field (e.g., by applying a positive asymmetric small loop) causes electron injection and capture of electrons at the interface layer 44 to establish an inhomogeneous internal field, which induces an imprinting effect and resists dipole reversal. This situation implies degradation or fatigue (e.g., the first condition) of the switched polarization value of the Pos.AmL state portion in the ferroelectric capacitor 40. An opposite polarity cycle (e.g., a negative asymmetric small loop) is applied to restore the fatigued Pos.AmL state portion in the ferroelectric capacitor 40. For example, a reverse asymmetric field is correspondingly generated and provides additional electron injection into the metal electrode 42, thereby generating a reverse internal field. Therefore, the self-energy vacancy V of the trapped electron is released O 2+ Release to achieve the recovery process of the ferroelectric capacitor 40. In other words, the portion of the ferroelectric capacitor 40 that was in the first condition (fatigue) changes to the second condition (recovery).

[0106] Figure 4 Part (B) of FIG. 4 illustrates a Neg.AmL state portion in the ferroelectric capacitor 40 and an embodiment of fatigue induced by applying a negative asymmetric small loop. The configuration of the recovery process is similar to that of part (A). Therefore, repeated description is omitted here.

[0107] Based on the reference Figure 4 As discussed above, during the AFCR operation, the fatigued Pos.AmL state portion of the ferroelectric capacitor 40, whose switched polarization value is approximately zero, will be recovered by the reverse electric field generated during the negative AmL cycling operation, and the polarization of the Neg.AmL state portion of the ferroelectric capacitor 40 will be simultaneously established / changed due to the negative AmL cycling operation.

[0108] Figure 5FIG. 1 is a diagram illustrating a process of an asymmetric field cycling recovery (AFCR) operation of a ferroelectric capacitor corresponding to the memory cell 11 or 12 according to some embodiments. Figure 6 For illustration Figure 5 , and 7A to 7C For example, according to some embodiments, Figure 5 to Figure 6 The switching polarization value (△2P r )’s picture.

[0109] View now Figure 1A to Figure 1B , Figure 3 and Figure 5 to Figure 6 The ferroelectric capacitor C in the memory cell 11 FE1 As an example, initially, the ferroelectric capacitor C FE1 The Pos.AmL state part and the Neg.AmL state part in are the original states, such as Figure 5 shown in.

[0110] During the first AmL cycle period, a plurality of positive (Pos.) AmL cycle operations are performed on the memory cell 11, resulting in the Pos. AmL state portion eventually fatigued (e.g., changed to the first condition); while the Neg. AmL state portion remains in the original state. Specifically, the memory cell 11 transmits a pulse of voltage VP1 (e.g., +3V) and then transmits a pulse of voltage VP2 (e.g., -1V) to the plate wiring PL through the control circuit 150 for each Pos. AmL cycle operation. Figure 3 The voltage VP1 and voltage VP2 cycle, such as Figure 1A and Figure 6 In some embodiments, the transmission pulse in the above-mentioned operation is implemented in performing a memory operation, such as a read and / or write operation, on the Pos.AmL state portion of the memory cell 11. In some embodiments, the Pos.AmL state portion reaches a fatigue threshold and is referred to as fatigued. In some embodiments, the fatigue threshold implies that the switching polarization value (Δ2P r ) is reduced to approximately zero, as Figure 7B In Fig. 7A More specifically, the memory cell 11 undergoes a number of Pos.AmL cycle operations (e.g., 5×10 9 cycles), and the switching polarization value of the Pos.AmL state part (△2P r ) is reduced to almost zero.

[0111] Continue to view Figure 5, after the first AmL cycle, the Pos.AmL state part is fatigued, and the Neg.AmL state part remains in the original state.

[0112] During the second AmL cycle period, a plurality of negative (Neg.) AmL cycle operations are performed on the memory cell 11, thereby causing the Neg. AmL state portion to eventually fatigue (e.g., change to the first condition). At the same time, in response to the opposite electric field generated by the Neg. AmL cycle operation, the fatigued Pos. AmL state portion undergoes AFCR operation and is recovered (e.g., changes to the second condition), as shown in FIG. Figure 4 Discussed.

[0113] Specifically, the memory cell 11 transmits a pulse of voltage VN1 (eg, -3V) and then transmits a pulse of voltage VN2 (eg, +1V) to the plate wiring PL through the control circuit 150 for each Neg.AmL cycle operation. Figure 3 The voltage VP1 and voltage VP2 cycle, such as Figure 1A and Figure 6 In some embodiments, the transmission pulse in the above-mentioned operation is implemented in performing a memory operation, such as a read and / or write operation, on the Neg.AmL state portion of the memory cell 11. In some embodiments, the Neg.AmL state portion reaches a fatigue threshold and is referred to as fatigued. In some embodiments, the fatigue threshold implies that the switching polarization value (Δ2P r ) is reduced to approximately zero, as Figure 7B In Fig. 7A More specifically, the memory cell 11 undergoes a number of Neg.AmL cycle operations (e.g., 5×10 9 cycles), and the switching polarization value (△2P r ) is reduced to almost zero.

[0114] Continue to view Figure 5 , after the second AmL cycle, the Pos.AmL state portion has a recovery state, and the Neg.AmL state portion is fatigued.

[0115] The configurations in the third AmL cycle are configured to be related to those in the first AmL cycle, for example. Specifically, the Pos.AmL state is partially restored and can be polarized, such as by Figure 7BThe third AmL cycle period is shown by curve 703. Therefore, multiple Pos.AmL cycle operations are performed on the memory cell 11, resulting in the Pos.AmL state portion being eventually fatigued. At the same time, in response to the opposite electric field generated by the Pos.AmL cycle operation, the fatigued Neg.AmL state portion undergoes AFCR operation and is recovered, as shown in FIG. Figure 4 Discussed.

[0116] Continue to view Figure 5 , after the third AmL cycle, the Neg.AmL state portion has a recovery state, and the Pos.AmL state portion is fatigued.

[0117] For the fourth AmL cycle, the configurations in the fourth AmL cycle are configured with respect to those in the second AmL cycle, for example. Specifically, the Neg.AmL state is partially restored and can be polarized, such as by Figure 7B As shown in the curve 704 in FIG. 1 , multiple Neg.AmL cycle operations are performed on the memory cell 11, resulting in the Neg.AmL state portion eventually being fatigued. At the same time, in response to the opposite electric field generated by the Neg.AmL cycle operation, the fatigued Pos.AmL state portion undergoes the AFCR operation and is recovered, as shown in FIG. Figure 4 Discussed.

[0118] Continue to view Figure 5 , after the fourth AmL cycle, the Pos.AmL state portion has a recovery state, and the Neg.AmL state portion is fatigued.

[0119] View now Fig. 7A and Figure 7C , Figure 7C yes Fig. 7A Detailed diagram of part B in the figure. Figure 7C Plotting the switching polarization curves 705 and 707 corresponding to the Pos.AmL state portion and the switching polarization curves 706 and 708 corresponding to the Neg.AmL state portion in the 199th and 200th AmL cycle periods. For illustration, the Pos.AmL state portion and the Neg.AmL state portion have undergone 10 cycles in 200 cycles. 12 The switching polarization value remains almost the same as that depicted in Figure 7B The switching polarization values ​​are the same as those in , thereby demonstrating the long endurance of the memory cell 11 achieved by the AFCR operation and advocating unrestricted operation for application of non-volatile memory devices.

[0120] In some embodiments, a method of operating the memory device 10 implementing an AFCR operation is presented, as shown in Table 1 below and with reference to FIG. Figure 1A to Figure 1B as well as Figure 5 and Figure 6 As shown. Figure 1A As shown in FIG. 1 , the control circuit 150 is used to control the voltage VPL1 on the plate wiring PL to perform operations on the memory cells 11 and 12. The driver circuit 140 is used to generate the voltage VPL2 in response to the voltage VPL1. According to some embodiments, the voltage VPL2 is inverted from the voltage VPL1. In other words, the driver circuit 140 increases the voltage VPL2 (e.g., from VN1 to VN2) in response to decreasing the voltage VPL1 (e.g., from VP1 to VP2), and decreases the voltage VPL2 (e.g., from VN2 to VN1) in response to increasing the voltage VPL1 (e.g., from VP2 to VP1).

[0121]

[0122] Table I

[0123] For example, a Pos.AmL cycle operation is performed on the memory cell 11 to restore the ferroelectric capacitor C FE1 The Neg.AmL state portion of the memory cell 12 is used for write / read operations, and at the same time, the Neg.AmL cycle operation is performed on the Neg.AmL state portion of the memory cell 12 until the Neg.AmL state portion of the memory cell 12 is fatigued.

[0124] Specifically, see Figure 6 , the memory cell 11 is cycled at a voltage VP1 (e.g., +3 V) and a voltage VP1 (e.g., -1 V) in a Pos.AmL cycling operation. Due to the reverse electric field, the Neg.AmL state portion of the memory cell 11 is undergoing a recovery operation, while the Pos.AmL state portion of the memory cell 11 is polarized during the Pos.AmL cycling operation.

[0125] In addition, see Figure 6 , memory cell 12 is cycled at voltage VN1 (e.g., -3V) and voltage VN2 (e.g., +1V) in the Neg.AmL cycling operation. Due to the reverse electric field, the Pos.AmL state portion of memory cell 12 is undergoing a recovery operation, while the Neg.AmL state portion of memory cell 11 is polarized during the Neg.AmL cycling operation.

[0126] In some embodiments, the ferroelectric capacitor C FE1 After the Neg.AmL state portion of the memory cell 11 is restored, the Neg.AmL cycle operation is performed on the Neg.AmL state portion of the memory cell 11 for write / read operations until the Neg.AmL state portion of the memory cell 11 is fatigued. At the same time, the Pos.AmL cycle operation is performed on the memory cell 12 to restore the fatigued ferroelectric capacitor CFE2 The Neg.AmL state part.

[0127] Specifically, see Figure 6 , the memory cell 11 is cycled with a voltage VN1 (e.g., -3V) and a voltage VN2 (e.g., +1V) in the Neg.AmL cycling operation. Due to the reverse electric field, the Pos.AmL state portion of the memory cell 11 is undergoing a recovery operation, while the Neg.AmL state portion of the memory cell 11 is polarized during the Neg.AmL cycling operation.

[0128] In addition, see Figure 6 , the memory cell 12 is cycled at a voltage VP1 (e.g., +3V) and a voltage VP2 (e.g., -1V) in a Pos.AmL cycling operation. Due to the reverse electric field, the Neg.AmL state portion of the memory cell 12 is undergoing a recovery operation while the Pos.AmL state portion of the memory cell 12 is polarized during the Pos.AmL cycling operation.

[0129] View now FIG. 8A to FIG. 8B . FIG. 8A to FIG. 8B According to some embodiments, Figures 1A to 7C The read current-time characteristics, read voltage characteristics and polarization-voltage (PV) characteristics of the Pos.AmL state portion of the memory cell 11 in the memory cell.

[0130] For illustration, see Figure 1A , in a ferroelectric capacitor, for example, C in memory cell 11 FE1 , the storage status of the Pos.AmL status part is read during operation, with Figure 3 A voltage VPL1 having a value of the voltage VP1 in the bit line (eg, +3 V) may be applied to the ferroelectric capacitor C via the plate wiring PL when the bit line is grounded. FE1 In response, the polarization P changes, and the degree of change depends on the initial polarization. For example, Fig. 8AThe hysteresis loop 801 corresponding to the Pos.AmL state portion in FIG. 8 illustrates two possible polarization states P81 and P82. In response to the voltage VPL1 being the voltage VP1, the polarization of the Pos.AmL state portion changes from the polarization state P81 to the polarization state P83, which is indicated by the path 811 and induces a significant switching current (read current) 821 to the bit line. Therefore, when the sensing circuit 120 senses the switching current 821 and determines that the memory cell 11 has a data state corresponding to the polarization P81, for example, a logical "0". Similarly, when the polarization of the Pos.AmL state portion changes from the polarization state P82 to the polarization state P83, the change is indicated by the path 812 and induces a small non-switching current (read current) 822 to the bit line. Therefore, when the sensing circuit 120 senses the non-switching current 822 and determines that the memory cell 11 has a data state corresponding to the polarization P82, for example, a logical "1".

[0131] In various embodiments of reading the stored state of the Pos.AmL state portion, having Figure 3 When the bit line is grounded, a voltage VPL1 having a value of the voltage VP2 (eg, -1 V) is applied to the ferroelectric capacitor C via the plate wiring PL. FE1 For example, Figure 8B As shown in FIG. 8 , in response to voltage VPL1 being voltage VP2, the polarization of the Pos.AmL state portion changes from polarization state P81 to polarization state P84, which change is indicated by path 813 and induces a small non-switching current (read current) 823 to the bit line. Therefore, when the sensing circuit 120 senses the non-switching current 823 and determines that the memory cell 11 has a data state corresponding to polarization P81, for example, a logical "0". Similarly, when the polarization of the Pos.AmL state portion changes from polarization state P82 to polarization state P84, the change is indicated by path 814 and induces a significant switching current 824 to the bit line. Therefore, when the sensing circuit 120 senses the switching current 824 (read current) and determines that the memory cell 11 has a data state corresponding to polarization P82, for example, a logical "1".

[0132] View now FIG. 9A to FIG. 9B . FIG. 9A to FIG. 9B According to some embodiments, Figures 1A to 7C The read current-time characteristics, read voltage characteristics and polarization-voltage (PV) characteristics of the Neg.AmL state portion of the memory cell 11 in the memory cell.

[0133] For illustration, see Figure 1A , in a read operation, such as C in memory cell 11 FE1 The Neg.AmL state of the ferroelectric capacitor has a stored state Figure 3When the bit line is grounded, a voltage VPL1 of the value of the voltage VN1 (e.g., -3 V) is passed through the plate wiring PL across the ferroelectric capacitor C FE1 In response, the polarization P changes, and the degree of change depends on the initial polarization. For example, Fig. 9A The hysteresis loop 802 corresponding to the Neg.AmL state portion in FIG. 8 illustrates two possible polarization states P81 and P85. In response to the voltage VPL1 being the voltage VN1, the polarization of the Neg.AmL state portion changes from the polarization state P81 to the polarization state P85, which is indicated by the path 815 and induces a significant switching current 825 (read current) to the bit line. Therefore, when the sensing circuit 120 senses the switching current 825 and determines that the memory cell 11 has a data state corresponding to the polarization P81, for example, a logical "0". Similarly, when the polarization of the Neg.AmL state portion changes from the polarization state P85 to the polarization state P86, the change is indicated by the path 816 and induces a small non-switching current (read current) 826 to the bit line. Therefore, when the sensing circuit 120 senses the non-switching current 826 and determines that the memory cell 11 has a data state corresponding to the polarization P85, for example, a logical "1".

[0134] In various embodiments of reading the stored state of the Neg.AmL state portion, having Figure 3 When the bit line is grounded, a voltage VPL1 having a value of the voltage VN2 (e.g., +1V) can pass through the ferroelectric capacitor C through the plate wiring PL. FE1 For example, if Fig. 9B As shown in FIG. 8 , in response to voltage VPL1 being voltage VN2, the polarization of the Neg.AmL state portion changes from polarization state P81 to polarization state P87, which is indicated by path 817 and induces a small non-switching current 827 to the bit line. Therefore, when the sensing circuit 120 senses the non-switching current (read current) 827 and determines that the memory cell 11 has a data state corresponding to polarization P81, for example, a logical "0". Similarly, when the polarization of the Neg.AmL state portion changes from polarization state P85 to polarization state P87, the change is indicated by path 818 and induces a significant switching current (read current) 828 to the bit line. Therefore, when the sensing circuit 120 senses the switching current 828 and determines that the memory cell 11 has a data state corresponding to polarization P85, for example, a logical "1".

[0135] Configurations using the voltages VP1, VP2, VN1, VN2 for the read operation of the memory cell 12 are similar to those of the memory cell 11 using the voltages VP1, VP2, VN1, VN2 as the voltage VPL2. Therefore, repeated descriptions are omitted here.

[0136] In some embodiments, according to the operation of the memory device 10 , a write operation for changing the data states in the memory cells 11 and 12 may be performed by utilizing the voltages VP1 , VP2 , VN1 , and VN2 .

[0137] In some approaches, a high electric field is applied to the ferroelectric memory cell for recovery, which consumes significant power in cycling the memory cell and causes the memory device to experience a time loss during the recovery operation. In addition, due to the operating scheme, the ferroelectric memory cell is configured for one-bit operation by using the full switched polarization value for storing data in the memory cell.

[0138] The present application provides a memory device and an operating method thereof, thereby utilizing a reduced operating voltage to generate half of a complete switching scheme for storing data in a memory cell. In addition, the proposed asymmetric field cycle recovery operation grants a simultaneous dual application of a memory operation (write / read operation) to a portion of a ferroelectric capacitor and a recovery operation to another portion of the ferroelectric capacitor, which achieves a 0% recovery time allocation and indicates no additional recovery time for non-volatile memory (NVM). In addition, in some embodiments, the proposed asymmetric field cycle recovery operation is applied via a driver circuit coupled between two different ferroelectric memory cells to perform memory operations and recovery operations on the two memory cells, thereby improving the feasibility of the operation of the memory device. Therefore, compared with some methods, a lower power consumption and zero recovery time of the memory device are provided. In the configuration of the present application, the durability of the memory device is guaranteed.

[0139] According to some embodiments, a memory device is provided and includes: a plurality of first memory cells, each having a first terminal coupled to a first node and a second terminal coupled to a corresponding first bit line among a plurality of first bit lines; a plurality of second memory cells, each having a first terminal coupled to a second node and a second terminal coupled to a corresponding second bit line among a plurality of second bit lines; and a driver circuit coupled between the first node and the second node and configured to generate a second voltage at the second node in response to a first voltage at the first node when a memory operation is performed on one of the plurality of first memory cells. The first voltage and the second voltage have different polarities.

[0140] In some embodiments, the memory device includes a board connection, the board connection is coupled to the first node to transmit the first voltage to the first memory unit and an input terminal of the driver circuit. An output terminal of the driver circuit is coupled to the second node.

[0141] In some embodiments, the driver circuit includes an inverting amplifier having a first input terminal receiving the first voltage, a second input terminal coupled to a ground, and an output terminal coupled to the second node.

[0142] In some embodiments, the driver circuit further includes a first resistor coupled between the first input terminal and the first node, and a second resistor coupled between the first input terminal and the second node.

[0143] In some embodiments, the first input terminal is a negative input of the inverting amplifier, and the second input terminal is a positive input of the inverting amplifier.

[0144] In some embodiments, the first memory cell and the second memory cell are a plurality of ferroelectric memory cells.

[0145] In some embodiments, the first voltage and the second voltage have a same absolute value.

[0146] In some embodiments, the driver circuit is further configured to increase the second voltage to have a second voltage value greater than the first voltage value in response to the first voltage being decreased to have a first voltage value.

[0147] In some embodiments, the driver circuit is further configured to reduce the second voltage from the second voltage value to a fourth voltage value in response to the first voltage increasing from the first voltage value to a third voltage value. An absolute value of the second voltage value is different from an absolute value of the third voltage value.

[0148] According to some embodiments, an operating method of a memory device is provided and includes performing a plurality of cycle operations of a first polarity on a first memory cell to restore a first portion of the first memory cell having a first condition, and simultaneously performing a plurality of cycle operations of a second polarity on a first portion of a second memory cell until the first portion of the second memory cell changes to the first condition. The first polarity and the second polarity are different from each other.

[0149] In some embodiments, performing the multi-cycle operation of the first polarity on the first memory cell to restore the first portion of the first memory cell includes cycling the first memory cell with a first positive voltage and a first negative voltage. The first positive voltage and the first negative voltage have different absolute values ​​from each other.

[0150] In some embodiments, the absolute value of the first positive voltage is greater than the absolute value of the first negative voltage.

[0151] In some embodiments, performing a plurality of cycles of the second polarity on the second memory cell until the first portion of the second memory cell has the first condition includes cycling the second memory cell with a second negative voltage and a second positive voltage. The absolute value of the first positive voltage and an absolute value of the second negative voltage are the same. The plurality of absolute values ​​of the first negative voltage and an absolute value of the second positive voltage are the same.

[0152] In some embodiments, when the first polarity cycling operation is performed on the first memory cell, a second portion of the first memory cell changes to the first condition. When the second polarity cycling operation is performed on the second memory cell, a second portion of the second memory cell changes to a second condition different from the first condition.

[0153] In some embodiments, the operating method further includes the following steps: after the first portion of the first memory cell is restored to have a second condition different from the first condition, performing the second polarity cycling operation on the first memory cell until the first portion of the first memory cell has the first condition and simultaneously performing the first polarity cycling operation on the first portion of the second memory cell to restore the first portion of the second memory cell to have the first condition.

[0154] In some embodiments, the first memory cell is coupled between a first bit line and an input terminal of a driver circuit, and the second memory cell is coupled between a second bit line and an output terminal of the driver circuit. The operating method further includes inverting a first voltage at the input terminal to a second voltage at the output terminal by the driver circuit.

[0155] According to some embodiments, a memory device is provided and includes: a first memory cell having a first terminal coupled to a plate connection and a second terminal coupled to a first bit line; a driver circuit having a first terminal coupled to the plate connection; a second memory cell having a first terminal coupled to a second terminal of the driver circuit and a second terminal coupled to a second bit line; and a control circuit for controlling a first voltage on the plate connection to perform a memory operation on a first portion of the first memory cell. The driver circuit is used to generate a second voltage at its second terminal in response to the first voltage to perform a recovery operation on a first portion of the second memory cell.

[0156] In some embodiments, the first voltage and the second voltage have different polarities, and the first voltage and the second voltage have the same absolute value.

[0157] In some embodiments, the first memory cell includes: a first ferroelectric capacitor having a first cell bottom and a first cell plate coupled to the first terminal of the driver circuit; and a first selection element coupled between the first cell bottom and the first bit line.

[0158] In some embodiments, the second memory cell includes a second ferroelectric capacitor having a second cell bottom and a second cell plate coupled to the second terminal of the driver circuit; and a second selection element coupled between the second cell bottom and the second bit line. The driver circuit includes an inverting amplifier having an input coupled to the first terminal of the driver circuit and an output coupled to the second terminal of the driver circuit.

[0159] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of an embodiment of the present disclosure. Those skilled in the art will appreciate that they may readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. A memory device, characterized in that: Include: A plurality of first memory cells, each of the plurality of first memory cells having a first terminal coupled to a first node and a second terminal coupled to a corresponding first bit line among a plurality of first bit lines; a plurality of second memory cells, each of the plurality of second memory cells having a first terminal coupled to a second node and a second terminal coupled to a corresponding second bit line of the plurality of second bit lines; and a driver circuit coupled between the first node and the second node and configured to generate a second voltage at the second node in response to a first voltage at the first node when a memory operation is performed on one of the plurality of first memory cells, The first voltage and the second voltage have different polarities.

2. The memory device according to claim 1, wherein: The driver circuit contains: an inverting amplifier having a first input terminal receiving the first voltage, a second input terminal coupled to a ground, and an output terminal coupled to the second node, wherein the first input terminal is a negative input of the inverting amplifier, and the second input terminal is a positive input of the inverting amplifier; a first resistor coupled between the first input terminal and the first node; and A second resistor is coupled between the first input terminal and the second node.

3. The memory device according to claim 1, wherein: The first memory cells and the second memory cells are ferroelectric memory cells.

4. The memory device according to claim 1, wherein: The first voltage and the second voltage have a same absolute value.

5. The memory device according to claim 1, wherein: The driver circuit is further configured to increase the second voltage to have a second voltage value greater than the first voltage value in response to the first voltage being reduced to have a first voltage value.

6. A method for operating a memory device, characterized in that: The following steps are involved: performing a plurality of cycle operations of a first polarity on a first memory cell to restore a first portion of the first memory cell to a first condition, and simultaneously performing a plurality of cycle operations of a second polarity on a first portion of a second memory cell until the first portion of the second memory cell changes to the first condition, The first polarity and the second polarity are different from each other.

7. The operating method according to claim 6, characterized in that: The step of performing the plurality of cycle operations of the first polarity on the first memory cell to restore the first portion of the first memory cell comprises the following steps: The first memory cell is cycled with a first positive voltage and a first negative voltage, wherein the first positive voltage and the first negative voltage have multiple absolute values ​​different from each other, and the absolute value of the first positive voltage is greater than the absolute value of the first negative voltage.

8. The operating method according to claim 7, characterized in that: The step of performing the plurality of cycle operations of the second polarity on the second memory cell until the first portion of the second memory cell has the first condition comprises the following steps: cycling the second memory cell with a second negative voltage and a second positive voltage, wherein the absolute value of the first positive voltage and an absolute value of the second negative voltage are the same, and The absolute values ​​of the first negative voltage and an absolute value of the second positive voltage are the same.

9. The operating method according to claim 6, characterized in that: When the plurality of cycles of the first polarity are performed on the first memory cell, a second portion of the first memory cell changes to the first condition, When the plurality of cycle operations of the second polarity are performed on the second memory cell, a second portion of the second memory cell is changed to a second condition different from the first condition.

10. A memory device, characterized in that: Include: A first memory cell having a first terminal coupled to a plate connection and a second terminal coupled to a first bit line; a driver circuit having a first terminal coupled to the board connection; a second memory cell having a first terminal coupled to a second terminal of the driver circuit and a second terminal coupled to a second bit line; and a control circuit for controlling a first voltage on the board connection to perform a memory operation on a first portion of the first memory cell, The driver circuit is used for generating a second voltage at the second terminal thereof in response to the first voltage so as to perform a recovery operation on a first part of the second memory cell.

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