Circuit for accelerating writing balance training efficiency of DDR (Double Data Rate) type dynamic memory

Abstract

The invention aims to provide a circuit for accelerating writing balance training efficiency of a DDR (Double Data Rate) type dynamic memory. The circuit comprises at least one delay circuit and at least one sampling circuit, the delay circuit is located at a particle end and is used for increasing the delay of a command clock and a data clock; the sampling circuit is located at the particle end and used for detecting the phase relation between the command clock and the data clock delayed by the delay circuit. According to the invention, a plurality of different time delay and sampling circuits are added at the particle end, so that the controller end can obtain phase deviation information under various time delay settings based on one time delay setting.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a circuit for accelerating the writing balance training efficiency of a DDR-type dynamic memory. Background Art

[0002] ‌Dynamic Random Access Memory (DRAM) is a semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. Since transistors in reality have leakage current, the amount of charge stored on the capacitor is not enough to correctly judge the data, resulting in data corruption. Therefore, for DRAM, periodic charging is an inevitable requirement. Due to this characteristic of requiring regular refresh, it is called "dynamic" memory. The main difference between DRAM and static random access memory (SRAM) is that once SRAM stores data, it will not lose memory even if it is not refreshed, while DRAM needs to be refreshed regularly to maintain data integrity. DRAM has a shorter storage time, usually between 10-100 milliseconds, but since computer processing speed is at the nanosecond level, it is sufficient for computer systems. DRAM uses dynamic storage cells and is suitable for main memory because of its large capacity and low power consumption, but it needs to be refreshed regularly to maintain data integrity.

[0003] The current mainstream dynamic memories such as DDR5 and LPDDR5 need to continuously adjust the relative delay to detect the phase deviation in the initialization training phase to achieve the purpose of aligning the command clock and the data clock. In the LPDDR5 protocol, the WCK2CK leveling is defined in that the particle side compares the relationship between the rising edge of WCK and the rising edge of CK, and feeds back the controller side through high or low on all DQ signals (bidirectional data ports) to make corresponding phase adjustments, ultimately achieving the purpose of rising edge alignment. Since the existing feedback method is that all DQ signals synchronously feedback high or low, one delay adjustment can only feedback the phase relationship of the two clocks once and cannot indicate the degree of phase deviation, making the efficiency of equalization training low. Summary of the invention

[0004] The purpose of the present invention is to provide a circuit for accelerating the write balance training efficiency of DDR type dynamic memory. The circuit adds multiple different delay and sampling circuits on the particle end so that the controller end can obtain phase deviation information under multiple delay settings based on one delay setting.

[0005] A circuit for accelerating the writing balance training efficiency of a DDR-type dynamic memory comprises: at least one delay circuit and at least one sampling circuit; The delay circuit is located at the particle end and is used to increase the delay of the command clock and the data clock; The sampling circuit is located at the particle end and is used to detect the phase relationship between the command clock and the data clock after being delayed by the delay circuit.

[0006] Preferably, the delay of each of the delay circuits is unequal.

[0007] Preferably, the delay circuit comprises: a voltage-controlled voltage bias module, a delay module and a differential-to-single-ended module; The voltage-controlled voltage bias module is connected to the delay module and is used to control the delay time of the clock; The delay module is connected to the differential to single-ended module and is used to delay the reference clock signal; The differential to single-ended module is used to combine and output delayed clock signals.

[0008] Preferably, the voltage-controlled voltage bias module comprises: a bias module and a delay enhancement module; The bias module is connected to the delay enhancement module and is used to bias the voltage; The delay enhancement module is used to expand the current range output by the bias module.

[0009] Preferably, the bias module comprises: an output terminal, an input terminal and a bias terminal; The input end includes: a first MOS tube, a seventh MOS tube, an eighth MOS tube and a first resistor; The gate of the first MOS tube is connected to the gate of the second MOS tube, and the drain is connected to the drain of the seventh MOS tube; The source of the seventh MOS tube is connected to the first end of the first resistor, and the gate is connected to the control voltage; The source of the eighth MOS tube is grounded; The output end includes: a second MOS tube, a sixth MOS tube, a twelfth MOS tube, a thirteenth MOS tube and a first capacitor and a second capacitor; The drain of the second MOS tube is connected to the delay enhancement module; The gate of the sixth MOS tube is connected to the second end of the second capacitor; The drain of the twelfth MOS tube is connected to the delay enhancement module, the source is grounded, and the gate is connected to the gate of the thirteenth MOS tube; The drain of the thirteenth MOS tube is connected to the source of the sixth MOS tube, and the source is grounded; The bias end includes: an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a first resistor, a second resistor, a third resistor and a fourth resistor; The drain of the eighth MOS tube is connected to the second end of the first resistor and the first end of the second resistor, and the source is grounded; The drain of the ninth MOS tube is connected to the second end of the second resistor and the first end of the third resistor, and the source is grounded; The drain of the tenth MOS tube is connected to the second end of the third resistor and the first end of the fourth resistor, and the source is grounded; The drain of the eleventh MOS tube is connected to the second end of the fourth resistor, and the source is grounded.

[0010] Preferably, the delay enhancement module comprises: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first transmission gate and a second transmission gate; The gate of the third MOS tube is connected to the first transmission gate, and the source is connected to the source of the fifth MOS tube and the source of the fourth MOS tube; The gate of the fourth MOS tube is connected to the second transmission gate; The gate of the fifth MOS tube is connected to the second transmission gate The first transmission gate and the second transmission gate are connected.

[0011] Preferably, the delay module comprises: a four-way push-pull delay unit; The push-pull delay unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube; The drain of the fourteenth MOS tube is connected to the source of the fifteenth MOS tube, and the gate is connected to Vbp; The gate of the fifteenth MOS tube is connected to the input, and the drain is connected to the output; The gate of the sixteenth MOS tube is connected to the input, the drain is connected to the output, and the source is connected to the drain of the seventeenth MOS tube; The gate of the seventeenth MOS tube is connected to Vbn, and the source is grounded.

[0012] Preferably, the sampling circuit comprises: a sampling resistor, an isolation capacitor and a variable resistor; The isolation capacitor and the variable resistor are connected in series; The sampling resistor is connected in parallel with the isolation capacitor and the variable resistor, and the sampling resistor is used to collect the clock signal on the delay circuit.

[0013] A circuit control method for accelerating the write-balance training efficiency of a DDR-type dynamic memory comprises: Obtain a reference clock signal; Acquire multiple delayed signals on the delay circuit; The phase relationship between the command clock and the data clock is calculated according to the reference clock signal and a plurality of delay signals.

[0014] An electronic device includes: a processor and a memory, wherein the memory is used to store computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a circuit control method for accelerating the write-leveling training efficiency of a DDR-type dynamic memory.

[0015] The beneficial effects of the present invention are as follows: 1. The present invention adds multiple delay and sampling circuits on the basis of the original receiving sampling circuit at the particle end, and utilizes the condition that the controller and the particle have multiple DQ IOs to feed back the original phase relationship of the two clocks on DQ0, and feed back the phase relationship of the two clocks after adding delays of delay1 to delay n to the data clock on the remaining DQ1 to DQn; 2. The present invention can help the controller end to reduce the phase deviation range of the two clocks through information fed back by only one phase detection, thereby significantly improving the efficiency of write equalization training. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor. Figure 1 A circuit structure diagram of the present invention for accelerating the writing balance training efficiency of a DDR-type dynamic memory; Figure 2 It is a schematic diagram of the delay circuit structure of the present invention; Figure 3 It is a schematic diagram of the structure of the voltage-controlled voltage bias circuit of the present invention; Figure 4 It is a schematic diagram of the delay enhancement circuit structure of the present invention; Figure 5 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0019] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0020] The current mainstream dynamic memories such as DDR5 and LPDDR5 need to continuously adjust the relative delay to detect the phase deviation in the initialization training phase to achieve the purpose of aligning the command clock and the data clock. In the LPDDR5 protocol, the WCK2CK leveling is defined in that the particle side compares the relationship between the rising edge of WCK and the rising edge of CK, and feeds back the controller side through high or low on all DQ signals (bidirectional data ports) to make corresponding phase adjustments, ultimately achieving the purpose of rising edge alignment. Since the existing feedback method is that all DQ signals synchronously feedback high or low, one delay adjustment can only feedback the phase relationship of the two clocks once and cannot indicate the degree of phase deviation, making the efficiency of equalization training low.

[0021] The present invention adds multiple delay and sampling circuits on the basis of the original receiving sampling circuit at the particle end, utilizes the condition that the controller and the particle have multiple DQ IOs, feeds back the original phase relationship of the two clocks on DQ0, and feeds back the phase relationship of the two clocks after delays of delay1 to delay n are added to the data clock on the remaining DQ1 to DQn respectively; the present invention can help the controller end to reduce the phase deviation range of the two clocks through the information fed back by only one phase detection, thereby significantly improving the efficiency of write equalization training.

[0022] Example 1 A circuit to accelerate the efficiency of DDR-type dynamic memory write balance training, reference Figure 1 , comprising: at least one delay circuit and at least one sampling circuit; The delay circuit is located at the particle end and is used to increase the delay of the command clock and the data clock; The main function of the delay circuit is to achieve delayed output of signals in electronic circuits, thereby completing various functions. The delay circuit achieves its purpose by connecting certain circuit devices between the input and output or using delay elements to control the time output of the signal, thereby controlling the duration of the signal. This circuit design is simple and can achieve a wide range of delay control without affecting the quality of the connected signal. The application of the delay circuit includes but is not limited to: Control signal duration: The delay circuit can be used to control the duration of the signal to achieve timer and pulse control functions. For example, it is used to connect and disconnect between two signals, or to send signals below a fixed frequency. Signal hysteresis control: The delay circuit can also be used to control signal hysteresis to avoid coordination errors and filter unbalanced pulse signals. Wideband filter construction: The delay circuit can also be used to realize the construction of broadband filters for multi-channel signal control and adjustment to achieve timing functions. Synchronous communication system: The delay circuit can be used in synchronous communication systems to achieve control of connecting multiple signals and calculate time differences. The delay circuit can also be used to change the order of signals, adjust the distribution time, etc., to ensure that the electronic system can maintain consistent timing performance under any changes. The delay circuit is simple in design and low in cost, and can easily achieve a wide range of delay control while providing timing and wide filtering functions, as well as pulse width control.

[0023] The sampling circuit is located at the particle end and is used to detect the phase relationship between the command clock and the data clock after being delayed by the delay circuit.

[0024] The main function of the sampling circuit is to convert the continuous analog signal into discrete samples so that the signal can be processed and analyzed by the digital system. The sampling circuit converts the analog signal into a digital signal through periodic sampling, realizes analog-to-digital conversion (ADC) or digital-to-analog conversion (DAC), so that the signal can be stored, processed and transmitted in the digital system. The functions of the sampling circuit include: Signal extraction: Through periodic sampling, the continuous analog signal is converted into discrete samples so that the signal can be processed and analyzed by the digital system. Data conversion: The sampling circuit converts the analog signal into a digital signal, realizes analog-to-digital conversion (ADC) or digital-to-analog conversion (DAC), so that the signal can be stored, processed and transmitted in the digital system. Signal reconstruction: Through appropriate reconstruction algorithms, the sampling circuit can use discrete samples to restore the original continuous analog signal, realize digital-to-analog conversion and signal reconstruction. In the A / D conversion process, the sample-and-hold circuit is widely used in data acquisition systems and real-time control systems. It has two functions: one is the sampling tracking state, which accepts the input signal as quickly as possible; the other is the holding state, which holds the input signal at the moment before the end of sampling so that the output and the held signal are consistent. In addition, sampling circuits are also widely used in various scenarios such as voltage sampling, current sampling, DC sampling and AC sampling.

[0025] Preferably, the delay of each delay circuit is unequal.

[0026] The delay of a delay circuit refers to the time delay experienced by a signal during transmission or processing in a circuit. This delay can be achieved through different electronic components and circuit designs, including RC delay circuits, master-slave JK trigger delay circuits, counter delay circuits, monostable trigger delay circuits, digital logic delay circuits, microprocessor delay circuits, etc. At the same time, attention should be paid to the stability and accuracy of the delay circuit to ensure accurate transmission and processing of the signal.

[0027] Preferably, reference Figure 2 , the delay circuit includes: a voltage-controlled voltage bias module, a delay module and a differential-to-single-ended module; The voltage-controlled voltage bias module is connected to the delay module to control the delay time of the clock; The delay module is connected to the differential to single-ended module to delay the reference clock signal; The function of the delay circuit is to achieve delayed output of the signal in the electronic circuit to complete a specific function. The delay circuit controls the time output of the signal by connecting certain circuit devices between the input and output or using delay elements. The main purpose is to control the duration of the signal so that it can achieve a specific purpose. This circuit design is simple, low cost, and can achieve a wide range of delay control without affecting the quality of the connected signal. The delay circuit can provide timing and wide filtering functions, as well as pulse width control, which is used to achieve functions such as timing, synchronous communication, and calculation of time difference. In addition, the delay circuit can also be used to control the signal sequence, change the distribution time, etc., to ensure that the electronic system can maintain consistent timing performance under any changes.

[0028] The differential to single-ended module is used to combine and output delayed clock signals.

[0029] The function of the differential to single-ended circuit is to convert the differential signal into a single-ended signal in order to adapt to different application scenarios. This circuit structure is widely used in electronic devices and can be used to provide the system with a single-ended voltage, resist electromagnetic interference, monitor the changes in the double-ended voltage, and improve the stability and reliability of the system.

[0030] Differential signaling is a signal transmission method consisting of two voltage signals with equal amplitude and opposite phases, while a single-ended signal has only one voltage reference point. The basic principle of the differential to single-ended circuit is to use a differential amplifier to convert the differential signal into a single-ended signal by amplifying the difference of the differential signal. This conversion allows the signal to have a high immunity to common-mode interference during transmission, while simplifying the signal processing process, allowing single-ended devices to directly process differential signals, expanding the application range of differential signals. The differential to single-ended circuit not only simplifies the signal processing process by converting the differential signal into a single-ended signal, but also improves the stability and reliability of the system. Therefore, it plays an important role in electronic devices.

[0031] In an embodiment of the present invention, the control voltage Vc first passes through the voltage-controlled voltage bias module unit to generate two currents, which are copied to the internal charge-discharge current source of the delay module by bn and bp through the current mirror structure. The magnitude of the current determines the final delay time. After the reference clock CLKref is converted into the differential clocks inn and inp, it will first pass through the delay module delay, and then enter the differential to single-ended module to synthesize a clock and realize the output of the first-level delay. In an embodiment of the present invention, considering the requirements of wide range and high-precision multi-phase clock generation, multiple identical delay modules and differential to single-ended modules can be set to generate multi-phase uniform output clocks for the input clock. After adding a configurable circuit structure, the circuit configuration is performed first, and then the final delay of the delay circuit is determined by the control voltage Vc.

[0032] Preferably, reference Figure 3 , the voltage-controlled voltage bias module includes: a bias module and a delay enhancement module; The bias module is connected to the delay enhancement module and is used to bias the voltage; The delay enhancement module is used to extend the current range of the bias module output.

[0033] The voltage-controlled bias module can select different configuration paths. When the input control voltage is constant, the size of the replicable current can be set according to the configuration. That is, when the control voltage range is limited, a larger output range can be achieved, thereby expanding the charge and discharge current size of the delay module and achieving the purpose of expanding the dynamic delay range of the delay circuit.

[0034] The main function of the voltage-controlled bias circuit is to set the static operating point of each level to ensure that each level of the circuit operates at a suitable static operating point. The voltage-controlled bias circuit ensures that each level of the circuit operates at the optimal static operating point by providing a suitable bias current for each level of the circuit. This process is essential to maintaining the stability and performance of the circuit. Specifically, the functions of the voltage-controlled bias circuit include: Stabilizing the operating point: The voltage-controlled bias circuit can provide a stable operating point for semiconductor devices to ensure that they can maintain stable performance under different operating conditions. Reducing temperature drift: Through methods such as temperature compensation, the voltage-controlled bias circuit can reduce the drift of the operating point of the semiconductor device caused by the temperature, thereby improving the stability of the circuit. Reducing noise: The voltage-controlled bias circuit can reduce the noise caused by power supply fluctuations, environmental interference and other factors, and improve the signal-to-noise ratio of the circuit. Improving linearity: By reducing nonlinear distortion, the voltage-controlled bias circuit can improve the linearity of semiconductor devices, thereby improving the signal quality of the circuit. By setting the static operating point of each level, the voltage-controlled bias circuit not only ensures the stability and performance of the circuit, but also improves the anti-interference ability and signal quality of the circuit.

[0035] Preferably, the bias module comprises: an output terminal, an input terminal and a bias terminal; The input end includes: a first MOS tube (M1), a seventh MOS tube (M7), an eighth MOS tube (M8) and a first resistor (R1); The gate of the first MOS tube (M1) is connected to the gate of the second MOS tube (M2), and the drain is connected to the drain of the seventh MOS tube (M7); The source of the seventh MOS tube (M7) is connected to the first end of the first resistor (R1), and the gate is connected to the control voltage; The source of the eighth MOS tube (M8) is grounded; The output end includes: a second MOS tube (M2), a sixth MOS tube (M6), a twelfth MOS tube (M12), a thirteenth MOS tube (M13) and a first capacitor (C1) and a second capacitor (C2); The drain of the second MOS tube (M2) is connected to the delay enhancement module; The gate of the sixth MOS tube (M6) is connected to the second end of the second capacitor (C2); The drain of the twelfth MOS tube (M12) is connected to the delay enhancement module, the source is grounded, and the gate is connected to the gate of the thirteenth MOS tube (M13); The drain of the thirteenth MOS tube (M13) is connected to the source of the sixth MOS tube (M6), and the source is grounded; The bias end includes: an eighth MOS tube (M8), a ninth MOS tube (M9), a tenth MOS tube (M10), an eleventh MOS tube (M11), a first resistor (R1), a second resistor (R2), a third resistor (R3) and a fourth resistor (R4); The drain of the eighth MOS tube (M8) is connected to the second end of the first resistor (R1) and the first end of the second resistor (R2), and the source is grounded; The drain of the ninth MOS tube (M9) is connected to the second end of the second resistor (R2) and the first end of the third resistor (R3), and the source is grounded; The drain of the tenth MOS tube (M10) is connected to the second end of the third resistor (R3) and the first end of the fourth resistor (R4), and the source is grounded; The drain of the eleventh MOS tube (M11) is connected to the second end of the fourth resistor (R4), and the source is grounded.

[0036] The main function of the bias circuit is to provide appropriate bias current for each level of the circuit so that it can work at a suitable static operating point. It ensures that the semiconductor device can work stably and reliably under a specific working state, thereby improving the performance of the device. By setting a suitable static operating point for the semiconductor device, the bias circuit can ensure that the device can maintain stable performance under various working conditions. In addition, the bias circuit can also reduce temperature drift, reduce noise, and improve linearity, thereby improving the stability and signal-to-noise ratio of the circuit and further enhancing the performance of the circuit.

[0037] Preferably, the delay enhancement module comprises: a third MOS tube (M3), a fourth MOS tube (M4), a fifth MOS tube (M5), a first transmission gate (TG1) and a second transmission gate (TG2); The gate of the third MOS tube (M3) is connected to the first transmission gate (TG1), and the source is connected to the source of the fifth MOS tube (M5) and the source of the fourth MOS tube (M4); The gate of the fourth MOS tube (M4) is connected to the second transmission gate (TG2); The gate of the fifth MOS tube (M5) is connected to the second transmission gate (TG2) The first transmission gate (TG1) and the second transmission gate (TG2) are connected.

[0038] The main function of the delay enhancement module is to output the signal after a certain time delay after the signal is input, so as to realize various functions that require time delay. The delay circuit plays an important role in electronic circuits. By delaying the electrical signal, many specific functions can be realized. For example, it can be used to produce echo effects and realize hysteresis in automatic control systems. The working principle of the delay circuit is based on the use of comparators and timers. When the input signal reaches the comparator, the comparator starts to compare the input signal with the reference voltage. When the input signal is greater than the reference voltage, the comparator outputs a high level, and the timer starts timing. When the timer reaches the set time, the voltage at the input end of the comparator rises to a threshold value sufficient to flip the comparator. At this time, the comparator outputs a low level, and the large capacitor discharges at the moment of the comparator flipping, thereby generating a delayed output signal. This circuit is simple, easy to implement, and highly stable.

[0039] The delay enhancement circuit can also be used to perform a variety of functions, but its common use is to calculate the delay, connected to the output node, and usually works when certain circuits are operated. There are many types of delay circuits, including precise long delay circuits, RC delay circuits, simple long delay circuits composed of 555 timers, etc. Each circuit has its specific application scenarios and advantages. For example, although the RC delay circuit is simple, it has the disadvantages of short delay time and low accuracy; while the precise long delay module can achieve precise delay control for a longer time through complex time base circuits and frequency division technology. The delay enhancement module introduces a certain time delay after the signal input, so as to achieve multiple functions such as echo effect in audio equipment and hysteresis in automatic control systems. Preferably, reference Figure 4 ,The delay module includes: four-way push-pull delay unit; The push-pull delay unit includes: a fourteenth MOS tube (M14), a fifteenth MOS tube (M15), a sixteenth MOS tube (M16) and a seventeenth MOS tube (M17); The drain of the fourteenth MOS tube (M14) is connected to the source of the fifteenth MOS tube (M15), and the gate is connected to Vbp; The gate of the fifteenth MOS tube (M15) is connected to the input, and the drain is connected to the output; The gate of the sixteenth MOS tube (M16) is connected to the input, the drain is connected to the output, and the source is connected to the drain of the seventeenth MOS tube (M17); The gate of the seventeenth MOS tube (M17) is connected to Vbn, and the source is grounded.

[0040] The push-pull delay circuit is an electronic component that combines the functions of a push-pull circuit and a delay circuit. It is mainly composed of two transistors with the same parameters (such as BJT or MOSFET). These transistors exist in the circuit in a push-pull manner, each responsible for the waveform amplification task of the positive and negative half cycles. When the circuit is working, only one of the two symmetrical power switch tubes is turned on at a time, so the conduction loss is small and the efficiency is high. In addition, this circuit structure also has a delay function, which can delay signal transmission or processing for a certain period of time.

[0041] Preferably, the sampling circuit comprises: a sampling resistor, an isolation capacitor and a variable resistor; Isolation capacitor and variable resistor are connected in series; ‌Isolation capacitor‌ is a component used in circuits, whose main function is to isolate intrinsically safe circuits from non-intrinsically safe circuits on the DC loop, and has specified performance. Isolation capacitors are usually used to protect key components to prevent chips from being disturbed and working abnormally or producing unexpected results. The implementation principle of isolation capacitors mainly relies on the charging and discharging characteristics of capacitors. Through the isolation effect of capacitors, the electrical system can be effectively separated, thereby preventing DC current and harmful AC current from being generated between two devices, while still allowing signal and power transmission. The principle of isolation capacitors is based on the characteristics of capacitors, using logic input and output buffers separated by a double capacitor insulation barrier. SiO2 has high dielectric strength and good insulation, which makes capacitive isolation have high reliability and safety. Compared with optocoupler isolation and magnetic isolation, capacitive isolation is widely used in low-voltage electronic circuits, especially in protecting valuable devices and key components. Capacitive isolation has strong anti-electromagnetic interference ability, low speed and power consumption, but it is difficult to perform power transmission‌.

[0042] The sampling resistor is connected in parallel with the isolation capacitor and the variable resistor, and the sampling resistor is used to collect the clock signal on the delay circuit.

[0043] The sampling resistor is a key component used to measure the current in a circuit. By introducing a resistor with a specific resistance value into the circuit, the current to be measured is converted into a voltage signal proportional to it. The sampling resistor device has a low resistance value, high precision and stability, and is widely used in various electronic devices and measuring instruments for real-time monitoring and control of current. The main function of the signal sampling resistor is to convert the current into a voltage signal, which is convenient for current measurement and control.

[0044] Example 2 A circuit control method for accelerating the write-balance training efficiency of a DDR-type dynamic memory comprises: S100, obtaining a reference clock signal; S200, obtaining multiple delayed signals on the delay circuit; S300, calculating a phase relationship between a command clock and a data clock according to a reference clock signal and a plurality of delay signals.

[0045] The present invention adds different delay and sampling circuits at the particle end, so that the controller end can obtain phase deviation information under multiple delay settings based on one delay setting. For example, under the condition that delay1 to delay n are uniformly set to values ​​​​from tCK / n to (n-1)tCK / n, the information fed back by a phase detection can help the controller end narrow the phase deviation range of the two clocks to within tCK / n, significantly improving the efficiency of write balance training.

[0046] While still using multiple DQ IO synchronous feedback or using other IOs as feedback signals, the present invention can also adopt a method of sequentially feeding back the phase relationship of two clocks under different delay conditions to achieve the purpose of improving training efficiency.

[0047] Example 3 An electronic device includes: a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, when the processor executes the computer instructions, the electronic device executes a circuit control method for accelerating the write equalization training efficiency of DDR type dynamic memory.

[0048] refer to Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0049] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0050] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0051] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0052] The present invention adds multiple delay and sampling circuits on the basis of the original receiving sampling circuit at the particle end, utilizes the condition that the controller and the particle have multiple DQ IOs, feeds back the original phase relationship of the two clocks on DQ0, and feeds back the phase relationship of the two clocks after delays of delay1 to delay n are added to the data clock on the remaining DQ1 to DQn respectively; the present invention can help the controller end to reduce the phase deviation range of the two clocks through the information fed back by only one phase detection, thereby significantly improving the efficiency of write equalization training.

[0053] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A circuit for accelerating the writing balance training efficiency of DDR-type dynamic memory, characterized in that: include: at least one delay circuit and at least one sampling circuit; The delay circuit is located at the particle end and is used to increase the delay of the command clock and the data clock; The sampling circuit is located at the particle end and is used to detect the phase relationship between the command clock and the data clock after being delayed by the delay circuit.

2. A circuit for accelerating the writing balance training efficiency of DDR-type dynamic memory according to claim 1, characterized in that: The delays of each of the delay circuits are not equal.

3. A circuit for accelerating the writing balance training efficiency of DDR-type dynamic memory according to claim 1, characterized in that: The delay circuit includes: a voltage-controlled voltage bias module, a delay module and a differential-to-single-ended module; The voltage-controlled voltage bias module is connected to the delay module and is used to control the delay time of the clock; The delay module is connected to the differential to single-ended module and is used to delay the reference clock signal; The differential to single-ended module is used to combine and output delayed clock signals.

4. A circuit for accelerating the writing balance training efficiency of a DDR-type dynamic memory according to claim 3, characterized in that: The voltage-controlled voltage bias module includes: a bias module and a delay enhancement module; The bias module is connected to the delay enhancement module and is used to bias the voltage; The delay enhancement module is used to expand the current range output by the bias module.

5. The circuit for accelerating the writing balance training efficiency of DDR-type dynamic memory according to claim 3, characterized in that: The bias module comprises: an output end, an input end and a bias end; The input end includes: a first MOS tube, a seventh MOS tube, an eighth MOS tube and a first resistor; The gate of the first MOS tube is connected to the gate of the second MOS tube, and the drain is connected to the drain of the seventh MOS tube; The source of the seventh MOS tube is connected to the first end of the first resistor, and the gate is connected to the control voltage; The source of the eighth MOS tube is grounded; The output end includes: a second MOS tube, a sixth MOS tube, a twelfth MOS tube, a thirteenth MOS tube and a first capacitor and a second capacitor; The drain of the second MOS tube is connected to the delay enhancement module; The gate of the sixth MOS tube is connected to the second end of the second capacitor; The drain of the twelfth MOS tube is connected to the delay enhancement module, the source is grounded, and the gate is connected to the gate of the thirteenth MOS tube; The drain of the thirteenth MOS tube is connected to the source of the sixth MOS tube, and the source is grounded; The bias end includes: an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a first resistor, a second resistor, a third resistor and a fourth resistor; The drain of the eighth MOS tube is connected to the second end of the first resistor and the first end of the second resistor, and the source is grounded; The drain of the ninth MOS tube is connected to the second end of the second resistor and the first end of the third resistor, and the source is grounded; The drain of the tenth MOS tube is connected to the second end of the third resistor and the first end of the fourth resistor, and the source is grounded; The drain of the eleventh MOS tube is connected to the second end of the fourth resistor, and the source is grounded.

6. A circuit for accelerating the writing balance training efficiency of DDR-type dynamic memory according to claim 4, characterized in that: The delay enhancement module includes: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a first transmission gate and a second transmission gate; The gate of the third MOS tube is connected to the first transmission gate, and the source is connected to the source of the fifth MOS tube and the source of the fourth MOS tube; The gate of the fourth MOS tube is connected to the second transmission gate; The gate of the fifth MOS tube is connected to the second transmission gate; The first transmission gate and the second transmission gate are connected.

7. The circuit for accelerating the writing balance training efficiency of DDR-type dynamic memory according to claim 3, characterized in that: The delay module includes: a four-way push-pull delay unit; The push-pull delay unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube; The drain of the fourteenth MOS tube is connected to the source of the fifteenth MOS tube, and the gate is connected to Vbp; The gate of the fifteenth MOS tube is connected to the input, and the drain is connected to the output; The gate of the sixteenth MOS tube is connected to the input, the drain is connected to the output, and the source is connected to the drain of the seventeenth MOS tube; The gate of the seventeenth MOS tube is connected to Vbn, and the source is grounded.

8. The circuit for accelerating the writing balance training efficiency of DDR-type dynamic memory according to claim 1, characterized in that: The sampling circuit comprises: a sampling resistor, an isolation capacitor and a variable resistor; The isolation capacitor and the variable resistor are connected in series; The sampling resistor is connected in parallel with the isolation capacitor and the variable resistor, and the sampling resistor is used to collect the clock signal on the delay circuit.

9. A circuit control method for accelerating the write-leveling training efficiency of DDR-type dynamic memory, characterized in that: include: Obtain a reference clock signal; Acquire multiple delayed signals on the delay circuit; The phase relationship between the command clock and the data clock is calculated according to the reference clock signal and a plurality of delay signals.

10. An electronic device, characterized in that: include: A processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a circuit control method for accelerating the write-leveling training efficiency of a DDR-type dynamic memory as described in claim 9.

Images