Phase change memory and memory system

Abstract

The invention relates to a phase change memory and a memory system, and the phase change memory comprises a memory array and a peripheral circuit. Wherein the peripheral circuit is coupled with the storage array and is configured to perform initial reading operation on a target storage unit in the storage array to obtain a first reading result; and under the condition that the error rate of the first reading result is greater than or equal to a first preset value, performing secondary reading operation on the target storage unit to obtain a second reading result, wherein the reading voltage of the secondary reading operation is greater than the reading voltage of the primary reading operation. Therefore, under the condition that the read interference of the phase change memory is voltage drift, the phase change memory can ensure the accuracy of the read result by increasing the read voltage, and write-in refreshing operation does not need to be carried out on a memory unit with an error, so that the write-in refreshing times of the phase change memory can be reduced, and the service life of the phase change memory is prolonged.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a phase change memory and a memory system. Background Art

[0002] The storage cell in phase change memory (PCM) realizes the reading, writing and erasing of information through the reversible change of phase change materials (such as GeSbTe, etc.) between the crystalline state and the amorphous state. Phase change memory has the characteristics of high integration density, low power consumption, high read and write times and strong anti-interference.

[0003] During the operation of phase change memory, the phase change material in the storage unit will switch between the crystalline state and the amorphous state. After multiple conversions of the phase change material, read disturbance (RD) will be generated, which will affect the data reading process and cause read data errors. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a phase change memory and a memory system to improve the efficiency of data reading.

[0005] The technical solution of the present invention is achieved in this way:

[0006] An embodiment of the present disclosure provides a phase change memory, comprising: a memory array and a peripheral circuit; wherein the peripheral circuit is coupled to the memory array and is configured to perform an initial read operation on a target memory cell in the memory array to obtain a first read result; and, when a bit error rate of the first read result is greater than or equal to a first preset value, perform a secondary read operation on the target memory cell to obtain a second read result; wherein a read voltage of the secondary read operation is greater than a read voltage of the initial read operation.

[0007] In the above solution, the peripheral circuit is further configured to determine a bit error rate of the second reading result; and output the second reading result when the bit error rate of the second reading result is less than a second preset value.

[0008] In the above solution, the peripheral circuit is further configured to perform a write refresh operation on the target storage unit when the bit error rate of the second read result is greater than or equal to the second preset value.

[0009] In the above solution, the second preset value is less than or equal to the first preset value.

[0010] In the above solution, the peripheral circuit is further configured to confirm the memory cell to be refreshed in the target memory cell based on the second reading result; and perform the write refresh operation on the memory cell to be refreshed.

[0011] In the above solution, the read voltage of the second read operation is determined according to the voltage drift rate of the target memory cell.

[0012] In the above solution, the peripheral circuit is further configured to determine a bit error rate of the first reading result; wherein, when the bit error rate of the first reading result is less than the first preset value, the first reading result is output.

[0013] In the above solution, the peripheral circuit is further configured to compare the second read result with expected data, and confirm the storage unit to be refreshed based on the comparison result; wherein the expected data is data written to the target storage unit.

[0014] In the above solution, the peripheral circuit is further configured to adjust the read voltage of the remaining memory cells except the memory cell to be refreshed to the read voltage of the secondary read operation.

[0015] An embodiment of the present disclosure also provides a memory system, comprising: one or more phase change memories as described in the above scheme, and a memory controller; the memory controller is coupled to the phase change memory; the memory controller controls the phase change memory.

[0016] The disclosed embodiment provides a phase change memory, including: a memory array and a peripheral circuit; wherein the peripheral circuit is coupled to the memory array and is configured to perform an initial read operation on a target memory cell in the memory array to obtain a first read result; and, when the error rate of the first read result is greater than or equal to a first preset value, perform a secondary read operation on the target memory cell to obtain a second read result; wherein the read voltage of the secondary read operation is greater than the read voltage of the primary read operation. In this way, when the read disturbance of the phase change memory is voltage drift, the phase change memory can ensure the accuracy of the read result by increasing the read voltage, and does not need to perform a write refresh operation on the memory cell with an error, thereby reducing the number of write refreshes of the phase change memory and improving the life of the phase change memory. Moreover, in the process of reading the second read result, the secondary read operation corrects the error of the memory cell with the error, that is, the secondary read operation can simultaneously complete data reading and error correction, thereby reducing the time for reading data and improving the efficiency of reading data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A schematic diagram of the structure of the phase change memory provided in the embodiment of the present disclosure Figure 1 ;

[0018] Figure 2 A curve diagram showing the read disturbance provided by the embodiment of the present disclosure Figure 1 ;

[0019] Figure 3 A curve diagram showing the read disturbance provided by the embodiment of the present disclosure Figure 2 ;

[0020] Figure 4 A schematic diagram of the structure of the phase change memory provided in the embodiment of the present disclosure Figure 2 ;

[0021] Figure 5 Schematic diagram of the reading method provided in the embodiment of the present disclosure Figure 1 ;

[0022] Figure 6 Schematic diagram of the reading method provided in the embodiment of the present disclosure Figure 2 ;

[0023] Figure 7 Schematic diagram of the reading method provided in the embodiment of the present disclosure Figure 3 ;

[0024] Figure 8 A schematic diagram of the structure of a memory system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0026] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0029] Figure 1 is an optional structural diagram of the phase change memory 100 provided in the embodiment of the present disclosure, refer to Figure 1 The phase change memory 100 includes a memory array 10 and a peripheral circuit 20. The peripheral circuit 10 is coupled to the memory array 20. The peripheral circuit 10 is configured to perform a first read operation on a target memory cell in the memory array 20 to obtain a first read result. The peripheral circuit 10 is also configured to perform a second read operation on the target memory cell when the bit error rate of the first read result is greater than or equal to a first preset value to obtain a second read result. The read voltage of the second read operation is greater than the read voltage of the first read operation.

[0030] In the embodiments of the present disclosure, reference Figure 1 , the peripheral circuit 10 can be coupled to at least one storage array 20. The peripheral circuit 10 can perform an initial read operation on the target storage cell in the storage array 20 based on a read command received from the outside, and obtain the data of the target storage cell in the storage array 20 (i.e., the first read result). The read command can come from a device such as a processor (CPU). The read command can include a target address. The target address can be the address of the target storage cell in the storage array 20 that needs to perform the initial read operation. The target storage cell may include multiple storage cells. For example, the peripheral circuit 10 can decode the target address corresponding to the read command based on the received read command. Since the resistivity difference between the phase change material in the storage cell in the crystalline state and the amorphous state is very large, the peripheral circuit 10 can apply a first read voltage to the target storage cell corresponding to the target address in the storage array 20, determine the logical value of each storage cell through the current of each storage cell, and read out the first read result of the target storage cell.

[0031] In the embodiments of the present disclosure, reference Figure 1 , the peripheral circuit 10 can read the first read result corresponding to the read command from the storage array 20, and determine the bit error rate of the first read result. For example, the read command can also include expected data, and the expected data can be data written to multiple storage cells corresponding to the target address in the storage array 20. The peripheral circuit 10 can compare the first read result corresponding to the target address bit by bit based on the expected data, and count the number of inconsistent bits, that is, count the bit error rate of the first read result. For another example, the peripheral circuit 10 can also determine the bit error rate of the first read result by using error checking and correction technology (Error Checking and Correcting, ECC).

[0032] In the embodiments of the present disclosure, reference Figure 1 , the first preset value can be used to evaluate the reliability level of the first read result and determine whether the first read result is within an acceptable bit error rate range of the phase change memory 100. The first preset value can be stored in a register of the peripheral circuit 10. The peripheral circuit 10 can call the stored first preset value to determine whether the bit error rate of the first read result is greater than or equal to the first preset value. In this way, if the bit error rate of the first read result is less than the first preset value, it means that the bit error rate of the first read result is within the acceptable bit error rate range of the phase change memory 100, and the peripheral circuit 10 can output the first read result to perform subsequent operation steps. Conversely, if the bit error rate of the first read result is greater than or equal to the first preset value, it means that the bit error rate of the first read result exceeds the acceptable bit error rate range of the phase change memory 100, and there is read interference during the data reading process of the target storage unit.

[0033] It should be noted that the reference Figure 1 The read disturbance that causes the data of the first read result to be erroneous usually includes voltage drift and unexpected crystal state change.

[0034] Voltage drift is the read voltage drift caused by the phase change material and other devices in the phase change memory 100 changing over time. Figure 2 As shown, when voltage drift occurs during the reading process of the phase change memory 100, the curve of the number of errors (number of error bits) in the reading result caused by the voltage drift changes with the reading voltage from L1 to L2. The peripheral circuit 10 uses the first reading voltage (voltage 1) to read data, and the number of errors in the reading result corresponding to the curve L2 after the voltage drift is greater than the number of errors in the reading result corresponding to the curve L1 before the voltage drift, that is, the bit error rate of the reading result will increase. At this time, the peripheral circuit 10 uses the second reading voltage (voltage 2) to read data, and the number of errors in the reading result corresponding to the curve L2 after the voltage drift will significantly decrease or disappear. In other words, the reading error of the storage unit caused by voltage drift can be eliminated by increasing the reading voltage.

[0035] Unexpected crystal state change is the unexpected crystal state change of the phase change material in the memory cell caused by multiple readings. Figure 3 As shown, in the case where an unexpected crystalline state change occurs during the reading process of the phase change memory 100, a curve showing the number of errors in the reading result caused by the unexpected crystalline state change as the reading voltage changes is shown in FIG. Figure 2 The L1 changes in Figure 3L3 in. At this time, the read voltage of the peripheral circuit 10 increases from the first read voltage (voltage 1) to the second read voltage (voltage 2), and the decrease in the number of errors in the read result corresponding to the curve L3 after the unexpected crystalline change occurs is not large. In other words, the read error of the memory cell caused by the unexpected crystalline change cannot be eliminated by increasing the read voltage. In this way, the peripheral circuit 10 needs to perform a write refresh operation on the memory cell with the error so that the memory cell with the error can continue to be used.

[0036] In the case where both unexpected crystal state change and voltage drift read disturbance exist, the curve of the number of errors (number of error bits) in the read result versus the read voltage is shown in Figure 2 The L1 changes in Figure 3 L4 in. At this time, compared with the number of errors in the read result read by the peripheral circuit 10 using the first read voltage (voltage 1), the number of errors in the read result read by the peripheral circuit 10 using the second read voltage (voltage 2) decreases. That is, in the case where both unexpected crystal state changes and voltage drifts are present, the peripheral circuit 10 can eliminate the read errors of the storage cells caused by the voltage drift by increasing the read voltage, thereby reducing the number of storage cells with errors in the read result.

[0037] In the embodiments of the present disclosure, reference Figure 1 , usually, if the data of the first read result is wrong, the peripheral circuit in the related art will directly perform a write refresh operation on the target memory cell where the error occurs. However, the number of writes and erases that the memory cell in the phase change memory can withstand is limited. In order to improve the life of the phase change memory 100, the peripheral circuit 10 of the embodiment of the present disclosure performs a secondary read operation on the target memory cell when the bit error rate of the first read result is greater than or equal to the first preset value. For example, the peripheral circuit 10 can perform a secondary read operation on the target memory cell using a second read voltage (voltage 2) to obtain a second read result. The second read voltage is greater than the first read voltage. In this way, the peripheral circuit 10 can confirm whether there is a voltage drift in the target memory cell by whether the bit error rate of the second read result of the secondary read operation changes. For example, if the bit error rate of the secondary read operation is less than the bit error rate of the first read result, it means that the secondary read operation eliminates some of the read errors in the first read result, and the main source of read interference of the memory cell with errors in the first read result is voltage drift. That is to say, the embodiment of the present disclosure can eliminate the read data errors caused by voltage drift by adding a larger read voltage to perform a secondary read operation on the target memory cell.

[0038] It can be understood that in the embodiment of the present disclosure, when an error occurs in the first read result of the initial read operation, a larger read voltage is added to perform a secondary read operation on the target storage unit. In this way, when the read disturbance of the phase change memory 100 is voltage drift, the phase change memory 100 can use the method of increasing the read voltage to eliminate the read data error caused by the voltage drift, thereby improving the accuracy of the read result, and the phase change memory 100 does not need to perform a write refresh operation on the storage unit with an error, thereby reducing the number of write refreshes of the phase change memory 100 and improving the life of the phase change memory 100. In addition, in the process of reading the second read result, the secondary read operation eliminates the error caused by the voltage drift in the first read result, that is, the error correction is performed on some of the storage units with errors in the first read result, thereby, the secondary read operation can complete data reading and error correction at the same time, which can reduce the time of reading data and improve the efficiency of reading data.

[0039] In some embodiments of the present disclosure, reference Figure 1 The peripheral circuit 10 is further configured to determine the bit error rate of the second read result. The peripheral circuit 10 is further configured to perform a write refresh operation on the target storage unit when the bit error rate of the second read result is greater than or equal to a second preset value.

[0040] In the embodiments of the present disclosure, reference Figure 1 , the peripheral circuit 10 can apply a second read voltage to the target memory cell in the memory array 20 to read out the corresponding second read result. The peripheral circuit 10 can also determine the bit error rate of the second read result. The process of determining the bit error rate of the second read result can be understood with reference to the above-mentioned first read result, and will not be repeated here.

[0041] In the embodiments of the present disclosure, reference Figure 1 , the second preset value can also be stored in the register in the peripheral circuit 10. The peripheral circuit 10 can call the stored second preset value to determine whether the second read result is greater than the second preset value. For example, the second preset value can be equal to the first preset value. In this way, if the bit error rate of the second read result is greater than or equal to the second preset value, it means that the bit error rate of the secondary read operation has not changed (or the change is not large), and the secondary read operation has not eliminated the read interference of the storage unit with errors in the first read result. The source of the read interference that caused the error in the first read result is mainly unexpected crystalline changes. In other words, the embodiment of the present disclosure can determine the source of the read interference that causes the read data error through a secondary read operation.

[0042] Furthermore, the peripheral circuit 10 can perform a write refresh operation on the target storage cell based on the second read result. For example, the peripheral circuit 10 can compare the expected data with the second read result, determine the address of the storage cell where the error occurs in the second read result, and perform a write refresh operation on the storage cell where the error occurs in the second read result. In the case where the read interference of the phase change memory 100 is voltage drift, the secondary read operation can correct the error of the storage cell where the error occurs, that is to say: the read error of the storage cell where only the voltage offset exists can be eliminated through the secondary read operation. In this way, the embodiment of the present disclosure performs a write refresh operation on the target storage cell based on the second read result, and can eliminate the storage cell where only the voltage offset causes the data error, thereby reducing the number of storage cells where the error occurs in the secondary read operation and improving the error correction efficiency of the phase change memory 100.

[0043] In some embodiments of the present disclosure, reference Figure 1 The peripheral circuit 10 is further configured to output the second read result when the bit error rate of the second read result is less than a second preset value.

[0044] In the embodiments of the present disclosure, reference Figure 1 , the bit error rate of the second read result is less than the second preset value, which means that the secondary read operation corrects the storage unit with errors in the first read result, and the source of read interference that causes the error in the first read result is mainly voltage drift. The bit error rate of the second read result is less than the second preset value, and the error level of the data in the second read result is within an acceptable range. The peripheral circuit 10 can output the second read result to perform subsequent operation steps. In other words, the secondary read operation can complete data reading and error correction at the same time, so that the embodiment of the present disclosure can reduce the time of reading data and improve the efficiency of reading data.

[0045] In some embodiments of the present disclosure, the second preset value is equal to or less than the first preset value.

[0046] The present disclosure embodiment refers to Figure 2 , the second preset value is equal to the first preset value, or the second preset value is less than the first preset value. In this way, the embodiment of the present disclosure can determine whether the bit error rate of the second read result is less than the bit error rate of the first read result according to whether the bit error rate of the second read result is greater than or equal to the second preset value. Thus, the embodiment of the present disclosure can confirm the source of the read disturbance in the phase change memory 100 according to whether the bit error rate of the second read result changes.

[0047] In some embodiments of the present disclosure, reference Figure 1 The peripheral circuit 10 is further configured to confirm the memory cells to be refreshed in the target memory cells based on the second read result. The peripheral circuit 10 is further configured to perform a write refresh operation on the memory cells to be refreshed.

[0048] In the embodiments of the present disclosure, reference Figure 2 , the peripheral circuit 10 can confirm the storage cell to be refreshed in the target storage cell based on the second read result. For example, the peripheral circuit 10 is configured to compare the second read result with the expected data, and confirm the storage cell to be refreshed based on the comparison result. The peripheral circuit 10 can compare the expected data and the second read result bit by bit, and the storage cell in which the second read result and the expected data are inconsistent (data errors) is the storage cell to be refreshed. For another example, the peripheral circuit 10 can also determine the address of the storage cell where the error occurs through error checking and correction technology, and then confirm the output storage cell to be refreshed. The read error of the storage cell with only voltage offset can be eliminated through a secondary read operation. In this way, the storage cell to be refreshed in the embodiment of the present disclosure is determined based on the second read result of the secondary read operation, and the storage cell with data errors caused by voltage offset can be eliminated. Thereby, the number of storage cells to be refreshed is reduced, and the error correction efficiency of the phase change memory 100 can be improved.

[0049] In the embodiments of the present disclosure, reference Figure 2 , the peripheral circuit 10 can perform a write refresh operation on the memory cell to be refreshed. For example, if the expected data of the memory cell with an error (the memory cell to be refreshed) is 0, then in the preset refresh operation cycle, a strong short pulse is applied to the memory cell with an error, the temperature of the phase change material is raised to above the melting temperature, and then the phase change material is quickly cooled to achieve the transformation from polycrystalline to amorphous state, and the logic value of the data of the memory cell with an error is converted from 1 to 0, that is: the memory cell with an error is erased (Reset). If the expected data of the memory cell with an error (the memory cell to be refreshed) is 1, then in the preset refresh cycle, a medium-strong long pulse is applied to the memory cell with an error, the temperature of the phase change material is raised to above the crystallization temperature and below the melting temperature, and is maintained for a period of time to achieve the transformation of the material from amorphous state to crystalline state, and the logic value of the data of the memory cell with an error is converted from 0 to 1, that is: the memory cell with an error is written (Set).

[0050] In the embodiments of the present disclosure, reference Figure 2, the peripheral circuit 10 is also configured to adjust the read voltage of the remaining memory cells except the memory cells to be refreshed to the read voltage of the secondary read operation. That is to say, the peripheral circuit can set the read voltage of the memory cells in the target memory cells that do not need to be written to the second read voltage. In this way, in the subsequent read operation, the peripheral circuit 10 can directly use the second read voltage to read the data of these memory cells that do not need to be written to the refresh operation, that is: the peripheral circuit 10 only needs to perform a read operation on these memory cells once in the subsequent read operation. Thereby, the time for reading data can be reduced and the efficiency of reading data can be improved.

[0051] It should be noted that the reference Figure 2 , the peripheral circuit 10 can also compare the first read data with the expected data, and identify the storage cells in the target storage cells that do not need to adjust the read voltage based on the comparison result. For example, the peripheral circuit 10 can compare the expected data and the first read result bit by bit, and the first read result of any storage cell in the target storage cells is consistent with the expected data, that is, the data of the storage cell in the initial read operation is correct, and there is no read interference. Therefore, it is not necessary to set the read voltage of the storage cell in the subsequent reading process to the second read voltage.

[0052] In some embodiments of the present disclosure, a read voltage of the second read operation is determined according to a voltage drift rate of a target memory cell.

[0053] In the embodiments of the present disclosure, reference Figure 1 The voltage drift rate of the phase change memory 100 can be determined by parameters such as the resistance drift of the phase change material of the memory cell. Therefore, the embodiment of the present disclosure can determine the read voltage of the secondary read operation based on the voltage drift rate of the phase change memory 100, ensuring that the read voltage of the secondary read operation is within a suitable voltage range.

[0054] Figure 4 1 is an optional structural diagram of an optional phase change memory 100 provided in an embodiment of the present disclosure. It should be noted that the preset threshold value may include a first preset value and a second preset value. The preset threshold value may be stored in a register of the peripheral circuit 10 during the process of configuring the mode register of the peripheral circuit 10.

[0055] In the embodiments of the present disclosure, reference Figure 4, the peripheral circuit 10 may include a logic control module 110 and a verification module 120. The logic control module 110 may perform an initial read operation on a target storage cell in the phase change memory to obtain a first read result. For example, in the process of the peripheral circuit 10 performing an initial data read operation on a target storage cell in the storage array 20, the logic control module 110 may generate a clock signal, an address signal, and a command signal required to read the data in the storage array 20 based on a read command. Furthermore, the storage array 20 may ensure that the read data is read at the correct timing based on the control of the clock signal, the address signal, and the command signal. The address signal is used to determine the position of the target storage cell corresponding to the target address, and the address signal may include a column address signal and a row address signal. The command signal is used to instruct the storage array 20 to perform a read operation. The command signal may include a first read voltage and a second read voltage.

[0056] In the embodiments of the present disclosure, reference Figure 4 , the verification module 120 can determine the bit error rate of the first read result, and judge whether the bit error rate of the first read result is greater than the first preset value. For example, the verification module 120 may include a comparator and a counter. The first read result and the expected data may include 128 bits, and the corresponding first preset value may be 18. The two input ends of the comparator in the verification module 120 receive the first read result and the expected data respectively, and judge whether the read data and the expected data are consistent bit by bit, and generate corresponding multiple comparison results. The counter in the verification module 120 can count multiple comparison results. When the number of bits that the read data and the expected data are inconsistent (i.e., the number of error bits of the first read result) is greater than or equal to 18, the verification module 120 confirms that the bit error rate of the first read result is greater than or equal to the first preset value.

[0057] In the embodiments of the present disclosure, reference Figure 4 , the verification module 120 can also determine whether the bit error rate of the second read result is greater than a second preset value. For example, the second preset value can be 16. In this way, the embodiment of the present disclosure can determine the source of the read disturbance of the storage unit with errors in the first read result according to whether the bit error rate of the second read result is greater than the second preset value. For example, Figure 5 As shown, if the bit error rate of the first read result is greater than or equal to the first preset value, it means that the logic control module 110 uses the first read voltage and the second read voltage to perform the initial read operation on the target storage unit and there is read interference, that is: Figure 5 As shown in S401 , there is read disturbance in the voltage 1 reading.

[0058] Furthermore, the logic control module 110 can perform a second read operation on the target storage unit using the second read voltage to obtain a second read result. If the bit error rate of the second read result is greater than or equal to the second preset value, it means that the logic control module 110 performs a second read operation on the target storage unit using the second read voltage and there is read interference, that is: Figure 5 As shown in S403, the voltage 2 read disturbance still exists. Therefore, the verification module 120 can confirm that the source of the read disturbance of the initial read operation is as follows: Figure 5 The unexpected crystalline change shown in S405.

[0059] On the contrary, if the bit error rate of the second reading result is less than the second preset value, it means that there is no read disturbance when the logic control module 110 performs a second reading operation on the target memory cell using the second reading voltage. Figure 5 As shown in S402, the voltage 2 read disturbance disappears. Thus, the verification module 120 can confirm that the source of the read disturbance in the initial read operation is as follows: Figure 5 Thus, the verification module 120 can confirm the source of the read disturbance of the initial read operation such as Figure 5 That is, the embodiment of the present disclosure can confirm the source type of read disturbance in the phase change memory 100 by performing the initial read operation and the secondary read operation, and determining the change of the bit error rate of the corresponding first read result and the second read result.

[0060] In the embodiments of the present disclosure, reference Figure 4 , when the bit error rate of the second read result is less than the second preset value, the logic control module 110 can output the second read result. When the bit error rate of the second read result is greater than or equal to the second preset value, the verification module 120 can confirm the address of the storage unit in which the error occurs in the second read result, and the logic control module 110 can perform a write refresh operation on the storage unit in which the error occurs in the target storage unit according to the address of the storage unit in which the error occurs. In this way, the embodiment of the present disclosure performs a write refresh operation on the target storage unit based on the second read result, which can reduce the number of storage units in which the error occurs in the second read result, thereby improving the error correction efficiency of the phase change memory 100.

[0061] Figure 6 is an optional structural diagram of a method for reading a phase change memory provided by an embodiment of the present disclosure, which is combined with Figure 6 The steps shown are described below. It should be noted that Figure 1 and Figure 4 The phase change memory 100 shown in FIG. Figure 6 The reading method shown performs data reading.

[0062] S101: Perform an initial read operation on a target storage unit to obtain a first read result.

[0063] S102: Determine the bit error rate of the first reading result.

[0064] In the embodiments of the present disclosure, reference Figure 4 , the logic control module 110 can perform an initial read operation on the target storage unit in the phase change memory based on the read command received from the outside to obtain a first read result. Then, the verification module 120 can receive the first read result from the logic control module 110 (or the storage array 20) and determine the bit error rate of the first read result. Finally, the verification module 120 can call the first preset value from the register of the peripheral circuit 10 and determine whether the bit error rate of the first read result is greater than the first preset value.

[0065] S103 . If the bit error rate of the first read result is greater than or equal to the first preset value, perform a second read operation on the target storage unit to obtain a second read result; wherein the read voltage of the second read operation is greater than the read voltage of the initial read operation.

[0066] In the embodiments of the present disclosure, reference Figure 4 , when the bit error rate of the first read result is greater than or equal to the first preset value, the verification module 120 can issue an instruction to perform a secondary read operation to the logic control module 110. The logic control module 110 can apply a second read voltage to the target storage unit based on the received instruction of the secondary read operation, perform a secondary read operation on the target storage unit, and obtain a second read result. When the bit error rate of the first read result is less than the first preset value, the logic control module 110 does not receive the instruction to perform a secondary read operation, and can directly output the first read result. In this way, the embodiment of the present disclosure can perform a secondary read operation on the target storage unit by adding a larger read voltage to confirm whether the source of the read disturbance that causes the read data error is voltage drift. Therefore, in the case where the read disturbance of the phase change memory 100 is voltage drift, the secondary read operation can correct the error of the storage unit with the error, and there is no need to perform a write refresh operation on the storage unit with the error, thereby reducing the number of write refreshes of the phase change memory 100 and improving the life of the phase change memory 100. In addition, the secondary read operation can complete data reading and error correction at the same time, thereby reducing the time for reading data and improving the efficiency of reading data.

[0067] In some embodiments of the present disclosure, after completing Figure 6 After S101 to S103 in the above, the reading method can be further implemented through S201 to S202, which will be described in combination with each step.

[0068] S201. Determine a bit error rate of the second reading result.

[0069] In the embodiments of the present disclosure, reference Figure 4 , the verification module 120 can receive the second read result from the logic control module 110 (or the storage array 20) and determine the bit error rate of the second read result. Then, the verification module 120 can call the second preset value from the register of the peripheral circuit 10 and determine whether the bit error rate of the second read result is greater than the second preset value.

[0070] S202: If the bit error rate of the second reading result is less than a second preset value, output the second reading result; or, if the bit error rate of the second reading result is less than the second preset value, output the second reading result.

[0071] In the embodiments of the present disclosure, reference Figure 4 In the case where the bit error rate of the second read result is greater than or equal to the second preset value, the verification module 120 can determine the storage unit to be refreshed that needs to be written and refreshed, and send an instruction to perform the write refresh operation to the logic control module 110. The logic control module 110 can perform a write refresh operation on the storage unit to be refreshed in the target storage unit based on the received instruction of the write refresh operation and the address of the storage unit to be refreshed. In the case where the bit error rate of the second read result is less than the second preset value, the logic control module 110 does not receive the instruction to perform the write refresh operation and can directly output the second read result. In this way, in the case where the read disturbance of the phase change memory 100 is voltage drift, the secondary read operation can correct the error of the storage unit in which the error occurs, that is to say: the read error of the storage unit with only voltage offset can be eliminated by the secondary read operation. Thereby, the number of storage units in which the error occurs in the secondary read operation can be reduced, and the error correction efficiency of the phase change memory 100 can be improved.

[0072] Figure 7 is a flowchart of another optional reading method provided by the embodiment of the present disclosure, and can also be performed by Figure 7 The method for reading the phase change memory shown in S301 to S307 will be described in combination with each step.

[0073] S301, voltage 1 input.

[0074] In the embodiments of the present disclosure, reference Figure 4Before the expected data is written into the phase change memory 100, the peripheral circuit 10 may generate additional redundant check bits for the expected data through error checking and correction technology. Then, the generated redundant check bits and the expected data are stored in the phase change memory 100. In the subsequent process of the initial read operation performed by the peripheral circuit 10, voltage 1 is input, that is, a first read voltage is applied to the corresponding memory cell in the memory array 20, and a first read result of the target memory cell in the memory array 20 is read. The first read data may include the generated redundant check bits.

[0075] S302, determine the read data.

[0076] In the embodiments of the present disclosure, reference Figure 4 The peripheral circuit 10 may use an error checking and correction technique to decode the received first read result, and then determine whether the bit error rate of the first read result is greater than a threshold value 1 (a first preset value) through the decoded redundant check bits.

[0077] S303: The bit error rate reaches threshold 1.

[0078] In the embodiments of the present disclosure, reference Figure 4 If the bit error rate does not reach the threshold value 1 (the first preset value), that is, the bit error rate of the first read result is within the allowable range of the phase change memory 100, the peripheral circuit 10 can execute Figure 7 In S306, the first reading result is output for subsequent operations.

[0079] On the contrary, if the bit error rate of the first read result reaches the threshold value 1 (the first preset value), that is, the bit error rate of the first read result exceeds the allowable range of the phase change memory 100, then the execution Figure 7 S304 in.

[0080] S304, voltage 2 input.

[0081] In the embodiments of the present disclosure, reference Figure 4 If the bit error rate of the first read result read out by the peripheral circuit 10 reaches the threshold value 1, that is, the bit error rate of the first read result is greater than or equal to the first preset value, the peripheral circuit 10 inputs voltage 2 to the corresponding storage cell in the storage array 20, that is, applies the second read voltage to the corresponding storage cell in the storage array 20, reads the data of the target storage cell in the storage array 20, and generates a second read result.

[0082] S305: The bit error rate reaches threshold 2.

[0083] In the embodiments of the present disclosure, reference Figure 2, the peripheral circuit 10 can determine whether the bit error rate of the second read result is greater than threshold 2 (second preset value). If the bit error rate of the second read result read by the peripheral circuit 10 reaches threshold 2, that is, the bit error rate of the second read result is within the allowable range of the phase change memory 100, the peripheral circuit 10 can execute Figure 7 In S306, the second reading result is output for subsequent operations.

[0084] On the contrary, if the bit error rate of the second read result reaches the threshold 2 (the first preset value), that is, the bit error rate of the first read result exceeds the allowable range of the phase change memory 100, then the execution Figure 7 S304 in.

[0085] S306, output.

[0086] S307, write refresh.

[0087] In the embodiments of the present disclosure, reference Figure 4 If the bit error rate of the second read result read out by the peripheral circuit 10 reaches threshold 2 (second preset value), that is, the bit error rate of the second read result is greater than or equal to the second preset value, the peripheral circuit 10 can use the information in the redundant check bit to determine the address of the storage unit where the error occurs in the second read result, and perform a write refresh operation on the storage unit where the error occurs.

[0088] Figure 8 A schematic diagram of the structure of an optional memory system 300 provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the memory system 300 includes one or more phase change memories 100 , and a memory controller 200 .

[0089] In the embodiments of the present disclosure, reference Figure 8 The memory controller 200 is coupled to the phase change memory 100 and the host HOST, and is configured to control the phase change memory 100. The host HOST may be a processor (CPU) or a graphics processor (GPU). The host HOST may be configured to send data to the phase change memory 100, or to receive data from the phase change memory 100.

[0090] Continue to refer Figure 8 The memory controller 200 may manage data in the phase-change memory 100 and communicate with the host HOST. The memory controller 200 may be configured to control operations of the phase-change memory 100, such as read and write operations.

[0091] In the embodiments of the present disclosure, reference Figure 8The memory controller 200 may send data to the host HOST and receive data from the host HOST; and the memory controller 200 may send a command CMD and an address ADDR to the phase change memory 100 .

[0092] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0093] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0094] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A phase change memory, characterized in that: include: Storage array and peripheral circuits; wherein, The peripheral circuit is coupled to the memory array and is configured to perform an initial read operation on a target memory cell in the memory array to obtain a first read result; and When the bit error rate of the first reading result is greater than or equal to a first preset value, a second reading operation is performed on the target storage unit to obtain a second reading result; wherein, The read voltage of the second read operation is greater than the read voltage of the first read operation.

2. The phase change memory according to claim 1, characterized in that: The peripheral circuit is further configured to output the second reading result when a bit error rate of the second reading result is less than a second preset value.

3. The phase change memory according to claim 2, characterized in that: The peripheral circuit is further configured to perform a write refresh operation on the target storage unit when the bit error rate of the second read result is greater than or equal to the second preset value.

4. The phase change memory according to claim 2, characterized in that: The second preset value is less than or equal to the first preset value.

5. The phase change memory according to claim 3, characterized in that: The peripheral circuit is further configured to confirm the memory cell to be refreshed in the target memory cell based on the second reading result; and perform the write refresh operation on the memory cell to be refreshed.

6. The phase change memory according to claim 5, characterized in that: The peripheral circuit is further configured to compare the second read result with expected data, and confirm the storage unit to be refreshed based on the comparison result; wherein the expected data is data written to the target storage unit.

7. The phase change memory according to claim 5, characterized in that: The peripheral circuit is further configured to adjust the read voltage of the remaining memory cells except the memory cell to be refreshed to the read voltage of the secondary read operation.

8. The phase change memory according to claim 1, characterized in that: A read voltage of the second read operation is determined according to a voltage drift rate of the target memory cell.

9. The phase change memory according to claim 1, characterized in that: The peripheral circuit is further configured to output the first reading result when a bit error rate of the first reading result is less than the first preset value.

10. A memory system, characterized in that: include: One or more phase change memories as claimed in claims 1 to 9, and a memory controller; wherein, The memory controller is coupled to the phase change memory; the memory controller controls the phase change memory.

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