Memory

Abstract

The invention discloses a memory, and the memory comprises at least one storage library, each storage library comprises two storage surfaces, and each storage surface comprises a plurality of storage resources and a plurality of redundant replacement resources; wherein the damaged storage resources of each storage surface can be replaced by the redundant replacement resources of the other storage surface, so that normal read-write operation can be carried out. Through the mode, redundant replacement resources in different storage surfaces can be shared mutually, so that the flexibility of replacement and the yield of the memory are improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a memory. Background Art

[0002] In the manufacturing process of memory, especially dynamic random access memory (DRAM), there may be defects in the memory cells (MC) in the row direction, which cannot perform storage operations normally; or the memory cells in the column direction may have defects, which cannot perform storage operations normally. Therefore, in order to improve the yield of random access memory, it is necessary to add some spare circuits and spare memory cells to replace damaged word lines, bit lines and memory cells. These spare circuits and spare memory cells are collectively referred to as replacement (RDN, redundancy) resources. Specifically, when there are defects in the memory cells in the row direction and replacement in the row direction is required, it is called row redundancy; when there are defects in the memory cells in the column direction and replacement in the column direction is required, it is called column redundancy.

[0003] As the storage capacity of dynamic random access memory continues to increase, in order to facilitate access and control, the storage array is divided into multiple banks, and each bank is divided into two adjacent storage planes, such as a first storage plane P0 and a second storage plane P1. A fixed number of replacement resources are set in each storage plane to replace damaged storage resources in the corresponding storage plane. However, in the actual process manufacturing process, the probability and number of damaged storage resources in the first storage plane P0 and the second storage plane P1 are different, which may result in sufficient replacement resources for one of the two storage planes, while insufficient replacement resources for the other of the two storage planes. Summary of the invention

[0004] In order to solve the above problems, the present application provides a memory that can share redundant replacement resources in different storage planes, thereby improving the flexibility of replacement and the yield of the memory.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a memory, comprising: at least one storage library, each of the storage libraries comprising two storage planes, each of the storage planes comprising multiple storage resources and multiple redundant replacement resources; wherein the damaged storage resources of each storage plane can be replaced by the redundant replacement resources of another storage plane to perform normal read and write operations.

[0006] Each of the storage resources includes a plurality of ordinary storage units arranged in rows or columns, and each of the redundant replacement resources includes a plurality of redundant storage units arranged in rows or columns. When any of the storage resources has a damaged ordinary storage unit, the storage resource is defined as the damaged storage resource.

[0007] Wherein, each of the storage planes can selectively operate in a first operating mode or a second operating mode; wherein, when the storage plane operates in the first operating mode, the damaged storage resources in the storage plane are only replaced by the redundant replacement resources in the same storage plane; when the storage plane operates in the second operating mode, the damaged storage resources in the storage plane can be replaced by the redundant replacement resources in another storage plane.

[0008] Among them, when the storage plane operates in the second working mode, the priority level of the damaged storage resource in the storage plane being replaced by the redundant replacement resource in the same storage plane is greater than the priority level of the damaged storage resource in the storage plane being replaced by the redundant replacement resource in another storage plane.

[0009] Wherein, the storage resources include column storage resources, and the redundant replacement resources include column redundant replacement resources; each of the storage banks includes column decoding circuits corresponding to the two storage planes respectively, and in response to a mode signal being a first logic level, the column decoding circuit can only enable the column redundant replacement resources in the corresponding storage plane to replace the damaged column storage resources in the same storage plane; in response to a mode signal being a second logic level, the column decoding circuit can enable the column redundant replacement resources in the corresponding storage plane to replace the damaged column storage resources in another storage plane; wherein, the first logic level and the second logic level are opposite.

[0010] Wherein, the column storage resources include ordinary column selection signal lines, each of which is coupled to multiple ordinary storage units, the column redundant replacement resources include redundant column selection signal lines, each of which is coupled to multiple redundant storage units, and the column decoding circuit enables the column redundant replacement resources to replace the damaged column storage resources by enabling the redundant column selection signal lines to replace the damaged ordinary column selection signal lines; wherein, the ordinary column selection signal line coupled to the damaged ordinary storage unit is defined as the damaged ordinary column selection signal line.

[0011] Wherein, the memory includes an address matching circuit, which couples the column decoding circuits corresponding to the two storage surfaces; when performing a column addressing operation, the address matching circuit compares the column addressing address with a bad block address set, and when the column addressing address matches any bad block address in the bad block address set, the address matching circuit transmits redundant enable information to the column decoding circuit to enable the redundant column enable signal line.

[0012] Wherein, the memory includes a programmable storage circuit and a redundant latch circuit, the programmable storage circuit is coupled to the redundant latch circuit, and the redundant latch circuit is coupled to the address matching circuit to transmit the bad block address set to the address matching circuit; wherein the mode signal is controlled by the trimming bit in the programmable storage circuit.

[0013] Each of the memory banks includes a row decoding circuit, and the row decoding circuit is respectively coupled to the two memory planes and is disposed between the two memory planes.

[0014] Each of the storage planes includes a plurality of storage areas, each of the storage areas includes a plurality of storage blocks, each of the storage blocks includes x portions of the storage resources and y portions of the redundant replacement resources, wherein y is less than x.

[0015] The beneficial effect of the embodiment of the present application is: Different from the prior art, the memory provided by the present application includes: at least one storage library, each of which includes two storage planes, each of which includes multiple storage resources and multiple redundant replacement resources; wherein the damaged storage resources of each storage plane can be replaced by the redundant replacement resources of another storage plane to perform normal read and write operations. In the above manner, the redundant replacement resources in different storage planes can be shared with each other, thereby improving the flexibility of replacement and the yield of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] in:

[0018] Figure 1 is a schematic structural diagram of an embodiment of a memory provided by the present application;

[0019] Figure 2 It is a structural diagram of an embodiment of a storage library provided by the present application;

[0020] Figure 3 It is a structural schematic diagram of an embodiment of a storage surface provided by the present application;

[0021] Figure 4 is a structural schematic diagram of another embodiment of a storage surface provided by the present application;

[0022] Figure 5 is a structural schematic diagram of another embodiment of the memory provided by the present application;

[0023] Figure 6 It is a structural schematic diagram of an embodiment of an electronic device provided by the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] The memory provided by the present application includes: at least one storage library, each of which includes two storage planes, each of which includes multiple storage resources and multiple redundant replacement resources; wherein the damaged storage resources of each storage plane can be replaced by the redundant replacement resources of another storage plane to perform normal read and write operations. In the above manner, the redundant replacement resources in different storage planes can be shared with each other, thereby improving the flexibility of replacement and the yield of the memory.

[0027] See also Figure 1 , Figure 1 1 is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 1000 is a memory device based on semiconductor elements. In this embodiment, the memory device 1000 is a dynamic random access memory (DRAM). The memory device 1000 includes at least one storage bank 100. In this embodiment, the storage bank Bank 100 includes a plurality of storage banks 100, 100 and 100, respectively. <0> To Bank <n>, where n is a positive integer. It can be understood that as the storage capacity of the memory continues to increase, in order to facilitate access and control, the memory is made into a form of superimposed multiple storage banks, and the read and write operations are performed on one of the storage banks at a time.

[0028] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of an embodiment of a storage memory provided by the present application. The storage memory 100 may include, but is not limited to, a storage plane 110, a column decoding circuit 120, and a row decoding circuit 170. The storage plane 110 includes a first storage plane P0 and a second storage plane P1. The column decoding circuit 120 includes a first column decoding circuit YDEC0 and a second column decoding circuit YDEC1. The row decoding circuit 170 is coupled to the first storage plane P0 and the second storage plane P1, respectively, and is arranged between the first storage plane P0 and the second storage plane P1. The first column decoding circuit YDEC0 is coupled to the first storage plane P0. The second column decoding circuit YDEC1 is coupled to the second storage plane P1. The first storage plane P0 and the second storage plane P1 include multiple storage resources and multiple redundant replacement resources. The row decoding circuit 170 is used to enable the storage resources or redundant replacement resources of the first storage plane P0 and the second storage plane P1 in the row direction. The first column decoding circuit YDEC0 is used to enable the storage resources or redundant replacement resources of the first storage plane P0 in the column direction. The second column decoding circuit YDEC1 is used to enable the storage resources or redundant replacement resources of the second storage plane P1 in the column direction. Among them, the damaged storage resources of one of the first storage plane P0 and the second storage plane P1 can be replaced by the redundant replacement resources of the other of the first storage plane P0 and the second storage plane P1 to perform normal storage operations. Specifically, the damaged storage resources in the first storage plane P0 can be replaced by the redundant replacement resources in the second storage plane P1 to perform normal read and write operations. At the same time, the damaged storage resources in the second storage plane P1 can also be replaced by the redundant replacement resources in the first storage plane P0 to perform normal read and write operations. Each storage resource includes a plurality of ordinary storage cells arranged in rows or columns. Each redundant replacement resource includes a plurality of redundant storage cells arranged in rows or columns. Among them, when there is a damaged ordinary storage cell in any storage resource, the storage resource is defined as a damaged storage resource. The first storage plane P0 and the second storage plane P1 can selectively operate in the first working mode or the second working mode. Wherein, when the first storage plane P0 and the second storage plane P1 operate in the first operating mode, the damaged storage resources of one of the first storage plane P0 and the second storage plane P1 are only replaced by the redundant replacement resources in the same storage plane. When the first storage plane P0 and the second storage plane P1 operate in the second operating mode, the damaged storage resources of one of the first storage plane P0 and the second storage plane P1 can be replaced by the redundant replacement resources in the other of the first storage plane P0 and the second storage plane P1. When the first storage plane P0 and the second storage plane P1 operate in the second operating mode, the priority level of replacing the damaged storage resources in one of the first storage plane P0 and the second storage plane P1 with the redundant replacement resources in the same storage plane is greater than the priority level of replacing the damaged storage resources in one of the first storage plane P0 and the second storage plane P1 with the redundant replacement resources in the other of the first storage plane P0 and the second storage plane P1.In this way, redundant replacement resources in different storage planes can be shared with each other, thereby improving the flexibility of replacement and the yield of the memory.

[0029] It is understandable that in the manufacturing process of the memory, there may be defects in the memory cells in the row direction, and the memory operation cannot be performed normally; or there may be defects in the memory cells in the column direction, and the memory operation cannot be performed normally. Therefore, in order to improve the yield of the random access memory, it is necessary to add some spare circuits and spare memory cells to replace the damaged word lines, bit lines and memory cells. These spare circuits and spare memory cells are collectively referred to as redundant replacement resources. Specifically, when there are defects in the memory cells in the row direction and replacement in the row direction is required, it is called row replacement; when there are defects in the memory cells in the column direction and replacement in the column direction is required, it is called column replacement. In this embodiment, the application of shared redundant replacement resources between the first storage plane P0 and the second storage plane P1 in column replacement technology is taken as an example.

[0030] See also Figure 3 , Figure 3 1 is a schematic diagram of a storage surface according to an embodiment of the present application. The storage surface 110 includes a plurality of storage areas 111. In this embodiment, the storage surface 110 includes k+1 storage areas 111 arranged in a row up and down, specifically including storage area section <0> To storage area section <k>, where k is a positive integer. Each storage area 111 includes a plurality of storage blocks 1111. In this embodiment, the storage area 1111 includes 8 storage blocks 1111 arranged in a row from left to right. Specifically, the storage blocks mat <0> To storage block mat <7> When the memory 1000 performs a read / write operation, it performs a read / write operation on only one of the storage areas 111 at a time. Each storage block 1111 outputs or writes 8 bits of data, and each storage area 111 outputs or writes 64 bits of data. Each storage block 1111 includes x storage resources and y redundant replacement resources, where x and y are both positive integers and y is less than x. In this embodiment, the x storage resources include the normal column selection signal line YST <0> To the normal column strobe signal line YST <x-1>. y redundant replacement resources include redundant column strobe signal line RYST <0> To the redundant column strobe signal line RYST <y-1>The column decoding circuit 120 can decode the column addressing address and drive the corresponding common column selection signal line YST or the redundant column selection signal line RYST to access the data in each storage block 1111 in the storage area 111. The data in each storage block 1111 can be amplified by the sensitive amplifier circuit 130 and then output to the outside through the input and output circuit 140.

[0031] Please refer to Figure 3 and Figure 4 , Figure 4 It is a structural schematic diagram of another embodiment of the storage plane provided by the present application. The storage plane 110 includes a plurality of word lines WL, a plurality of pairs of complementary bit line pairs BL / BL# and a plurality of storage cells MC. Among them, the plurality of storage cells MC include a plurality of ordinary storage cells and a plurality of redundant storage cells. Each storage cell MC is coupled to a word line WL and a pair of complementary bit line pairs BL / BL#. The complementary bit line pair BL / BL# includes a target bit line BL and a complementary bit line BL#. The storage cell MC includes a storage capacitor CP and an access switch CT. The storage capacitor CP is coupled between the access switch CT and the common terminal. The access switch CT is coupled between the storage capacitor CP and the target bit line BL, and the control terminal of the access switch CT is coupled to the word line WL. The storage capacitor CP represents logical "1" and "0" by the amount of charge stored therein, or the high and low voltage difference across the storage capacitor. The on and off of the access switch CT determines whether the information stored in the storage capacitor CP is allowed or prohibited to be read and rewritten. Specifically, the word line WL determines whether the access switch CT is turned on or off. The bit line BL is the only channel for the outside world to access the storage capacitor CP. When the access switch CT is turned on, the outside world can read or write to the storage capacitor CP through the bit line BL.

[0032] The storage plane 110 also includes a plurality of initialization modules 112, a plurality of sensitive amplifier modules 113 and a plurality of column selection modules 114. Each initialization module 112 is coupled to a pair of corresponding complementary bit line pairs BL / BL# to charge the corresponding complementary bit line pairs BL / BL# to the initialization potential Vref in the pre-charging stage. Each sensitive amplifier module 113 is coupled to a pair of corresponding complementary bit line pairs BL / BL# to perform a signal amplification operation on the corresponding complementary bit line pairs BL / BL#. Each column selection module 114 is coupled to a pair of complementary bit line pairs BL / BL# and each column selection module 114 is coupled to a common column selection signal line YST / redundant column selection signal line RYST to enable the complementary bit line pair BL / BL# and the complementary intermediate input and output line pair MIO / MIO# to be selected when the column decoding circuit 120 drives the common column selection signal line YST / redundant column selection signal line RYST.

[0033] The input-output circuit 140 includes a plurality of pairs of complementary intermediate input-output line pairs MIO / MIO# and a plurality of pairs of complementary input-output line pairs IO / IO#. The complementary intermediate input-output line pairs MIO / MIO# are coupled to the complementary bit line pairs BL / BL# through the column strobe module 114. The complementary intermediate input-output line pairs MIO / MIO# include a target intermediate input-output line MIO and a complementary intermediate input-output line MIO#. The target intermediate input-output line MIO is coupled to the target bit line BL through the column strobe module 114, and the complementary intermediate input-output line MIO# is coupled to the complementary bit line BL# through the column strobe module 114. It is worth noting that in other embodiments, the input-output circuit 140 further includes multiple pairs of complementary local input-output line pairs LIO / LIO# (not shown), multiple pairs of complementary intermediate input-output line pairs MIO / MIO# and multiple pairs of complementary input-output line pairs IO / IO#, wherein the complementary local input-output line pair LIO / LIO# is coupled to the complementary bit line pair BL / BL# through the column selection module 114, and the complementary local input-output line pair LIO / LIO# is further coupled to the complementary intermediate input-output line pair MIO / MIO# through a switch circuit (not shown).

[0034] When the memory 1000 performs a read operation, the data in the memory cell MC to be accessed is first amplified by the sensitive amplifier module 113, and then the corresponding complementary bit line pair BL / BL# and the complementary intermediate input-output line pair MIO / MIO# are selected by the column selection module 114. Then, the data in the memory cell MC is further amplified by the sensitive amplifier circuit 130 and then output to the corresponding complementary input-output line pair IO / IO#. The sensitive amplifier circuit 130 includes a plurality of secondary sensitive amplifier modules, which are used to further amplify the data on the complementary intermediate input-output line pair MIO / MIO# and then output to the corresponding complementary input-output line pair IO / IO#.

[0035] In other embodiments, the input-output circuit 140 may further include a write-in driver module, and the write-in driver module is used to write external data into the storage unit MC.

[0036] Furthermore, each column selection module 114 is coupled to a pair of complementary bit line pairs BL / BL# and each column selection module 114 is coupled to a common column selection signal line YST / redundant column selection signal line RYST, so that the complementary bit line pair BL / BL# and the complementary intermediate input / output line pair MIO / MIO# are selected when the column decoding circuit 120 drives the common column selection signal line YST / redundant column selection signal line RYST. In this embodiment, one common column selection signal line YST / redundant column selection signal line RYST is coupled to eight column selection modules 114.

[0037] In this embodiment, if the first storage plane P0 and the second storage plane P1 operate in the second operating mode, when a storage cell MC corresponding to a common column selection signal line YST in one of the first storage plane P0 and the second storage plane P1 is defective (a damaged common storage cell) and cannot be read or written normally, the storage cell MC (redundant storage cell) corresponding to the redundant column selection signal line RYST in the other of the first storage plane P0 and the second storage plane P1 can be used to replace it, so as to improve the yield of the memory.

[0038] Please refer to Figure 3 , Figure 4 and Figure 5 , Figure 5 1 is a schematic diagram of the structure of another embodiment of the memory provided by the present application. The memory 1000 may include but is not limited to a memory bank 100, an address matching circuit 150 and a redundant latch circuit 160. The memory bank 100 may include but is not limited to a first memory plane P0, a second memory plane P1, a first column decoding circuit YDEC0 and a second column decoding circuit YDEC1. The storage resources in the first memory plane P0 and the second memory plane P1 include column storage resources. The column storage resources include a common column selection signal line YST, and in this embodiment, specifically include a common column selection signal line YST <0> To the normal column strobe signal line YST <x-1>Each common column selection signal line YST is coupled to a plurality of common storage cells. The redundant replacement resources in the first storage plane P0 and the second storage plane P1 include column redundant replacement resources. The column redundant replacement resources include redundant column selection signal lines RYST, specifically including redundant column selection signal lines RYST <0> To the redundant column strobe signal line RYST <y-1>Each redundant column selection signal line RYST is coupled to a plurality of redundant memory cells. Among them, the ordinary column selection signal line YST coupled to the damaged ordinary memory cell is defined as a damaged ordinary column selection signal line. The first column decoding circuit YDEC0 and / or the second column decoding circuit YDEC1 enables the redundant column selection signal line RYST to replace the damaged ordinary column selection signal line to enable the column redundant replacement resource to replace the damaged column storage resource.

[0039] Specifically, the first column decoding circuit YDEC0 corresponds to the first storage plane P0, and is used to enable the ordinary column selection signal line YST or the redundant column selection signal line RYST in the first storage plane P0 to access the storage cell MC. The second decoding circuit YDEC1 corresponds to the second storage plane P1, and is used to enable the ordinary column selection signal line YST or the redundant column selection signal line RYST in the second storage plane P1 to access the storage cell MC. In response to the mode signal MOD being a first logic level, the first column decoding circuit YDEC0 can only enable the column redundancy replacement resource (redundant column selection signal line RYST) in the first storage plane P0 to replace the damaged column storage resource (damaged ordinary column selection signal line YST) in the first storage plane P0; the second column decoding circuit YDEC1 can only enable the column redundancy replacement resource (redundant column selection signal line RYST) in the second storage plane P1 to replace the damaged column storage resource (damaged ordinary column selection signal line YST) in the second storage plane P1. In response to the mode signal MOD being at the second logic level, the first column decoding circuit YDEC0 can enable the column redundant replacement resources (redundant column selection signal line RYST) in the first storage plane P0 to replace the damaged column storage resources (damaged ordinary column selection signal line YST) in the second storage plane P1; the second column decoding circuit YDEC1 can enable the column redundant replacement resources (redundant column selection signal line RYST) in the second storage plane P1 to replace the damaged column storage resources (damaged ordinary column selection signal line YST) in the first storage plane P0. Wherein, the first logic level and the second logic level are opposite. Optionally, the first logic level is a logic high level, and the second logic level is a logic low level. In this way, when the first storage plane P0 and the second storage plane P1 operate in the second operating mode, the column redundant replacement resources in the first storage plane P0 and the second storage plane P1 can be shared with each other, making the replacement more flexible, thereby improving the yield of the memory 1000.

[0040] Further, the address matching circuit 150 is coupled to the first column decoding circuit YDEC0 and the second column decoding circuit YDEC1. When performing a column addressing operation, the address matching circuit 150 compares the column addressing address CA<9:3> with the bad block address set m*CRCAT<9:0>, and when the column addressing address CA<9:3> matches any bad block address in the bad block address set m*CRCAT<9:0>, the address matching circuit 150 transmits the redundancy enable information CRFG <y:1>To the column decoding circuit 120, to enable the redundant column selection signal line RYST. Wherein, m is a positive integer. Specifically, the column addressing address CA<9:3> is compared bit by bit with any bad block address in the bad block address set m*CRCAT<9:0>. In one embodiment, when the column addressing address CA<9:3> and the bits corresponding to the bad block address are the same, the column addressing address CA<9:3> matches the bad block address, and the address matching circuit 150 generates the redundant enable information CRFG <y:1>When the mode signal MOD is at the first logic level, the first column decoding circuit YDEC0 or the second column decoding circuit YDEC1 responds to the redundancy enable information CRFG <y:1>, and enables the corresponding redundant column selection signal line RYST in the corresponding storage plane 110 through the column selection enable signal YS_en to access the corresponding redundant storage unit, thereby replacing the corresponding damaged ordinary column selection signal line YST in the same storage plane 110 to achieve normal storage operation. When the mode signal MOD is at the second logic level, the first column decoding circuit YDEC0 or the second column decoding circuit YDEC1 responds to the redundancy enable information CRFG <y:1>, and can enable the corresponding redundant column enable signal line RYST in the corresponding storage plane 110 through the column enable signal YS_en to access the corresponding redundant storage unit, thereby replacing the corresponding damaged ordinary column enable signal line YST in another storage plane 110 to achieve normal storage operation.

[0041] Furthermore, the memory 1000 further includes a programmable storage circuit (not shown), which is coupled to the redundant latch circuit 160. The programmable storage circuit stores a bad block address set m*CRCAT<9:0>, and transmits the bad block address set m*CRCAT<9:0> to the redundant latch circuit 160 when powered on. The redundant latch circuit 160 is coupled to the address matching circuit 150 to transmit the bad block address set m*CRCAT<9:0> to the address matching circuit 150. The mode signal MOD is controlled by a trim bit in the programmable storage circuit. Optionally, when the trim bit in the programmable storage circuit is 1, the mode signal MOD is at a first logic level. When the trim bit in the programmable storage circuit is 0, the mode signal MOD is at a second logic level.

[0042] The memory 1000 provided by the present application includes: at least one storage library 100, each storage library 100 includes two storage planes 110, each storage plane 110 includes multiple storage resources and multiple redundant replacement resources; wherein the damaged storage resources of each storage plane 110 can be replaced by the redundant replacement resources of another storage plane 110 to perform normal read and write operations. In the above manner, the redundant replacement resources in different storage planes 110 can be shared with each other, thereby improving the flexibility of replacement and the yield of the memory 1000.

[0043] See also Figure 6 , Figure 6 The electronic device 2000 may include, but is not limited to, a data storage circuit 2001 , a storage controller 2002 , a buffer memory 2003 , and an input / output interface 2004 .

[0044] According to the control signal generated by the storage controller 2002, the data storage circuit 2001 can store the data output by the storage controller 2002 or output the stored data to the storage controller 2002. The data storage circuit 2001 may include at least one memory 1000. The data storage circuit 2001 may also include a non-volatile memory capable of retaining the stored data after power failure. The non-volatile memory may be a NOR flash memory or a NAND flash memory, a phase change random access memory (PRAM), a variable resistance random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), etc.

[0045] The storage controller 2002 can receive instructions from an external device through the input / output interface 2004, and can interpret the instructions to control the operation of inputting data to the data storage circuit 2001 or the buffer memory 2003, or the operation of outputting data stored in the data storage circuit 2001 or the buffer memory 2003. Optionally, the external device can be a host device. The storage controller 2002 can include a control for the data storage circuit 2001 including a non-volatile memory and another control for the buffer memory 2003 including a volatile memory.

[0046] The buffer memory 2003 is used to temporarily store data generated by the storage controller 2002. That is, the buffer memory 2003 is used to temporarily store data output by the data storage circuit 2001 or to be stored in the data storage circuit 2001. Based on the control signal, the buffer memory 2003 can store the data output by the storage controller 2002. In addition, the buffer memory 2003 can also read and output the data stored in the storage controller 2002. The buffer memory 2003 may include a volatile random access memory, such as a dynamic random access memory (DRAM), a mobile memory or a solid state random access memory (SRAM).

[0047] The input / output interface 2004 is used to physically and electrically connect the storage controller 2002 and the external device. The external device may be a host. Therefore, the storage controller 2002 may receive instructions and data from the external device through the input / output interface 2004, and may output the data generated by itself to the external device through the input / output interface 2004. In other words, the electronic device 2000 may exchange data with the external device through the input / output interface 2004. The input / output interface 2004 may include any of the following various interfaces, such as a universal serial bus (USB), a media card (MMC), a peripheral component interconnect high-speed interface (PCI-E), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small device interface (ESDI), and an integrated drive circuit (IDE).

[0048] The electronic device 2000 may be used as an auxiliary storage device or an external storage device of the host. The electronic device 2000 may include a solid state disk (SSD), a USB memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro-SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), a standard flash memory card, etc.

[0049] The above description is only an implementation method of the present application, and does not limit the scope of the patent application. Any equivalent structure or equivalent process transformation made according to the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of this application. < / k> < / n>

Claims

1. A memory, characterized in that: include: At least one storage library, each of which includes two storage planes, each of which includes multiple storage resources and multiple redundant replacement resources; The damaged storage resource of each storage plane can be replaced by the redundant replacement resource of another storage plane to perform normal read and write operations.

2. The memory according to claim 1, characterized in that: Each of the storage resources includes a plurality of ordinary storage units arranged in rows or columns, and each of the redundant replacement resources includes a plurality of redundant storage units arranged in rows or columns, wherein when any of the storage resources has a damaged ordinary storage unit, the storage resource is defined as the damaged storage resource.

3. The memory according to claim 1, characterized in that: Each of the storage surfaces can selectively operate in a first operating mode or a second operating mode; Wherein, when the storage plane operates in the first operating mode, the damaged storage resource in the storage plane is only replaced by the redundant replacement resource in the same storage plane; When the storage plane operates in the second operation mode, the damaged storage resource in the storage plane can be replaced by the redundant replacement resource in another storage plane.

4. The memory according to claim 3, characterized in that: When the storage plane operates in the second operating mode, the priority level of replacing the damaged storage resource in the storage plane with the redundant replacement resource in the same storage plane is higher than the priority level of replacing the damaged storage resource in the storage plane with the redundant replacement resource in another storage plane.

5. The memory according to claim 1, characterized in that: The storage resource comprises a column storage resource, and the redundant replacement resource comprises a column redundant replacement resource; Each of the memory banks comprises column decoding circuits corresponding to two of the memory planes respectively. In response to the mode signal being at a first logic level, the column decoding circuit can only enable the column redundant replacement resource in the corresponding storage plane to replace the damaged column storage resource in the same storage plane; In response to the mode signal being at a second logic level, the column decoding circuit is capable of enabling the column redundant replacement resource in the corresponding storage plane to replace the damaged column storage resource in another storage plane; The first logic level and the second logic level are opposite.

6. The memory according to claim 5, characterized in that: The column storage resource includes a common column selection signal line, each of which is coupled to a plurality of common storage units. The column redundancy replacement resource includes a redundant column strobe signal line, each of which is coupled to a plurality of redundant storage units. The column decoding circuit enables the column redundant replacement resource to replace the damaged column storage resource by enabling the redundant column selection signal line to replace the damaged common column selection signal line; The common column enable signal line coupled to the damaged common memory cell is defined as the damaged common column enable signal line.

7. The memory according to claim 6, characterized in that: The memory comprises an address matching circuit, wherein the address matching circuit is coupled to the column decoding circuits corresponding to the two storage planes; When performing a column addressing operation, the address matching circuit compares the column addressing address with a bad block address set, and when the column addressing address matches any bad block address in the bad block address set, the address matching circuit transmits redundant enable information to the column decoding circuit to enable the redundant column enable signal line.

8. The memory according to claim 7, characterized in that: The memory includes a programmable storage circuit and a redundant latch circuit, wherein the programmable storage circuit is coupled to the redundant latch circuit, and the redundant latch circuit is coupled to the address matching circuit to transmit the bad block address set to the address matching circuit; Wherein, the mode signal is controlled by a trim bit in the programmable storage circuit.

9. The memory according to any one of claims 1 to 8, characterized in that: Each of the memory banks includes a row decoding circuit, which is respectively coupled to the two memory planes and disposed between the two memory planes.

10. The memory according to any one of claims 1 to 9, characterized in that: Each of the storage planes includes a plurality of storage areas, each of the storage areas includes a plurality of storage blocks, each of the storage blocks includes x portions of the storage resources and y portions of the redundant replacement resources, wherein y is less than x.

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