Fault data acquisition method and device, test data processing system and readable medium

Abstract

The invention relates to a fault data acquisition method and device, a test data processing system and a readable storage medium, and the method comprises the steps: obtaining a fault number threshold value of batch test data and access address information of the batch test data in a tested storage device based on a received fault data reading instruction; based on the access address information, fault test data and corresponding access addresses in the batch test data are obtained in sequence, and the number of the fault test data is accumulated; and when the accumulated quantity of the fault test data reaches a fault quantity threshold value, stopping the process of acquiring the fault test data and the corresponding access address, and returning fault statistical data generated based on the fault test data and the corresponding access address, the fault data can be obtained without reading and judging all the test data in the batch test data, and the problems of long processing time and low efficiency of storage device fault data statistics are solved.

Description

Technical Field

[0001] The present application relates to the field of memory testing technology, and in particular to a fault data acquisition method, device, test data processing system and readable storage medium. Background Art

[0002] Storage devices need to be tested before leaving the factory to detect faults as early as possible to avoid the faults being discovered during user use after leaving the factory, causing unnecessary losses to users. The test method usually uses a processor to write pre-set data to the storage device under test, and then reads the written data, and compares the written data with the read data to test whether the storage device has a fault. For the test of batch storage devices, the cumulative number of faults can be counted after multiple tests on multiple storage devices under test to obtain the fault data of the batch storage devices. When the number of storage devices under test is large, the capacity is large, and the number of tests is large, a large amount of test data will be generated for the statistics of fault data. These test data need to be read and judged one by one to obtain the corresponding fault results, resulting in long test data processing and fault data statistics time, and low statistical efficiency.

[0003] Currently, no effective solution has been proposed to solve the problems of long processing time and low efficiency in statistics of storage device failure data in related technologies. Summary of the invention

[0004] In this embodiment, a fault data acquisition method, device, test data processing system and readable storage medium are provided to solve the problems of long processing time and low efficiency of storage device fault data statistics existing in the related art.

[0005] In a first aspect, a method for acquiring fault data is provided in this embodiment, and the method includes:

[0006] Based on the received fault data read instruction, acquiring a fault quantity threshold of batch test data and access address information of the batch test data in the memory device under test;

[0007] Based on the access address information, sequentially obtain the fault test data and the corresponding access addresses in the batch test data, and accumulate the number of the fault test data;

[0008] When the accumulated number of the fault test data reaches the fault number threshold, the process of acquiring the fault test data and the corresponding access address is stopped, and the fault statistical data generated based on the fault test data and the corresponding access address is returned.

[0009] In some embodiments, sequentially acquiring the fault test data and the corresponding access addresses in the batch test data based on the access address information includes:

[0010] Based on the access address information, sequentially obtain the test data and the corresponding access addresses in the batch test data;

[0011] Based on the value of the test data, determining whether the test data is fault test data;

[0012] In a case where the test data is fault test data, corresponding fault statistical data is generated based on the fault test data and the corresponding access address.

[0013] In some embodiments, sequentially acquiring the test data and the corresponding access addresses in the batch test data based on the access address information includes:

[0014] Based on the access address information, sequentially acquiring access addresses and physical addresses of test data in the batch test data in the memory device under test;

[0015] storing the access addresses into the address cache in sequence;

[0016] Based on the physical address, reading corresponding test data in sequence, and storing the test data in the data cache in sequence;

[0017] The data cache and the address cache are read in sequence according to the storage order to obtain the test data and the corresponding access address.

[0018] In some embodiments, the access address information includes an access address range and an address mapping relationship, and sequentially acquiring access addresses and physical addresses of test data in the batch test data in the memory device under test based on the access address information includes:

[0019] Based on the access address range, obtaining a row start address, a row end address, a column start address and a column end address of the batch test data in the memory device under test;

[0020] Perform row accumulation or column accumulation based on the row start address, the row end address, the column start address and the column end address to sequentially obtain access addresses of the test data;

[0021] Based on the access address and the address mapping relationship, a physical address corresponding to the access address is obtained.

[0022] In some embodiments, acquiring the physical address corresponding to the access address based on the access address and the address mapping relationship includes:

[0023] Determine the value of the corresponding physical address bit based on the correspondence between the access address bit and the physical address bit in the address mapping relationship and the value of the access address bit;

[0024] Arrange the physical address bits in order to obtain a physical address corresponding to the access address.

[0025] In some embodiments, determining whether the test data is fault test data based on the value of the test data includes:

[0026] Based on the fault data read instruction, obtaining access data bits of the test data;

[0027] Based on the access data bit, reading a corresponding data value in the test data;

[0028] Based on the data value, it is determined whether the test data is fault data.

[0029] In some embodiments, after determining whether the test data is fault test data based on the value of the test data, the method further includes:

[0030] In the case where it is determined that the test data is not fault test data, discarding the test data and the corresponding access address;

[0031] In the case where it is determined that the test data is fault test data, the test data is identified by a fault identification bit.

[0032] In some embodiments, generating corresponding fault statistics data based on the fault test data and the corresponding access address includes:

[0033] Combining the fault test data and the corresponding access address to generate corresponding fault statistical data;

[0034] The fault statistical data is stored in a fault data cache.

[0035] In some embodiments, the method further comprises:

[0036] Based on the access address information, obtaining the total amount of test data in the batch test data;

[0037] When the accumulated number of the fault test data does not reach the fault number threshold, the process of acquiring the fault test data and the corresponding access address is repeated until the number of the read test data reaches the total number of the test data.

[0038] In a second aspect, a fault data acquisition device is provided in this embodiment, and the device includes:

[0039] A first acquisition module, configured to acquire a fault quantity threshold of batch test data and access address information of the batch test data in a memory device under test based on a received fault data read instruction;

[0040] A second acquisition module, configured to sequentially acquire the fault test data and the corresponding access addresses in the batch test data based on the access address information, and accumulate the number of the fault test data;

[0041] The return module is used to stop the process of obtaining the fault test data and the corresponding access address when the cumulative number of the fault test data reaches the fault number threshold, and return the fault statistical data generated based on the fault test data and the corresponding access address.

[0042] In a third aspect, a test data processing system is provided in this embodiment, the test data processing system comprising the fault data acquisition device as described in the second aspect, as well as a storage unit, a data cache, an address cache and a result cache;

[0043] The fault data acquisition device is used to read test data from the storage unit in sequence, store the test data and the corresponding access address into the data cache and the address cache respectively, and store the fault statistical data into the result cache.

[0044] In a fourth aspect, a readable storage medium is provided in this embodiment, on which a program is stored, and when the program is executed by a processor, the steps of the fault data acquisition method described in the first aspect are implemented.

[0045] Compared with the related art, the fault data acquisition method provided in the present embodiment obtains the fault number threshold of batch test data and the access address information of the batch test data in the tested storage device based on the received fault data reading instruction, and gives the maximum fault number condition of the batch test data and the address for obtaining the batch test data; obtains the fault test data and the corresponding access address in the batch test data in sequence based on the access address information, and accumulates the number of fault test data, and screens the batch test data by sequentially reading and judging to obtain individual fault test data, and accumulates the number of individual fault test data during the screening process; stops the process of obtaining the fault test data and the corresponding access address when the accumulated number of fault test data reaches the fault number threshold, and returns the fault statistics data generated based on the fault test data and the corresponding access address, and terminates the process of screening the individual fault test data from the batch test data when the accumulated number of individual fault test data reaches the fault number threshold of the batch test data, and completes the acquisition of the fault data without reading and judging all the test data in the batch test data, thereby improving the efficiency of fault data acquisition and solving the problems of long processing time and low efficiency of storage device fault data statistics.

[0046] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0048] Figure 1 is a computer hardware structure block diagram of a method for acquiring fault data in some embodiments of the present application;

[0049] Figure 2 is a flow chart of a method for acquiring fault data in some embodiments of the present application;

[0050] Figure 3 is a flowchart of sequentially obtaining fault test data and corresponding access addresses in some embodiments of the present application;

[0051] Figure 4 is a flowchart of sequentially acquiring test data and corresponding access addresses in some embodiments of the present application;

[0052] Figure 5 is a flow chart of sequentially obtaining access addresses and physical addresses of test data in some embodiments of the present application;

[0053] Figure 6 is a flowchart of obtaining a physical address based on an access address and an address mapping relationship in some embodiments of the present application;

[0054] Figure 7 is a flowchart of determining whether test data is fault test data in some embodiments of the present application;

[0055] Figure 8 is a flow chart of generating fault statistics data based on fault test data and access addresses in some embodiments of the present application;

[0056] Fig. 9 is a flow chart of a method for acquiring fault data in some embodiments of the present application;

[0057] Fig.10 is a schematic diagram of a test data processing system of some preferred embodiments of the present application;

[0058] Fig.11 is a flow chart of a method for acquiring fault data in some preferred embodiments of the present application;

[0059] Fig.12 It is a structural block diagram of a fault data acquisition device in some embodiments of the present application. DETAILED DESCRIPTION

[0060] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0061] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not represent quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. Usually, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0062] The fault data acquisition method provided in the embodiment of the present application can be executed in a terminal, a computer or a similar computing device, and the computing device can be a host computer of a storage device test system, and the storage device test system can include a storage device under test and a memory for storing test data. When the method is applied to a computer, Figure 1 1 is a hardware structure diagram of a computer of a method for acquiring fault data in some embodiments of the present application. Figure 1 As shown, the computer may include one or more ( Figure 1 Only one is shown in the figure) processor 102 and memory 104 for storing data, wherein processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above computer may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0063] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the fault data acquisition method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some embodiments, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0064] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by a communication provider. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0065] In this embodiment, a method for acquiring fault data is provided. Figure 2 is a flowchart of a method for acquiring fault data in some embodiments of the present application. Figure 2 As shown, the process includes the following steps:

[0066] Step S201 : acquiring a fault quantity threshold of batch test data and access address information of the batch test data in a memory device under test based on a received fault data read instruction.

[0067] After the memory device under test completes the test, the corresponding test data is stored in the memory. The test data may include fault data and normal data. According to the fault statistics requirements, it is necessary to obtain the fault data and the corresponding memory address from a large amount of test data, and count the number of fault data to calculate the failure rate of the memory device under test.

[0068] In practical applications, for batch detection of the memory devices under test, the test pass or fail can be determined by setting a fault rate threshold. If the fault rate is higher than the set threshold, the test of the memory devices under test in this batch is determined to have failed. If it is lower than the set threshold, the test of the memory devices under test in this batch is determined to have passed. In the process of acquiring fault data, the fault number threshold corresponding to the batch test data can be calculated based on the fault rate threshold, the number of memory devices under test, and the number of test data corresponding to each memory device under test. The fault number threshold is used as the test pass condition for the batch test data. If the number of fault test data in the batch test data is greater than the fault number threshold, the test corresponding to the batch test data is determined to have failed; if it is less than the fault number threshold, the test corresponding to the batch test data is determined to have passed.

[0069] The access address information is used to specify an access address range of the memory, and corresponding test data is read according to the access address range to obtain fault test data in the test data.

[0070] Step S202: based on the access address information, sequentially obtain the faulty test data and the corresponding access addresses in the batch test data, and accumulate the number of the faulty test data.

[0071] According to the access address information, the test data is read from the batch test data in sequence, and it is determined whether the test data is faulty test data. If so, corresponding fault statistics are generated based on the faulty test data and the corresponding access address, and the number of faulty test data is accumulated. If not, the test data and the corresponding access address can be discarded.

[0072] Step S203, when the accumulated number of fault test data reaches the fault number threshold, the process of obtaining the fault test data and the corresponding access address is stopped, and fault statistical data generated based on the fault test data and the corresponding access address is returned.

[0073] In the process of reading and judging the test data in sequence, determine whether the cumulative number of faulty test data has reached the fault number threshold. If so, it means that the number of faults in the batch of test data has reached the threshold for judging as test failure. There is no need to continue to obtain other faulty test data. The test data reading and judgment process can be terminated and the generated fault statistics data can be returned.

[0074] Through the above steps S201 to S203, by obtaining the fault number threshold of the batch test data and the access address information of the batch test data in the tested storage device based on the received fault data reading instruction, the maximum fault number condition of the batch test data and the address for obtaining the batch test data are given; by sequentially obtaining the fault test data and the corresponding access address in the batch test data based on the access address information, and accumulating the number of fault test data, the batch test data is screened by sequentially reading and judging to obtain individual fault test data, and the number of individual fault test data is accumulated during the screening process; by stopping the process of obtaining the fault test data and the corresponding access address when the accumulated number of fault test data reaches the fault number threshold, and returning the fault statistics data generated based on the fault test data and the corresponding access address, when the accumulated number of individual fault test data reaches the fault number threshold of the batch test data, the process of screening the individual fault test data from the batch test data is terminated, and the acquisition of the fault data can be completed without reading and judging all the test data in the batch test data, thereby improving the efficiency of fault data acquisition and solving the problems of long processing time and low efficiency of storage device fault data statistics.

[0075] In some embodiments, Figure 3 is a flowchart of sequentially obtaining fault test data and corresponding access addresses in some embodiments of the present application, such as Figure 3 As shown, the process includes the following steps:

[0076] Step S301, based on the access address information, sequentially obtain the test data and the corresponding access addresses in the batch test data.

[0077] The access address in the access address information may be a logical address or a physical address, and the corresponding memory space may be read according to the access address information to obtain the test data. For batch test data, operations such as reading the test data and determining whether the test data is faulty test data may be performed serially, that is, one test data is read each time according to the access address sequence, and one test data is determined each time to determine whether it is faulty test data. If the test data is determined to be faulty test data, the cumulative number of faulty test data is increased by 1.

[0078] Step S302: determining whether the test data is faulty test data based on the value of the test data.

[0079] The initial value of the test data is predetermined, for example, all data bits are 0. If the value of the read test data does not match the initial value, the test data can be determined to be faulty test data. Further, a data bit at a preset position in the test data, or a data segment consisting of multiple data bits, can be read to determine whether the test data is faulty test data based on the value of the data bit or data segment. If it is determined to be faulty test data, the faulty test data can be identified.

[0080] Step S303: when the test data is fault test data, generate corresponding fault statistical data based on the fault test data and the corresponding access address.

[0081] If the test data is fault test data, the fault test data and the corresponding access address can be assembled in a predetermined format to generate corresponding fault statistics data. If the test data is not fault test data, the test data and the corresponding access address can be discarded.

[0082] Through the above steps S301 to S303, the test data and the corresponding access addresses in the batch test data are obtained in sequence based on the access address information, and the individual test data are obtained in sequence using serial access; based on the value of the test data, it is determined whether the test data is fault test data, and the fault test data is judged and collected in sequence; when the test data is fault test data, corresponding fault statistical data is generated based on the fault test data and the corresponding access address, to obtain fault statistical data that meets the data format requirements, and the test data without faults is discarded, saving subsequent processing resources.

[0083] In some embodiments, Figure 4 is a flowchart of sequentially acquiring test data and corresponding access addresses in some embodiments of the present application, such as Figure 4 As shown, the process includes the following steps:

[0084] Step S401 : based on the access address information, sequentially obtain the access address and the physical address of the test data in the batch test data in the memory device under test.

[0085] In this embodiment, the access address in the access address information may be the storage address of the storage device under test, and the physical address may be the memory address for storing batch test data. In practical applications, the test user is only concerned with the address situation of the storage device under test, and is not aware of the address situation of the memory, so the address space of the storage device under test and the memory address space need to be associated through address mapping. The mapping relationship between the logical address and the physical address may be a set of functional relationships, or the physical address may be obtained by performing logical operations on the corresponding address data bits of the logical address. The address mapping relationship may be obtained in the access address information, or may be pre-stored in the memory. The access address in the access address information may be a set of multiple logical addresses, or may be parameter information including a start address, an end address, and an address range.

[0086] Step S402, storing the access addresses into the address cache in sequence.

[0087] In this embodiment, the test data and the corresponding access address are temporarily stored by the data cache and the address cache to adjust the speed difference between the reading of the test data and the fault determination of the test data, so as to ensure the orderly progress of the serial work. The access addresses are sequentially stored in the address cache according to the order of the access addresses, and the address cache is also read in the order of storage when reading. The address cache can be a FIFO storage structure.

[0088] Step S403, based on the physical address, read the corresponding test data in sequence, and store the test data in the data cache in sequence.

[0089] Read the corresponding test data from the memory according to the physical address. The order of the physical addresses corresponds to the order of the access addresses one by one, and the read test data also corresponds to the access addresses one by one. Therefore, the order in which the test data is saved in the data cache corresponds to the order in which the access addresses are saved in the address cache. The data cache can be a FIFO storage structure.

[0090] Steps S402 and S403 may be performed in reverse order.

[0091] Step S404, reading the data cache and the address cache in sequence according to the storage order, and obtaining the test data and the corresponding access address.

[0092] Through the above steps S401 to S403, the access address and physical address of the test data in the batch test data in the storage device under test are obtained in sequence based on the access address information, and the address of the batch test data in the storage device under test is converted into the address of the individual test data in the memory; the reading order of the individual test data is determined by storing the access addresses in the address cache in sequence; the arrangement order of the test data corresponding to the address order is obtained by reading the corresponding test data in sequence based on the physical address, and storing the test data in the data cache in sequence; the test data and the corresponding access address are obtained by reading the data cache and the address cache in sequence according to the storage order, and the speed difference between the reading of the test data and the fault judgment of the test data is adjusted through the address and data cache to ensure the orderly serial reading of the test data and the fault judgment.

[0093] In some embodiments, the access address information includes an access address range and an address mapping relationship. Figure 5 is a flowchart of sequentially obtaining the access address and physical address of test data in some embodiments of the present application, such as Figure 5 As shown, the process includes the following steps:

[0094] Step S501 : acquiring a row start address, a row end address, a column start address and a column end address of batch test data in a memory device under test based on an access address range.

[0095] The access address range refers to the address range of the memory device under test, that is, the row start address and row end address, column start address and column end address of the memory device under test.

[0096] Step S502 , performing row accumulation or column accumulation based on the row start address, the row end address, the column start address and the column end address, and sequentially acquiring access addresses of the test data.

[0097] The starting address of the test data is determined according to the row starting address and the column starting address, and the row address is incremented by 1 or the column address is incremented by 1 in sequence according to the row accumulation mode or the column accumulation mode to obtain the access address of the test data.

[0098] Step S503: based on the access address and the address mapping relationship, obtain the physical address corresponding to the access address.

[0099] The physical address corresponding to the access address is obtained according to the logical operation or function operation in the address mapping relationship.

[0100] Through the above steps S501 to S503, the row start address, row end address, column start address and column end address of the batch test data in the tested storage device are obtained based on the access address range to obtain the access address of the batch test data; the access addresses of the test data are obtained in sequence by performing row accumulation or column accumulation based on the row start address, row end address, column start address and column end address, and the access address and access order of the individual test data are determined; the physical address corresponding to the access address is obtained based on the access address and the address mapping relationship, and the address of the tested storage device is converted into a memory address to read the test data.

[0101] In some embodiments, Figure 6 is a flowchart of obtaining a physical address based on an access address and an address mapping relationship in some embodiments of the present application, such as Figure 6 As shown, the process includes the following steps:

[0102] Step S601, based on the correspondence between the access address bit and the physical address bit in the address mapping relationship, and the value of the access address bit, determine the value of the corresponding physical address bit.

[0103] In practical applications, the size of the memory space used to store test data may be the same or different from the size of the storage space of the memory device under test, that is, the number of physical address bits and the number of access address bits may be the same or different. Assume that X is the access address space with n address bits, and Y is the physical address space with m address bits, where m and n may be different or the same. In this embodiment, m≤n.

[0104] The mapping relationship between X and Y can be expressed by the following correspondence:

[0105] Y1-------------------Xa

[0106] Y2-------------------Xb

[0107] ....-------------------....

[0108] Ym-------------------Xi

[0109] Among them, Y1, Y2, and Ym are the address bits of the physical address space, and Xa, Xb, and Xi are the address bits of the access address space. The correspondence table is stored in advance, and the corresponding physical address bit value can be obtained according to the correspondence table and the value of the access address bit. For example, Y1 corresponds to X3, Y2 corresponds to X4, Y3 corresponds to X1, and Y4 corresponds to X5. The X address is 10110, and the arrangement order is X5 to X1. Then it can be determined that Y1=1, Y2=0, Y3=0, and Y4=1.

[0110] Furthermore, the above correspondence can be simplified by encoding the X address and arranging the corresponding X address codes in the order of Y1 to Ym. The resulting array is the address mapping array. The X space address can be represented by an n-bit wide binary one-dimensional array, arranged in the order of X1-Xn or Xn-X1, and each element of the array takes a value of 0 or 1. Based on the address mapping array and the X space address array, the value of each address bit of the Y space can be obtained.

[0111] Step S602, arranging the physical address bits in order to obtain the physical address corresponding to the access address.

[0112] After obtaining the value of each physical address bit, the physical address bits are arranged in order from low to high or from high to low to obtain the physical address corresponding to the access address.

[0113] Through the above steps S601 to S602, the value of the corresponding physical address bit is determined based on the correspondence between the access address bit and the physical address bit in the address mapping relationship, and the value of the access address bit, and the access address value is converted into a physical address value by simply querying the correspondence table or querying the array value, thereby reducing the resources required for reading test data; by arranging the physical address bits in sequence, the physical address corresponding to the access address is obtained, thereby providing an actual physical address for reading test data.

[0114] In some embodiments, Figure 7 is a flowchart of determining whether test data is fault test data in some embodiments of the present application, such as Figure 7 As shown, the process includes the following steps:

[0115] Step S701, obtaining access data bits of test data based on a fault data read instruction.

[0116] The access data bit of the test data refers to the starting data bit selected when reading the test data. The access data bit can be issued through the fault data read instruction.

[0117] Step S702: based on the access data bit, read the corresponding data value in the test data.

[0118] According to the access data bit, the value of the corresponding data bit in the test data is read as the basis for judging the fault. For example, if the access data bit is the 4th bit, the value of the 4th bit of the test data is read and used as the basis for judging whether the test data is faulty.

[0119] Step S703: determining whether the test data is fault data based on the data value.

[0120] Through the above steps S701 to S703, the access data bits of the test data are obtained based on the fault data reading instruction, and specific data bits in the test data are selected to be read; the corresponding data values ​​in the test data are read based on the access data bits, thereby improving the data reading efficiency; and whether the test data is fault data is determined based on the data value, thereby improving the fault judgment efficiency.

[0121] In some embodiments, a method for processing test data after determining whether the test data is faulty test data based on the value of the test data is also provided, the method comprising:

[0122] When it is determined that the test data is not faulty test data, the test data and the corresponding access address are discarded; when it is determined that the test data is faulty test data, the test data is identified by a fault identification bit.

[0123] If it is determined that the test data is fault test data, the test data and the corresponding access address need to be retained for subsequent testers to read as reference data for locating the cause of the fault. The fault test data can be identified by the fault identification bit to facilitate subsequent data processing. The fault identification bit can be a fixed data bit of the test data. Subsequent other data processing modules can process the data differently according to the state of the fault identification bit. If it is determined that the test data is not fault test data, the test data and the access address have no analysis value, and the test data and the corresponding access address can be discarded to save data storage and fault statistics resources.

[0124] The fault data acquisition method of the present embodiment saves data storage and fault statistics resources by discarding the test data and the corresponding access address when it is determined that the test data is not fault test data; and improves the efficiency of subsequent fault test data processing by marking the test data with a fault identification bit when it is determined that the test data is fault test data.

[0125] In some embodiments, Figure 8 is a flowchart of generating fault statistics based on fault test data and access addresses in some embodiments of the present application, such as Figure 8 As shown, the process includes the following steps:

[0126] Step S801, combining fault test data and corresponding access addresses to generate corresponding fault statistical data.

[0127] According to a predetermined format, the fault test data and the corresponding access address are assembled into fault statistical data. In practical applications, data assembly and fault determination may be performed by different functional modules. The functional module corresponding to the fault determination may set a fault identification bit for the fault test data after determining that the test data is fault test data, and the functional module corresponding to the data assembly may determine that the data is fault test data according to the fault identification bit.

[0128] Step S802: storing the fault statistics into the fault data cache.

[0129] The fault data cache may adopt a RAM storage structure, and the fault statistical data are sequentially stored in the fault data cache in an address increasing manner. The RAM storage structure may specify an address range to flexibly read the corresponding fault statistical data.

[0130] Through the above steps S801 to S802, by combining the fault test data and the corresponding access address, the corresponding fault statistical data is generated, and data that meets the statistical requirements is obtained, providing a data basis for subsequent fault analysis and further statistics; by storing the fault statistical data in the fault data cache, the fault statistics personnel can flexibly read the corresponding data by specifying the address.

[0131] In some embodiments, Fig. 9 is a flowchart of a method for acquiring fault data in some embodiments of the present application. Fig. 9 As shown, the process includes the following steps:

[0132] Step S901, based on the access address information, obtaining the total amount of test data in the batch test data.

[0133] The total amount of test data within the address range can be calculated based on the access address range, that is, the total amount of test data = (row end address - row start address + 1) × (column end address - column start address + 1).

[0134] Step S902 , when the accumulated number of faulty test data does not reach the fault number threshold, repeat the process of obtaining the faulty test data and the corresponding access address until the number of test data that has been read reaches the total number of test data.

[0135] During the test data reading and fault determination process, if the accumulated number of faulty test data does not reach the fault number threshold, the test data reading and fault determination can be continued until all the tested data within the address range has been read.

[0136] Through the above steps S901 to S902, the total number of test data in the batch test data is obtained based on the access address information, and the quantity parameter used to terminate the data reading process is obtained; when the cumulative number of fault test data does not reach the fault number threshold, the process of obtaining fault test data and the corresponding access address is repeated until the number of test data read reaches the total number of test data. When the number of fault test data is less than the fault number threshold, the end timing of the fault data acquisition process is controlled by the total number of test data.

[0137] The present embodiment is described and illustrated below through preferred embodiments. Fig.10 1 is a schematic diagram of a test data processing system of some preferred embodiments of the present application, the test data processing system includes a storage unit 1001, an access control module 1002, a data processing module 1003, a result reading module 1004, an address cache 1005, a data cache 1006 and a result cache 1007. Among them, the data processing module 1003 includes a data judgment module 10031 and a data assembly / discarding module 10032, and the access control module 1002 includes an address generation module 10021 and a condition control module 10022. Fig.11 Flowchart of the method for acquiring fault data in some preferred embodiments of the present application. Fig.11 As shown, the process includes the following steps:

[0138] Step S1101, the access control module receives an access parameter command and a process control command from the software layer, the access parameter command including an access data bit, an access address mapping, an access address range, and a maximum fault data statistic value;

[0139] Step S1102, the condition control module determines the total amount of test data according to the access address range, and sends the total amount of test data and the maximum fault statistics value to the data processing module;

[0140] The total number of test data = (row end address - row start address + 1) × (column end address - column start address + 1).

[0141] Step S1103, the address generation module sequentially generates a read address for reading a storage unit according to the access address range and the access address mapping;

[0142] Step S1104, the address generation module sends the mapped storage unit addresses to the storage units in sequence, and sends the unmapped access addresses to the address cache in sequence;

[0143] Step S1105, the storage unit sends the corresponding test data to the data cache according to the storage unit address;

[0144] Step S1106, the data determination module reads the test data of the corresponding data bit according to the access data bit;

[0145] Step S1107, the data judgment module judges whether the test data contains fault data according to the read data value;

[0146] Step S1108, if the test data contains fault data, marking the test data;

[0147] Step S1109, the data assembly / discarding module identifies the fault identification bit;

[0148] Step S1110, if the fault flag is valid, combine the test data and the corresponding access address into fault statistical data and store it in the result cache;

[0149] Step S1111, if the fault flag is invalid, discard the test data and the corresponding access address;

[0150] Step S1112, determining whether the accumulated number of fault test data in the result cache reaches a fault number threshold;

[0151] Step S1113, when the fault quantity threshold is reached, stop reading test data and fault determination, and return the existing fault statistics;

[0152] Step S1114 , when the fault quantity threshold is not reached, the process of reading the test data and determining the fault is repeated until the quantity of the test data that has been read reaches the total quantity of the test data.

[0153] Through the above steps S1101 to S1114, the physical address of the test data in the storage unit is obtained through access address mapping, the test data and the corresponding access address are stored in the data cache and the address cache respectively, the fault judgment of the batch test data is converted into the serial reading and fault judgment of the individual test data, and the processing speed of the data reading and fault judgment link is adjusted; the first exit condition of the test data reading and fault judgment process is defined by the fault number threshold, and the acquisition of fault data can be completed without reading and judging all the test data in the batch test data, thereby improving the efficiency of fault data acquisition; the second exit condition of the test data reading and fault judgment process is defined by the total number of test data, and the test data reading and fault judgment process is completed when the first exit condition is not met, and all fault test data and corresponding access addresses of the batch test data are obtained, thereby realizing the acquisition of fault data and providing a data basis for further fault analysis.

[0154] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0155] In some embodiments, the present application further provides a fault data acquisition device, which is used to implement the above embodiments and preferred implementations, and will not be repeated for what has been described. The terms "module", "unit", "sub-unit", etc. used below may be a combination of software and / or hardware that implements a predetermined function. In some embodiments, Fig.12 is a structural block diagram of the fault data acquisition device of this embodiment, such as Fig.12 As shown, the device comprises:

[0156] A first acquisition module 1201 is used to acquire a fault quantity threshold of batch test data and access address information of the batch test data in the memory device under test based on a received fault data read instruction;

[0157] The second acquisition module 1202 is used to sequentially acquire the fault test data and the corresponding access addresses in the batch test data based on the access address information, and accumulate the number of the fault test data;

[0158] The return module 1203 is used to stop the process of obtaining the fault test data and the corresponding access address when the accumulated number of fault test data reaches the fault number threshold, and return the fault statistical data generated based on the fault test data and the corresponding access address.

[0159] The fault data acquisition device of this embodiment provides the conditions for quickly determining whether the number of faults in batch test data exceeds a threshold value and the address for acquiring batch test data through the first acquisition module 1201; the batch test data is screened by sequentially reading and judging through the second acquisition module 1202 to obtain individual fault test data, and the number of individual fault test data is accumulated during the screening process; the process of screening individual fault test data from the batch test data is terminated through the return module 1203 when the accumulated number of individual fault test data reaches the threshold value of the number of faults in the batch test data, and the acquisition of fault data can be completed without reading and judging all the test data in the batch test data, thereby improving the efficiency of fault data acquisition and solving the problems of long processing time and low efficiency of storage device fault data statistics.

[0160] In some of the embodiments, the second acquisition module includes an acquisition sub-module, a determination sub-module and a generation sub-module. The acquisition sub-module is used to sequentially acquire the test data and the corresponding access addresses in the batch test data based on the access address information; the determination sub-module is used to determine whether the test data is fault test data based on the value of the test data; and the generation sub-module is used to generate corresponding fault statistical data based on the fault test data and the corresponding access address when the test data is fault test data.

[0161] The fault data acquisition device of this embodiment acquires individual test data in sequence by using serial access through an acquisition submodule; determines and collects fault test data in sequence through a determination submodule; obtains fault statistical data that meets the data format requirements through a generation submodule when the test data is fault test data, and discards test data without fault, thereby saving subsequent processing resources.

[0162] In some of the embodiments, the acquisition submodule includes a first acquisition unit, a cache unit, a read unit, and a second acquisition unit. The first acquisition unit is used to sequentially acquire the access address and physical address of the test data in the batch test data in the storage device under test based on the access address information; the cache unit is used to store the access addresses into the address cache in sequence; the read unit is used to sequentially read the corresponding test data based on the physical address, and store the test data into the data cache in sequence; the second acquisition unit is used to sequentially read the data cache and the address cache in the order of storage to acquire the test data and the corresponding access address.

[0163] The fault data acquisition device of this embodiment converts the addresses of batch test data in the tested storage device into the addresses of individual test data in the memory through a first acquisition unit; determines the reading order of the individual test data through a cache unit; obtains the arrangement order of the test data corresponding to the address order through a reading unit; and uses the address cache and the data cache through a second acquisition unit to adjust the speed difference between the reading of the test data and the fault judgment of the test data, thereby ensuring the orderly serial reading of the test data and the fault judgment.

[0164] In some of the embodiments, the access address information includes an access address range and an address mapping relationship, the first acquisition unit includes a first acquisition sub-unit, a second acquisition sub-unit and a third acquisition sub-unit, the first acquisition sub-unit is used to obtain the row start address, row end address, column start address and column end address of the batch test data in the tested storage device based on the access address range; the second acquisition sub-unit is used to perform row accumulation or column accumulation based on the row start address, row end address, column start address and column end address to obtain the access address of the test data in sequence; the third acquisition sub-unit is used to obtain the physical address corresponding to the access address based on the access address and the address mapping relationship.

[0165] The fault data acquisition device of this embodiment acquires the access address of batch test data through the first acquisition subunit; determines the access address and access order of individual test data through the second acquisition subunit; and converts the address of the tested storage device into a memory address through the third acquisition subunit to read the test data.

[0166] In some of the embodiments, the third acquisition sub-unit is also used to determine the value of the corresponding physical address bit based on the correspondence between the access address bit and the physical address bit in the address mapping relationship, and the value of the access address bit, and arrange the physical address bits in order to obtain the physical address corresponding to the access address.

[0167] The fault data acquisition device of this embodiment converts the access address value into a physical address value by simply querying the correspondence table or querying the array value through the third acquisition sub-unit, thereby reducing the resources required for reading test data, providing an actual physical address for reading test data, and realizing sequential reading of test data.

[0168] In some of the embodiments, the determination submodule is further used to obtain access data bits of the test data based on the fault data reading instruction; based on the access data bits, read corresponding data values ​​in the test data; based on the data values, determine whether the test data is fault data.

[0169] The fault data acquisition device of this embodiment improves the reading efficiency and fault determination efficiency by determining the submodule to select a specific data bit in the test data to be read.

[0170] In some of the embodiments, the generating submodule is further used to combine the fault test data and the corresponding access address, generate corresponding fault statistical data, and store the fault statistical data into the fault data cache.

[0171] The fault data acquisition device of this embodiment obtains fault data that meets statistical requirements through the generation submodule, provides a data basis for subsequent fault analysis and further statistics, and stores the fault statistical data into the fault data cache for the fault statistics personnel to flexibly read the corresponding data by specifying the address.

[0172] In some of the embodiments, the fault data acquisition device also includes a third acquisition module and a repetition module, the third acquisition module is used to obtain the total number of test data in the batch test data based on the access address information; the repetition module is used to repeat the process of acquiring the fault test data and the corresponding access address when the cumulative number of fault test data does not reach the fault number threshold, until the number of test data read reaches the total number of test data.

[0173] The fault data acquisition device of this embodiment obtains the quantity parameter for terminating the data reading process through the third acquisition module; and controls the end timing of the fault data acquisition process through the total number of test data when the number of fault test data is less than the fault number threshold through the repetition module.

[0174] In some embodiments, the present application also provides a test data processing system, which includes the fault data acquisition device in the above embodiments, as well as a storage unit, a data cache, an address cache and a result cache; the fault data acquisition device is used to read test data from the storage unit in sequence, store the test data and the corresponding access address into the data cache and the address cache respectively, and store fault statistics data into the result cache.

[0175] The test data processing system of this embodiment acquires batch test data through a fault data acquisition device and performs data processing to obtain the fault test data and the corresponding access address therein, and stores intermediate data and result data through a data cache, an address cache and a result cache. The acquisition of fault data can be completed without reading and judging all the test data in the batch test data, thereby improving the efficiency of fault data acquisition.

[0176] In addition, in combination with the fault data acquisition method provided in the above embodiments, a readable storage medium may be provided in this embodiment to implement the method. The readable storage medium stores a program; when the program is executed by a processor, any one of the fault data acquisition methods in the above embodiments is implemented.

[0177] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0178] It should be understood that the specific embodiments described here are only used to explain this application, rather than to limit it. According to the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0179] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0180] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0181] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A method for acquiring fault data, characterized in that: The method comprises: Based on the received fault data read instruction, acquiring a fault quantity threshold of batch test data and access address information of the batch test data in the memory device under test; Based on the access address information, sequentially obtain the fault test data and the corresponding access addresses in the batch test data, and accumulate the number of the fault test data; When the accumulated number of the fault test data reaches the fault number threshold, the process of acquiring the fault test data and the corresponding access address is stopped, and the fault statistical data generated based on the fault test data and the corresponding access address is returned.

2. The method according to claim 1, characterized in that The acquiring, based on the access address information, the fault test data and the corresponding access addresses in the batch test data in sequence comprises: Based on the access address information, sequentially obtain the test data and the corresponding access addresses in the batch test data; Based on the value of the test data, determining whether the test data is fault test data; In a case where the test data is fault test data, corresponding fault statistical data is generated based on the fault test data and the corresponding access address.

3. The method according to claim 2, characterized in that The acquiring, based on the access address information, the test data in the batch test data and the corresponding access address in sequence comprises: Based on the access address information, sequentially acquiring access addresses and physical addresses of test data in the batch test data in the memory device under test; storing the access addresses into the address cache in sequence; Based on the physical address, reading corresponding test data in sequence, and storing the test data in the data cache in sequence; The data cache and the address cache are read in sequence according to the storage order to obtain the test data and the corresponding access address.

4. The method according to claim 3, characterized in that The access address information includes an access address range and an address mapping relationship, and sequentially acquiring access addresses and physical addresses of test data in the batch test data in the memory device under test based on the access address information includes: Based on the access address range, obtaining a row start address, a row end address, a column start address and a column end address of the batch test data in the memory device under test; Perform row accumulation or column accumulation based on the row start address, the row end address, the column start address and the column end address to sequentially obtain access addresses of the test data; Based on the access address and the address mapping relationship, a physical address corresponding to the access address is obtained.

5. The method according to claim 4, characterized in that The acquiring the physical address corresponding to the access address based on the access address and the address mapping relationship comprises: Determine the value of the corresponding physical address bit based on the correspondence between the access address bit and the physical address bit in the address mapping relationship and the value of the access address bit; Arrange the physical address bits in order to obtain a physical address corresponding to the access address.

6. The method according to claim 2, characterized in that The determining, based on the value of the test data, whether the test data is fault test data comprises: Based on the fault data read instruction, obtaining access data bits of the test data; Based on the access data bit, reading a corresponding data value in the test data; Based on the data value, it is determined whether the test data is fault data.

7. The method according to claim 2, characterized in that After determining whether the test data is fault test data based on the value of the test data, the method further includes: In the case where it is determined that the test data is not fault test data, discarding the test data and the corresponding access address; In the case where it is determined that the test data is fault test data, the test data is identified by a fault identification bit.

8. The method according to claim 2, characterized in that: The generating corresponding fault statistics data based on the fault test data and the corresponding access address comprises: Combining the fault test data and the corresponding access address to generate corresponding fault statistical data; The fault statistical data is stored in a fault data cache.

9. The method according to claim 1, characterized in that: The method further comprises: Based on the access address information, obtaining the total amount of test data in the batch test data; When the accumulated number of the fault test data does not reach the fault number threshold, the process of acquiring the fault test data and the corresponding access address is repeated until the number of the read test data reaches the total number of the test data.

10. A fault data acquisition device, characterized in that: The device comprises: A first acquisition module, configured to acquire a fault quantity threshold of batch test data and access address information of the batch test data in a memory device under test based on a received fault data read instruction; A second acquisition module, configured to sequentially acquire the fault test data and the corresponding access addresses in the batch test data based on the access address information, and accumulate the number of the fault test data; The return module is used to stop the process of obtaining the fault test data and the corresponding access address when the cumulative number of the fault test data reaches the fault number threshold, and return the fault statistical data generated based on the fault test data and the corresponding access address.

11. A test data processing system, characterized in that: The test data processing system comprises the fault data acquisition device according to claim 10, as well as a storage unit, a data cache, an address cache and a result cache; The fault data acquisition device is used to read test data from the storage unit in sequence, store the test data and the corresponding access address into the data cache and the address cache respectively, and store the fault statistical data into the result cache.

12. A readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the steps of the fault data acquisition method according to any one of claims 1 to 9 are implemented.

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