Test data processing method and device and memory device test system

Abstract

The invention relates to a test data processing method and device and a memory device test system.The method is applied to the memory device test system, the memory device test system comprises a tested memory device and a memory used for storing test data, and the method comprises the steps that the memory address of the tested memory device is stored on the basis of target test data and a pre-obtained corresponding memory address; the historical test data stored in the memory address is updated, and after the target test data is stored in a preset address of the tested memory device based on the historical test data, the tested memory device completes one-time test and reads the preset address to obtain the target test data; the updating process of the historical test data is repeated on the basis of the predetermined number of times of testing; and based on the historical test data after the test and the initial test data before the test, determining the fault occurrence number of the tested memory device, thereby solving the problems of long processing time and low test efficiency of the test data of the memory device.

Description

Technical Field

[0001] The present application relates to the field of memory testing technology, and in particular to a test data processing method, device and memory device testing system. Background Art

[0002] Semiconductor memory devices have a development trend of increasing capacity, operating frequency and process complexity. Therefore, it is very important to detect the failure of memory devices before leaving the factory through testing in the production process to reduce the failure rate of memory devices after leaving the factory. The testing method usually writes pre-set data to the memory device under test through a processor, and then reads the written data, and compares the written data with the read data to test whether the memory device has a fault. For the test of batch memory devices, the cumulative number of failures can be counted after multiple tests on multiple memory devices under test to obtain the failure rate data of batch memory devices. When the number of memory devices under test is large, the capacity is large, and the number of tests is large, there is also a lot of test data that needs to be compared and post-processed, which will result in a long time for test data processing and failure data statistics, and low test efficiency.

[0003] Currently, no effective solution has been proposed to solve the problems of long processing time and low test efficiency of memory device test data in the related art. Summary of the invention

[0004] In this embodiment, a test data processing method, apparatus and storage device test system are provided to solve the problems of long processing time and low test efficiency of storage device test data existing in the related art.

[0005] In a first aspect, a test data processing method is provided in this embodiment. The method is applied to a memory device test system. The memory device test system includes a memory device under test and a memory for storing test data. The method includes:

[0006] Based on the target test data and the corresponding memory address acquired in advance, the historical test data stored in the memory address is updated, and the target test data is stored in the preset address of the memory device under test based on the historical test data, and is obtained by the memory device under test completing a test and reading the preset address;

[0007] Repeating the updating process of the historical test data based on a predetermined number of tests;

[0008] The number of failures of the tested memory device is determined based on the historical test data after the test and the initial test data before the test.

[0009] In some embodiments, the updating of the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance includes:

[0010] Based on the memory address, reading corresponding historical test data from the memory;

[0011] comparing the target test data with the historical test data based on a predetermined storage mode;

[0012] When the target test data is inconsistent with the historical test data, acquiring update data based on the target test data and the historical test data;

[0013] Based on the memory address, the update data is written into the memory.

[0014] In some embodiments, the storage mode includes a flag mode, and comparing the target test data with the historical test data based on a predetermined storage mode includes:

[0015] Acquire the marker data corresponding to the target test data;

[0016] Performing an AND operation on the marker data and the target test data, and then performing an OR operation with the historical test data to obtain marker test data;

[0017] The signature test data is compared to the historical test data.

[0018] In some embodiments, the storage mode includes a mask mode, and comparing the target test data with the historical test data based on a predetermined storage mode includes:

[0019] Obtaining mask data corresponding to the historical test data;

[0020] Performing an AND operation on the inverted value of the mask data and the target test data, and then performing an OR operation with the historical test data to obtain mask test data;

[0021] The masked test data is compared with the historical test data.

[0022] In some embodiments, when the target test data is inconsistent with the historical test data, acquiring update data based on the target test data and the historical test data includes:

[0023] An OR operation is performed on the target test data and the historical test data to obtain the update data.

[0024] In some embodiments, determining the number of failures of the tested memory device based on historical test data after the test and initial test data before the test includes:

[0025] Compare the historical test data corresponding to the same memory address with the initial test data by data bit;

[0026] Determining the number of failures in the historical test data based on the number of data bits with inconsistent data values;

[0027] The number of failures of the memory device under test is determined based on the number of failures of each historical test data stored in the memory device under test.

[0028] In some embodiments, before updating the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance, the method further includes:

[0029] Based on a predetermined burst length, determining whether a target data bit in the target test data is faulty;

[0030] In the event of a failure of the target data bit, the historical test data stored in the memory address is updated based on the target test data and the memory address.

[0031] In some embodiments, the memory device test system further includes a test flow module and a cache, and before updating the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance, the method further includes:

[0032] storing the target test data and the corresponding memory address read during the test of the memory device under test into the cache;

[0033] When the amount of data stored in the cache is greater than a pre-configured overflow watermark, a back pressure signal is sent to the test flow module to control the test flow module to suspend testing.

[0034] In a second aspect, a test data processing device is provided in this embodiment, the device is applied to a memory device test system, the memory device test system includes a memory device under test and a memory for storing test data, the device includes:

[0035] An update module, configured to update historical test data stored in the memory address based on target test data and a corresponding memory address acquired in advance, wherein after the target test data is stored in a preset address of the memory device under test based on the historical test data, the memory device under test completes a test and reads the preset address to obtain;

[0036] A testing module, used for repeating the updating process of the historical test data based on a predetermined number of tests;

[0037] The first determination module is used to determine the number of failures of the tested storage device based on the historical test data after the test and the initial test data before the test.

[0038] In some embodiments, the update module includes:

[0039] A reading submodule, used for reading corresponding historical test data from the memory based on the memory address;

[0040] a first comparison submodule, configured to compare the target test data with the historical test data based on a predetermined storage mode;

[0041] an acquisition submodule, configured to acquire update data based on the target test data and the historical test data when the target test data is inconsistent with the historical test data;

[0042] A writing submodule is used to write the update data into the memory based on the memory address.

[0043] In some embodiments, the storage mode includes a flag mode, and the first comparison submodule includes:

[0044] A first acquisition unit, used to acquire the mark data corresponding to the target test data;

[0045] A first logic operation unit, configured to perform an AND operation on the flag data and the target test data, and then perform an OR operation on the flag data and the target test data to obtain the flag test data;

[0046] The first comparing unit is used to compare the marker test data with the historical test data.

[0047] In some embodiments, the storage mode includes a mask mode, and the first comparison submodule includes:

[0048] A second acquisition unit, used to acquire mask data corresponding to the historical test data;

[0049] A second logic operation unit is used to perform an AND operation on the inverted value of the mask data and the target test data, and then perform an OR operation on the inverted value of the mask data and the historical test data to obtain mask test data;

[0050] The second comparing unit is used to compare the mask test data with the historical test data.

[0051] In some embodiments, the storage device testing system further includes a test flow module and a cache, and the test data processing device further includes:

[0052] A storage module, used for storing the target test data and the corresponding memory address read during the test of the memory device under test into the cache;

[0053] The back pressure module is used to send a back pressure signal to the test flow module to control the test flow module to suspend the test when the amount of data stored in the cache is greater than a pre-configured overflow watermark.

[0054] In a third aspect, a memory device test system is provided in this embodiment, and the memory device test system includes the test data processing apparatus as described in the second aspect, a memory device under test, and a memory for storing test data.

[0055] Compared with the related art, the test data processing method provided in the present embodiment updates the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance. After the target test data is stored in the preset address of the memory device under test based on the historical test data, the memory device under test completes a test and reads the preset address to obtain the target test data; that is, in the process of multiple tests of the memory device under test, the updated data is generated according to the target test data read in each test and written into the memory for the next test to read until the test is completed. If the target test data fails in a certain test, the updated data with the failure information is written into the memory and persists in the subsequent tests; by repeating the historical test based on a predetermined number of times, the updated data is repeated. The updating process of historical test data updates the historical test data stored in the memory according to the target test data read in each test; the number of failures of the tested storage device is determined based on the historical test data after the test and the initial test data before the test; the number of failures corresponding to the historical test data is determined according to the comparison result between the historical test data finally stored in the memory and the initial test data; the number of failures of the tested storage device is counted according to the multiple historical test data corresponding to the tested storage device; the number of failures of each test is automatically accumulated as the number of tests is accumulated, and there is no need to count the failure conditions of the test data every time a test is completed, thereby solving the problems of long processing time and low test efficiency of storage device test data.

[0056] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0058] Figure 1 is a block diagram of the computer hardware structure of the test data processing method for running some embodiments of the present application;

[0059] Figure 2 is a flow chart of a test data processing method according to some embodiments of the present application;

[0060] Figure 3 is a flowchart of updating historical test data based on target test data and memory address in some embodiments of the present application;

[0061] Figure 4 is a flow chart of comparing target test data with historical test data in a flag mode in some embodiments of the present application;

[0062] Figure 5 is a flowchart of comparing target test data with historical test data in mask mode in some embodiments of the present application;

[0063] Figure 6 is a flow chart of determining the number of failures of a memory device under test according to some embodiments of the present application;

[0064] Figure 7 is a flowchart of target test data preprocessing in some embodiments of the present application;

[0065] Figure 8 is a flow chart of data cache overflow control of some embodiments of the present application;

[0066] Fig. 9 is a schematic diagram of the internal connection of a storage device test system in some preferred embodiments of the present application;

[0067] Fig.10 is a flow chart of a test data processing method according to some preferred embodiments of the present application;

[0068] Fig.11 It is a structural block diagram of a test data processing device according to some embodiments of the present application. DETAILED DESCRIPTION

[0069] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0070] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not represent quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. Usually, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0071] The test data processing method provided in the embodiment of the present application can be executed in a terminal, a computer or a similar computing device, and the computing device can be a host computer of a storage device test system, and the storage device test system can include a storage device under test and a memory for storing test data. When the method is applied to a computer, Figure 1 1 is a hardware structure diagram of a computer for testing data processing methods in some embodiments of the present application. Figure 1 As shown, the computer may include one or more ( Figure 1 Only one is shown in the figure) processor 102 and memory 104 for storing data, wherein processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above computer may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0072] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the test data processing method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some embodiments, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0073] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by a communication provider. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0074] In this embodiment, a test data processing method is provided. Figure 2 is a flow chart of a test data processing method according to some embodiments of the present application. Figure 2 As shown, the process includes the following steps:

[0075] Step S201, based on the target test data and the corresponding memory address obtained in advance, the historical test data stored in the memory address is updated. The target test data is stored in the preset address of the memory device under test based on the historical test data, and is obtained after the memory device under test completes a test and reads the preset address.

[0076] Before the memory device test begins, the predetermined initial test data is stored in the memory, and the initial test data is written into the preset address of the memory device under test, and the corresponding memory address is input into the test process of the memory device under test for testing. There may be multiple memory devices under test, and each memory device under test may correspond to multiple initial test data, which are stored in different addresses of the memory. After completing a test, the target test data is read from the preset address of the memory device under test, and the corresponding memory address is obtained from the test process. Furthermore, the test process can also output a control signal for controlling the target test data and the corresponding memory address to be stored in the cache, in preparation for subsequent data comparison and post-processing.

[0077] According to the memory address, the corresponding initial test data is read from the memory storing the initial test data, and after being compared with the corresponding target test data, the initial test data in the memory is updated according to the comparison result. This process is repeated once after each test, and the data updated in the memory each time is called historical test data. During multiple tests, the memory address storing the historical test data may be changed or may not be changed, which is not limited in this embodiment. If the memory address changes, the corresponding test data update can be completed in the changed memory address.

[0078] Step S202, repeating the updating process of historical test data based on a predetermined number of tests.

[0079] Assuming that the number of tests of the memory device under test is N, the number of updates of the historical test data in the memory is also N.

[0080] Step S203 , determining the number of failures of the tested memory device based on the historical test data after the test and the initial test data before the test.

[0081] After the test is completed, the historical test data in the memory is compared with the initial test data. If the two are exactly the same, it can be determined that no fault occurred during the test; if there is a difference between the two in a specific data bit, it means that the tested memory device has a fault during the test. The number of faults that occurred in the historical test data is determined based on the number of different data bits. By counting all the historical test data corresponding to the tested memory device, the number of faults that occurred in the tested memory device can be obtained.

[0082] Through the above steps S201 to S203, the historical test data stored in the memory address is updated based on the target test data and the corresponding memory address obtained in advance, that is, in the process of multiple tests of the memory device under test, the updated data is generated according to the target test data read in each test and written into the memory for the next test to read until the test is completed. If the target test data fails in a certain test, the updated data with the fault information is written into the memory and persists in the subsequent tests; the updating process of the historical test data is repeated based on the predetermined number of tests, and the historical test data stored in the memory is updated according to the target test data read in each test; the number of faults of the memory device under test is determined based on the historical test data after the test and the initial test data before the test, the number of faults of the historical test data is determined according to the comparison result between the historical test data and the initial test data, the number of faults of the memory device under test is counted according to the historical test data corresponding to the memory device under test, and the number of faults is automatically accumulated following the test process, so that the fault situation of the test data does not need to be counted every time a test is completed, thereby solving the problems of long processing time and low test efficiency of the memory device test data.

[0083] In some of these embodiments, Figure 3 is a flowchart of updating historical test data based on target test data and memory address in some embodiments of the present application, such as Figure 3 As shown, the process includes the following steps:

[0084] Step S301, reading corresponding historical test data from the memory based on the memory address.

[0085] This embodiment is a process of updating historical test data corresponding to one of the tests in the entire test process of the tested memory device. The historical test data refers to the test data updated by the last test of the current test. The memory address corresponding to the historical test data can be obtained from the test process.

[0086] Step S302 : comparing the target test data with the historical test data based on a predetermined storage mode.

[0087] Storage mode refers to the storage format of test data, which can include normal mode, flag mode and mask mode, which are predetermined according to different test requirements. Among them, the flag mode can correspond to the business of fault data capture under specific conditions; the mask mode can correspond to the business of incremental fault data testing; the normal mode can correspond to other businesses except the above two special businesses.

[0088] The target test data is the test data read from the memory device under test after this test. Different storage modes lead to different comparison methods between the target test data and the historical test data. For example, in the normal mode, the target test data and the historical test data can be directly compared for each data bit. If the data of any one or more data bits are different, it is determined that the target test data is inconsistent with the historical test data. However, the flag mode and mask mode require the target test data to be processed accordingly before being compared with the historical test data.

[0089] Step S303: when the target test data is inconsistent with the historical test data, update data is obtained based on the target test data and the historical test data.

[0090] If the result of the comparison is that the target test data is inconsistent with the historical test data, then update data is obtained according to the target test data and the historical test data, and the update data can be the result of a logical operation between the target test data and the historical test data. If the target test data is consistent with the historical test data, the historical test data in the memory remains unchanged and the target test data can be discarded.

[0091] Step S304, writing the updated data into the memory based on the memory address.

[0092] The updated data is written into the memory space corresponding to the memory address to complete an update of the historical test data.

[0093] Through the above steps S301 to S304, the corresponding historical test data is read from the memory based on the memory address to obtain reference data for comparison with the target test data; the target test data is compared with the historical test data based on a predetermined storage mode to determine whether a data reading and writing failure occurs in the storage device under test in this test; when the target test data and the historical test data are inconsistent, update data is obtained based on the target test data and the historical test data, and in the event of a failure, update data is generated using the target test data with fault information and the original historical test data to obtain the fault information; based on the memory address, the update data is written into the memory, and the update data retains the fault information until the end of the test, thereby providing test data for subsequent statistics of fault information.

[0094] In some of the embodiments, the storage mode of the test data includes a flag mode, Figure 4 is a flowchart of comparing target test data with historical test data in the mark mode of some embodiments of the present application, such as Figure 4 As shown, the process includes the following steps:

[0095] Step S401, obtaining marker data corresponding to target test data.

[0096] Before comparing the target test data with the historical test data, the flag data corresponding to the target test data can be obtained first. The flag data is used to identify the data bit that needs to be tested for the target test data, and the data bit that needs to be tested can be one or more. When the data bit is 1, it indicates that the corresponding data bit of the target test data needs to be tested for faults, and when the data bit is 0, it indicates that the corresponding data bit of the target test data does not need to be tested for faults.

[0097] Step S402, performing an AND operation on the marker data and the target test data, and then performing an OR operation with the historical test data to obtain the marker test data.

[0098] In this embodiment, under normal circumstances, all data bits of the target test data are 0. When one or more data bits in the flag data are 1, it indicates that the corresponding data bits of the target test data need to be tested. Perform an AND operation on the flag data and the target test data. When a specific data bit of the flag data is 0, no matter whether the data bit corresponding to the target test data is 0 or 1, the result of the AND operation on the data bit is 0, that is, the data bit does not need to be tested for faults; when a specific data bit of the flag data is 1, if the corresponding data bit of the target test data is 0, the result of the AND operation on the data bit is also 0. If all data bits in the result obtained after performing the AND operation are 0, the target test data can be directly discarded; if a data bit in the result obtained after performing the AND operation is 1, it indicates that there is a fault in the corresponding data bit of the target test data.

[0099] In the case that the target test data has a fault, the result data of the AND operation is ORed with the historical test data to obtain the flag test data. That is, if any data bit in the result data of the AND operation or the historical test data is 1, the corresponding data bit of the flag test data is 1. If all data bits of the flag test data are 0, the target test data can be discarded; if a data bit of the flag test data is 1, it means that at least one of the target test data and the historical test data has a fault in the data bit.

[0100] Step S403, comparing the marked test data with the historical test data.

[0101] If the flag test data has a data bit of 1, the flag test data is compared with the historical test data. If the two are consistent, that is, the flag test data and the historical test data are both 1 in the same one or more data bits, the target test data can be discarded. If the flag test data is inconsistent with the historical test data, it means that there is a new fault in the target test data, and the flag test data is stored in the memory.

[0102] Through the above steps S401 to S403, the fault detection data bit corresponding to the target test data is determined by acquiring the flag data corresponding to the target test data; the fault in the target test data is detected by performing an AND operation on the flag data and the target test data, and then obtaining the flag test data by ORing with the historical test data; by comparing the flag test data with the historical test data, it is further determined whether the target test data is faulty, and the fault information of the fault data bit is retained by updating the historical test data, thereby providing data for subsequent fault statistics.

[0103] In some of the embodiments, the storage mode of the test data includes a mask mode, Figure 5 FIG. 1 is a flowchart of comparing target test data with historical test data in mask mode in some embodiments of the present application. Figure 5 As shown, the process includes the following steps:

[0104] Step S501, obtaining mask data corresponding to historical test data.

[0105] Mask data refers to all-1 data used to mask some predetermined data bits in the test data, which can be one bit or multiple bits. For example, the test data has 0 to 31 bits in total, of which 24 to 31 bits correspond to the mask data 11111111. The mask data can be used to distinguish test data from different sources or different processing methods. For example, the mask data of 24 to 31 bits can correspond to the test data that has already failed, and the corresponding data bits of the test data can be set without fault judgment and processing. The data bits that need to be masked for each historical test data can be different, that is, the corresponding mask data can be different.

[0106] Step S502 , performing an AND operation on the inverted value of the mask data and the target test data, and then performing an OR operation with the historical test data to obtain mask test data.

[0107] In this embodiment, the mask data is 1, and is 0 after being inverted. The mask data and the target test data read from the memory device under test are subjected to an AND operation. Regardless of whether the data bit corresponding to the mask data in the target test data is 0 or 1, the result data obtained by the AND operation is 0. In other words, the AND operation masks the faults that occur in the data bits corresponding to the mask data in the target test data. The result of the AND operation is then ORed with the historical test data to obtain the mask test data. That is, if any one of the data bits in the result data of the AND operation and the historical test data is 1, the data bit corresponding to the mask test data is 1. If the mask test data is 0, it means that the target test data and the historical test data are both fault-free; if the mask test data has a data bit that is 1 (non-masked data bit), it means that at least one of the target test data and the historical test data has a fault in the data bit.

[0108] Step S503: compare the masked test data with the historical test data.

[0109] Similar to step S403 of the above embodiment, the mask test data is compared with the historical test data. If the two are consistent, it means that the target test data has no fault and the target test data can be discarded. If the mask test data is inconsistent with the historical test data, it means that the target test data has a fault and the mask test data is stored in the memory.

[0110] Through the above steps S501 to S503, the mask data corresponding to the historical test data is obtained to obtain the mask data bits corresponding to the target test data; the mask data bits corresponding to the target test data are obtained by performing an AND operation on the inverted value of the mask data and the target test data, and then performing an OR operation with the historical test data to obtain the mask test data, thereby shielding the data bit faults corresponding to the mask data, and accumulating the number of faults in the historical test data and the target test data; whether the target test data is faulty is determined by comparing the mask test data with the historical test data, and the fault information of the faulty data bits is retained by updating the historical test data to provide data for subsequent fault statistics.

[0111] In some embodiments, a specific method for obtaining update data based on target test data and historical test data is provided, and the method includes:

[0112] An OR operation is performed on the target test data and the historical test data to obtain updated data.

[0113] The storage mode of the test data of this embodiment is a normal mode. In the normal mode, the target test data is directly compared with the historical test data. If the two are consistent, it means that the target test data has no fault and the target test data can be discarded; if the two are inconsistent, it means that the target test data has a fault. At this time, an OR operation is performed on the target test data and the historical test data to obtain updated data, and the updated data is stored in the memory.

[0114] The test data processing method of this embodiment performs an OR operation on the target test data and the historical test data. When a fault exists in the target test data, that is, the value of at least one data bit is 1 and the value of the corresponding data bit of the historical test data is 0, the value of the corresponding data bit of the updated data is set to 1, thereby retaining the fault data bit information of the target test data until the test is completed, thereby providing valid fault data for subsequent fault statistics.

[0115] In some of these embodiments, Figure 6 is a flow chart of determining the number of failures of a tested memory device according to some embodiments of the present application, such as Figure 6 As shown, the process includes the following steps:

[0116] Step S601, comparing historical test data corresponding to the same memory address with initial test data by data bit.

[0117] After the test is completed, the historical test data corresponding to the memory address retains the fault data bit information of each test, and is compared with the initial test data by data bit to obtain the fault data bit information. For example, if the historical test data has a total of 8 bits, which is 11000010, and the initial test data is 00000000, it can be determined that the 1st, 6th, and 7th bits of the historical test data are faulty.

[0118] Step S602, determining the number of faults occurring in the historical test data based on the number of data bits with inconsistent data values.

[0119] For each historical test data, the number of data bits with inconsistent data values ​​is equal to the number of failures occurring in the historical test data.

[0120] Step S603 , determining the number of failures of the memory device under test based on the number of failures stored in each historical test data of the memory device under test.

[0121] Each memory device under test may correspond to multiple historical test data. The number of failures in each historical test data is accumulated to obtain the number of failures in the memory device under test. The failure rate of the memory devices under test in this batch can also be calculated based on the cumulative number of failures and the cumulative number of tests of all memory devices under test in this batch of tests.

[0122] Through the above steps S601 to S603, by comparing the historical test data corresponding to the same memory address with the initial test data according to the data bit, it is determined whether the historical test data fails during the test; by determining the number of failures of the historical test data based on the number of data bits with inconsistent data values, the cumulative number of failures of the historical test data during the test process is obtained; by determining the number of failures of the memory device under test based on the number of failures of each historical test data stored in the memory device under test, the failure statistics of this batch of memory devices under test are obtained, and the efficiency of failure data statistics is improved.

[0123] In some of the embodiments, before the historical test data in the memory address is updated, a method for preprocessing the target test data is also involved. Figure 7 is a flowchart of target test data preprocessing in some embodiments of the present application, such as Figure 7 As shown, the process includes the following steps:

[0124] Step S701 , based on a predetermined burst length, determining whether a target data bit in target test data is faulty.

[0125] The burst length is a predetermined length of one or more data bits. For example, if the target test data is 32 bits, the burst length can be 1, 2, 4 bits, etc. When reading the target test data, the burst length data is read starting from the predetermined data bits, for example, starting from the 8th bit, the 8th and 9th bits of data, i.e., the target data bits, are read to determine whether the two bits of data are faulty.

[0126] Step S702 , in the case of a target data bit failure, based on the target test data and the memory address, the historical test data stored in the memory address is updated.

[0127] In the case of a target data bit failure, the target test data is determined to be faulty, and the operation of updating the historical test data is then performed, otherwise the target test data can be discarded.

[0128] Through the above steps S701 to S702, by determining whether the target data bit in the target test data is faulty based on a predetermined burst length, it is possible to determine whether the target test data is faulty when only a small amount of target test data is read, without having to read all the target test data, thereby improving data throughput and test efficiency; by updating the historical test data stored in the memory address based on the target test data and the memory address when the target data bit is faulty, pre-processing the target test data, and discarding non-faulty data, subsequent data processing resources are saved and the efficiency of faulty data processing is improved.

[0129] In some embodiments, the memory device test system further includes a test flow module and a cache. Before updating the historical test data in the memory address, a method for the test flow module and the test data processing module to coordinate the test progress through the cache is also involved. Figure 8 is a flow chart of data cache overflow control in some embodiments of the present application, such as Figure 8 As shown, the process includes the following steps:

[0130] Step S801 , storing the target test data and the corresponding memory address read during the test of the memory device under test into a cache.

[0131] Since there is a difference in the processing speed of the test data between the test flow module and the test data processing module, the present embodiment sets a cache to connect the test flow module and the test data processing module respectively to store the target test data, memory address and corresponding control signal generated by the test flow module for reading by the test data processing module. Usually, the processing speed of the test flow module is faster than that of the test data processing module, so there is a risk of overflow of the data in the cache. To avoid overflow, the cache can be configured with an overflow waterline in advance. The overflow waterline can be a specific parameter of the cache capacity or a total capacity ratio parameter.

[0132] Step S802: When the amount of data stored in the cache is greater than a pre-configured overflow watermark, a back pressure signal is sent to the test process module to control the test process module to suspend the test.

[0133] When the amount of data stored in the cache exceeds the overflow watermark, the cache sends a back pressure signal to the test process module, and the test process module suspends the test until the amount of data stored in the cache is lower than the overflow watermark and then resumes the test.

[0134] Through the above steps S801 to S802, the target test data and the corresponding memory address read during the test of the tested storage device are stored in the cache, so as to adjust the difference in data processing speed between the test flow module and the test data processing module; when the amount of data stored in the cache is greater than the pre-configured overflow watermark, a back pressure signal is sent to the test flow module to control the test flow module to suspend the test, avoid cache overflow, adjust the serial processing speed of the target test data, and control the orderly execution of the storage device test process and the test data processing process.

[0135] The present embodiment is described and illustrated below through preferred embodiments. Fig. 9 1 is a schematic diagram of the internal connection of a storage device test system of some preferred embodiments of the present application, wherein the storage device test system includes a DUT test flow module 91, a data processing module 92, a parameter configuration module 93, and a data cache 94. The data processing module 92 includes a data preprocessing module 921, a read / write control module 922, and a DDR memory 923. Fig.10 Flowchart of the test data processing method of some preferred embodiments of the present application. Fig.10 As shown, the process includes the following steps:

[0136] Step S1001, the parameter configuration module receives the configuration instruction from the software, and after parsing, sends the configuration parameters to the registers corresponding to the data cache and the data processing module. The configuration parameters include: overflow watermark and storage mode;

[0137] Step S1002, the DUT test flow module sends target test data, corresponding memory address and control signal to the data cache;

[0138] Step S1003, when the data capacity of the data cache exceeds the overflow watermark, a back pressure signal is sent to the test process module to suspend the test;

[0139] Step S1004, the data preprocessing module reads the target test data from the data cache, and determines whether the target data bit in the target test data is faulty according to a predetermined burst length;

[0140] Step S1005, when there is no fault in the target data bit, discard the target test data;

[0141] Step S1006, when there is a fault in the target data bit, the read / write control module reads the corresponding historical test data from the DDR memory based on the memory address corresponding to the target test data;

[0142] Step S1007, when the storage mode is the normal mode, compare the historical test data with the target test data;

[0143] Step S1008, when the comparison results are inconsistent, perform an OR operation on the historical test data and the target test data to obtain updated data and write it into the DDR memory corresponding to the memory address;

[0144] Step S1009, when the storage mode is the flag mode, obtaining flag data corresponding to the target test data;

[0145] Step S1010, performing an AND operation on the marker data and the target test data, and then performing an OR operation with the historical test data to obtain the marker test data;

[0146] Step S1011, comparing the marked test data with the historical test data;

[0147] Step S1012, when the comparison result is inconsistent, writing the flag test data into the DDR memory corresponding to the memory address;

[0148] Step S1013, when the storage mode is the mask mode, obtaining mask data corresponding to the historical test data;

[0149] Step S1014, performing an AND operation on the inverted value of the mask data and the target test data, and then performing an OR operation with the historical test data to obtain mask test data;

[0150] Step S1015, comparing the mask test data with the historical test data;

[0151] Step S1016, when the comparison result is inconsistent, writing the mask test data into the DDR memory corresponding to the memory address;

[0152] Step S1017, in each of the above storage modes, when the comparison results are consistent, discard the target test data, the mark test data or the mask test data;

[0153] Step S1018, repeating steps S1004 to S1017 until the test is completed; comparing the historical test data corresponding to the same memory address with the initial test data by data bit, and determining the number of faults in the historical test data according to the number of data bits with inconsistent data values;

[0154] Step S1019, determining the number of failures of the memory device under test based on the number of failures stored in each historical test data of the memory device under test.

[0155] Through the above steps S1001 to S1019, during multiple tests of the memory device under test, the serial processing speed of the target test data is adjusted by the buffer overflow back pressure; update data is generated according to the target test data read in each test and written into the memory for the next test to read until the test is completed. If the target test data fails in a certain test, the update data with the fault information is written into the memory and persists in the subsequent tests; according to different storage modes, the target test data is processed differently and compared with the historical test data, and the target test data is discarded when the comparison results are consistent, saving subsequent data processing resources; when the comparison results are inconsistent, the or operation is performed to retain the fault information of the target test data; according to the comparison results of the finally generated historical test data and the initial test data, the number of faults of the historical test data is determined, and the number of faults of the memory device under test is counted according to the historical test data corresponding to the memory device under test, and the number of faults is automatically accumulated synchronously with the test process, so that there is no need to count the fault conditions of the test data every time a test is completed, thereby improving the processing efficiency of the test data and saving processing resources.

[0156] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0157] In some embodiments, the present application also provides a test data processing device, which is applied to a memory device test system, and the memory device test system includes a memory device under test and a memory for storing test data. The test data processing device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. The terms "module", "unit", "sub-unit", etc. used below can be a combination of software and / or hardware that implements a predetermined function. In some embodiments, Fig.11 is a structural block diagram of the test data processing device of this embodiment, such as Fig.11 As shown, the device comprises:

[0158] An updating module 1101, configured to update historical test data stored in a memory address based on target test data and a corresponding memory address obtained in advance, wherein the target test data is stored in a preset address of a memory device under test based on the historical test data, and the memory device under test completes a test and reads the preset address to obtain the target test data;

[0159] A testing module 1102, configured to repeat the updating process of historical test data based on a predetermined number of tests;

[0160] The first determination module 1103 is used to determine the number of failures of the tested memory device based on the historical test data after the test and the initial test data before the test.

[0161] The test data processing device of this embodiment updates the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance through the update module 1101, that is, in the process of multiple tests of the memory device under test, the update data is generated according to the target test data read in each test and written into the memory for the next test to read until the test is completed. If the target test data fails in a certain test, the update data with the failure information is written into the memory and persists in the subsequent test; the test module 1102 repeats the updating process of the historical test data based on the predetermined number of tests, and updates the historical test data stored in the memory according to the target test data read in each test; the first determination module 1103 determines the number of failures of the memory device under test based on the historical test data after the test and the initial test data before the test, determines the number of failures of the historical test data according to the comparison result of the historical test data and the initial test data, and counts the number of failures of the memory device under test according to the historical test data corresponding to the memory device under test, and automatically accumulates the number of failures following the test process, so that it is not necessary to count the failure of the test data every time a test is completed, thereby solving the problems of long processing time and low test efficiency of the memory device test data.

[0162] In some of the embodiments, the update module includes a read submodule, a first comparison submodule, an acquisition submodule and a write submodule, the read submodule is used to read the corresponding historical test data from the memory based on the memory address; the first comparison submodule is used to compare the target test data with the historical test data based on a predetermined storage mode; the acquisition submodule is used to acquire update data based on the target test data and the historical test data when the target test data is inconsistent with the historical test data; the write submodule is used to write the update data into the memory based on the memory address.

[0163] The test data processing device of this embodiment reads the corresponding historical test data from the memory based on the memory address through the reading submodule to obtain reference data for comparison with the target test data; compares the target test data with the historical test data based on a predetermined storage mode through the first comparison submodule to determine whether a data reading and writing failure occurs in the storage device under test in this test; obtains update data based on the target test data and the historical test data when the target test data and the historical test data are inconsistent through the acquisition submodule, and generates update data using the target test data with fault information and the original historical test data in the event of a fault to obtain the fault information; writes the update data into the memory based on the memory address through the writing submodule, and the update data retains the fault information until the end of the test, providing test data for subsequent statistics of fault information.

[0164] In some of the embodiments, the storage mode includes a flag mode, and the first comparison submodule includes a first acquisition unit, a first logic operation unit and a first comparison unit, the first acquisition unit is used to acquire flag data corresponding to the target test data; the first logic operation unit is used to perform an AND operation on the flag data and the target test data, and then OR them with the historical test data to obtain the flag test data; the first comparison unit is used to compare the flag test data with the historical test data.

[0165] The test data processing device of this embodiment obtains the fault detection data bit corresponding to the target test data through the first acquisition unit; performs an AND operation on the flag data and the target test data through the first logic operation unit, and then obtains the flag test data by ORing with the historical test data to detect the fault in the target test data; compares the flag test data with the historical test data through the first comparison unit to further determine whether the target test data is faulty, and retains the fault information of the fault data bit by updating the historical test data to provide data for subsequent fault statistics.

[0166] In some of the embodiments, the storage mode includes a mask mode, and the first comparison submodule includes a second acquisition unit, a second logic operation unit and a second comparison unit, the second acquisition unit is used to obtain mask data corresponding to the historical test data; the second logic operation unit is used to perform an AND operation on the inverted value of the mask data and the target test data, and then OR them with the historical test data to obtain the mask test data; the second comparison unit is used to compare the mask test data with the historical test data.

[0167] The test data processing device of this embodiment obtains the mask data corresponding to the historical test data through the second acquisition unit, and obtains the mask data bits corresponding to the target test data; performs an AND operation on the inverted value of the mask data and the target test data through the second logic operation unit, and then performs an OR operation with the historical test data to obtain the mask test data, thereby shielding the data bit faults corresponding to the mask data, and accumulating the number of faults in the historical test data and the target test data; compares the mask test data with the historical test data through the second comparison unit to determine whether the target test data is faulty, and retains the fault information of the faulty data bits by updating the historical test data, thereby providing data for subsequent fault statistics.

[0168] In some of the embodiments, the acquisition submodule includes an OR operation unit, and the OR operation unit is used to perform an OR operation on the target test data and the historical test data to obtain the updated data.

[0169] The test data processing device of this embodiment performs an OR operation on the target test data and the historical test data through an OR operation unit. When there is a fault in the target test data, that is, the value of at least one data bit is 1 and the value of the corresponding data bit of the historical test data is 0, the value of the corresponding data bit of the updated data is set to 1, and the fault data bit information of the target test data is retained until the test is completed, thereby providing valid fault data for subsequent fault statistics.

[0170] In some embodiments, the first determination module includes a second comparison submodule, a first determination submodule, and a second determination submodule. The second comparison submodule is used to compare the historical test data corresponding to the same memory address with the initial test data according to the data bit; the first determination submodule is used to determine the number of faults of the historical test data based on the number of data bits with inconsistent data values; and the second determination submodule is used to determine the number of faults of the memory device under test based on the number of faults of each historical test data stored in the memory device under test.

[0171] The test data processing device of this embodiment compares the historical test data corresponding to the same memory address with the initial test data according to the data bit through the second comparison submodule to determine whether the historical test data fails during the test; determines the number of failures of the historical test data based on the number of data bits with inconsistent data values ​​through the first determination submodule, and obtains the cumulative number of failures of the historical test data during the test; determines the number of failures of the memory device under test based on the number of failures of each historical test data stored in the memory device under test through the second determination submodule, obtains the failure statistics of the batch of memory devices under test, and improves the efficiency of failure data statistics.

[0172] In some embodiments, the test data processing device further comprises a second determination module, the second determination module being used to determine whether a target data bit in the target test data is faulty based on a predetermined burst length, and to update the historical test data if the target data bit is faulty.

[0173] The test data processing device of this embodiment determines whether the target data bit in the target test data is faulty based on a predetermined burst length through the second determination module. It can determine whether the target test data is faulty when only a small amount of target test data is read, and there is no need to read all the target test data, thereby improving data throughput and test efficiency. When the target data bit is faulty, the historical test data is updated, the target test data is pre-processed, and non-faulty data is discarded, thereby saving subsequent data processing resources and improving the efficiency of faulty data processing.

[0174] In some of the embodiments, the storage device testing system also includes a test process module and a cache, and the test data processing device also includes a storage module and a back pressure module. The storage module is used to store the target test data and the corresponding memory address read during the test of the storage device under test into the cache; the back pressure module is used to send a back pressure signal to the test process module to control the test process module to suspend the test when the amount of data stored in the cache is greater than a pre-configured overflow waterline.

[0175] The test data processing device of this embodiment stores the target test data and the corresponding memory address read during the test of the tested storage device into a cache through a storage module, and adjusts the difference in data processing speed between the test flow module and the test data processing module; when the amount of data stored in the cache is greater than a pre-configured overflow watermark, a back pressure signal is sent to the test flow module through a back pressure module to control the test flow module to suspend the test, avoid cache overflow, adjust the serial processing speed of the target test data, and control the orderly execution of the storage device test process and the test data processing process.

[0176] In some embodiments, the present application further provides a storage device testing system, which includes the test data processing apparatus in the above embodiments, a storage device under test, and a memory for storing test data.

[0177] In the memory device test system of this embodiment, each time the memory device under test is tested, the test data processing device reads the target test data from the preset address of the memory device under test, and based on the target test data and the corresponding memory address obtained in advance, updates the historical test data stored in the memory address, and the number of updates of the historical test data corresponds to the number of tests of the memory device under test. The test data processing device automatically accumulates the number of failures in each test based on the historical test data after the test and the initial test data before the test, according to the accumulation of the number of tests, and does not need to count the failure conditions of the test data every time a test is completed, thereby solving the problem of long processing time and low test efficiency of memory device test data.

[0178] In addition, in combination with the test data processing method provided in the above embodiments, a readable storage medium may be provided in this embodiment to implement the test data processing method. The readable storage medium stores a program; when the program is executed by a processor, any test data processing method in the above embodiments is implemented.

[0179] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0180] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0181] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0182] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0183] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A test data processing method, characterized in that: The method is applied to a memory device test system, the memory device test system comprising a memory device to be tested and a memory for storing test data, and the method comprises: Based on the target test data and the corresponding memory address acquired in advance, the historical test data stored in the memory address is updated, and the target test data is stored in the preset address of the memory device under test based on the historical test data, and is obtained by the memory device under test completing a test and reading the preset address; Repeating the updating process of the historical test data based on a predetermined number of tests; The number of failures of the tested memory device is determined based on the historical test data after the test and the initial test data before the test.

2. The method according to claim 1, characterized in that The updating of the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance includes: Based on the memory address, reading corresponding historical test data from the memory; comparing the target test data with the historical test data based on a predetermined storage mode; When the target test data is inconsistent with the historical test data, acquiring update data based on the target test data and the historical test data; Based on the memory address, the update data is written into the memory.

3. The method according to claim 2, characterized in that The storage mode includes a flag mode, and the comparing the target test data with the historical test data based on the predetermined storage mode includes: Acquire the marker data corresponding to the target test data; Performing an AND operation on the marker data and the target test data, and then performing an OR operation with the historical test data to obtain marker test data; The signature test data is compared to the historical test data.

4. The method according to claim 2, characterized in that: The storage mode includes a mask mode, and the comparing the target test data with the historical test data based on the predetermined storage mode includes: Obtaining mask data corresponding to the historical test data; Performing an AND operation on the inverted value of the mask data and the target test data, and then performing an OR operation with the historical test data to obtain mask test data; The masked test data is compared with the historical test data.

5. The method according to claim 2, characterized in that: When the target test data is inconsistent with the historical test data, acquiring update data based on the target test data and the historical test data includes: An OR operation is performed on the target test data and the historical test data to obtain the update data.

6. The method according to claim 1, characterized in that The determining the number of failures of the tested memory device based on the historical test data after the test and the initial test data before the test includes: Compare the historical test data corresponding to the same memory address with the initial test data by data bit; Determining the number of failures in the historical test data based on the number of data bits with inconsistent data values; The number of failures of the memory device under test is determined based on the number of failures of each historical test data stored in the memory device under test.

7. The method according to claim 1, characterized in that Before updating the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance, the method further includes: Based on a predetermined burst length, determining whether a target data bit in the target test data is faulty; In the event of a failure of the target data bit, the historical test data stored in the memory address is updated based on the target test data and the memory address.

8. The method according to claim 1, characterized in that The memory device test system further includes a test flow module and a cache. Before updating the historical test data stored in the memory address based on the target test data and the corresponding memory address obtained in advance, the method further includes: storing the target test data and the corresponding memory address read during the test of the memory device under test into the cache; When the amount of data stored in the cache is greater than a pre-configured overflow watermark, a back pressure signal is sent to the test flow module to control the test flow module to suspend testing.

9. A test data processing device, characterized in that: The device is applied to a memory device test system, the memory device test system includes a memory device to be tested and a memory for storing test data, and the device includes: An update module, configured to update historical test data stored in the memory address based on target test data and a corresponding memory address acquired in advance, wherein after the target test data is stored in a preset address of the memory device under test based on the historical test data, the memory device under test completes a test and reads the preset address to obtain; A testing module, used for repeating the updating process of the historical test data based on a predetermined number of tests; The first determination module is used to determine the number of failures of the tested storage device based on the historical test data after the test and the initial test data before the test.

10. The test data processing device according to claim 9, characterized in that: The update module includes: A reading submodule, used for reading corresponding historical test data from the memory based on the memory address; a first comparison submodule, configured to compare the target test data with the historical test data based on a predetermined storage mode; an acquisition submodule, configured to acquire update data based on the target test data and the historical test data when the target test data is inconsistent with the historical test data; A writing submodule is used to write the update data into the memory based on the memory address.

11. The test data processing device according to claim 10, characterized in that: The storage mode includes a flag mode, and the first comparison submodule includes: A first acquisition unit, used to acquire the mark data corresponding to the target test data; A first logic operation unit, configured to perform an AND operation on the flag data and the target test data, and then perform an OR operation on the flag data and the target test data to obtain the flag test data; The first comparing unit is used to compare the marker test data with the historical test data.

12. The test data processing device according to claim 10, characterized in that: The storage mode includes a mask mode, and the first comparison submodule includes: A second acquisition unit, used to acquire mask data corresponding to the historical test data; A second logic operation unit is used to perform an AND operation on the inverted value of the mask data and the target test data, and then perform an OR operation on the inverted value of the mask data and the historical test data to obtain mask test data; The second comparing unit is used to compare the mask test data with the historical test data.

13. The test data processing device according to claim 9, characterized in that: The storage device testing system further includes a test flow module and a cache, and the test data processing device further includes: A storage module, used for storing the target test data and the corresponding memory address read during the test of the memory device under test into the cache; The back pressure module is used to send a back pressure signal to the test flow module to control the test flow module to suspend the test when the amount of data stored in the cache is greater than a pre-configured overflow watermark.

14. A memory device testing system, characterized in that: The memory device test system comprises the test data processing device as claimed in any one of claims 9 to 13, a memory device to be tested, and a memory for storing test data.

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