A high integration semiconductor package structure and a manufacturing method thereof

Abstract

The application relates to a high-integration semiconductor packaging structure and a manufacturing method thereof. The structure comprises a substrate, a high-performance power supply and heat dissipation module containing micro flow channels, a plastic packaging layer, a rewiring layer, a chip module including a first chip module, a second chip module and a third chip module, a bottom filling glue, a micro flow channel inlet and a micro flow channel outlet interconnected with the micro flow channels, and solder balls. The high-integration semiconductor packaging structure provided by the application integrates the high-performance power supply and heat dissipation module containing the micro flow channels in the cavity of the substrate, the chip module is rapidly heat-dissipated through the bumps, the rewiring layer and the micro flow channels, and the heat dissipation capacity is significantly improved; the gate drive layer and the power transistor layer are vertically interconnected through the through silicon vias and interconnected with the substrate, and the power supply efficiency is significantly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a high-integration semiconductor packaging structure and a manufacturing method thereof. BACKGROUND

[0002] Applications such as artificial intelligence and high-performance computing have increasing demands for bandwidth, storage, high-power heat dissipation, large power supply and capacitor decoupling. Currently, 2.5D packaging based on a conversion board is often used for high-performance chip and HBM (High Bandwidth Memory) integration. However, as the number of integrated HBM increases and the performance of chips gradually improves, the integration of high-performance chips and HBM will be limited by the area of the conversion board, the D2D (Die to Die) high-speed interconnection, the power supply and the heat dissipation capacity. Among them, high-performance chips often use DRAM stacked directly on the top of a high-power ASIC, so the demand for bottom heat dissipation increases, and the commonly used heat dissipation cover, heat sink and air cooling heat dissipation methods cannot meet the high heat dissipation capacity and efficiency requirements of high-performance chips. In addition, to meet the bandwidth and storage requirements of high-performance chips, more HBM needs to be connected with D2D high-speed interconnection, and the demand for large power supply and power decoupling needs to be met. SUMMARY

[0003] To solve some or all of the problems in the prior art, the present application provides a high-integration semiconductor packaging structure, which comprises:

[0004] a substrate, the substrate comprising a substrate bottom, a substrate middle and a substrate top, a plurality of cavities being arranged in the substrate, the side of the plurality of cavities being the substrate middle and the substrate top, and the lower surface of the plurality of cavities being the substrate middle;

[0005] a high-performance power supply and heat dissipation module and a deep trench capacitor module arranged in the plurality of cavities, the high-performance power supply and heat dissipation module comprising a micro-channel;

[0006] a plastic encapsulation layer, the plastic encapsulation layer encapsulating and covering the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module;

[0007] a redistribution layer, the redistribution layer being arranged on the upper surface of the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module, and the redistribution layer being electrically connected with the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module;

[0008] a chip module, the chip module comprising a first chip module, a second chip module and a third chip module, and being arranged on the upper surface of the redistribution layer, the chip module being electrically connected with the redistribution layer through bumps;

[0009] underfill glue, filling the bottom of the chip module;

[0010] microfluidic channel inlet and microfluidic channel outlet, arranged in the re-distribution layer, the microfluidic channel inlet and the microfluidic channel outlet being interconnected with the microfluidic channel, realizing inflow and outflow of the cooling liquid;

[0011] solder balls, arranged on the lower surface of the substrate bottom.

[0012] Further, the substrate bottom comprises a first interconnection circuit layer; and / or

[0013] the middle part of the substrate comprises a second interconnection circuit layer; and / or

[0014] the top part of the substrate comprises a third interconnection circuit layer.

[0015] Further, the high-performance power supply heat dissipation module comprises:

[0016] a power transistor layer;

[0017] a bonding layer, arranged on the upper surface of the power transistor layer;

[0018] a gate drive layer, arranged on the upper surface of the bonding layer, the gate drive layer being bonded with the power transistor layer through the bonding layer;

[0019] a fourth interconnection circuit layer, arranged on the upper surface of the gate drive layer;

[0020] a through-silicon via, penetrating through the high-performance power supply heat dissipation module;

[0021] a microfluidic channel, arranged in the power transistor layer, the gate drive layer and the bonding layer.

[0022] Further, the first chip module comprises a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or

[0023] the second chip module comprises a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or

[0024] the third chip module comprises a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

[0025] The application also provides a manufacturing method of the high-integration semiconductor packaging structure, comprising the following steps:

[0026] a temporary bonding layer is made on the upper surface of the carrier.

[0027] A substrate is arranged on the upper surface of the temporary bonding layer, the substrate comprising a substrate bottom, a substrate middle and a substrate top, and a plurality of cavities are arranged in the substrate;

[0028] A high-performance power supply and heat dissipation module and a deep trench capacitor module are arranged in the plurality of cavities, the high-performance power supply and heat dissipation module comprising micro-channels;

[0029] A plastic encapsulation layer is made, the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module are encapsulated and covered, the plastic encapsulation layer is thinned, and the interconnection pads on the substrate top, the interconnection pads on the high-performance power supply and heat dissipation module top and the interconnection pads on the deep trench capacitor module top are exposed;

[0030] A redistribution layer is made on the upper surfaces of the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module;

[0031] Chip modules are arranged on the upper surface of the redistribution layer, the chip modules comprising a first chip module, a second chip module and a third chip module, and the chip modules are electrically connected to the redistribution layer through bumps;

[0032] Bottom filling glue is filled in the bottoms of the chip modules;

[0033] The redistribution layer is perforated at positions corresponding to the micro-channel inlets and outlets, forming micro-channel inlets and outlets;

[0034] The carrier sheet is removed, the substrate is cut, and solder balls are arranged on the lower surface of the substrate bottom, forming a high-integration semiconductor packaging structure.

[0035] Further, the carrier sheet is a glass or silicon sheet or a metal plate; and / or

[0036] The temporary bonding layer is silicon oxide or silicon nitride or silicon oxynitride or organic bonding glue.

[0037] Further, the plastic encapsulation is injection molding; and / or

[0038] The material of the plastic encapsulation layer is epoxy resin.

[0039] Further, the redistribution layer comprises a plurality of dielectric layers and a plurality of metal layers.

[0040] Further, the first chip module comprises a plurality of identical chips, a plurality of chips of the same type or a plurality of chips of different types; and / or

[0041] The second chip module comprises a plurality of identical chips, a plurality of chips of the same type or a plurality of chips of different types; and / or

[0042] The third chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

[0043] Further, the slide is removed using mechanical separation or thermal sliding or laser separation.

[0044] The technical solution provided by the present invention has the following beneficial effects:

[0045] 1. The highly integrated semiconductor package structure provided by this invention integrates a high-performance power supply and heat dissipation module containing microchannels within a substrate cavity. The chip module rapidly dissipates heat through bumps, a redistribution layer, and the microchannels, significantly improving heat dissipation capabilities. Heat is dissipated from the bottom of the chip module, without interfering with its normal operation.

[0046] 2. The highly integrated semiconductor packaging structure provided by the present invention integrates a high-performance power supply and heat dissipation module in the substrate cavity. The gate drive layer and the power transistor layer are vertically interconnected through silicon vias and interconnected with the substrate, which can significantly improve the power supply efficiency and reduce power loss.

[0047] 3. The highly integrated semiconductor packaging structure provided by the present invention integrates a deep trench capacitor (DTC) module or an inductor module in the substrate cavity, which can significantly improve the power decoupling performance and power integrity performance.

[0048] 4. The highly integrated semiconductor packaging structure provided by the present invention arranges an interconnection line layer on top of a high-performance power supply and heat dissipation module. The chip modules can achieve fast D2D interconnection through bumps, redistribution layers and interconnection line layers, meeting the bandwidth and storage requirements of high-performance chips.

[0049] 5. The highly integrated semiconductor packaging structure provided by the present invention adopts a large-size cavity substrate instead of an adapter plate, which can break through the size limitation of the adapter plate, accommodate more chip modules, and significantly improve bandwidth and storage capacity.

[0050] 6. The highly integrated semiconductor packaging structure provided by the present invention embeds a high-performance power supply and heat dissipation module in the substrate cavity, and the substrate warping is smaller than that of the original substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding components will be represented by the same or similar reference numerals.

[0052] Figure 1 a schematic diagram of a high-density semiconductor package structure according to an embodiment of the present application is shown;

[0053] Figure 2 a schematic diagram of a high-performance power supply and heat dissipation module according to an embodiment of the present application is shown;

[0054] Figure 3 a flowchart of a manufacturing method of a high-density semiconductor package structure according to an embodiment of the present application is shown; and

[0055] Figures 4a-4i a cross-sectional view of a process of forming a high-density semiconductor package structure according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0056] In the following description, reference is made to specific embodiments of the application. Those skilled in the art will recognize that the application can be practiced with

[0057] In this specification, reference can be made to "one embodiment", or "the embodiment", meaning that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrases "in one embodiment" or "in the embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0058] In this specification, unless specifically stated otherwise, "disposed on", "disposed above", and "disposed over" do not exclude the presence of an intermediate element between the elements being described. Furthermore, "disposed on or above" merely indicates a relative position of two components, and can be converted to "disposed below or under" in some cases, such as when the product is turned upside down, and vice versa.

[0059] In this specification, unless specifically stated otherwise, "upper surface", "lower surface", and "side surface" are used to describe surfaces of the same component.

[0060] In this specification, unless specifically stated otherwise, the indefinite article "a" or "an" does not exclude a plurality of elements, and the indefinite article "a" or "an" means one or more.

[0061] It should be noted that the embodiments of the present application describe the method steps in a specific order, but this is only for the purpose of describing the specific embodiments, and does not limit the order of the steps. On the contrary, in different embodiments of the present application, the order of the steps can be adjusted according to the actual needs of the adjustment.

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0063] High-performance processing chips have high requirements for bandwidth, storage, large power dissipation, large power supply and capacitor decoupling, and conventional 2.5D packaging based on Si adapter plates are limited by the area of the adapter plate and the heat dissipation. The present application provides a high-integration semiconductor packaging structure, which integrates a high-performance power supply and heat dissipation module containing a micro-channel in a cavity of a substrate, and the chip module is rapidly cooled through bumps, a rewiring layer and a micro-channel, significantly improving the heat dissipation capacity; the gate drive layer and the power transistor layer are vertically interconnected through a through silicon via, and are interconnected with the substrate, significantly improving the power supply efficiency and reducing the power loss; a deep trench capacitor module or an inductor module is integrated in the cavity of the substrate, which can significantly improve the power decoupling performance and the power integrity performance; an interconnection line layer is arranged on the top of the high-performance power supply and heat dissipation module, and the chip module can realize rapid D2D interconnection through bumps, a rewiring layer and an interconnection line layer, meeting the requirements of high-performance chips for bandwidth and storage.

[0064] Figure 1 A schematic diagram of a high-integration semiconductor packaging structure of an embodiment of the present application is shown. The high-integration semiconductor packaging structure includes a substrate, a high-performance power supply and heat dissipation module, a deep trench capacitor module, a plastic encapsulation layer, a rewiring layer, a chip module, an underfilling glue, a micro-channel inlet, a micro-channel outlet and a solder ball.

[0065] As shown in Figure 1 The substrate includes a substrate bottom 103, a substrate middle 104 and a substrate top 105, the substrate is drilled to form a plurality of cavities, the side surfaces of the plurality of cavities are the substrate middle and the substrate top, and the lower surfaces of the plurality of cavities are the substrate middle, that is, the substrate middle is partially drilled and not drilled through. In an embodiment of the present application, the substrate bottom 103 comprises a first interconnection line layer; the substrate middle 104 comprises a second interconnection line layer; the substrate top 105 comprises a third interconnection line layer, and the substrate top 105 further comprises an interconnection pad, the interconnection pad of the substrate top 105 is electrically connected with the rewiring layer; the first interconnection line layer, the second interconnection line layer and the third interconnection line layer are electrically connected.

[0066] As shown in Figure 1 The high-performance power supply and heat dissipation module 106 is arranged in the cavity of the substrate. Figure 2A schematic diagram of a high performance power supply and heat dissipation module is shown. As Figure 2 shown, the high performance power supply and heat dissipation module 106 includes a through silicon via 1061, a microfluidic channel 1062, a fourth interconnection circuit layer 1063, a gate driver layer 1064, a bonding layer 1065, and a power transistor layer 1066. The through silicon via 1061 penetrates through the high performance power supply and heat dissipation module. The microfluidic channel 1062 is arranged in the power transistor layer 1066, the gate driver layer 1064, and the bonding layer 1065. The fourth interconnection circuit layer 1063 is arranged on the upper surface of the gate driver layer 1064, and the top of the fourth interconnection circuit layer 1063 is provided with an interconnection pad. The bonding layer 1065 is arranged on the upper surface of the power transistor layer 1066, the power transistor is Power Transistors, the gate driver is Gate Drivers, the gate driver layer 1064 is arranged on the upper surface of the bonding layer 1065, and the gate driver layer 1064 is bonded to the power transistor layer 1066 through the bonding layer 1065. The bonding layer 1065 is preferably silicon oxide or silicon nitride or silicon oxynitride, and the bonding is preferably hybrid bonding. The gate driver layer 1064 and the power transistor layer 1066 are vertically interconnected through the through silicon via 1061 and interconnected with the substrate, significantly improving power supply efficiency and reducing power loss.

[0067] As Figure 1 shown, a plurality of deep trench capacitor modules 107 are arranged in a plurality of cavities of the substrate. In an embodiment of the present application, the deep trench capacitor module 107 can also be an inductor module. Integrating the deep trench capacitor module or the inductor module in the substrate cavity can significantly improve the power decoupling performance and the power integrity performance.

[0068] As Figure 1 shown, a plastic encapsulation layer 108 encapsulates and covers the substrate, the high performance power supply and heat dissipation module, and the deep trench capacitor module. In an embodiment of the present application, the plastic encapsulation is injection molding, and the material of the plastic encapsulation layer 108 is epoxy resin.

[0069] As Figure 1 shown, a redistribution layer 109 is arranged on the upper surface of the substrate, the high performance power supply and heat dissipation module, and the deep trench capacitor module. In an embodiment of the present application, the redistribution layer 109 includes a plurality of dielectric layers and a plurality of metal layers. As Figure 1 shown, the redistribution layer 109 does not provide metal wiring at the positions of the microfluidic channel inlet and outlet, the redistribution layer at the positions of the microfluidic channel inlet and outlet is etched to form a microfluidic channel inlet 115 and a microfluidic channel outlet 116. The microfluidic channel inlet 115 and the microfluidic channel outlet 116 are interconnected with the microfluidic channel to realize the inflow and outflow of the cooling liquid. Through the flow of the cooling liquid in the microfluidic channel, the chip module is rapidly cooled. The redistribution layer is electrically connected with the substrate, the high performance power supply and heat dissipation module, and the deep trench capacitor module.

[0070] As shown in Figure 1 , the chip modules are arranged on the upper surface of the redistribution layer 109. The chip modules include a first chip module 110, a second chip module 111 and a third chip module 112, and the chip modules are electrically connected with the redistribution layer 109 through bumps 113. The underfill adhesive 114 fills the bottom of the chip modules. In an embodiment of the present application, the first chip module 110 contains a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; the second chip module 111 contains a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and the third chip module 112 contains a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types. In an embodiment of the present application, the chips can be logic chips such as CPU, DSP, GPU, FPGA, etc., or memory chips such as DRAM, Flash, HBM, etc., or other types of chips such as SOC, or sensors such as MEMS sensors, etc. In an embodiment of the present application, the first chip module 110 and the second chip module 111 are preferably HBM memory chips, and the third chip module 112 is preferably a stacked chip formed by hybrid bonding of a CPU, a DSP, a GPU, an FPGA, etc. and a DRAM, and the third chip module 112 can also be other high-power chips or chips with high bandwidth and storage requirements. In an embodiment of the present application, the material of the bumps 113 can be pure metals such as Au, Cu, Sn, In, etc., or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. In an embodiment of the present application, the main material of the underfill adhesive 114 is preferably an epoxy resin matrix and fillers such as SiO2, Al2O3, etc.

[0071] In an embodiment of the present application, the upper surface of the redistribution layer 109 also includes a bump structure, and the material of the bump structure can be pure metals such as Au, Cu, Sn, In, etc., or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. The size and pitch of the bumps for Die to Die interconnection at the bottom of the chip modules are smaller than those of the bump structure for interconnection with the upper surface of the redistribution layer.

[0072] As shown in Figure 1 , the solder balls 117 are arranged on the lower surface of the substrate bottom 103 and are electrically connected with the substrate bottom 103. In an embodiment of the present application, the material of the solder balls 117 can be a single layer of metal such as copper, nickel, tin, silver or other metals, or a composite metal.

[0073] Figure 3A flow chart of a method for manufacturing a high-density semiconductor package structure according to an embodiment of the present application is shown. Figures 4a-4i A cross-sectional view of a process for forming a high-density semiconductor package structure according to an embodiment of the present application is shown.

[0074] A method for manufacturing a high-density semiconductor package structure according to an embodiment of the present application is described below with reference to the accompanying drawings. Figure 3 and Figures 4a-4i A method for manufacturing a high-density semiconductor package structure according to an embodiment of the present application is described below with reference to the accompanying drawings.

[0075] First, a temporary bonding layer 102 is made on the upper surface of a carrier wafer 101, as shown in FIG. 1. In an embodiment of the present application, the carrier wafer 101 can be a glass wafer or a silicon wafer or a metal plate. In an embodiment of the present application, the temporary bonding layer 102 can be silicon oxide or silicon nitride or silicon oxynitride or an organic bonding glue, which can be TMAT, BSI, 3M, and DuPont bonding glue. Figure 4a

[0076] Next, a substrate is arranged on the upper surface of the temporary bonding layer 102, as shown in FIG. 2. The substrate is formed by digging holes to form a plurality of cavities, the side surfaces of the plurality of cavities being the middle and top portions of the substrate, and the lower surfaces of the plurality of cavities being the middle portion of the substrate, i.e., the middle portion of the substrate is partially dug, but not completely dug through. In an embodiment of the present application, the bottom portion 103 of the substrate contains a first interconnection layer; the middle portion 104 of the substrate contains a second interconnection layer; the top portion 105 of the substrate contains a third interconnection layer, and the top portion 105 of the substrate further contains an interconnection pad, which is electrically connected to the redistribution layer; the first, second, and third interconnection layers are electrically connected. Figure 4b

[0077] Next, a high-performance power supply and heat dissipation module 106 and a deep trench capacitor module 107 are arranged in the plurality of cavities, as shown in FIG. 3. The high-performance power supply and heat dissipation module 106 contains micro-channels. In an embodiment of the present application, the deep trench capacitor module 107 can also be an inductor module. Figure 4c

[0078] Next, a plastic encapsulation layer 108 is made, encapsulating and covering the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module, and the plastic encapsulation layer is thinned to expose the interconnection pad of the top portion of the substrate, the interconnection pad of the top portion of the high-performance power supply and heat dissipation module, and the interconnection pad of the top portion of the deep trench capacitor module, as shown in FIG. 4. In an embodiment of the present application, the plastic encapsulation is injection molding; and the material of the plastic encapsulation layer 108 is epoxy resin. Figure 4d

[0079] ​​​​Next, a redistribution layer 109 is made on the upper surface of the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module, as shown in Figure 4e In an embodiment of the present application, the redistribution layer 109 includes multiple dielectric layers and multiple metal layers. In an embodiment of the present application, the upper surface of the redistribution layer 109 also includes bump structures, which can be made of pure metals such as Au, Cu, Sn, In, etc., or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. The redistribution layer is electrically connected to the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module.

[0080] Next, chip modules including a first chip module 110, a second chip module 111, and a third chip module 112 are arranged on the upper surface of the redistribution layer, as shown in Figure 4f The chip modules are electrically connected to the redistribution layer 109 through bumps 113. In an embodiment of the present application, the first chip module 110 contains multiple identical chips, multiple chips of the same type, or multiple chips of different types; the second chip module 111 contains multiple identical chips, multiple chips of the same type, or multiple chips of different types; and the third chip module 112 contains multiple identical chips, multiple chips of the same type, or multiple chips of different types. In an embodiment of the present application, the chips can be logic chips such as CPUs, DSPs, GPUs, FPGAs, etc., memory chips such as DRAMs, Flash, HBMs, etc., or other types of chips such as SOCs or sensors (such as MEMS sensors, etc.). In an embodiment of the present application, the first chip module 110 and the second chip module 111 are preferably HBM memory chips, and the third chip module 112 is preferably a stacked chip formed by hybrid bonding of a CPU, a DSP, a GPU, an FPGA, etc. and a DRAM, and can also be other high-power chips or chips with high bandwidth and storage requirements. In an embodiment of the present application, the bumps 113 can be made of pure metals such as Au, Cu, Sn, In, etc., or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc.

[0081] Next, a bottom filling adhesive 114 is filled at the bottom of the chip modules, as shown in Figure 4g In an embodiment of the present application, the main material of the bottom filling adhesive 114 is preferably an epoxy resin matrix and fillers such as SiO2, Al2O3, etc.

[0082] Next, the redistribution layer is punched at positions corresponding to the inlet and outlet of the microfluidic channel to form a microfluidic channel inlet 115 and a microfluidic channel outlet 116, as shown in Figure 4hThe microfluidic channel inlet 115 and the microfluidic channel outlet 116 are interconnected with the microfluidic channel to realize the inflow and outflow of the cooling liquid. Through the flow of the cooling liquid in the microfluidic channel, the chip module is rapidly cooled.

[0083] Finally, the carrier is removed, the substrate is cut, and the solder balls 117 are arranged on the lower surface of the bottom of the substrate to form a high-integration semiconductor packaging structure, as shown in Figure 4i In an embodiment of the present application, the carrier is removed by mechanical separation or thermal slip or laser separation. The solder balls 117 are electrically connected with the bottom 103 of the substrate. In an embodiment of the present application, the material of the solder balls 117 can be a single layer of metal such as copper, nickel, tin, silver or other metals, or a composite metal.

[0084] The high-integration semiconductor packaging structure provided by the present application integrates a high-performance power supply and heat dissipation module containing a microfluidic channel in the cavity of the substrate. The chip module is rapidly cooled through the bumps, the redistribution layer and the microfluidic channel, which significantly improves the heat dissipation capacity. The gate drive layer and the power transistor layer are vertically interconnected through the through-silicon via and are interconnected with the substrate, which significantly improves the power supply efficiency and reduces the power loss. The deep trench capacitor module or the inductor module is integrated in the cavity of the substrate, which can significantly improve the power decoupling performance and the power integrity performance. The interconnection line layer is arranged on the top of the high-performance power supply and heat dissipation module. The chip module can be rapidly interconnected through D2D by the bumps, the redistribution layer and the interconnection line layer, which meets the demand of high-performance chips for bandwidth and storage.

[0085] Although the embodiments of the present application are described above, it should be understood that they are presented only as examples and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made without departing from the spirit and scope of the present application. Therefore, the width and scope of the present application disclosed herein should not be limited by the above disclosed exemplary embodiments, but should only be defined according to the appended claims and their equivalent replacements.

Claims

1. A highly integrated semiconductor packaging structure, characterized in that: include: A substrate, the substrate comprising a substrate bottom, a substrate middle, and a substrate top, wherein a plurality of cavities are arranged in the substrate, side surfaces of the plurality of cavities are the substrate middle and the substrate top, and lower surfaces of the plurality of cavities are the substrate middle; A high-performance power supply and heat dissipation module and a deep trench capacitor module are arranged in the plurality of cavities; a plastic encapsulation layer, the plastic encapsulation layer encapsulating and covering the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module; a redistribution layer, the redistribution layer being arranged on the upper surface of the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module, the redistribution layer being electrically connected to the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module; Chip modules, including a first chip module, a second chip module, and a third chip module, are arranged on the upper surface of the redistribution layer, and the chip modules are electrically connected to the redistribution layer through bumps; Bottom filling glue, filling the bottom of the chip module; A microchannel inlet and a microchannel outlet are arranged in the redistribution layer, and the microchannel inlet and the microchannel outlet are interconnected with the microchannel to realize the inflow and outflow of the cooling liquid; as well as Solder balls are arranged on the lower surface of the bottom of the substrate; The high-performance power supply and heat dissipation module includes: Power transistor layer; a bonding layer, the bonding layer being arranged on an upper surface of the power transistor layer; a gate drive layer, the gate drive layer being arranged on an upper surface of the bonding layer, the gate drive layer being bonded to the power transistor layer through the bonding layer; a fourth interconnection circuit layer, the fourth interconnection circuit layer being arranged on an upper surface of the gate drive layer; Through silicon vias (TSVs), the TSVs passing through the high-performance power supply and heat dissipation module; A microchannel is arranged in the power transistor layer, the gate drive layer and the bonding layer.

2. The highly integrated semiconductor package structure according to claim 1, wherein: The bottom of the substrate comprises a first interconnection circuit layer; and / or The middle portion of the substrate comprises a second interconnection circuit layer; and / or The top of the substrate includes a third interconnection line layer.

3. The highly integrated semiconductor package structure according to claim 1, wherein: The first chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The second chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The third chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

4. A method for manufacturing a highly integrated semiconductor packaging structure, characterized in that: The steps include: A temporary bonding layer is formed on the upper surface of the slide; Arranging a substrate on the upper surface of the temporary bonding layer, wherein the substrate includes a substrate bottom, a substrate middle, and a substrate top, and a plurality of cavities are arranged in the substrate; A high-performance power supply and heat dissipation module and a deep trench capacitor module are arranged in the plurality of cavities, wherein the high-performance power supply and heat dissipation module includes a microchannel; Making a plastic encapsulation layer, encapsulating and covering the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module, and thinning the plastic encapsulation layer to expose the interconnection pads on the top of the substrate, the interconnection pads on the top of the high-performance power supply and heat dissipation module, and the interconnection pads on the top of the deep trench capacitor module; Fabricating a redistribution layer on the upper surfaces of the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module; Arranging chip modules on the upper surface of the redistribution layer, wherein the chip modules include a first chip module, a second chip module, and a third chip module, and the chip modules are electrically connected to the redistribution layer through bumps; Filling the bottom of the chip module with bottom filling glue; Punching holes at positions of the redistribution layer corresponding to the inlet and outlet of the microfluidic channel to form the inlet and outlet of the microfluidic channel; The carrier wafer is removed, the substrate is cut, and solder balls are arranged on the lower surface of the bottom of the substrate to form a highly integrated semiconductor packaging structure.

5. The method for manufacturing a highly integrated semiconductor package structure according to claim 4, wherein: The carrier is a glass, silicon wafer or metal plate; and / or The temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride, or organic bonding glue.

6. The method for manufacturing a highly integrated semiconductor package structure according to claim 4, wherein: The plastic encapsulation is injection molding; and / or The material of the plastic sealing layer is epoxy resin.

7. The method for manufacturing a highly integrated semiconductor package structure according to claim 4, wherein: The redistribution layer includes multiple dielectric layers and multiple metal layers.

8. The method for manufacturing a highly integrated semiconductor package structure according to claim 4, wherein: The first chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The second chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The third chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

9. The method for manufacturing a highly integrated semiconductor package structure according to claim 4, wherein: The slide is removed using mechanical separation or thermal sliding or laser separation.

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