High frequency TSV silicon interposer and design method thereof

Abstract

The application provides a high-frequency TSV silicon adapter plate and a design method thereof, wherein two ends of a ground wire through silicon via and a ground wire redundant through silicon via are electrically coupled with a ground pad respectively; two ends of a signal wire through silicon via and a signal wire redundant through silicon via are electrically coupled with a signal wire pad respectively; the ground wire through silicon via and the ground wire redundant through silicon via are first through silicon vias, the signal wire through silicon via and the signal wire redundant through silicon via are second through silicon vias, and a preset distance exists between the first through silicon vias and the second through silicon vias. In the application, the first through silicon vias and the second through silicon vias in the high-frequency TSV silicon adapter plate are quasi-coaxially distributed, the distance between the first through silicon vias and the second through silicon vias is adjusted to reduce the impedance discontinuity problem between the through silicon vias and transmission lines in the high-frequency TSV silicon adapter plate, and the radio frequency performance of the high-frequency TSV silicon adapter plate is improved. Meanwhile, the redundant through silicon via which is only used in the field of digital signal transmission to improve the fault tolerance rate is designed in the silicon adapter plate for the first time, the signal through silicon via and the multiple redundant through silicon vias share the pad, the radio frequency performance of the silicon adapter plate is optimized, and the process reliability is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a high-frequency TSV silicon adapter board and its design method. Background Technology

[0002] High-frequency impedance discontinuities in integrated circuits lead to reflection losses, causing some signals to be reflected while others are distorted and continue propagating. This significantly impacts the RF transmission performance of the integrated circuit's signal path. As circuit integration increases, the wiring density of the transmission path also increases, and the number of layers crossed by traces also increases. This results in insufficient hardware space for optimization and makes it impossible to effectively improve reflection losses using traditional methods. Especially at the chip-package and package-board interfaces, the capacitive parasitic effects generated by vias, traces, pads, and solder balls are significant, leading to impedance discontinuities and impedance resonances.

[0003] In the existing PCB (Printed Circuit Board) field, impedance control can generally be achieved through anti-pad design. However, anti-pad design is suitable for multi-layer metal structures, where a large copper area is laid outside the metal layers to carve out the anti-pad area to achieve impedance control. But silicon interposers only have two metal layers, one on each side, and through-silicon vias (TSVs) pass through the intermediate dielectric silicon to interconnect signals between the two metal layers. Therefore, when designing anti-pads by laying copper outside the metal layers of a silicon interposer, only a reference ground structure can be formed on both metal layers. It is impossible to form a closed ground cavity structure around the TSVs (Through Silicon Vias) of the silicon interposer. This results in a serious impact on the RF performance of the silicon interposer when designing anti-pads. Meanwhile, during the manufacturing process, interconnect failures may occur due to misalignment of the pads or insufficient filling of conductive material. Redundant through-silicon via (TSV) designs can be used to reduce the risk of interconnect failures. However, when redundant TSVs used in the digital field are directly designed into silicon interposers, the RF impedance characteristics of the silicon interposers are easily deteriorated. Therefore, those skilled in the art generally do not design redundant TSVs in silicon interposers.

[0004] Therefore, high-frequency TSV silicon adapter boards cannot solve the impedance discontinuity problem at the connection between the TSV and the transmission line by using anti-pads. At the same time, the use of redundant TSVs designed to improve signal fault tolerance can easily degrade the RF impedance, resulting in a serious impact on the RF transmission performance of high-frequency TSV silicon adapter boards in RF application scenarios. This is more obvious in highly integrated high-frequency TSV silicon adapter boards, making it difficult to use redundant TSVs to improve fault tolerance in highly integrated high-frequency TSV silicon adapter boards, resulting in poor process reliability of high-frequency TSV silicon adapter boards.

[0005] Therefore, there is an urgent need for a structure or method that can solve the impedance discontinuity problem in high-frequency TSV silicon interposers, achieve impedance optimization, and improve the reliability of through-silicon via (TSV) manufacturing processes.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of this invention is to provide a high-frequency TSV silicon adapter board and its design method, which solves the problems of impedance discontinuity and low reliability of silicon via process in the prior art.

[0008] To achieve the above objectives, the present invention provides a high-frequency TSV silicon adapter board, the high-frequency TSV silicon adapter board comprising: ground silicon via, signal silicon via, redundant ground silicon via and / or redundant signal silicon via, ground transmission line, signal transmission line, ground pad and signal pad;

[0009] Each of the two ends of the ground silicon via is electrically coupled to one of the ground pads; each of the two ends of the signal silicon via is electrically coupled to one of the signal pads.

[0010] When the redundant silicon vias exist, each end of the redundant silicon via is electrically coupled to the grounding pad where the redundant silicon via is located; each grounding pad where the redundant silicon via is located includes n redundant silicon vias, where n is an integer greater than or equal to 0;

[0011] When the redundant signal line vias exist, each end of the redundant signal line via is electrically coupled to the signal line pad where the signal line via is located; each signal line pad where the signal line via is located includes m redundant signal line vias, where m is an integer greater than or equal to 0;

[0012] The ground wire through-silicon via and the redundant ground wire through-silicon via are both first through-silicon vias, and the signal line through-silicon via and the redundant signal line through-silicon via are both second through-silicon vias. The first through-silicon vias and the second through-silicon vias are both perpendicular to the first plane, and there is a preset distance between each first through-silicon via and each second through-silicon via.

[0013] The grounding pad is electrically connected to the grounding transmission line, and the signal line pad is electrically connected to the signal transmission line.

[0014] Optionally, m and n may not both be 0.

[0015] Optionally, the grounding pad where one of the grounding vias is located includes one redundant grounding via, and the signal pad where one of the signal vias is located includes one redundant signal via.

[0016] Optionally, the projections of each of the first through-silicon vias onto the first plane are all on the first circle, and the projections of each of the second through-silicon vias onto the first plane are all on the second circle, wherein the first circle and the second circle are concentric circles.

[0017] Optionally, the line connecting each of the first through-silicon vias (TSVs) to the nearest second TSV coincides radially with the first circle.

[0018] Optionally, the diameter of each first through-silicon via is 5 micrometers to 20 micrometers, and the thickness of each first through-silicon via is 25 micrometers to 200 micrometers.

[0019] Optionally, the diameter of each second through-silicon via is 5 micrometers to 20 micrometers, and the thickness of each second through-silicon via is 25 micrometers to 200 micrometers.

[0020] Optionally, the projection of the first through-silicon via onto the first plane is located within the projection of the ground pad onto the first plane.

[0021] Optionally, the projection of the second through-silicon via onto the first plane lies within the projection of the signal line pad onto the first plane.

[0022] This invention also provides a design method for a high-frequency TSV silicon adapter board, the design method being used to design any of the high-frequency TSV silicon adapter boards described above, the design method comprising:

[0023] A simulation model of the high-frequency TSV silicon adapter board is designed. The high-frequency TSV silicon adapter board includes ground through-silicon vias (TSVs), signal through-silicon vias (TSVs), redundant ground through-silicon vias (TSVs) and / or redundant signal through-silicon vias (TSVs), ground transmission lines, signal transmission lines, ground pads, and signal pads. The ground TSVs and signal through-silicon vias are perpendicular to a first plane. Each end of a ground TSV is electrically coupled to one of the ground pads. Each end of a signal through-silicon via is electrically coupled to one of the signal pads. When redundant ground TSVs exist, each end of a redundant ground TSV is electrically coupled to the ground pad where the ground TSV is located. Each of the... The grounding pad containing the ground via includes n redundant ground vias, where n is an integer greater than or equal to 0; when a redundant signal via exists, each end of the redundant signal via is electrically coupled to the signal pad containing the redundant signal via; each signal pad containing the redundant signal via includes m redundant signal vias, where m is an integer greater than or equal to 0; both the ground via and the redundant ground via are first vias, and both the signal via and the redundant signal via are second vias, with a preset distance between each first via and each second via;

[0024] Adjust the number of redundant silicon vias for ground lines and / or redundant silicon vias for signal lines; adjust the distance between the first silicon via and the second silicon via; simulate the adjusted simulation model; and measure the S11 curve, S21 curve, and time domain reflectometer measured impedance curve of the simulation model.

[0025] Select the number of redundant ground vias and / or redundant signal vias corresponding to the impedance curves with the matched impedance as the reference line, the minimum S11 reflection coefficient in the S11 curve, and the minimum RF insertion loss in the S21 curve, and the distance between the first via and the second via.

[0026] The number of selected ground redundant through-silicon vias and / or signal redundant through-silicon vias, and the distance between the first through-silicon via and the second through-silicon via are used as the number and spacing of the first through-silicon via and the second through-silicon via in the high-frequency TSV silicon adapter board.

[0027] As described above, the high-frequency TSV silicon adapter board and its design method of the present invention have the following beneficial effects:

[0028] This invention adjusts the spacing between the first and second through-silicon vias by designing the positions of redundant through-silicon vias and through-silicon vias in the high-frequency TSV silicon adapter board. Under the condition that there are no anti-pads available for adjustment, it reduces the impedance discontinuity problem between the through-silicon vias and transmission lines in the high-frequency TSV silicon adapter board and improves the RF performance of the high-frequency TSV silicon adapter board.

[0029] This invention is the first to incorporate redundant through-silicon vias (TSVs), currently used only in digital signal transmission to improve fault tolerance, into a silicon adapter board. The signal TSVs and multiple redundant TSVs share a common pad, optimizing the RF performance of the silicon adapter board while improving its signal fault tolerance and process reliability.

[0030] The present invention can further improve the reduction effect on impedance discontinuity by setting the first silicon via and the second silicon via to be quasi-coaxially distributed. Attached Figure Description

[0031] Figure 1 The diagram shown is a structural schematic of the high-frequency TSV silicon adapter board in Embodiment 1 of the present invention.

[0032] Figure 2 The figure shows a comparison of the S11 reflection coefficient curves of the transmission lines and through-silicon via signals through a high-frequency TSV silicon adapter board for different numbers of first and second through-silicon vias in Example 1 of the present invention.

[0033] Figure 3 The figure shows a comparison of the S21 insertion loss curves of the transmission lines and through-silicon via signals through a high-frequency TSV silicon adapter board for different numbers of first and second through-silicon vias in Example 1 of the present invention.

[0034] Figure 4 The diagram shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 1 of the present invention.

[0035] Figure 5 The diagram shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 1 of the present invention.

[0036] Figure 6 The diagram shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 1 of the present invention.

[0037] Figure 7 The diagram shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 2 of the present invention.

[0038] Figure 8 The diagram shown is a schematic diagram of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 2 of the present invention.

[0039] Figure 9 The diagram shown is a schematic representation of the structure of a high-frequency TSV silicon adapter board in an example of Embodiment 4 of the present invention.

[0040] Figure 10 The figure shows a comparison of the TDR measurement impedance curves of the transmission line and the through-silicon via signal through a high-frequency TSV silicon adapter board with different distances between the first and second through-silicon vias in an example of Embodiment 4 of the present invention.

[0041] Figure 11 The figure shows a comparison of the S11 reflection coefficient curves of the transmission line and the through-silicon via signal through a high-frequency TSV silicon adapter board with different distances between the first and second through-silicon vias in an example of Embodiment 4 of the present invention.

[0042] Component designation explanation

[0043] 10. First through-silicon via (TSV); 11. Ground TSV; 12. Redundant ground TSV; 20. Second TSV; 21. Signal line TSV; 22. Signal line redundant TSV; 31. Ground transmission line; 32. Signal transmission line; 41. Ground pad; 42. Signal line pad. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0046] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0047] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] Example 1:

[0050] This embodiment provides a high-frequency TSV silicon adapter board, such as Figure 1 As shown, the high-frequency TSV silicon adapter board includes: a ground silicon via 11, a signal silicon via 21, a ground redundant silicon via 12 and / or a signal redundant silicon via 22, a ground transmission line 31, a signal transmission line 32, a ground pad 41, and a signal pad 42.

[0051] Each of the two ends of the ground silicon via 11 is electrically coupled to a ground pad 41; each of the two ends of the signal silicon via 21 is electrically coupled to a signal pad 42.

[0052] When the redundant silicon via 12 exists, each end of the redundant silicon via 12 is electrically coupled to the grounding pad 41 where the redundant silicon via 11 is located; each grounding pad 41 where the redundant silicon via 11 is located includes n redundant silicon vias 12, where n is an integer greater than or equal to 0;

[0053] When the redundant silicon via 22 for signal lines exists, each end of the redundant silicon via 22 for signal lines is electrically coupled to the signal line pad 42 where the redundant silicon via 21 for signal lines is located; each signal line pad 42 where the redundant silicon via 21 for signal lines is located includes m redundant silicon vias 22 for signal lines, where m is an integer greater than or equal to 0;

[0054] The ground wire through-silicon via 11 and the redundant ground wire through-silicon via 12 are both first through-silicon vias 10, and the signal line through-silicon via 21 and the redundant signal line through-silicon via 22 are both second through-silicon vias 20. The first through-silicon via 10 and the second through-silicon via 20 are both perpendicular to the first plane, and there is a preset distance between each first through-silicon via 10 and each second through-silicon via 20.

[0055] The grounding pad 41 is electrically connected to the grounding transmission line 31, and the signal line pad 42 is electrically connected to the signal transmission line 32.

[0056] In existing technologies, high-frequency impedance discontinuities in integrated circuits lead to reflection losses, causing some signals to be reflected while others are distorted and continue propagating. This significantly impacts the RF transmission performance of the integrated circuit's signal channels. In the PCB (Printed Circuit Board) field, impedance control is typically achieved through anti-pad design. However, anti-pad design is suitable for multi-layer metal structures, where a large copper layer is laid outside the metal layers to create the anti-pad area for impedance control. But silicon interposers only have two metal layers, and through-silicon vias (TSVs) connect the two metal layers. Therefore, when designing anti-pads on silicon interposers, only a reference ground structure can be formed on both metal layers, failing to create a closed ground cavity around the TSVs. This results in a severe impact on the RF performance of the silicon interposer when designing anti-pads. Meanwhile, during the manufacturing process, interconnect failures may occur due to misalignment of the pads or insufficient filling of conductive material. Redundant through-silicon via (TSV) designs can be used to reduce the risk of interconnect failures. However, when redundant TSVs used in the digital field are directly designed into silicon interposers, the RF impedance characteristics of the silicon interposers are easily deteriorated. Therefore, those in the field generally do not design redundant TSVs in silicon interposers, and there is currently no research on the impact of redundant TSV structures on the RF performance of silicon interposers.

[0057] This invention adjusts the spacing between the first through-silicon via 10 and the second through-silicon via 20 in a high-frequency TSV silicon adapter board, thereby regulating the capacitive impedance formed by the two vias. This significantly reduces impedance discontinuities between the through-silicon vias and transmission lines in the high-frequency TSV silicon adapter board, even when process limitations prevent the design of anti-pads, greatly improving the RF performance of the board. Furthermore, in more highly integrated circuits, misalignment of TSV pads leading to interconnect failures or insufficient conductive material filling can cause product defects. To prevent RF performance degradation of the silicon adapter board due to body failure, redundant TSVs are set up, and the distance between redundant TSVs and other through-silicon vias is designed to avoid deterioration. This can effectively improve product yield. Therefore, in circuits with higher integration, more redundant TSVs are designed, which gives more room for adjustment of the position of redundant ground through-silicon vias 11 and redundant signal through-silicon vias 21 in the high-frequency TSV silicon adapter board. Moreover, by designing multiple through-silicon vias to connect the same pads, there is no need to introduce extra transmission line structures, which is more conducive to solving the impedance discontinuity problem between through-silicon vias and transmission lines in the high-frequency TSV silicon adapter board.

[0058] Specifically, the high-frequency TSV silicon adapter board in this invention refers to a high-frequency silicon adapter board that includes TSV.

[0059] Specifically, redundant ground silicon vias 11 and redundant signal silicon vias 21 are provided to solve the impedance discontinuity problem of the high-frequency TSV silicon adapter board. However, the increase of these redundant silicon vias will also improve the circuit reliability of the high-frequency TSV silicon adapter board. This breaks the technical bias in the prior art of avoiding the application of redundant TSVs in the high-frequency TSV silicon adapter board in order to avoid the degradation of the radio frequency performance of the high-frequency TSV silicon adapter board by redundant TSVs, and achieves a dual improvement in radio frequency performance and signal fault tolerance.

[0060] Specifically, the number of ground silicon vias 11 and signal silicon vias 21 are both integers greater than or equal to 1, which can be designed according to the needs of circuit design. The positions of redundant ground silicon vias 12 and redundant signal silicon vias 22 are determined based on the ground silicon vias 11 and signal silicon vias 21.

[0061] In this embodiment, n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.

[0062] Specifically, the number of ground redundant silicon vias 12 and signal redundant silicon vias 22 can be set according to the signal fault tolerance requirements of the circuit in the high-frequency adapter board.

[0063] Specifically, the number and distance of the first through-silicon via 10 and the second through-silicon via 20 described in this invention are only structural designs for the connection between a transmission line and a through-silicon via in a high-frequency TSV silicon adapter board. Similar structural design methods can be adopted for the connection between each transmission line and the through-silicon via in the high-frequency TSV silicon adapter board. Different numbers and distances of the first through-silicon via 10 and the second through-silicon via 20 can also be selected for different connection points according to requirements.

[0064] Specifically, "each end of the ground silicon via 11 is electrically coupled to one of the ground pads 41" means that one end of the ground silicon via 11 is electrically coupled to one ground pad 41 and the other end is electrically coupled to another ground pad 41; "each end of the signal line silicon via 21 is electrically coupled to one of the signal line pads 42" means that one end of the signal line silicon via 21 is electrically coupled to one signal line pad 42 and the other end is electrically coupled to another signal line pad 42.

[0065] Specifically, the first through-silicon via 10, the second through-silicon via 20, the ground redundant through-silicon via 12, and the signal redundant through-silicon via 21 are all through-silicon vias (TSVs), the ground redundant through-silicon via 12 and the signal redundant through-silicon via 21 are both redundant TSVs, and the ground transmission line 31 and the signal transmission line 32 are both transmission lines.

[0066] In one embodiment, such as Figure 1As shown, at the connection between each transmission line and through-silicon via on a high-frequency TSV silicon adapter board, a ground pad 41 includes two first through-silicon vias 10, and a signal line pad 42 includes two second through-silicon vias 20.

[0067] Specifically, when the spacing between the first through-silicon via 10 and the second through-silicon via 20, and the sizes of the ground pad 41 and the signal line pad 42 are constant, such as Figure 2 The diagram shows a comparison of the signal S11 reflection coefficient curves of the transmission line and the through-silicon vias (TSVs) of different numbers of first TSVs 10 and second TSVs 20 through a high-frequency TSV silicon adapter board. 1S1G represents a high-frequency adapter board with one first TSV 10 and one second TSV 20, 2S2G represents a high-frequency adapter board with two first TSVs 10 and two second TSVs 20, and 4S4G represents a high-frequency adapter board with four first TSVs 10 and four second TSVs 20. It can be seen that the signal S11 reflection coefficient curves of the transmission line and the through-silicon vias through the high-frequency TSV silicon adapter board with two first TSVs 10 and two second TSVs 20 are all below -10dB within 60GHz, indicating a matched state. This suggests that the high-frequency adapter board with two first TSVs 10 and two second TSVs 20 has the best impedance matching.

[0068] And, as Figure 3 The diagram shows a comparison of the S21 insertion loss curves of the transmission line and the signal through the silicon vias of a high-frequency TSV silicon adapter with different numbers of first through-silicon vias 10 and second through-silicon vias 20. 1S1G represents a high-frequency adapter with one first through-silicon via 10 and one second through-silicon via 20, 2S2G represents a high-frequency adapter with two first through-silicon vias 10 and two second through-silicon vias 20, and 4S4G represents a high-frequency adapter with four first through-silicon vias 10 and four second through-silicon vias 20. It can be seen that the S21 insertion loss curves of the transmission line and the signal through the silicon vias of the high-frequency TSV silicon adapter with two first through-silicon vias 10 and two second through-silicon vias 20 have the lowest RF loss within 60GHz. Therefore, it can be determined that the high-frequency TSV silicon adapter with this specific number of first through-silicon vias 10 and second through-silicon vias 20 exhibits the best RF performance.

[0069] In one embodiment, such as Figure 4 As shown, at the connection between a transmission line and a through-silicon via (TSV) on the high-frequency TSV silicon adapter board, the first TSV 10 includes a ground TSV 11 and a ground redundant TSV 12, and the second TSV 20 includes a signal line TSV 21 and a signal line redundant TSV 22.

[0070] In one embodiment, such as Figure 5As shown, at the connection between each transmission line and through-silicon via on a high-frequency TSV silicon adapter board, a ground pad 41 includes four first through-silicon vias 10, and a signal line pad 42 includes four second through-silicon vias 20.

[0071] In one embodiment, such as Figure 6 As shown, at the connection between a transmission line and a through-silicon via (TSV) on the high-frequency TSV silicon adapter board, the first TSV 10 includes one ground TSV 11 and three redundant ground TSVs 12, and the second TSV 20 includes one signal line TSV 21 and three redundant signal line TSVs 22.

[0072] In one embodiment, the projections of each of the first through-silicon vias 10 onto the first plane are all on a first circle, and the projections of each of the second through-silicon vias 20 onto the first plane are all on a second circle, wherein the first circle and the second circle are concentric circles.

[0073] This invention, by setting the first through-silicon via 10 and the second through-silicon via 20 in the aforementioned quasi-coaxial arrangement, makes the capacitive impedance formed by the first through-silicon via 10 and the second through-silicon via 20 more significant. This makes the distance between the first through-silicon via 10 and the second through-silicon via 20 have a significant impact on the impedance, thereby further solving the problem of impedance discontinuity at the connection between through-silicon vias and transmission lines on high-frequency TSV silicon adapter boards. At the same time, it is easier to conduct orderly experimental design of the spacing between the corresponding first through-silicon via 10 and the second through-silicon via 20, which is beneficial to improving the efficiency of designing redundant through-silicon vias in high-frequency silicon adapter boards, and can also improve the RF performance and space utilization of high-frequency TSV silicon adapter boards.

[0074] In one embodiment, the line connecting each of the first through-silicon via 10 and the nearest second through-silicon via 20 coincides radially with the first circle.

[0075] This invention sets the first through-silicon via 10 and the closest second through-silicon via 20 to be radially distributed, making the capacitive impedance formed by the first through-silicon via 10 and the second through-silicon via 20 more obvious. This makes the distance between the first through-silicon via 10 and the second through-silicon via 20 have a greater impact on the impedance, which can further facilitate the impedance adjustment between the two corresponding first through-silicon vias 10 and second through-silicon vias 20, thereby better solving the problem of impedance discontinuity in high-frequency adapter boards.

[0076] In one embodiment, the signal line pad 42 is circular, and the ground pad 41 is an annular ring concentric with the signal line pad 42.

[0077] In one embodiment, the diameter of each first through-silicon via 10 is 5 micrometers to 20 micrometers, and the thickness of each first through-silicon via 10 is 25 micrometers to 200 micrometers.

[0078] In one embodiment, the diameter of each second through-silicon via 20 is 5 micrometers to 20 micrometers, and the thickness of each second through-silicon via 20 is 25 micrometers to 200 micrometers.

[0079] In one embodiment, the projection of the first through-silicon via 10 onto the first plane is located within the projection of the grounding pad 41 onto the first plane.

[0080] In one embodiment, the projection of the second through-silicon via 20 onto the first plane lies within the projection of the signal line pad 42 onto the first plane.

[0081] The present invention sets the first through-silicon via 10 and the second through-silicon via 20 within the projection of the corresponding ground pad 41 and signal line pad 42, so that the pad can fully support the corresponding through-silicon via, thereby ensuring the soldering yield of the high-frequency TSV silicon adapter board and further improving the RF performance of the high-frequency TSV silicon adapter board.

[0082] Example 2:

[0083] This embodiment provides a high-frequency TSV silicon adapter board, which is basically the same as the high-frequency TSV silicon adapter board in Embodiment 1 in other features, except that:

[0084] In this embodiment, the high-frequency TSV silicon adapter board does not include signal line redundant silicon vias 22, and each signal line silicon via 21 has 0 signal line redundant silicon vias 22 on the signal line pad 42; each ground silicon via 11 has n ground redundant silicon vias 12 on the ground pad 41, where n is an integer greater than or equal to 1.

[0085] In one embodiment, such as Figure 7 As shown, at the connection between each transmission line and through-silicon via on a high-frequency TSV silicon adapter board, a ground pad 41 includes two first through-silicon vias 10, and a signal line pad 42 includes one second through-silicon via 20.

[0086] In one embodiment, such as Figure 8 As shown, at the connection between a transmission line and a through-silicon via (TSV) on the high-frequency TSV silicon adapter board, the first TSV 10 includes a ground TSV 11 and a ground redundant TSV 12, and the second TSV 20 is a signal line TSV 21.

[0087] Example 3:

[0088] This embodiment provides a high-frequency TSV silicon adapter board, which is basically the same as the high-frequency TSV silicon adapter board in Embodiment 1 in other features, except that:

[0089] In this embodiment, the high-frequency TSV silicon adapter board does not include ground redundant silicon vias 12, and each ground pad 41 where the ground silicon via 11 is located includes 0 ground redundant silicon vias 12; each signal pad 42 where the signal line silicon via 21 is located includes m signal line redundant silicon vias 22, where m is an integer greater than or equal to 1.

[0090] In one embodiment, at the connection between each transmission line and through-silicon via (TSV) on a high-frequency TSV silicon adapter board, a ground pad 41 includes one first TSV 10, and a signal line pad 42 includes two second TSV 20.

[0091] In one embodiment, at the connection between a transmission line and a through-silicon via (TSV) on the high-frequency TSV silicon adapter board, the first TSV 10 is a ground TSV 11, and the second TSV 20 includes a signal line TSV 21 and a signal line redundant TSV 22.

[0092] Example 4:

[0093] This embodiment provides a high-frequency TSV silicon adapter board, which is basically the same as the high-frequency TSV silicon adapter board in Embodiment 1 in other features, except that:

[0094] In this embodiment, the high-frequency TSV silicon adapter board does not include ground redundant silicon vias 12 and signal redundant silicon vias 22. Each ground pad 41 where a ground silicon via 11 is located includes 0 ground redundant silicon vias 12; each signal pad 42 where a signal silicon via 21 is located includes 0 signal redundant silicon vias 22.

[0095] In one embodiment, such as Figure 9 As shown, at the connection between a transmission line and a through-silicon via (TSV) on the high-frequency TSV silicon adapter board, a ground pad 41 includes a first TSV 10, which is a ground TSV 11; a signal pad 42 includes a second TSV 20, which is a signal TSV 21.

[0096] In one embodiment, the preset distance between the ground silicon via 11 and the signal silicon via 21 is 60 micrometers.

[0097] Specifically, such as Figure 10The figure shows a comparison of the Time Domain Reflectometry (TDR) curves of the transmission line and the through-silicon via (TSV) of the high-frequency TSV silicon adapter board when the preset distances between the ground via 11 and the signal via 21 are 40 μm, 60 μm, 80 μm, and 90 μm, respectively. The change of the characteristic impedance of the transmission line over time, measured by the time domain reflectometry, shows that the impedance continuity is best when the preset distance is 60 μm and the matching impedance is 50 Ω.

[0098] like Figure 11 The figure shows a comparison of the signal S11 reflection coefficient curves of the transmission line and the through-silicon via (TSV) through the high-frequency TSV silicon adapter board when the preset distances between the ground through-silicon via 11 and the signal through-silicon via 21 are 40 micrometers, 60 micrometers, 80 micrometers and 90 micrometers respectively. It can be seen that the reflection coefficient is the smallest and the impedance matching is the best when the preset distance is 60 micrometers.

[0099] It can be seen that adjusting the distance between the first through-silicon via 10 and the second through-silicon via 20 can adjust the impedance continuity and impedance matching effect. This also reflects that the high-frequency TSV silicon adapter board in Examples 1-3 can also improve impedance continuity and RF performance by adjusting the distance between the first through-silicon via 10 and the second through-silicon via 20.

[0100] Example 5:

[0101] This embodiment provides a design method for a high-frequency TSV silicon adapter board, which is used to design any one of the high-frequency TSV silicon adapter boards described in embodiments 1-4.

[0102] The design method of the high-frequency TSV silicon adapter board of the present invention will be described in detail below. It should be noted that the order described does not strictly represent the design method order of the high-frequency TSV silicon adapter board protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0103] First, in step 1, a simulation model of the high-frequency TSV silicon adapter board is designed. The high-frequency TSV silicon adapter board includes a ground silicon via 11, a signal silicon via 21, a ground redundant silicon via 12 and / or a signal redundant silicon via 22, a ground transmission line 31, a signal transmission line 32, a ground pad 41, and a signal pad 42. The ground silicon via 11 and the signal silicon via 21 are both perpendicular to the first plane. Each end of the ground silicon via 11 is electrically coupled to one of the ground pads 41. Each end of the signal silicon via 21 is electrically coupled to one of the signal pads 42. When the ground redundant silicon via 12 exists, each end of the ground redundant silicon via 12 is electrically coupled to the ground pad 41 where the ground silicon via 11 is located. Each grounding via 11 has n redundant grounding vias 12 on its grounding pad 41, where n is an integer greater than or equal to 0. When a redundant signal via 22 exists, both ends of the redundant signal via 22 are electrically coupled to the signal pad 42 where the redundant signal via 21 is located. Each signal pad 42 where the redundant signal via 21 is located has m redundant signal vias 22, where m is an integer greater than or equal to 0. The grounding via 11 and the redundant grounding via 12 are both first vias 10, and the signal via 21 and the redundant signal via 22 are both second vias 20. There is a preset distance between each first via 10 and each second via 20.

[0104] Preferably, the simulation model is an electronic model to improve measurement efficiency and reduce trial-and-error costs. Specifically, the simulation model can also be set as a physical structure to ensure the consistency between the measurement results and the actual structure, thereby improving the solution to the impedance discontinuity problem of actual high-frequency TSV silicon adapter boards.

[0105] Then, proceed to step 2, adjust the number of redundant silicon vias 12 for ground and / or redundant silicon vias 22 for signal; adjust the distance between the first silicon via 10 and the second silicon via 20, simulate the adjusted simulation model, and measure the S11 curve, S21 curve and time domain reflectometer measured impedance curve of the simulation model.

[0106] Next, proceed to step 3, selecting the number of ground redundant silicon vias 12 and / or signal redundant silicon vias 22 corresponding to the smallest change with the matched impedance as the reference line in the time domain reflectometer measurement impedance curve, the smallest S11 reflection coefficient in the S11 curve, and the smallest RF insertion loss in the S21 curve, as well as the distance between the first silicon via 10 and the second silicon via 20.

[0107] In one embodiment, the matching impedance is 50Ω, and the high-frequency TSV silicon adapter includes a 50Ω matching microstrip line.

[0108] Finally, step 4 is performed, where the number of selected ground redundant vias 12 and / or signal redundant vias 22, and the distance between the first via 10 and the second via 20 are used as the number and spacing of the first via 10 and the second via 20 in the high-frequency TSV silicon adapter board.

[0109] In summary, the high-frequency TSV silicon adapter board and its design method of the present invention can reduce the impedance discontinuity problem between the silicon vias and transmission lines in the high-frequency TSV silicon adapter board by designing the first and second silicon vias to be quasi-coaxially distributed in the high-frequency TSV silicon adapter board, and by setting the positions of redundant silicon vias and silicon vias to adjust the spacing between the first and second silicon vias. This can be achieved by adjusting the size of the quasi-coaxial region, thereby improving the RF performance of the high-frequency TSV silicon adapter board. At the same time, the present invention is the first to design redundant silicon vias, which are currently only used in the field of digital signal transmission to improve fault tolerance, into the silicon adapter board. The signal silicon vias and multiple redundant silicon vias share a pad, optimizing the RF performance of the silicon adapter board, while improving the signal fault tolerance and process reliability of the silicon adapter board. In addition, by designing multiple silicon vias to connect to the same pad, without introducing redundant transmission line structures, the problem of RF impedance discontinuity can be further optimized while improving the signal fault tolerance.

[0110] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high frequency TSV silicon interposer, characterized by, The high-frequency TSV silicon adapter plate comprises: ground silicon vias, signal line silicon vias, ground redundant silicon vias and / or signal line redundant silicon vias, ground transmission lines, signal transmission lines, ground pads and signal line pads; Two ends of the ground silicon via are respectively electrically coupled with one of the ground pads; two ends of the signal line silicon via are respectively electrically coupled with one of the signal line pads; When the ground redundant silicon via exists, two ends of the ground redundant silicon via are respectively electrically coupled with the ground pad where the ground silicon via is located; the ground pad where each ground silicon via is located comprises n ground redundant silicon vias, and n is an integer greater than or equal to 0; When the signal line redundant silicon via exists, two ends of the signal line redundant silicon via are respectively electrically coupled with the signal line pad where the signal line silicon via is located; the signal line pad where each signal line silicon via is located comprises m signal line redundant silicon vias, and m is an integer greater than or equal to 0; m and n are not zero at the same time; The ground silicon via and the ground redundant silicon via are first silicon vias, the signal line silicon via and the signal line redundant silicon via are second silicon vias, the first silicon via and the second silicon via are perpendicular to a first plane, and a preset distance exists between each first silicon via and each second silicon via; the first plane is a projection plane perpendicular to the axis direction of the first silicon via and the second silicon via; The ground pad is electrically connected with the ground transmission line, and the signal line pad is electrically connected with the signal transmission line; The projection of each first silicon via on the first plane is on a first circle, the projection of each second silicon via on the first plane is on a second circle, and the first circle and the second circle are concentric circles; the first circle is a circle with the center of the signal line pad as the center and with the distance between the first silicon via and the center of the signal line pad as the radius on the first plane; the second circle is a circle with the center of the signal line pad as the center and with the distance between the second silicon via and the center of the signal line pad as the radius on the first plane.

2. The high-frequency TSV silicon interposer of claim 1, wherein, The ground pad where one ground silicon via is located comprises 1 ground redundant silicon via, and the signal line pad where one signal line silicon via is located comprises 1 signal line redundant silicon via.

3. The high-frequency TSV silicon interposer of claim 1, wherein, The line between each first silicon via and the closest second silicon via is radially coincident with the first circle.

4. The high-frequency TSV silicon interposer of claim 1, wherein, The diameter of each first silicon via is 5-20 microns, and the thickness of each first silicon via is 25-200 microns.

5. The high-frequency TSV silicon interposer of claim 1, wherein, The diameter of each second silicon via is 5-20 microns, and the thickness of each second silicon via is 25-200 microns.

6. The high-frequency TSV silicon interposer of claim 1, wherein, The projection of the first silicon via on the first plane is located in the projection of the ground pad on the first plane.

7. The high-frequency TSV silicon interposer of claim 1, wherein, The projection of the second silicon via on the first plane is located in the projection of the signal line pad on the first plane.

8. A design method of a high-frequency TSV silicon interposer, characterized by, The design method is used for designing the high-frequency TSV silicon adapter plate in any one of claims 1-7, and the design method comprises: A simulation model of the high-frequency TSV silicon adapter plate is designed, the high-frequency TSV silicon adapter plate includes ground silicon vias, signal line silicon vias, ground redundant silicon vias and / or signal line redundant silicon vias, ground transmission lines, signal transmission lines, ground pads and signal line pads; the ground silicon vias and the signal line silicon vias are perpendicular to the first plane; the two ends of the ground silicon via are respectively electrically coupled with one of the ground pads; the two ends of the signal line silicon via are respectively electrically coupled with one of the signal line pads; when the ground redundant silicon via exists, the two ends of the ground redundant silicon via are respectively electrically coupled with the ground pad where the ground silicon via is located; the ground pad where each ground silicon via is located includes n ground redundant silicon vias, n is an integer greater than or equal to 0; when the signal line redundant silicon via exists, the two ends of the signal line redundant silicon via are respectively electrically coupled with the signal line pad where the signal line silicon via is located; the signal line pad where each signal line silicon via is located includes m signal line redundant silicon vias, m is an integer greater than or equal to 0; the ground silicon via and the ground redundant silicon via are first silicon vias, the signal line silicon via and the signal line redundant silicon via are second silicon vias, and a preset distance exists between each first silicon via and each second silicon via; The number of ground redundant silicon vias and / or signal line redundant silicon vias is adjusted; the distance between the first silicon via and the second silicon via is adjusted, and the adjusted simulation model is simulated to measure the S11 curve, the S21 curve and the time domain reflectometer measured impedance curve of the simulation model; The number of ground redundant silicon vias and / or signal line redundant silicon vias and the distance between the first silicon via and the second silicon via corresponding to the minimum change of the reference line in the time domain reflectometer measured impedance curve, the minimum S11 reflection coefficient in the S11 curve and the minimum radio frequency insertion loss in the S21 curve are selected; The selected number of ground redundant silicon vias and / or signal line redundant silicon vias and the distance between the first silicon via and the second silicon via are used as the number and spacing of the first silicon via and the second silicon via in the high-frequency TSV silicon adapter plate.

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