Stacked single photon avalanche diode and high voltage device

Abstract

The invention relates to a stacked single photon avalanche diode and a high voltage device. Embodiments provide a circuit including a first die, a second die, and a third die that are vertically stacked. The second die may have a front side facing the third die and a back side facing the first die. The first die may include a plurality of single photon avalanche diodes (SPADs). The second die may include a plurality of switches coupled to cathode terminals of the plurality of SPADs in the first die. The third die may include digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die may be powered using a high voltage and sometimes referred to as analog high voltage switches. The digital readout logic in the third die may be powered using a lower voltage than the high voltage used to power the second die.

Description

Technical Field

[0001] The present disclosure relates generally to imaging systems, and more particularly, to imaging systems having single photon avalanche diodes (SPADs). Background Art

[0002] A SPAD is a type of PN junction diode that is biased above the breakdown voltage using a high voltage. In this state, the SPAD can be sensitive to a single impinging photon. The SPAD can be coupled to an associated high voltage switch and a digital readout circuit. The high voltage switch may include a pull-up transistor and a pull-down transistor. The digital readout circuit may include a comparator, a level shifter, and a pulse generator.

[0003] Conventionally, the SPAD array and high voltage switch are formed on separate chips or packages. In such configurations, it can be challenging to implement active pixel quenching and minimize package size while ensuring connection reliability. The embodiments described herein arise in this context. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a functional block diagram of an illustrative SPAD-based imaging system, according to some embodiments.

[0005] Figure 2 According to some embodiments, Figure 1 An illustration of an illustrative vehicle of the type shown.

[0006] Figure 3 is a schematic diagram of an exemplary SPAD pixel according to some embodiments.

[0007] Figure 4 is a cross-sectional side view of a sensor die, an analog high voltage die, and a digital readout logic die stacked vertically relative to each other according to some embodiments.

[0008] Figure 5 is a cross-sectional side view of an exemplary n-type high voltage transistor according to some embodiments.

[0009] Figure 6 is a cross-sectional side view of an exemplary p-type high voltage transistor according to some embodiments.

[0010] Fig. 7A is a cross-sectional side view illustrating front side processing for digital readout logic wafers and analog high voltage wafers according to some embodiments.

[0011] Figure 7B is a cross-sectional side view illustrating wafer bonding between a digital sense logic wafer and an analog high voltage wafer according to some embodiments.

[0012] Figure 7C is a cross-sectional side view showing removal of a handle wafer at the back side of an analog high voltage wafer according to some embodiments.

[0013] Fig.7D is a cross-sectional side view illustrating additional backside processing for simulating a high voltage wafer according to some embodiments.

[0014] Fig. 7E is a cross-sectional side view illustrating front-side processing for a sensor wafer according to some embodiments.

[0015] Figure 7F is a cross-sectional side view illustrating wafer bonding between a sensor wafer and a processed back side of an analog high voltage wafer according to some embodiments.

[0016] Figure 7G is a cross-sectional side view illustrating backside processing for a sensor wafer according to some embodiments.

[0017] Figure 8 According to some embodiments, a method for producing Figure 4 A flow chart of illustrative steps to implement a circuit of the type shown in FIG. 7 is provided.

[0018] Fig. 9 is a cross-sectional side view of a sensor die, an analog high voltage die without any n-type transistors, and a digital readout logic die stacked vertically relative to each other according to some embodiments. DETAILED DESCRIPTION

[0019] The imaging system or device may include a single photon avalanche diode (SPAD), forming a SPAD-based imaging system or device (sometimes referred to herein simply as a SPAD device). SPAD-based devices are sometimes referred to as silicon photomultipliers (SiPMs).

[0020] Some imaging systems include image sensors that sense light by converting impinging photons into electrons or holes that accumulate (collected) in pixel photodiodes within the sensor array. After completing the accumulation period, the collected charge is converted into a voltage that is provided to the output terminals of the sensor. In complementary metal oxide semiconductor (CMOS) image sensors, the charge-to-voltage conversion is done directly in the pixel itself, and the analog pixel voltage is transferred to the output terminal through various pixel addressing and scanning schemes. The analog pixel voltage may also be subsequently converted to a digital equivalent on-chip and processed in various ways in the digital domain.

[0021] On the other hand, SPAD devices use different photon detection mechanisms. In some illustrative configurations sometimes described as examples in this article, SPAD devices may form a light detection and ranging (LIDAR) device or imaging system. LIDAR devices may include a light source that emits light toward a target object or scene. The light sensing diode (SPAD) in the LIDAR device may be biased above its breakdown point, and when an incident photon from the light source (e.g., light reflected from a target object / scene) generates an electron-hole pair, the carrier triggers an avalanche breakdown while generating additional carriers. Since avalanche multiplication is a self-sustaining process, a current signal can be generated and can be easily detected by a readout circuit associated with the SPAD. The avalanche breakdown process needs to be stopped (quenched) in order to detect new photons by reducing the voltage bias across the diode to below its breakdown point. In a LIDAR device, a SPAD pixel can be used to measure the photon flight time (ToF) from a synchronized light source to a scene object point and back to the sensor, which can be used to obtain a three-dimensional image of the scene (as an example).

[0022] Figure 1 is a functional block diagram of an exemplary imaging system such as imaging system 10 . Figure 1 The imaging system 10 may be a vehicle safety system (eg, an active braking system or other vehicle safety system), a surveillance system, a medical imaging system, a general machine vision system, or any other desired type of system.

[0023] The imaging system 10 may include or implement a LIDAR-based device (sometimes referred to as a LIDAR module) having a SPAD device. The LIDAR module may use the SPAD device to capture an image of a scene and measure the distance to obstacles (also referred to as targets) in the scene. For example, in a vehicle safety system, information from the LIDAR module may be used by the vehicle safety system to determine environmental conditions around the vehicle. For example, the vehicle safety system may include systems such as parking assist systems, automatic or semi-automatic cruise control systems, automatic braking systems, collision avoidance systems, lane keeping systems (sometimes referred to as lane drift avoidance systems), pedestrian detection systems, etc. In at least some cases, the LIDAR module may form part of a semi-autonomous or autonomous unmanned vehicle.

[0024] Figure 2 An illustrative example of a vehicle, such as a car 8, is shown in FIG. Figure 2 As shown in the illustrative example of FIG, a car 8 may include one or more SPAD-based imaging systems 10. The imaging system may be a vehicle safety system, as described above. Figure 2In the illustrative example of FIG. 1 , the first imaging system 10 is shown mounted on the front of the vehicle 8 (e.g., to capture images of the surrounding environment in front of the vehicle), and the second imaging system 10 is shown mounted inside the vehicle 8 (e.g., to capture images of the driver of the vehicle). If desired, the imaging system 10 may be mounted on the rear end of the vehicle 8 (i.e., with the rear end of the vehicle 8 facing the vehicle 8). Figure 2 The imaging system 10 may be mounted at the end of the vehicle opposite to the position where the first imaging system 10 is mounted. The imaging system at the rear end of the vehicle may capture images of the surrounding environment behind the vehicle. These examples are merely illustrative. One or more imaging systems 10 may be mounted at any desired location on or within the vehicle 8.

[0025] Re-reference Figure 1 , the imaging system 10 may include one or more SPAD-based (semiconductor) devices 12. One or more lenses 14 may cover each SPAD-based device 12. During operation, the lens 14 (sometimes referred to as an optical device) may focus light onto the corresponding SPAD-based semiconductor device 12. The SPAD-based devices 12 may each include (an array of) SPAD pixels that convert light into digital data or analog signals in the case of SiPM. The SPAD-based device 12 may have any number of SPAD pixels (e.g., hundreds, thousands, millions, or more). In some SPAD-based devices, each SPAD pixel may be covered by a corresponding color filter element and / or a microlens.

[0026] The SPAD-based device 12 may include control circuitry. The control circuitry for the SPAD-based device 12 may be formed on-chip (e.g., on the same semiconductor substrate as the SPAD-based device 12) or off-chip (e.g., on a different semiconductor substrate than the SPAD-based device 12). The control circuitry may control the operation of the SPAD-based device 12. For example, the control circuitry may operate active quenching circuitry or other adjustable (transistor) circuitry within each SPAD pixel, may control one or more bias voltages provided to each SPAD pixel, may control / monitor readout circuitry associated with each SPAD pixel, and the like.

[0027] The SPAD-based semiconductor device 12 may optionally include additional circuits such as logic gates, digital counters, time-to-digital converters, bias circuits (e.g., source follower load circuits), sample and hold circuits, amplifier circuits, analog-to-digital (ADC) converter circuits, data output circuits, memories (e.g., buffer circuits), address circuits, etc. Any of the foregoing circuits may form part of the control circuitry or, when provided on a per-pixel bias, may form part of a SPAD pixel.

[0028] If desired, the 3D image data output from the SPAD-based device 12 may be provided to downstream image processing circuitry. The image processing circuitry may process the data acquired by the SPAD pixels to determine a depth map of the scene (for example) using the time-of-flight data. Complete 3D image data for a particular scene may be obtained by combining a depth map of the scene with an intensity map. An intensity map may refer to a spatial representation of photon intensity or photon counts obtained from detected photons, and in some applications may provide information about the spatial distribution of photon intensity / counts across a two-dimensional area or even a three-dimensional volume. In some cases, some or all of the control circuitry of the SPAD device 12 may be integrally formed with the image processing circuitry (e.g., on the same die or package).

[0029] The imaging system 10 may provide a number of advanced functions to the user. For example, the user may be provided with the ability to run user applications on the system 10. To implement these functions, the imaging system 10 may include input-output devices 16, such as a keypad, buttons, input-output ports, a joystick, and a display. If desired, other functional modules and / or additional storage and processing circuits (e.g., other components 20) may also be included in the imaging system 10. Other such modules or circuits may include volatile and non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid state drive, etc.), microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, and / or other processing circuits for other (non-imaging) functional modules.

[0030] The input-output devices 16 may include output devices that work in conjunction with the SPAD-based device 12. For example, one or more light-emitting components 18 may be included in the imaging system 10 to emit light (e.g., infrared or any other desired type of light). The light-emitting component 18 may be a laser, a light-emitting diode, or any other desired type of light-emitting component. The SPAD-based device 12 may measure the reflection of light from an object in a LIDAR scheme (e.g., in a scenario where the imaging system 10 implements or includes a LIDAR module) to measure the distance to the object. The control circuit used to control the operation of the SPAD-based device 12 may also be optionally used to control the operation of the light-emitting component 18 for coordinating the sensing scheme.

[0031] Figure 3 is a schematic diagram of an exemplary SPAD pixel such as SPAD pixel 30. Figure 1 As shown, a plurality of such SPAD pixels or an array thereof may be formed in the SPAD device 12. Figure 3 As shown, SPAD pixel 30 may include SPAD 24 having an anode terminal connected to voltage supply terminal 32 and a power supply line 38 (eg, a high voltage V may be provided thereon) connected via switch 36 (eg, transistor 36) when switch 36 is turned on or activated.H The cathode terminal 34 of the power supply terminal) is provided. The anode terminal 32 can be biased to a voltage V BS In preparation for detection operation using SPAD pixel 30, supply voltage terminals 32 and 38 may be used to bias SPAD 24 to a voltage (e.g., across SPAD 24) that is above the breakdown voltage of SPAD 24. The breakdown voltage may be defined as a reverse bias voltage that may be applied to SPAD 24 without causing an exponential increase in reverse forward current in SPAD 24. When SPAD 24 is reverse biased above the breakdown voltage in this manner, absorption of a single photon may trigger a short but relatively large avalanche current by impact ionization, thereby providing single photon sensitivity.

[0032] The quenching circuit can be used to reduce the bias voltage of the SPAD 24 to a level below or at the breakdown voltage. Reducing the bias voltage of the SPAD 24 to below the breakdown voltage will stop the avalanche process and the corresponding avalanche current. There are a variety of ways to form a quenching circuit. For example, the quenching circuit can be a passive quenching circuit or an active quenching circuit. Once the avalanche is initiated, the passive quenching circuit can automatically quench the avalanche current without external control or monitoring. For example, a resistor (e.g., a passive resistive component) coupled between the cathode terminal of the SPAD and the corresponding voltage supply terminal can act as a passive quenching circuit. On the other hand, the active quenching circuit may require external control or monitoring to apply a voltage to the cathode terminal of the SPAD.

[0033] exist Figure 3 In the example of FIG. 1 , pixel 30 includes an active quenching circuit. The active quenching circuit can reduce the time it takes SPAD 24 to be quenched and reset (e.g., dead time). The reduction in dead time can allow SPAD 24 to detect incident light at a faster rate than when using a passive quenching circuit, thereby improving the count rate of the SPAD device. Figure 3 As shown, the (active) quenching circuit of pixel 30 may include coupling cathode terminal 34 to ground supply line 42 (eg, on which a ground voltage V -SS When turned on, the switch 40 can connect the ground voltage V SS is provided to cathode terminal 34 of SPAD 24. Switch 40 configured in this manner is sometimes referred to as a pull-down transistor or a disable transistor.

[0034] To control the state of switch 40, the quenching circuit of pixel 30 may also include control circuit 50 that supplies a control signal along path 52 that controls the state of switch 40. For example, control circuit 50 may assert or deassert the control signal to switch between an on state and an off state of switch 40, or may control switch 40 in any suitable manner. Figure 3In the example of , an output signal from a delay circuit 44 coupled along a SPAD readout path (e.g., a signal along path 48) can be used to generate a control signal on path 52. In other words, in this active quenching scheme, the active quenching circuit can modulate the SPAD quenching resistance based on the SPAD operation. For example, before a photon is detected, the quenching resistance is set to a higher value, and then once a photon is detected, the quenching resistance is minimized so that the avalanche is quenched to reduce the recovery time. Figure 3 In the example of , control circuit 50 may control switch 40 to be in an open or high-resistivity state to set the SPAD quenching resistance to a higher value before a photon is detected, and may control switch 40 to be in a closed or low-resistivity state to quench the avalanche once a photon is detected.

[0035] In a similar manner, delay circuit 44 may provide a control signal on path 46 (e.g., based on the introduced delay) to control switch 36 to be in an open state or a closed state at a corresponding time. For example, a suitable time period after a quenching operation of SPAD 24 (e.g., assertion of a control signal on path 52 to close switch 40), delay circuit 44 may provide an asserted control signal to close switch 36, thereby resetting or recharging SPAD 24 and preparing for detection of subsequent photons. The time period after the quenching operation and reset / recharge operation of SPAD 24 may have a duration equal to tens or hundreds of nanoseconds (ns), less than 100 ns, less than 10 ns, less than 1 ns, or greater than 1 microsecond. Switch 36 is therefore sometimes referred to as a pull-up transistor or a recharge transistor.

[0036] exist Figure 3 In the example of , the readout path of pixel 30 may include delay circuit 44 and driver circuit 54. Delay circuit 44 and driver circuit 54 may pass a detection signal (in response to a detected impinging photon) from cathode terminal 34 to pixel output terminal 56. If desired, instead of or in addition to delay circuit 44 and / or driver circuit 54, specific functional circuits may be coupled between terminals 34 and 56 along the readout path of pixel 30. For example, such functional circuits may include a variable or constant holdoff timer circuit, a variable or constant reset timer circuit, and / or a reset timeout circuit, etc. The detection signal leaving pixel 30 from output terminal 56 may be processed by downstream digital processing circuitry.

[0037] To provide additional functionality to the SPAD pixel 30, the control circuit 50 may receive additional input signals such as DIS and TST. In particular, the input signal DIS may be a disable signal that, when asserted, enables the control circuit 50 to use (assert) the control signal on the path 52 to maintain the switch 40 in a closed or activated state so that the SPAD avalanche is prevented, thereby actively disabling the pixel 30 from performing a sensing operation. The input signal TST may be a test signal that, when asserted, enables the control circuit 50 to control the switch 40 and / or other pixel elements in response to a test input, thereby providing testability to the pixel 30.

[0038] The delay circuit 44, the control circuit 50, the driver 54 and / or any other circuit associated with the readout of the SPAD pixel 30 may be collectively referred to and defined herein as "digital readout logic". For example, the other circuits may include one or more comparators, one or more pulse generators, one or more level shifters, one or more inverters, etc. The digital readout logic may be provided by a supply voltage V H The low supply voltage used to power the digital readout logic may be equal to 1.8V, 1V-2V, 2V-3V, 3.3V, 3V-4V, or less than V H other voltages.

[0039] On the other hand, using a high voltage V H The powered switches 36 and 40 are sometimes referred to and defined herein as “high voltage” transistors or analog high voltage (HV) devices. The high voltage transistors 36 and 40 coupled to the cathode terminal 34 are considered analog devices because the signal generated at the cathode terminal 34 when the SPAD 24 senses an impinging photon is an analog signal. As an example, the high voltage V used to power the analog high voltage transistors 36 and 40 is H It may be equal to 5V, 6V, 7V, 5V-7V, 4V-6V, 6V-8V, 4V-8V, greater than 8V, or other voltage greater than the low voltage for powering the digital readout logic. On the other hand, the bias voltage V at the anode terminal 32 is BS It may be set equal to at least 17V, 18V, 19V, 20V, 17V-20V, greater than 10V, greater than 12V, greater than 14V, greater than 16V, or other suitable level to ensure that SPAD 24 is biased in the breakdown operating regime.

[0040] According to some embodiments, a SPAD pixel circuit can be implemented using a stacked die arrangement (sometimes referred to as a 3-dimensional (3D) stack). The stacked die arrangement may include two or more dies with different components and circuits that form a SPAD pixel circuit when stacked vertically together. Figure 4 1 is a cross-sectional side view of an exemplary SPAD circuit 100 implemented using a first die such as die 102, a second die such as die 104, and a third die such as die 106 stacked vertically relative to each other. Die 106 may include only a SPAD (e.g., a SPAD array) and is sometimes referred to and defined herein as sensor die 106. Sensor die 106 may be configured as a back-illuminated (BSI) sensor die. Die 104 may include a sensor die that uses a high voltage V H The analog high voltage (HV) transistor that supplies power to the analog high voltage die 104 is therefore sometimes referred to and defined herein as an analog high voltage die or analog die 104. The back-illuminated sensor die 106 can be stacked on the back side of the analog high voltage die 104, such as Figure 4 As shown. The die 102 may include using a voltage less than V H The analog high voltage die 104 may be stacked on the front side of the digital readout logic die 102, such as the digital readout logic die 102, and is therefore sometimes referred to and defined herein as the digital readout logic (low voltage) die or the digital die 102. Figure 4 In other words, the analog high voltage die 104 may be inserted or sandwiched between the BSI sensor die 106 and the digital readout logic (low voltage) die 102 .

[0041] like Figure 4 As shown, the digital readout logic die 102 may include a semiconductor substrate, such as a silicon substrate 110. A delay circuit 44 (see Figure 3 ), digital readout logic for control circuitry 50, driver 54, and / or any other circuitry associated with readout of each SPAD pixel 30 may be formed in or on semiconductor substrate 110. The digital readout logic may have one or more gate conductors, such as exemplary gate conductor 114 formed over semiconductor substrate 110.

[0042] An interconnect stack such as interconnect stack 112 may be formed on semiconductor substrate 110. Interconnect stack 112 may include alternating wiring layers and via layers. If desired, interconnect stack 112 may optionally include only one wiring layer and only one via layer. Each wiring layer may include a conductive (metal) wiring path, such as a metal wiring structure 116 formed in a dielectric material layer. Each via layer may include a conductive (metal) via, such as a metal via structure 118 formed in a dielectric material layer. Therefore, interconnect stack 112 is sometimes referred to as a dielectric stack (e.g., an interconnect stack having a conductive wiring path formed in a dielectric material such as silicon dioxide). Conductive wiring structure 116 and conductive via structure 118 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal wiring structures 116 and metal via structures 118 may form an electrical network for interconnecting various components within die 102 and for coupling digital readout logic on die 102 to other off-chip components (e.g., to components on die 104, die 106, and / or other external components).

[0043] The analog high voltage die 104 may be stacked on the digital readout logic die 102. The analog high voltage die 104 may include a semiconductor substrate such as a silicon substrate 120. High voltage devices such as an n-type transistor N1 and a p-type transistor P1 may be formed in the semiconductor substrate 120. The n-type transistor N1 may represent Figure 3 The high voltage pull-down switch 40 in the embodiment of the present invention is shown in FIG. Figure 3 The high voltage pull-up transistor 36 in FIG. Figure 4 As shown, each SPAD pixel 30 may include a HV n-type transistor N1 and a HV p-type transistor P1. This is exemplary. As another example, the SPAD pixel 30 may include only one HV n-type transistor without any p-type transistor. As another example, the SPAD pixel 30 may include only one HV p-type transistor without any n-type transistor. As another example, the SPAD pixel 30 may include one or more HV n-type transistors. As another example, the SPAD pixel 30 may include one or more HV p-type transistors. As another example, the SPAD pixel 30 may include one or more HV n-type transistors and one or more HV p-type transistors.

[0044] A more detailed view of the n-type high voltage (HV) transistor N1 is shown in Figure 5 As shown in Figure 5As shown, transistor N1 may include an n-type drift region 200, an n+ layer 202 formed on the back side of the n-type drift region 200, and an n++ contact 204 formed in a corresponding p-body (injection) region 206 at the front side of the n-type drift region 200. The n+ layer 202 may be configured as a drain terminal of the transistor N1, and the n++ contact 204 may be collectively configured as a source terminal of the transistor N1. The n-type transistor N1 having a source terminal and a drain terminal formed at or near the opposite side or surface of the substrate 120 in this manner is sometimes referred to and defined as a "vertical transistor" herein. When referring to the current conduction terminals of the transistor, the terms "source" and "drain" are sometimes used interchangeably. The source terminal and the drain terminal are therefore sometimes referred to as "source-drain" terminals (for example, the source terminal may be referred to as a first source-drain terminal, and the drain terminal may be referred to as a second source-drain terminal, or vice versa). Transistor N1 may have a gate conductor 124 formed on one side of semiconductor substrate 120 and connected to source terminal 204. The side of substrate 120 at / on which gate conductor 124 is formed is often referred to as the "front side" of the substrate or die.

[0045] A more detailed view of the p-type high voltage (HV) transistor P1 is shown in FIG. Figure 6 As shown in Figure 6 As shown, transistor P1 may include a p-type substrate region 210, a p+ layer 212 formed on the back side of the p-type substrate region 210, and a p++ contact 214 formed in a corresponding n-body (injection) region 216 at the front side of the p-type substrate region 210. The p+ layer 212 may be configured as a drain terminal of the transistor P1, and the p++ contact 214 may be collectively configured as a source terminal of the transistor P1. The p-type transistor P1 having a source terminal and a drain terminal formed at or near opposite sides or surfaces of the substrate 120 in this manner is sometimes referred to and defined as a "vertical transistor" herein. When referring to the current conducting terminals of the transistor, the terms "source" and "drain" are sometimes used interchangeably and are therefore sometimes referred to as "source-drain" terminals. The transistor P1 may have a gate conductor 124 formed on the front side of the semiconductor substrate 120 and connected to the source terminal 214.

[0046] Return to reference Figure 4, an interconnect stack such as interconnect stack 122 may be formed on the front side (surface) of semiconductor substrate 120. Interconnect stack 122 may include alternating wiring layers and via layers. Each wiring layer in interconnect stack 122 may include a conductive (metal) wiring path, such as a metal wiring structure 126 formed in a dielectric material layer. Each via layer in interconnect stack 122 may include a conductive (metal) via, such as a metal via structure 128 formed in a dielectric material layer. Therefore, interconnect stack 122 is sometimes referred to as a dielectric stack (e.g., an interconnect stack having a conductive wiring path formed in a dielectric material such as silicon dioxide). Conductive wiring structure 126 and conductive via structure 128 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal wiring structures 126 and metal via structures 128 may form an electrical network for interconnecting various components within die 104 together and for coupling high voltage devices (eg, transistors N1 and P1 ) to digital readout logic in die 102 .

[0047] The interconnect stack 122 of the die 104 may be bonded to the interconnect stack 112 at the wafer bonding interface 103. The bonding interface 103 may be formed to ensure that the dielectric materials in the interconnect stacks 112 and 122 are properly attached, and also to ensure that the conductive wiring structures 116 and 126 at the bonding interface 103 are properly connected (bonded). Such bonding at the interface 103 that ensures both physical coupling and electrical coupling is sometimes referred to herein as hybrid bonding.

[0048] The interconnect stack 122 formed on the front side of the semiconductor substrate 120 is exemplary. In addition, an interconnect stack such as the interconnect stack 142 may be formed on the back side (surface) of the semiconductor substrate 120. The interconnect stack 142 may include alternating wiring layers and via layers. Each wiring layer in the interconnect stack 142 may include a conductive (metal) wiring path, such as a metal wiring structure 146 formed in a dielectric material layer. Each via layer in the interconnect stack 142 may include a conductive (metal) via, such as a metal via structure 148 formed in a dielectric material layer. Therefore, the interconnect stack 142 is sometimes referred to as a dielectric stack (e.g., an interconnect stack having a conductive wiring path formed in a dielectric material such as silicon dioxide). The conductive wiring structure 146 and the conductive via structure 148 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal wiring structures 146 and metal via structures 148 may form an electrical network for interconnecting various components within die 104 together and for coupling high voltage devices (eg, transistors N1 and P1 ) to the SPADs in sensor die 106 .

[0049] One or more through silicon via (TSV) structures such as TSV 130 may be formed within analog high voltage die 104. Figure 4 In the example of FIG. 1 , the TSV structure 130 can extend through the entire depth of the semiconductor substrate 120 (e.g., from the back side of the substrate 120 to at least the front side of the substrate 120). In some implementations, the TSV structure 130 can extend at least partially into the front side interconnect stack 122 and make electrical connections with one of the metal wiring structures 126 or with a conductive via. If desired, the TSV structure 130 can additionally or alternatively extend at least partially into the back side interconnect stack 142. The TSV structure 130 can be directly or using a method such as Figure 4 The conductive via 148 is shown to be electrically connected to the metal wiring structure 146 in the backside interconnect stack 142. The TSV structure 130 can be lined with an insulating layer 132 and filled with a conductive material 134. The insulating layer 132 can be formed of silicon dioxide, silicon nitride, silicon oxynitride, or other insulating materials. The filling material 134 can be formed of tungsten, aluminum, copper, copper-tungsten alloy, titanium, tantalum, combinations of these materials, or other conductive materials suitable for the via structure.

[0050] The sensor die 106 may be stacked on the back side of the analog high voltage die 104. The sensor die 106 may include a semiconductor substrate such as a silicon substrate 150. A SPAD array may be formed in the semiconductor substrate 150. Each SPAD pixel 30 may include a corresponding SPAD (see, for example, SPAD1 and adjacent SPAD2, etc.). Each SPAD may include an n+ contact 154 formed in a p-type region 155 (e.g., p-substrate). The n+ contact 154 may serve as a cathode terminal on which a SPAD output voltage is generated, while the p-type region 155 may serve as a voltage configured to receive a bias voltage V BS anode terminal. Figure 4 In the example, the first SPAD1 can be configured to output a corresponding voltage V SPAD1 , and the second (adjacent) SPAD2 can be configured to output a corresponding voltage V SPAD2 The output voltage of each SPAD may be provided to downstream image processing circuitry, such as to digital readout logic on die 102 or to Figure 1 Other image processing circuits in the imaging system 10 of the present invention can be used to process the data collected by the SPAD pixels to determine a depth map of the scene using the time-of-flight data. The depth map can be combined with the intensity map to obtain a full 3D image of the physical scene or environment.

[0051] An interconnect stack such as interconnect stack 152 may be formed on the front side (surface) of semiconductor substrate 150. Interconnect stack 152 may include alternating wiring layers and via layers. Each wiring layer in interconnect stack 152 may include a conductive (metal) wiring path, such as a metal wiring structure 156 formed in a dielectric material layer. Each via layer in interconnect stack 152 may include a conductive (metal) via, such as a metal via structure 158 formed in a dielectric material layer. Therefore, interconnect stack 152 is sometimes referred to as a dielectric stack (e.g., an interconnect stack having a conductive wiring path formed in a dielectric material such as silicon dioxide). Conductive wiring structure 156 and conductive via structure 158 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal wiring structure 156 and metal via structure 158 may form an electrical network for interconnecting various components within die 106 together and for coupling the SPAD array to analog high voltage die 104. Metal wiring structure 156 can be coupled to a SPAD cathode terminal (eg, for sensing a SPAD output voltage) and can be coupled to a SPAD anode terminal (eg, for providing a voltage V BS to bias each SPAD component in the breakdown operation regime).

[0052] The interconnect stack 152 of the die 104 may be bonded to the interconnect stack 142 at the wafer bonding interface 105. The bonding interface 105 may be formed to ensure that the dielectric materials in the interconnect stacks 142 and 152 are properly attached, and also to ensure that the conductive wiring structures 146 and 156 at the bonding interface 105 are properly connected (bonded). Such bonding at the interface 105 that ensures both physical coupling and electrical coupling is sometimes referred to herein as hybrid bonding.

[0053] One or more through silicon via (TSV) structures such as TSV 160 may be formed within sensor die 106. In some embodiments, TSV structure 160 may extend through the entire depth of semiconductor substrate 150 (e.g., through silicon via 160 may extend from the back side of substrate 150 to at least the front side of substrate 150). TSV structure 160 may extend at least partially into interconnect stack 152 and be electrically connected to one of metal wiring structures 156 or to a conductive via. If desired, an additional interconnect stack may be formed between substrate layer 150 and passivation layer 170 in wafer 106, and TSV structure 160 may additionally or alternatively extend at least partially into or completely through the additional interconnect stack. TSV structure 160 may be lined with insulating layer 162 and filled with conductive material 164. Insulating layer 162 may be formed of silicon dioxide, silicon nitride, silicon oxynitride, or other insulating material. The conductive fill material 164 may be formed of tungsten, aluminum, copper, copper-tungsten alloy, titanium, tantalum, combinations of these materials, or other conductive materials suitable for via structures.

[0054] A passivation layer such as passivation layer 170 may be formed along the back side (surface) of substrate 150. Passivation layer 170 may be formed using silicon dioxide, silicon nitride, silicon oxynitride, polyimide, other polymers, or other passivation materials. Contact pads such as contact pads 172 (e.g., wire bonding pads or other types of metal pads) may be formed on passivation layer 170. Contact pads 172 may be coupled to through-silicon vias 160 that traverse substrate layer 150 of sensor die 106. During operation of SPAD circuit 100, incoming light 174 may enter through the back surface of sensor die 106 (i.e., the back side of sensor die substrate 150). Operating in this manner, SPAD circuit 100 may be referred to as a back-illuminated (BSI) SPAD-based sensor.

[0055] An imaging system as described herein may have a SPAD pixel and corresponding readout logic stacked vertically with a HV device. The SPAD may be connected to the HV device via an interconnect stack including TSVs and conductive vias. The HV device may also be connected to an external contact pad using another such interconnect stack. In some implementations, the HV device is stacked vertically with the corresponding readout logic for the SPAD via another interconnect stack, and the readout logic is then connected to the external contact pad via yet another interconnect stack. Figure 4 Arranged in the manner shown, wherein the HV devices are stacked vertically relative to the SPAD pixels, and wherein readout logic on wafer 102 is coupled to external contact pads using TSVs 130 that traverse substrate layer 120 in wafer 104 and using TSVs 160 that traverse substrate layer 150 in wafer 106, the vertically stacked SPAD circuit 100 is technically advantageous and beneficial by providing active in-pixel quenching, a smaller overall form factor, and improved reliability due to a reduced need for wire bonding between stacked dies. For example, the vertically stacked SPAD circuit can help reduce the total footprint of the package by at least 30% or more, at least 40% or more, or at least 50% or more, compared to a non-stacked configuration in which the SPAD pixels and HV devices are formed in the same wafer.

[0056] manufacture Figure 4 The process of the SPAD circuit 100 may be FIG. 7A to FIG. 7G A series of snapshots are shown. Fig. 7A 1 is a cross-sectional side view showing the front side processing of the digital readout logic wafer 102 and the analog high voltage wafer 104. Fig. 7AAs shown, an interconnect stack 112 may be formed on the front side (surface) of the semiconductor substrate 110. The digital readout logic wafer 102 is sometimes referred to as a digital readout logic layer, and may be separated or cut into a plurality of digital readout logic dies 102 later. On the other hand, an interconnect stack 122 may be formed on the front side (surface) of the semiconductor substrate 120 of the wafer 104. The analog HV wafer 104 is sometimes referred to as an analog high voltage layer, and may be separated or cut into a plurality of analog high voltage dies 104 later. Before the front side processing of the wafer 104, the semiconductor substrate 120 may be attached to an oxide layer such as a buried oxide (BOX) layer 300. The buried oxide layer 300 may be formed of silicon dioxide, aluminum oxide, zinc oxide, indium tin oxide, titanium oxide, or gallium oxide (as examples). The buried oxide layer 300 may be formed on a handle wafer such as a carrier wafer 302. The stacking of the semiconductor substrate 120 on the buried oxide layer 300 and the carrier wafer 302 is sometimes referred to as a silicon on insulator (SOI) configuration. The front surface of wafer 102 may be placed against the front surface of wafer 104. Figure 7B Prepare for the next bonding process, as indicated by arrow 304.

[0057] Figure 7B 1 is a cross-sectional side view showing wafer bonding between the digital readout logic wafer 102 and the analog high voltage wafer 104. Figure 7B As shown, wafers 102 and 104 may be bonded at interface 103. Bonding interface 103 may be formed to ensure that dielectric materials in interconnect stacks 112 and 122 are properly attached, and also to ensure that conductive wiring structures 116 and 126 at bonding interface 103 are electrically connected (bonded). Such bonding at interface 103 that ensures both physical coupling and electrical coupling is sometimes referred to herein as hybrid bonding.

[0058] Figure 7C is a cross-sectional side view showing the removal of the carrier wafer 302 from the back side of the analog high voltage wafer 104. Removal of the carrier (handle) wafer 302 may be accomplished via a mechanical grinding process and / or a wet etching process and chemical mechanical polishing (CMP). The wet etching process may involve the use of an etchant that may selectively remove the carrier wafer 302 while stopping at the buried oxide layer 300 (e.g., the wet etchant will only minimally remove silicon dioxide).

[0059] Fig.7D is a cross-sectional side view showing additional backside processing for simulating a high voltage wafer 104. Fig.7DAs shown, an interconnect stack 142 may be formed on the back side (surface) of the semiconductor substrate 120. The interconnect stack 142 may be formed by a buried oxide layer 300. The metal wiring structure 146 in the interconnect stack 142 may be coupled to one or more TSV structures 130 (e.g., using vias 148*), coupled to the drain terminals of one or more high voltage devices N1 (e.g., using vias 148'), and coupled to the drain terminals of one or more high voltage devices P1 (e.g., using vias 148"). This example in which the interconnect stack 142 is formed by the buried oxide layer 300 is illustrative. In other embodiments, the interconnect stack 142 may be formed separately on the back side of the substrate 120 without first forming the buried oxide layer 300.

[0060] Fig. 7E is a cross-sectional side view showing the front side processing of the sensor wafer 106. Fig. 7E As shown, an interconnect stack 152 may be formed on the front side (surface) of the semiconductor substrate 150. The sensor wafer 106 is sometimes referred to as a sensor or SPAD layer, and may be separated or cut into a plurality of sensor dies 106 later. Prior to front side processing of the wafer 106, the semiconductor substrate 150 may be attached to the p+ silicon layer 310. The substrate layer 150 may be an epitaxial silicon layer. The TSV structure 160 may be formed at least partially through the epitaxial silicon layer 150 and the interconnect stack 152. The front surface of the wafer 106 may be placed against the back surface of the wafer 104 to form a semiconductor substrate 150. Figure 7F Prepare for the next bonding process, as indicated by arrow 312.

[0061] Figure 7F is a cross-sectional side view showing wafer bonding between the sensor wafer 106 and the processed back side of the analog high voltage wafer 104. Figure 7F As shown, wafers 106 and 104 may be bonded at interface 105. Bonding interface 105 may be formed to ensure that dielectric materials in interconnect stacks 152 and 142 are properly attached, and also to ensure that conductive wiring structures 156 and 146 at bonding interface 105 are electrically connected (bonded). Such bonding at interface 105 that ensures both physical coupling and electrical coupling is sometimes referred to herein as hybrid bonding.

[0062] Figure 7G is a cross-sectional side view showing additional back-side processing of the sensor wafer 106. Figure 7G As shown, Figure 7FThe p+ silicon layer 310 may be removed via mechanical grinding and / or wet etching processes. A planarization process such as a chemical mechanical polishing (CMP) process may then be used to polish down the back side of the substrate layer 150 to reveal the TSV structures 160 (e.g., such that the TSVs 160 are exposed at the back side of the substrate layer 150). After the CMP or other planarization process, a passivation layer 170 may be formed on the back surface of the substrate layer 150. The passivation layer 170 may be formed using silicon dioxide, silicon nitride, silicon oxynitride, polyimide, other polymers, or other passivating materials. Additional processing steps may then be performed to selectively pattern the passivation layer 170 and form contact pads 172 coupled to one or more TSV structures 160 (see, e.g., Figure 4 of the completed die stack).

[0063] Figure 8 It is used to manufacture Figure 4 7 . During the operation of block 400, the front side of digital readout logic wafer 102 may be processed. For example, digital readout logic circuitry may be formed in the front side of semiconductor substrate 110, and interconnects 112 may be formed on the front side of semiconductor substrate 110. During the operation of block 402, the front side of analog high voltage wafer 104 may be processed. For example, high voltage switches N1 and P1 may be formed in the front side of semiconductor substrate 120, and interconnects 122 may be formed on the front side of semiconductor substrate 120. The results of blocks 400 and 402 may be obtained at Fig. 7A Although the operations of block 402 are shown as occurring after the operations of block 400, block 402 may alternatively occur before or in parallel (simultaneously) with block 400.

[0064] During the operations of block 404, the digital readout logic wafer 102 may be bonded to the analog high voltage wafer 104. The results of block 404 may be Figure 7B , where wafers 102 and 104 are attached at a hybrid bonding interface 103 .

[0065] During operations at block 406, the handle wafer 302 may be removed from the back side of the analog high voltage wafer 104. For example, mechanical grinding and / or a wet etching process may be used to remove the handle (carrier) wafer 302. The wet etching process may involve using an etchant that may selectively remove the carrier wafer 302 while stopping at the buried oxide layer 300 (e.g., the wet etchant will only minimally remove silicon dioxide). The results of block 406 may be recorded at Figure 7C Shown in.

[0066] During operations at block 408, the back side of the analog high voltage wafer 104 may be processed. For example, the interconnect stack 142 may be formed on the back side (surface) of the semiconductor substrate 120 (see, e.g., Fig.7D ). The interconnect stack 142 may be formed by a buried oxide layer 300. The metal wiring structure 146 in the interconnect stack 142 may be coupled to one or more TSV structures 130 (e.g., using vias 148*), to drain terminals of one or more high voltage devices N1 (e.g., using vias 148'), and to drain terminals of one or more high voltage devices P1 (e.g., using vias 148"). Vias 148*, 148', and 148" may be referred to as backside vias. The metal wiring structure 146 exposed at the surface of the interconnect stack 142 is sometimes referred to as a backside bonding pad.

[0067] During operations at block 410, the front side of the sensor wafer 106 may be processed. For example, the interconnect stack 152 may be formed on the front side (surface) of the semiconductor substrate 150 (see, e.g., Fig. 7E ). Before the front side processing of the wafer 106, the semiconductor substrate 150 may be attached to the p+ silicon layer 310. The substrate layer 150 may be an epitaxial silicon layer. The TSV structure 160 may be formed at least partially through the epitaxial silicon layer 150 and the interconnect stack 152. Although the operation of block 410 is shown as occurring after the operations of blocks 400 to 408, block 410 may alternatively occur before or in parallel (simultaneously) with any of blocks 400 to 408.

[0068] During the operations of block 412, the sensor wafer 106 may be bonded to the back side of the analog high voltage wafer 104. The results of block 412 may be Figure 7F , where wafers 104 and 106 are attached at a hybrid bonding interface 105 .

[0069] During operations at block 414, the back side of the sensor wafer 106 may be processed. For example, Figure 7F The p+ silicon layer 310 may be removed via mechanical grinding and / or wet etching processes. A planarization process such as a chemical mechanical polishing (CMP) process may then be used to polish down the back side of the substrate layer 150 to reveal the TSV structures 160. After the CMP or other planarization process, a passivation layer 170 may be formed on the back surface of the substrate layer 150 (see the operation of block 416). The passivation layer 170 is sometimes referred to as a BSI passivation layer. Additional processing steps may then be performed to selectively pattern the passivation layer 170 and form contact pads 172 coupled to one or more TSV structures 160 (see the operation of block 418).

[0070] Figure 8The operations described are illustrative. In some embodiments, one or more of the described operations may be modified, replaced, or omitted. In some embodiments, one or more of the described operations may be performed in parallel. In some embodiments, additional processing may be added or inserted between the described operations. If desired, the order of certain operations may be reversed or changed, and / or the timing of the described operations may be adjusted so that they occur at slightly different times.

[0071] Combination of the above Figures 3 to 8 The described embodiment in which the high voltage devices in the analog die 104 include both an n-type device N1 and a p-type device P1 is exemplary. Fig. 9 Another embodiment of a SPAD circuit 100' is shown that includes a high voltage p-type device P1 but does not include any high voltage n-type device N1. Fig. 9 As shown, the analog high voltage wafer 104 has a p-type vertical transistor P1 formed as part of each SPAD pixel 30, but does not include any n-type vertical transistor N1 (see the lack of transistor N1). This can help save one or more processing steps when manufacturing the wafer 104. The remaining structure of the entire wafer stack is combined with the Figures 4 to 8 Structures that have already been described are similar or identical and need not be repeated in detail to avoid obscuring the present embodiments.

[0072] Various embodiments of SPAD circuits are included. One aspect of the present disclosure provides a circuit comprising: a first die having a plurality of single photon avalanche diodes (SPADs), wherein each of the plurality of SPADs has an anode terminal and a cathode terminal configured to receive a bias voltage; and a second die having a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first die. The first die may be stacked on the back side of the second die. The first die may include: a first semiconductor substrate layer in which the plurality of SPADs are formed; a first interconnect stack of alternating wiring layers and via layers on a front surface of the first semiconductor substrate layer; and a first through-silicon via (TSV) extending from the back surface of the first semiconductor substrate layer to the front surface of the first semiconductor substrate layer and at least partially extending into the first interconnect stack. The second die may include: a second semiconductor substrate layer in which a plurality of switches are formed; a second interconnect stack of alternating wiring layers and via layers on a rear surface of the second semiconductor substrate layer; a second through-silicon via (TSV) extending from the rear surface of the second semiconductor substrate layer to the front surface of the second semiconductor substrate layer; and a third interconnect stack of alternating wiring layers and via layers on the front surface of the second semiconductor substrate layer, wherein the second TSV at least partially extends into the third interconnect stack.

[0073] The plurality of switches may include: a p-type transistor having a drain terminal coupled to a wiring structure in the second interconnect stack and having a source terminal and a gate terminal coupled to a wiring structure in the third interconnect stack; and optionally an n-type transistor having a drain terminal coupled to the wiring structure in the second interconnect stack and having a source terminal and a gate terminal coupled to the wiring structure in the third interconnect stack. The circuit may include a third die having digital readout logic coupled to the plurality of switches in the second die, wherein the second die is stacked on a front side of the third die. The third die may also include: a third semiconductor substrate layer in which digital readout logic is formed; and a fourth interconnect stack of alternating wiring layers and via layers on a front surface of the third semiconductor substrate layer.

[0074] One aspect of the present disclosure provides a method comprising: forming a first wafer including a plurality of single photon avalanche diodes (SPADs), wherein each of the plurality of SPADs has an anode terminal and a cathode terminal configured to receive a bias voltage; forming a second wafer including a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first wafer; and bonding the first wafer to the second wafer. The method may also include: forming a third wafer including digital readout logic coupled to the plurality of switches in the second wafer; and bonding the third wafer to the second wafer. The method may also include: forming a through silicon via (TSV) structure passing through a semiconductor substrate layer in the first wafer; and forming a through silicon via (TSV) structure passing through a semiconductor substrate layer in the second wafer.

[0075] One aspect of the present disclosure provides a device including a sensor die having a plurality of single photon avalanche diodes (SPADs); a digital die having digital readout logic powered by a first positive voltage; and an analog die having a switch powered by a second positive voltage greater than the first positive voltage, wherein the analog die is vertically stacked between the sensor die and the digital die. The analog die may have a front side configured to face the digital die and may have a back side configured to face the sensor die. The device may include a first through silicon via (TSV) structure in the sensor die and a second through silicon via (TSV) structure in the analog die. At least some of the second TSV structures may be coupled to wiring structures in the sensor die and to wiring structures in the digital die.

[0076] The above contents are merely exemplary, and various modifications may be made to the described embodiments. The above embodiments may be implemented individually or in any combination.

Claims

1. A circuit, comprising: a first die having a plurality of single photon avalanche diodes (SPADs), wherein each SPAD of the plurality of SPADs has an anode terminal and a cathode terminal; and A second die having a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first die, wherein the first die is stacked on the second die.

2. The circuit of claim 1 , wherein the first die further comprises: A first semiconductor substrate layer, in which the plurality of SPADs are formed; a first interconnect stack of alternating wiring layers and via layers on a front surface of the first semiconductor substrate layer; and A first through silicon via (TSV) extends from a rear surface of the first semiconductor substrate layer to the front surface of the first semiconductor substrate layer and at least partially extends into the first interconnect stack.

3. The circuit of claim 2, wherein the first die further comprises: a passivation layer on the rear surface of the first semiconductor substrate layer; and A conductive pad is on the passivation layer. 4 . The circuit of claim 2 , wherein the plurality of SPADs are configured to receive incident light from the back surface of the first semiconductor substrate layer.

5. The circuit of claim 2, wherein the second die further comprises: a second semiconductor substrate layer, in which the plurality of switches are formed; a second interconnect stack of alternating wiring layers and via layers on the rear surface of the second semiconductor substrate layer; and A second through silicon via TSV extends from the rear surface of the second semiconductor substrate layer to the front surface of the second semiconductor substrate layer.

6. The circuit of claim 5, wherein the second die further comprises: A third interconnect stack of alternating wiring layers and via layers on the front surface of the second semiconductor substrate layer, wherein the second TSV extends at least partially into the third interconnect stack.

7. The circuit of claim 6, wherein the plurality of switches comprises: A p-type transistor having a drain terminal coupled to the wiring structure in the second interconnect stack and having a source terminal and a gate terminal coupled to the wiring structure in the third interconnect stack.

8. The circuit of claim 7, wherein the plurality of switches further comprises: An n-type transistor having a drain terminal coupled to the wiring structure in the second interconnect stack and having a source terminal and a gate terminal coupled to the wiring structure in the third interconnect stack.

9. The circuit according to claim 6, further comprising A third die has digital readout logic coupled to the plurality of switches in the second die, wherein the second die is stacked on the third die.

10. The circuit of claim 9, wherein the third die further comprises: a third semiconductor substrate layer, in which the digital readout logic is formed; and A fourth interconnect stack of alternating wiring layers and via layers is provided on the front surface of the third semiconductor substrate layer.

11. A method comprising: forming a first wafer, the first wafer comprising a plurality of single photon avalanche diodes (SPADs), wherein each SPAD of the plurality of SPADs has an anode terminal and a cathode terminal; forming a second wafer comprising a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first wafer; as well as The first wafer is bonded to the second wafer.

12. The method according to claim 11, further comprising: forming a third wafer including digital readout logic coupled to the plurality of switches in the second wafer; as well as The third wafer is bonded to the second wafer.

13. The method according to claim 12, further comprising: A through silicon via (TSV) structure is formed through the semiconductor substrate layer in the first wafer, wherein the TSV structure at least partially extends into an interconnect stack on the semiconductor substrate layer in the first wafer.

14. The method according to claim 12, further comprising: A through silicon via (TSV) structure is formed through the semiconductor substrate layer in the second wafer, wherein the TSV structure at least partially extends into an interconnect stack on the semiconductor substrate layer in the second wafer.

15. The method according to claim 14, further comprising: A p-type vertical transistor is formed in the semiconductor substrate layer of the second wafer.

16. The method according to claim 15, further comprising: An n-type vertical transistor is formed in the semiconductor substrate layer of the second wafer.

17. A device, comprising: A sensor die having a plurality of single photon avalanche diodes (SPADs); a digital die having digital readout logic powered by a first positive voltage; and An analog die having a switch powered by a second positive voltage greater than the first positive voltage, wherein the analog die is vertically stacked between the sensor die and the digital die.

18. The apparatus according to claim 17, further comprising: First through silicon via (TSV) structures in the sensor die, wherein at least one of the first TSV structures has a first end coupled to a contact pad and a second end coupled to a wiring structure in the sensor die.

19. The apparatus according to claim 18, further comprising: Second through silicon via (TSV) structures in the analog die, wherein at least one of the second TSV structures has a first end coupled to the wiring structure in the sensor die and a second end coupled to the wiring structure in the digital die.

20. The apparatus of claim 19, wherein at least one of the switches in the analog die has a gate terminal and a source terminal coupled to the wiring structure in the digital die and a drain terminal coupled to the wiring structure in the sensor die.

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