Enhanced gallium nitride device and preparation method thereof and electronic device

Abstract

The present invention provides an enhancement-mode gallium nitride device, a preparation method thereof and an electronic device. A composite gate structure in which a groove gate and a P-cap layer gate are arranged in a gate region along a gate length direction is provided to realize a three-dimensional structured gate. On the one hand, the threshold voltage of the gallium nitride device can be effectively improved to realize an enhancement-mode gallium nitride device. On the other hand, the groove gate can adjust its threshold voltage and the gate-source voltage point corresponding to the transconductance peak by changing the etching depth of the groove, so that the gate-source voltage points corresponding to the transconductance peaks corresponding to the groove gate and the P-cap layer gate are misaligned. When the transconductance of the P-cap layer gate is reduced, the transconductance value of the groove gate can be increased, and the transconductance values ​​of the P-cap layer gate and the groove gate are complemented, thereby realizing the overall transconductance half-peak width widening of the composite gate structure and improving the linearity of the enhancement-mode gallium nitride device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an enhanced gallium nitride device, a preparation method thereof, and an electronic device. Background Art

[0002] Gallium nitride (GaN)-based high electron mobility transistors (HEMTs) have great potential in many RF applications, such as remote sensing, radar, and wireless communications, due to the advantages of heterojunction materials, including high breakdown electric field, high two-dimensional electron gas density, and high electron mobility. In RF communication systems, power amplifiers play a vital role, and their main task is to amplify signals to ensure that they can cover long-distance transmission. This requires GaN-based HEMT power amplifiers to have high linearity, but current GaN-based HEMT devices have serious nonlinear characteristics. Transconductance (G m ) is the main reason affecting the nonlinearity of GaN-based HEMT devices. m ) refers to the ratio of the change in drain current to the change in gate-source voltage. It means the change in drain current caused by the change in gate-source voltage when the source-drain voltage remains unchanged, reflecting the control ability of gate-source voltage on drain current. m ) at higher drain current density levels is the main cause of nonlinearity in GaN-based HEMT devices, resulting in signal distortion. This distortion can lead to a degradation of signal quality, affecting the reliability and efficiency of communications. Especially in modern communication technologies, such as 4G, 5G, and the upcoming 6G networks, which often use complex modulation techniques and high-frequency broadband transmission, the linearity requirements of power amplifiers are extremely high. Therefore, improving the linearity of power amplifiers is the key to improving the performance of the entire communication system. Highly linear power amplifiers can effectively reduce these distortions, maintain signal integrity and high quality, thereby improving the accuracy of data transmission and the spectrum efficiency of the system.

[0003] In the design of RF power amplifiers, in order to improve the linearity of the device, the current mainstream methods include graded polarization field effect transistors, dual-channel heterojunctions, coupled channel structures, and nanochannel structures. These technologies optimize the carrier distribution and electric field uniformity by applying different polarization electric fields in different regions of the transistor, combining different semiconductor materials, designing complex electric field distributions, and reducing the channel size to the nanometer level, thereby effectively improving the linearity of the RF power amplifier and meeting the strict requirements of high-frequency and high-power applications. These methods greatly improve the performance of the device by precisely controlling the material properties and device structure. However, these structures require special epitaxial structures or process methods, which are difficult to integrate on-chip with traditional GaN power devices, making it difficult to achieve full GaN RF modules.

[0004] In addition, the common GaN devices used in RF power amplifiers are normally-on devices, and their gate threshold voltage is less than 0 V. This will result in the need to provide two polarity power supply reference voltages for the gate and drain in the actual integrated circuit design process, which will complicate the design of the voltage reference circuit and increase the total chip area cost; during the operation of the circuit, once the gate of a transistor is out of control for a short period of time, the drain still maintains a high level, and the current in the device will increase instantly, threatening the safety of the device and other modules of the circuit; in addition, when the normally-on transistor in the circuit is in a static state, the negative voltage gate of the transistor needs to be continuously controlled to ensure that the conductive channel of the device is turned off, which increases additional power consumption. Summary of the invention

[0005] In view of this, the embodiments of the present disclosure provide an enhancement-mode gallium nitride device, a method for manufacturing the same, and an electronic device, for providing an enhancement-mode gallium nitride device with high linearity.

[0006] The embodiments of the present disclosure provide an enhanced gallium nitride device, a method for preparing the same, and an electronic device, the specific scheme of which is as follows:

[0007] On the one hand, an embodiment of the present disclosure provides an enhancement-mode gallium nitride device, comprising: a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer sequentially stacked on the substrate in a direction away from the substrate, and a composite gate structure;

[0008] The composite gate structure includes: a gate located on the side of the barrier layer facing away from the substrate, and a P-cap layer and a groove located on the side of the gate facing the barrier layer and arranged along the length direction of the gate; the P-cap layer is located between the barrier layer and the gate, and the groove is opened on the side of the barrier layer facing the gate.

[0009] In some embodiments, in the enhancement-mode gallium nitride device provided by the embodiments of the present disclosure, the number of the P-cap layer and the number of the grooves are both plural, and the P-cap layer and the grooves are alternately arranged along the gate length direction.

[0010] In some embodiments, in the above-mentioned enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, it also includes a source and a drain located on both sides of the barrier layer, the source and the drain are respectively in contact with the channel layer, and the orthographic projection of the composite gate structure on the substrate is located between the orthographic projections of the source and the drain on the substrate.

[0011] In some embodiments, in the above-mentioned enhanced gallium nitride device provided in the embodiments of the present disclosure, it also includes a passivation layer located between the P-cap layer and the gate, the source, and the drain, and the passivation layer includes a first hollow, and the orthographic projection of the first hollow on the substrate overlaps with the orthographic projection of the gate on the substrate.

[0012] In some embodiments, in the above-mentioned enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, it also includes a dielectric layer located between the gate and the source and the drain, the dielectric layer includes a second hollowing, the orthographic projection of the second hollowing on the substrate is located within the orthographic projection range of the P-cap layer on the substrate, and the dielectric layer is in contact with the bottom and sidewalls of the groove.

[0013] In some embodiments, in the above-mentioned enhanced gallium nitride device provided in the embodiments of the present disclosure, the width of the second hollowing along the direction perpendicular to the gate length is smaller than the width of the P-cap layer along the direction perpendicular to the gate length, and the width of the second hollowing along the gate length direction is smaller than the width of the P-cap layer along the gate length direction.

[0014] In some embodiments, in the above-mentioned enhanced gallium nitride device provided in the embodiments of the present disclosure, the width of the second hollowing along the direction perpendicular to the gate length is 0.7 to 0.9 times the width of the P-cap layer along the direction perpendicular to the gate length, and the width of the second hollowing along the gate length direction is 0.7 to 0.9 times the width of the P-cap layer along the gate length direction.

[0015] In some embodiments, in the enhancement-mode gallium nitride device provided by the embodiments of the present disclosure, the width of the groove along the direction perpendicular to the gate length is greater than or equal to 1.1 times the width of the P-cap layer along the direction perpendicular to the gate length.

[0016] In some embodiments, in the enhancement-mode gallium nitride device provided by the embodiments of the present disclosure, the width of the groove along the direction perpendicular to the gate length is less than or equal to 1.3 times the width of the P-cap layer along the direction perpendicular to the gate length.

[0017] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, the material of the channel layer is GaN, the material of the barrier layer is AlGaN, and the material of the P-cap layer is Mg-doped GaN.

[0018] In some embodiments, in the enhanced gallium nitride device provided in the embodiments of the present disclosure, the thickness of the P-cap layer is 50-150 nm, the thickness of the barrier layer corresponding to the position of the P-cap layer is 15-30 nm, and the thickness of the barrier layer corresponding to the position of the groove is 0-10 nm.

[0019] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, the thickness of the dielectric layer is 5-50 nm.

[0020] On the other hand, the embodiment of the present disclosure further provides a method for preparing the enhancement-mode gallium nitride device, which is used to prepare the enhancement-mode gallium nitride device provided by the embodiment of the present disclosure, and the preparation method comprises:

[0021] On one side of the substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-cap layer are sequentially formed in a stacked manner in a direction away from the substrate;

[0022] Etching the P-cap layer to remove the P-cap layer outside the gate region;

[0023] Etching the remaining P-cap layer and the corresponding barrier layer, removing a portion of the P-cap layer corresponding to the gate region to form a final P-cap layer, and forming a groove that penetrates a portion of the barrier layer thickness, wherein the final P-cap layer and the groove are arranged along the length direction of the gate region;

[0024] A gate metal is deposited on the side of the final P-cap layer facing away from the substrate, and the gate metal is etched to remove the gate metal outside the gate region to form a gate.

[0025] In some embodiments, in the above preparation method provided in the embodiments of the present disclosure, after etching the P-cap layer and before etching the remaining P-cap layer and the corresponding barrier layer, the method further includes:

[0026] An ohmic contact metal is deposited on the side of the remaining P-cap layer facing away from the substrate, and the ohmic contact metal is etched to remove the ohmic contact metal outside the source region and the drain region to form a source and a drain respectively contacting the channel layer.

[0027] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, after etching the P-cap layer and before depositing the ohmic contact metal on the side of the remaining P-cap layer facing away from the substrate, it also includes: depositing a passivation layer on the side of the remaining P-cap layer facing away from the substrate;

[0028] When etching the remaining P-cap layer and the corresponding barrier layer, the method further includes etching the passivation layer to remove the passivation layer corresponding to the groove position.

[0029] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, after etching the remaining P-cap layer and the corresponding barrier layer, and before depositing the gate metal on the side of the final P-cap layer away from the substrate, the method further includes:

[0030] Depositing a dielectric layer on a side of the passivation layer away from the substrate, wherein the dielectric layer is in contact with the bottom and sidewall of the groove;

[0031] The dielectric layer and the passivation layer are etched to remove the remaining passivation layer corresponding to the gate region to form a first hollow corresponding to the gate on the passivation layer, and a second hollow corresponding to the final P-cap layer is formed on the dielectric layer.

[0032] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned enhancement-mode gallium nitride device provided by an embodiment of the present disclosure.

[0033] The beneficial effects of the present disclosure are as follows:

[0034] An enhancement-mode gallium nitride device and a preparation method thereof and an electronic device provided by the embodiments of the present disclosure realize a three-dimensional structured gate by arranging a groove gate and a P-cap layer gate in a gate region along a gate length direction. On the one hand, the threshold voltage of the gallium nitride device can be effectively improved to realize an enhancement-mode gallium nitride device. On the other hand, the groove gate can adjust its threshold voltage and the gate-source voltage point corresponding to the transconductance peak by changing the etching depth of the groove, so that the gate-source voltage points corresponding to the transconductance peaks corresponding to the groove gate and the P-cap layer gate are misaligned. When the transconductance of the P-cap layer gate is reduced, the transconductance value of the groove gate can be increased, and the transconductance values ​​of the P-cap layer gate and the groove gate are complementary, thereby realizing the overall transconductance half-peak width widening of the composite gate structure and improving the linearity of the enhancement-mode gallium nitride device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic plan view of an enhanced gallium nitride device provided in an embodiment of the present disclosure;

[0036] Figure 2 for Figure 1 Schematic diagram of the cross section along the AA' direction;

[0037] Figure 3 for Figure 1 Schematic diagram of the cross section along the BB' direction;

[0038] Figure 4 for Figure 1 Schematic diagram of the cross section along CC' direction;

[0039] Figure 5 for Figure 1A local enlarged schematic diagram in FIG.

[0040] Fig. 6A A schematic diagram showing that a P-cap gate HEMT and a groove gate HEMT have different transconductance peak positions;

[0041] Figure 6B for Fig. 6A Schematic diagram of the relationship between gate voltage and drain current corresponding to the two transconductances;

[0042] Figure 6C A schematic diagram of the transconductance distribution of the composite gate structure provided by an embodiment of the present disclosure;

[0043] Fig.6D for Figure 6C Schematic diagram of the relationship between gate voltage and drain current corresponding to the three ratio structures;

[0044] Figure 7 A flow chart of a method for preparing an enhanced gallium nitride device provided in an embodiment of the present disclosure;

[0045] Figure 8 A flow chart of another method for preparing an enhancement-mode gallium nitride device provided in an embodiment of the present disclosure;

[0046] Fig. 9A for Figure 2 and Figure 3 A schematic diagram of the structure of an enhancement-mode gallium nitride device during the preparation process is shown;

[0047] Fig. 9B for Figure 2 and Figure 3 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0048] Fig. 9C for Figure 2 and Figure 3 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0049] Fig.9D for Figure 2 and Figure 3 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0050] Fig.9E for Figure 2 and Figure 3 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0051] Fig.9F for Figure 2 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0052] Figure 9G for Figure 2 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0053] Figure 9H for Figure 2 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0054] Fig. 10A for Figure 3 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0055] Fig. 10B for Figure 3 Another structural schematic diagram of an enhancement-mode gallium nitride device during the preparation process is shown;

[0056] Fig. 10C for Figure 3 Another structural schematic diagram of an enhancement mode gallium nitride device during the preparation process is shown. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thickness of the layers, films, panels, regions, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes do not represent the exact shapes of the illustrated areas, do not reflect the true proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0058] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0059] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0060] The present disclosure provides an enhanced gallium nitride device, such as Figure 1-Figure 4 As shown, Figure 1 A schematic plan view of an enhanced gallium nitride device provided in an embodiment of the present disclosure, Figure 2 for Figure 1 Schematic diagram of the cross section along the AA' direction, Figure 3 for Figure 1 Schematic diagram of the cross section along the BB' direction, Figure 4 for Figure 1 The schematic cross-sectional view along the CC' direction in FIG. 1 shows an enhanced gallium nitride device comprising: a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4 and a barrier layer 5 stacked in sequence on the substrate 1 in a direction away from the substrate 1, and a composite gate structure 8; wherein the barrier layer 5 and the channel layer 6 form a heterostructure, which can induce a two-dimensional electron gas (2DEG);

[0061] The composite gate structure 8 includes: a gate 81 located on the side of the barrier layer 5 facing away from the substrate 1, and a P-cap layer 82 and a groove 51 located on the side of the gate 81 facing the barrier layer 5 and arranged along the length direction (e.g., longitudinal direction) of the gate 81; the P-cap layer 82 is located between the barrier layer 5 and the gate 81, and a groove 51 is opened on the side of the barrier layer 5 facing the gate 81.

[0062] The enhancement-mode gallium nitride device provided by the embodiment of the present disclosure realizes a three-dimensional structure of the gate by arranging a composite gate structure in which a recessed gate and a P-cap layer gate are arranged in a gate region along the gate length direction. On the one hand, the threshold voltage of the gallium nitride device can be effectively improved to realize the enhancement-mode gallium nitride device; on the other hand, the recessed gate can adjust its threshold voltage and the gate-source voltage point corresponding to the transconductance peak by changing the etching depth of the recessed gate, so that the gate-source voltage points corresponding to the transconductance peaks corresponding to the recessed gate and the P-cap layer gate are misaligned, and when the transconductance of the P-cap layer gate is reduced, the transconductance value of the recessed gate can be increased, and the transconductance values ​​of the P-cap layer gate and the recessed gate can be complemented, thereby realizing the overall transconductance half-peak width widening of the composite gate structure (the transconductance half-peak width is the gate voltage range in which the device transconductance is maintained at half the peak value), and improving the linearity of the enhancement-mode gallium nitride device.

[0063] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 1-Figure 4 As shown, the material of the substrate 1 includes one or more of silicon, sapphire, silicon carbide, and aluminum nitride.

[0064] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, the material of the nucleation layer 2 can be AlN, the material of the buffer layer 3 can be GaN, the material of the channel layer 4 can be GaN, the material of the barrier layer 5 can be AlGaN, and the material of the P-cap layer 82 can be Mg-doped GaN, that is, the P-cap layer 82 is a P-GaN layer.

[0065] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, an insertion layer may be provided between the channel layer 4 and the barrier layer 5 , and the material of the insertion layer may be AlN; of course, the insertion layer may not be provided.

[0066] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 1As shown, the number of the P-cap layer 82 and the groove 51 can be multiple, and the P-cap layer 82 and the groove 51 are alternately arranged along the length direction of the gate 81. In this way, by setting the depth of the groove 51, the transconductance values ​​of the P-cap layer gate and the groove gate are complementary, thereby achieving the overall transconductance half-peak width widening of the composite gate structure 8 and improving the linearity of the enhancement-mode gallium nitride device.

[0067] Specifically, Figure 2-Figure 4 As shown, the threshold voltage of the P-cap layer gate is affected by factors such as the thickness of the P-cap layer 82 and its doping concentration, the thickness of the barrier layer 5 and its Al component size, and cannot be changed after epitaxy; while the groove gate can adjust the threshold voltage and the peak value of the transconductance value by controlling the thickness of the etching barrier layer 5. After the barrier layer 5 corresponding to the position of the gate 81 is etched and thinned, the 2DEG density is reduced, thereby increasing the threshold voltage, and then increasing the peak value of the transconductance value. Since the transconductance value of the P-cap layer gate cannot be changed after epitaxy, that is, its corresponding transconductance half-peak width remains unchanged, the transconductance value of the groove gate is adjusted by adjusting the depth of the groove 51, so that the transconductance half-peak width of the groove gate overlaps with the transconductance half-peak width of the P-cap layer gate, realizing the widening of the transconductance half-peak width of the overall composite gate structure, and providing the linearity of the device.

[0068] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, the thickness of the barrier layer 5 corresponding to the position of the P-cap layer 82 can be 15-30 nm, such as 15 nm, 20 nm, 25 nm, 30 nm, etc.; the thickness of the barrier layer 5 corresponding to the position of the groove 51 can be 0-10 nm, such as 0 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc., that is, the thickness of the barrier layer 5 outside the position of the groove 51 can be 15-30 nm. In this way, the present disclosure can adjust the threshold voltage and the peak value of the transconductance value of the composite gate structure 8 by controlling the depth of the groove 51, and realize a high-linearity enhancement-mode gallium nitride device.

[0069] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, the thickness of the P-cap layer 82 can be 50-150 nm, for example, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.

[0070] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4As shown, it also includes a source 6 and a drain 7 located on both sides of the barrier layer 5, the source 6 and the drain 7 are respectively in contact with the channel layer 4, and the orthographic projection of the composite gate structure 8 on the substrate 1 can be located between the orthographic projections of the source 6 and the drain 7 on the substrate 1.

[0071] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 1-Figure 4 As shown, the materials of the source 6 and the drain 7 include one or more of Ti, Al, Ta, Mo, Au, and Ni, and the material of the gate 81 may include one or more of Ti, Al, Ta, Mo, Au, and Ni. It is understandable that the materials of the source 6, the drain 7, and the gate 81 may be the same or different.

[0072] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, it also includes a passivation layer 9 located between the P-cap layer 82 and the gate 81, the source 6, and the drain 7. The passivation layer 9 can protect the device from oxidation; the passivation layer 9 includes a first hollow V1, and the orthographic projection of the first hollow V1 on the substrate 1 overlaps with the orthographic projection of the gate 81 on the substrate 1. For example, the gate 81 is Figure 1 The strip structure shown, so the first hollow V1 is also a strip structure, that is, a strip-shaped first hollow V1 in the same shape as the gate 81 is etched below the gate 81, and the gate 81 can cover the edges of the passivation layer 9 on both sides of the first hollow V1.

[0073] Optionally, the source electrode 6 may contact the channel layer 4 through a through hole penetrating the passivation layer 9 and the barrier layer 5 , and the drain electrode 7 may contact the channel layer 4 through a through hole penetrating the passivation layer 9 and the barrier layer 5 ; of course, it is not limited thereto.

[0074] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, the material of the passivation layer 9 can be aluminum nitride and silicon oxide.

[0075] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4As shown, it also includes a dielectric layer 10 located between the gate 81 and the source 6 and the drain 7. In the P-cap layer gate, the dielectric layer 10 acts as a passivation layer after the ohmic effect, and in the groove gate, the dielectric layer 10 is an insulating dielectric layer in the MIS (metal-insulating dielectric layer-semiconductor) structure, which plays a role in suppressing gate leakage; the dielectric layer 10 includes a second hollow V2, and the orthographic projection of the second hollow V2 on the substrate 1 is located within the orthographic projection range of the P-cap layer 82 on the substrate 1, and the dielectric layer 10 is in contact with the bottom and sidewall of the groove 51, that is, the dielectric layer 10 above the P-cap layer 82 is etched away to achieve the contact between the gate 81 and the P-cap layer 82, and the dielectric layer 10 at the position of the groove 51 is retained. In this way, the threshold voltage and the peak value of the transconductance value can be adjusted by adjusting the thickness of the dielectric layer 10, so as to achieve the dual adjustment of the depth of the groove 51 and the thickness of the dielectric layer 10, and realize the widening of the overall transconductance half-peak width of the composite gate structure 8.

[0076] Specifically, Figure 2 As shown, the first hollow V1 and the second hollow V2 can be formed by one etching process, and the gate 81 can cover the edges of the dielectric layer 10 on both sides of the second hollow V2.

[0077] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, the material of the dielectric layer 110 may be insulating dielectric materials such as oxides, nitrides, and nitride oxides such as silicon nitride, silicon oxide, aluminum nitride, aluminum oxide, silicon oxynitride, and aluminum oxynitride.

[0078] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 2-Figure 4 As shown, the thickness of the dielectric layer 10 can be 5-50 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0079] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 5 As shown, Figure 5 for Figure 1 In the partially enlarged schematic diagram, the width W1 of the second hollow V2 along the direction perpendicular to the length of the gate 81 (for example, the horizontal direction) is smaller than the width W2 of the P-cap layer 82 along the direction perpendicular to the length of the gate 81 (the horizontal direction), for example, W1 is 0.7 to 0.9 times of W2; the width W1 of the second hollow V2 along the length direction (the vertical direction) of the gate 81 is smaller than the width W2 of the P-cap layer 82 along the direction perpendicular to the length of the gate 81 (the horizontal direction). hole Smaller than the width W of the P-cap layer 82 along the length direction of the gate 81 P-GaN , for example W hole W P-GaN 0.7~0.9 times of.

[0080] In some embodiments, in order to cleanly etch the pGaN at the recessed gate position to form a recessed gate, in the enhancement-mode gallium nitride device provided in the embodiment of the present disclosure, as Figure 5 As shown, the width W3 of the groove 51 along the direction perpendicular to the length of the gate 81 (lateral direction) is greater than or equal to 1.1 times the width W2 of the P-cap layer 82 along the direction perpendicular to the length of the gate 81 (lateral direction).

[0081] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 5 As shown, the width W3 of the groove 51 along the direction perpendicular to the length of the gate 81 (lateral direction) is less than or equal to 1.3 times the width W2 of the P-cap layer 82 along the direction perpendicular to the length of the gate 81 (lateral direction).

[0082] In some embodiments, in the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure, if Figure 5 As shown, the width W of the P-cap layer 82 along the length direction of the gate 81 can be adjusted. P-GaN The width W of the groove 51 along the length direction (longitudinal direction) of the gate 81 is RMOS The ratio of the P-cap layer gate and the groove gate is changed in the CC' direction to adjust the transconductance of the composite gate structure 8, so as to adjust the transconductance half-peak width of the groove gate and the P-cap layer gate, thereby selecting the W corresponding to the better transconductance half-peak width. P-GaN With W RMOS size.

[0083] The following is an explanation of the principle of achieving high linearity of the enhanced gallium nitride device provided by the embodiment of the present disclosure by achieving transconductance half-width widening. Fig. 6A As shown, Fig. 6A Schematic diagram showing that the P-cap gate HEMT (denoted by A1) and the groove gate HEMT (denoted by A2) have different transconductance peak positions. Fig. 6A The transconductance (G m ) peak at gate voltage (V gs ) appears when it is 2.7V; the transconductance (G m ) peak at gate voltage (V gs ) is 4V. The half-peak width of transconductance of these two devices is 1.65V and 2.3V respectively. The half-peak width of transconductance is the gate voltage range in which the transconductance of the device is maintained at half the peak value. Figure 6B As shown, Figure 6B for Fig. 6A The gate voltages corresponding to the two transconductances in gs ) and the drain current (I ds) relationship diagram, it can be seen that the half-peak width of transconductance can be regarded as an intuitive standard for measuring the linear region of the device. The half-peak width of transconductance corresponding to A1 is 1.65V, which also corresponds to the drain current of the P-cap layer gate (I ds ) linear region, the transconductance half-peak width of A2 is 2.3V, which also corresponds to the drain current of the groove gate (I ds ) Linear region range.

[0084] like Figure 6C As shown, Figure 6C Schematic diagram of the transconductance distribution of the composite gate structure provided in the embodiment of the present disclosure, where curve D is W P-GaN With W RMOS The corresponding transconductance distribution diagram when the ratio is 1:1, curve E is W P-GaN With W RMOS The transconductance distribution diagram corresponding to the ratio of 1:1.5, curve F is W P-GaN With W RMOS The schematic diagram of the transconductance distribution when the ratio is 1:2. It can be seen that by adjusting W P-GaN With W RMOS The ratio of W can adjust the transconductance distribution of the composite gate structure, widen the transconductance half-peak width of the composite gate structure, and improve the linearity of the device. P-GaN With W RMOS When the ratio of W is mixed in the ratio of 1:1 and 1:2, the half-peak width of transconductance is increased to 2.85V; P-GaN With W RMOS When the ratio is adjusted to 1:1.5, the half-peak width of the transconductance is optimized to 2.95V. Therefore, the transconductance of the composite gate structure has a wider area maintained at a high peak position, such as Fig.6D As shown, Fig.6D for Figure 6C The gate voltages (V gs ) and the drain current (I ds ) relationship diagram, it can be seen that the drain current (I ds ) The linear region range is increased, thereby achieving high linearity of the device.

[0085] like Figure 6A-6DAs shown, the composite gate structure provided by the embodiment of the present disclosure can improve the linearity of the device because it can adjust the transconductance value distribution of the composite gate structure, thereby widening the transconductance half-width of the composite gate structure and improving the linearity of the device. The combination ratio of the P-cap layer gate and the groove gate in the CC' direction can be adjusted, which will affect the transconductance peak position of the device and the size of the transconductance half-width. By adjusting the width ratio of these structures, the transconductance value distribution of the composite gate structure can be changed, thereby widening the transconductance half-width. When the P-cap layer gate and the groove gate are mixed in the CC' direction with different width ratios, the transconductance half-width will change accordingly. When the P-cap layer gate and the groove gate are mixed in the CC' direction with a specific ratio, the transconductance half-width will increase, thereby improving the linearity of the device. By reasonably adjusting the width ratio of these structures, the performance of the enhanced gallium nitride device can be optimized, so that it has a wider linear region, thereby improving the overall linearity.

[0086] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned enhanced gallium nitride device. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned enhanced gallium nitride device, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned enhanced gallium nitride device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0087] In some embodiments, the method for preparing the enhancement-mode gallium nitride device provided in the embodiments of the present disclosure is as follows: Figure 7 As shown, it may include:

[0088] S701, forming a stacked nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-cap layer in sequence on one side of the substrate in a direction away from the substrate;

[0089] S702, etching the P-cap layer to remove the P-cap layer outside the gate region;

[0090] S703, etching the remaining P-cap layer and its corresponding barrier layer, removing a portion of the P-cap layer corresponding to the gate region to form a final P-cap layer, and forming a groove that penetrates a portion of the thickness of the barrier layer, wherein the final P-cap layer and the groove are arranged along the length direction of the gate region;

[0091] S704 , depositing a gate metal on the side of the final P-cap layer facing away from the substrate, etching the gate metal, removing the gate metal outside the gate region, and forming a gate.

[0092] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, after performing the above-mentioned step S702 to etch the P-cap layer, and before performing the above-mentioned step S703 to etch the remaining P-cap layer and the corresponding barrier layer, as follows Figure 8 As shown, step S801 can also be performed: depositing an ohmic contact metal on the side of the remaining P-cap layer facing away from the substrate, and etching the ohmic contact metal to remove the ohmic contact metal outside the source region and the drain region to form a source and a drain respectively contacting the channel layer.

[0093] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, after performing the above-mentioned step S702 and etching the P-cap layer, and before performing the above-mentioned step S801 and depositing the ohmic contact metal on the side of the remaining P-cap layer away from the substrate, as Figure 8 As shown, step S802 can also be performed: depositing a passivation layer on the side of the remaining P-cap layer facing away from the substrate; at this time, "depositing an ohmic contact metal on the side of the remaining P-cap layer facing away from the substrate" in step S801 is modified to "depositing an ohmic contact metal on the side of the passivation layer facing away from the substrate".

[0094] When the remaining P-cap layer and its corresponding barrier layer are etched in step S703, Figure 8 As shown, the method may further include: etching the passivation layer at the same time to remove the passivation layer corresponding to the groove position.

[0095] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, after performing the above-mentioned step S703 to etch the remaining P-cap layer and its corresponding barrier layer, and before performing the above-mentioned step S704 to deposit the gate metal on the side of the final P-cap layer away from the substrate, as shown in FIG. Figure 8 As shown, steps S803 and S804 may also be performed:

[0096] S803, depositing a dielectric layer on a side of the passivation layer facing away from the substrate, wherein the dielectric layer contacts the bottom and sidewall of the groove;

[0097] S804, etching the dielectric layer and the passivation layer to remove the remaining passivation layer corresponding to the gate region to form a first hollow corresponding to the gate on the passivation layer, and forming a second hollow corresponding to the final P-cap layer on the dielectric layer.

[0098] At this time, the step S704 of “depositing gate metal on the side of the final P-cap layer facing away from the substrate” is modified to “depositing gate metal on the side of the dielectric layer facing away from the substrate”.

[0099] In order to better understand the above preparation method provided in the embodiment of the present disclosure, the present disclosure forms Figure 2 and Figure 3 Taking the combined enhancement-mode gallium nitride device as an example, the preparation process of the enhancement-mode gallium nitride device is described in detail.

[0100] preparation Figure 2 and Figure 3 The specific process of the combined enhancement-mode GaN device is as follows:

[0101] (1) If Fig. 9A As shown, a substrate 1 is selected, and a stacked nucleation layer 2, a buffer layer 3, a channel layer 4, an insertion layer (not shown), a barrier layer 5, and a P-cap layer 82 are sequentially formed on one side of the substrate 1 along a direction away from the substrate 1.

[0102] (2) If Fig. 9B As shown, the P-cap layer 82 is etched to remove the P-cap layer 82 outside the gate region to form a conductive channel.

[0103] (3) If Fig. 9C As shown, a passivation layer 9 is deposited on the side of the remaining P-cap layer 82 facing away from the substrate 1. For example, the material of the passivation layer 9 is an aluminum nitride layer grown using atomic layer deposition technology and a silicon oxide layer grown using PECVD.

[0104] (4) If Fig.9D As shown, the passivation layer 9, the barrier layer 5 and the insertion layer are etched to remove the passivation layer 9, the barrier layer 5 and the insertion layer in the source region and the drain region, and through holes corresponding to the source region and the drain region are formed on the barrier layer 5 and the passivation layer 9.

[0105] (5) Fig.9E As shown, an ohmic contact metal is deposited on the side of the passivation layer 9 facing away from the substrate 1, and the ohmic contact metal is etched to remove the ohmic contact metal outside the source region and the drain region, and is rapidly annealed in a nitrogen or argon atmosphere to form a source 6 and a drain 7 that are in contact with the channel layer 4 through the through holes, respectively.

[0106] (6) If Fig.9E and Fig. 10A As shown, the remaining P-cap layer 82 and the corresponding barrier layer 5 are etched, and the passivation layer 9 is etched at the same time, and the part of the P-cap layer 82 corresponding to the gate area is removed to form the final P-cap layer 82, and a groove 51 that penetrates the thickness of the barrier layer 5 is formed to increase the threshold voltage of the groove gate, and the passivation layer 9 corresponding to the position of the groove 51 is removed at the same time, and the final P-cap layer 82 and the groove 51 are arranged along the length direction of the gate area. Specifically, the protruding positions of the passivation layer 9 on both sides above the groove 51 and the barrier layer 5 below the protrusion can also be etched away.

[0107] (7) Fig.9F and Fig. 10B As shown, a dielectric layer 10 is deposited on the side of the passivation layer 9 facing away from the substrate 1 , and the dielectric layer 10 is in contact with the bottom and sidewall of the groove 51 .

[0108] (8) Figure 9GAs shown, the dielectric layer 10 and the passivation layer 9 are etched to remove the remaining passivation layer 9 corresponding to the gate area to form a first hollow V1 corresponding to the gate area on the passivation layer 9, and a second hollow V2 corresponding to the final P-cap layer 82 is formed on the dielectric layer 10.

[0109] (9) Figure 9H and Fig. 10C As shown, a gate metal is deposited on the side of the dielectric layer 10 facing away from the substrate 1 , and the gate metal is etched to remove the gate metal outside the gate region to form a gate 81 .

[0110] pass Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G and Figure 9H Formed Figure 2 The structure shown, through Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig. 10A , Fig. 10B and Fig. 10C Formed Figure 3 The structure shown in the figure forms the embodiment of the present disclosure. Figure 1 Enhancement-mode GaN device shown.

[0111] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including the enhanced gallium nitride device provided in the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the enhanced gallium nitride device, the implementation of the electronic device provided in the embodiment of the present disclosure can refer to the implementation of the enhanced gallium nitride device provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0112] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, in addition to enhanced gallium nitride devices, the electronic devices provided by the present disclosure may also include other structures, for example, when the electronic device is a radar, it also includes: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it also includes: input ports, output ports, etc.

[0113] An enhancement-mode gallium nitride device and a preparation method thereof and an electronic device provided by the embodiments of the present disclosure realize a three-dimensional structured gate by arranging a groove gate and a P-cap layer gate in a gate region along a gate length direction. On the one hand, the threshold voltage of the gallium nitride device can be effectively improved to realize an enhancement-mode gallium nitride device. On the other hand, the groove gate can adjust its threshold voltage and the gate-source voltage point corresponding to the transconductance peak by changing the etching depth of the groove, so that the gate-source voltage points corresponding to the transconductance peaks corresponding to the groove gate and the P-cap layer gate are misaligned. When the transconductance of the P-cap layer gate is reduced, the transconductance value of the groove gate can be increased, and the transconductance values ​​of the P-cap layer gate and the groove gate are complementary, thereby realizing the overall transconductance half-peak width widening of the composite gate structure and improving the linearity of the enhancement-mode gallium nitride device.

[0114] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0115] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An enhancement-mode gallium nitride device, characterized in that: include: A substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a composite gate structure sequentially stacked on the substrate in a direction away from the substrate; The composite gate structure comprises: a gate located on a side of the barrier layer away from the substrate, and a P-cap layer and a groove located on a side of the gate facing the barrier layer and arranged along the length direction of the gate; the P-cap layer is located between the barrier layer and the gate, and the groove is provided on a side of the barrier layer facing the gate; A ratio of a width of the P-cap layer along the gate length direction to a width of the groove along the gate length direction is greater than or equal to 1:2 and less than 1:

1.

2. The enhancement-mode gallium nitride device according to claim 1, characterized in that: The number of the P-cap layer and the number of the grooves are both plural, and the P-cap layer and the grooves are alternately arranged along the length direction of the gate.

3. The enhancement-mode gallium nitride device according to claim 1, characterized in that: It also includes a source and a drain located on both sides of the barrier layer, the source and the drain are respectively in contact with the channel layer, and the orthographic projection of the composite gate structure on the substrate is located between the orthographic projections of the source and the drain on the substrate.

4. The enhancement-mode gallium nitride device according to claim 3, characterized in that: It also includes a passivation layer located between the P-cap layer and the gate, the source, and the drain. The passivation layer includes a first hollow, and the orthographic projection of the first hollow on the substrate overlaps with the orthographic projection of the gate on the substrate.

5. The enhancement-mode gallium nitride device according to claim 4, characterized in that: It also includes a dielectric layer located between the gate and the source and the drain, the dielectric layer includes a second hollow, the orthographic projection of the second hollow on the substrate is located within the orthographic projection range of the P-cap layer on the substrate, and the dielectric layer is in contact with the bottom and side walls of the groove.

6. The enhancement-mode gallium nitride device according to claim 5, characterized in that: The width of the second hollow along the direction perpendicular to the gate length is smaller than the width of the P-cap layer along the direction perpendicular to the gate length. The width of the second hollow along the gate length is smaller than the width of the P-cap layer along the gate length.

7. The enhancement-mode gallium nitride device according to claim 6, characterized in that: The width of the second hollow along the direction perpendicular to the gate length is 0.7 to 0.9 times the width of the P-cap layer along the direction perpendicular to the gate length, and the width of the second hollow along the gate length is 0.7 to 0.9 times the width of the P-cap layer along the gate length.

8. The enhancement-mode gallium nitride device according to claim 1, characterized in that: The width of the groove along the direction perpendicular to the gate length is greater than or equal to 1.1 times the width of the P-cap layer along the direction perpendicular to the gate length.

9. The enhancement-mode gallium nitride device according to claim 8, characterized in that: The width of the groove along the direction perpendicular to the gate length is less than or equal to 1.3 times the width of the P-cap layer along the direction perpendicular to the gate length.

10. The enhancement-mode gallium nitride device according to any one of claims 1 to 9, characterized in that: The material of the channel layer is GaN, the material of the barrier layer is AlGaN, and the material of the P-cap layer is Mg-doped GaN.

11. The enhancement-mode gallium nitride device according to any one of claims 1 to 9, characterized in that: The thickness of the P-cap layer is 50-150 nm, the thickness of the barrier layer corresponding to the position of the P-cap layer is 15-30 nm, and the thickness of the barrier layer corresponding to the position of the groove is 0-10 nm.

12. The enhancement-mode gallium nitride device according to claim 5, characterized in that: The thickness of the dielectric layer is 5-50 nm.

13. A method for preparing an enhancement-mode gallium nitride device, used for preparing the enhancement-mode gallium nitride device according to any one of claims 1 to 12, characterized in that: The preparation method comprises: On one side of the substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-cap layer are sequentially formed in a stacked manner in a direction away from the substrate; Etching the P-cap layer to remove the P-cap layer outside the gate region; Etching the remaining P-cap layer and the corresponding barrier layer, removing a portion of the P-cap layer corresponding to the gate region to form a final P-cap layer, and forming a groove that penetrates a portion of the barrier layer thickness, wherein the final P-cap layer and the groove are arranged along the length direction of the gate region; A gate metal is deposited on the side of the final P-cap layer facing away from the substrate, and the gate metal is etched to remove the gate metal outside the gate region to form a gate.

14. The preparation method according to claim 13, characterized in that: After etching the P-cap layer and before etching the remaining P-cap layer and the corresponding barrier layer, the method further includes: An ohmic contact metal is deposited on the side of the remaining P-cap layer facing away from the substrate, and the ohmic contact metal is etched to remove the ohmic contact metal outside the source region and the drain region to form a source and a drain respectively contacting the channel layer.

15. The preparation method according to claim 14, characterized in that: After etching the P-cap layer and before depositing an ohmic contact metal on the side of the remaining P-cap layer facing away from the substrate, the method further includes: depositing a passivation layer on the side of the remaining P-cap layer facing away from the substrate; When etching the remaining P-cap layer and the corresponding barrier layer, the method further includes: etching the passivation layer to remove the passivation layer corresponding to the groove position.

16. The preparation method according to claim 15, characterized in that: After etching the remaining P-cap layer and the corresponding barrier layer, and before depositing a gate metal on the side of the final P-cap layer away from the substrate, the method further includes: Depositing a dielectric layer on a side of the passivation layer away from the substrate, wherein the dielectric layer is in contact with the bottom and sidewall of the groove; The dielectric layer and the passivation layer are etched to remove the remaining passivation layer corresponding to the gate region to form a first hollow corresponding to the gate on the passivation layer, and a second hollow corresponding to the final P-cap layer is formed on the dielectric layer.

17. An electronic device, characterized in that: Comprising the enhancement-mode gallium nitride device as described in any one of claims 1 to 12.

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