Semiconductor device

Abstract

A semiconductor device includes: an oxide semiconductor layer; a first electrode and a second electrode disposed spaced apart from each other and adjacent to the oxide semiconductor layer, respectively; a metal oxide layer disposed between the oxide semiconductor layer and at least one of the first electrode and the second electrode; and a metal nitride layer disposed between the metal oxide layer and the oxide semiconductor layer.

Description

Technical Field

[0001] Various example embodiments relate to semiconductor devices and / or methods of manufacturing semiconductor devices. Background Art

[0002] A transistor is a semiconductor device that performs an electrical switching function and is used in various integrated circuit (IC) devices (including one or more of a memory, a driver IC, a logic device, etc.) In order to increase the integration of IC devices, the space occupied by the transistor included in the IC device has been reduced, and research is being conducted to reduce the size of the transistor while maintaining the performance of the transistor.

[0003] Oxide semiconductor devices are transparent semiconductor devices characterized by a wide bandgap of 3.0 eV or more and have been studied for many years. Oxide semiconductor devices used for large-area display drive devices have characteristics such as low off current, high on / off ratio and other electrical characteristics. By applying oxide semiconductor devices having the above characteristics to memory or logic devices or stacking oxide semiconductor devices on Si-based devices, the integration can be improved.

[0004] However, the short channel effect caused by the scaling down of the oxide semiconductor device may degrade the performance of the oxide semiconductor device. For example, as one or more of the width, length, thickness, etc. of the channel layer decreases, it is difficult to control the threshold voltage (Vth), and the reduced contact area between the channel layer and the source / drain may increase the contact resistance. More specifically, when an oxide semiconductor layer is formed on a source / drain formed of a metal material by using a precursor, the reaction between the precursor and the metal material may increase the contact resistance. Summary of the invention

[0005] A semiconductor device including a metal nitride layer is provided.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to some example embodiments, a semiconductor device includes: an oxide semiconductor layer; a first electrode and a second electrode, respectively adjacent to the oxide semiconductor layer and spaced apart from each other; a metal oxide layer, between at least one of the first electrode and the second electrode and the oxide semiconductor layer; a metal nitride layer, between the metal oxide layer and the oxide semiconductor layer; a gate electrode, spaced apart from the oxide semiconductor layer; and a gate insulating layer, arranged between the oxide semiconductor layer and the gate electrode.

[0008] The metal nitride layer may include oxygen. At least one of a thickness of the metal oxide layer and a thickness of the metal nitride layer may be smaller than a thickness of the oxide semiconductor layer.

[0009] The thickness of the oxide semiconductor layer can be 10 nm or less.

[0010] The length of the oxide semiconductor layer may be less than 1 micrometer.

[0011] The thickness of the metal oxide layer may be 5 nm or less.

[0012] The thickness of the metal oxide layer may be from about 0.5 nm to about 3.5 nm.

[0013] The thickness of the metal nitride layer may be 10 nm or less.

[0014] The thickness of the metal oxide layer may be 0.2 to 2 times the thickness of the metal nitride layer.

[0015] The thickness of the metal oxide layer may be less than or equal to 25% of the thickness of the first electrode.The metal oxide layer may include the same metal as a metal included in an electrode contacting the metal oxide layer from the first electrode and the second electrode.

[0016] The metal oxide layer may include at least one of W, Co, Ni, Fe, Ti, Mo, Cr, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Sn, V, Ru, Pt, Zn, and Mg.

[0017] The metal nitride layer may include at least one of Ga, W, Zn, V, and Ti.

[0018] The surface of at least one of the first electrode and the second electrode may be stepped by the metal oxide layer.

[0019] The width of the metal nitride layer may be greater than or equal to the width of the oxide semiconductor layer.

[0020] A difference between a width of the oxide semiconductor layer and a width of the metal nitride layer may be greater than or equal to a difference between a width of the oxide semiconductor layer and a width of the metal oxide layer.

[0021] The first electrode, the metal oxide layer, the metal nitride layer, the oxide semiconductor layer, and the second electrode may be sequentially arranged in a thickness direction of the first electrode.

[0022] The metal oxide layer may include a first metal oxide layer disposed between the first electrode and the oxide semiconductor layer and a second metal oxide layer disposed between the second electrode and the oxide semiconductor layer, and the metal nitride layer may be disposed between at least one of the first metal oxide layer and the second metal oxide layer and the oxide semiconductor layer.

[0023] The metal nitride layer may include a first metal nitride layer between the first metal oxide layer and the oxide semiconductor layer and a second metal nitride layer disposed between the second metal oxide layer and the oxide semiconductor layer.

[0024] The thickness of the first metal oxide layer may be different from the thickness of the second metal oxide layer.

[0025] Semiconductor devices can be manufactured through atomic layer deposition processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a diagram showing a thin film structure according to some example embodiments;

[0028] FIG. 2A to FIG. 2C Transmission electron micrograph (TEM) images and energy dispersive X-ray spectroscopy (EDS) analysis results showing a thin film structure including a metal layer, a metal oxide layer, a metal nitride layer, and an oxide semiconductor layer;

[0029] Figure 3 TEM images and EDS analysis results showing a thin film structure including a metal layer, a metal oxide layer, and an oxide semiconductor layer according to a comparative example;

[0030] Figure 4 is a graph showing IV characteristics of transistors according to examples and comparative examples;

[0031] Figure 5 is a diagram illustrating a semiconductor device including a metal oxide layer and a metal nitride layer according to some example embodiments;

[0032] Figure 6 is a diagram illustrating a semiconductor device according to some example embodiments;

[0033] Figure 7 is a diagram illustrating a semiconductor device according to some example embodiments;

[0034] Figure 8 is a diagram illustrating a semiconductor device according to some example embodiments;

[0035] Fig. 9 is a diagram illustrating a semiconductor device according to some example embodiments;

[0036] Fig.10 is a diagram illustrating a semiconductor device according to some example embodiments;

[0037] Fig.11 is a diagram illustrating a semiconductor device according to some example embodiments;

[0038] Fig.12 is a diagram illustrating a semiconductor device according to some example embodiments;

[0039] Fig.13 is a diagram illustrating a semiconductor device according to some example embodiments;

[0040] Fig.14 is a diagram illustrating a semiconductor device according to some example embodiments;

[0041] Fig.15 is a diagram illustrating a semiconductor device according to some example embodiments;

[0042] Figures 16 to 24 are reference diagrams for explaining a method of manufacturing a semiconductor device according to some example embodiments;

[0043] Fig.25 is a circuit diagram of a complementary metal oxide semiconductor (CMOS) inverter according to some example embodiments;

[0044] Fig.26 is a circuit diagram of a CMOS static random access memory (SRAM) device according to some example embodiments;

[0045] Fig. 27 is a circuit diagram of a CMOS NAND circuit according to some example embodiments;

[0046] Fig.28 is a block diagram illustrating an electronic system according to some example embodiments; and

[0047] Fig.29 is a block diagram illustrating an electronic system according to some example embodiments. DETAILED DESCRIPTION

[0048] Reference will now be made in detail to some embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, example embodiments are described below with reference to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Expressions such as "at least one of...", when following a column of elements, modify the entire column of elements, rather than modifying individual elements in the list.

[0049] Hereinafter, a semiconductor device and / or a method of manufacturing the semiconductor device will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals denote the same components, and the sizes of the components may be exaggerated for clarity and convenience of description.

[0050] Expressions used in the singular include expressions in the plural unless they have clearly different meanings in the context. When a part "includes" a component, unless otherwise described, another component may also be included, rather than excluding the presence of another component. For ease of explanation, the size or thickness of the components in the drawings may be arbitrarily enlarged. In addition, when a material layer is described as being arranged on a substrate or another layer, the material layer may be in contact with the substrate or another layer, or a third layer may be present between the material layer and the substrate or another layer. In an embodiment, the materials constituting each layer are provided only as examples, and other materials may also be used.

[0051] In addition, the terms "part", "module" and the like refer to a unit that processes at least one function or operation and can be implemented by hardware, software or a combination thereof.

[0052] The specific implementations shown and described herein are illustrative examples of implementations and are not intended to otherwise limit the scope of the implementations in any way.For the sake of brevity, conventional electronics, control systems, software development of systems and other functional aspects may not be described in detail.

[0053] Furthermore, the connecting lines or connectors shown in the various figures presented are intended to represent exemplary functional relationships and / or physical or logical connections between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may exist in a practical device.

[0054] The use of the terms "a," "an," and "the" and similar referents in the context of describing embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural.

[0055] In addition, unless otherwise described herein or clearly contradicted by context, the steps of all methods described herein can be performed in any suitable order. Unless otherwise stated, the use of any and all exemplary language (e.g., "such as") provided herein is only intended to better illustrate the technical idea and does not limit the scope of the rights.

[0056] Expressions such as "at least" used to list elements are intended to limit the list of all elements rather than the individual elements in the list. For example, expressions such as "at least one of A, B, and C" or "at least one selected from the group consisting of A, B, and C" can be interpreted as only A, only B, only C, or a combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0057] When terms such as "approximately" or "substantially" are used with respect to a numerical value, the relevant numerical value may be interpreted as including manufacturing or operating deviations (e.g., ±10%) of the numerical value. In addition, when expressions such as "approximately" and "substantially" are used with respect to geometric shapes, geometric precision may not be required, and it is intended that the degree of tolerance with respect to the shape is within the scope of the embodiments of the present disclosure. In addition, regardless of whether a shape or numerical value is defined by the use of "approximately" or "substantially", such numerical values ​​or shapes should be understood to include manufacturing or operating deviations (e.g., ±10%) of the numerical value.

[0058] Although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another component.

[0059] The use of any and all examples, or exemplary language provided herein, is intended merely to better illustrate the technical concepts and does not pose a limitation on the scope of the embodiments unless otherwise claimed.

[0060] Figure 1 is a diagram illustrating a thin film structure 10 according to various example embodiments. Figure 1 The thin film structure 10 may be a component of a semiconductor device, for example, may be included in a semiconductor device. Figure 1 The thin film structure 10 may include a metal layer 11 , a metal oxide layer 12 disposed on the metal layer 11 , a metal nitride layer 13 disposed on the metal oxide layer 12 , and an oxide semiconductor layer 14 disposed on the metal nitride layer 13 .

[0061] The metal layer 11 may include at least one of tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sn), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg). When the thin film structure 10 is applied to a semiconductor device, the metal layer 11 may be an electrode of the semiconductor device, such as but not limited to a gate electrode, a source electrode, a drain electrode, or a body electrode.

[0062] The metal oxide layer 12 may be disposed on the metal layer 11. The metal included in the metal oxide layer 12 may be the same as the metal included in the metal layer 11. For example, the metal oxide layer 12 may include at least one of W, Co, Ni, Fe, Ti, Mo, Cr, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Sn, V, Ru, Pt, Zn, and Mg.

[0063] The content of oxygen included in the metal oxide layer 12 may vary or be changed from the metal layer 11 toward the oxide semiconductor layer 14. For example, the content of oxygen included in the metal oxide layer 12 may decrease as the distance from the oxide semiconductor layer 14 increases.

[0064] In the process of forming the oxide semiconductor layer 14 or manufacturing a semiconductor device or an electronic device including the thin film structure 10, the metal oxide layer 12 can be formed by reacting a metal source on the metal layer 11 and / or oxidizing the metal of the metal layer 11 by heat treatment, etc. The interface between the metal layer 11 and the metal oxide layer 12 may be unclear or have no fixed shape or not exist. For example, the metal oxide layer 12 may be formed as a part of the metal layer 11. The metal oxide layer 12 may be formed discontinuously or continuously on the metal layer 11.

[0065] The metal nitride layer 13 may be disposed on the metal oxide layer 12. The electrical conductivity of the metal nitride layer 13 may be greater than the electrical conductivity of the oxide semiconductor layer 14 and may be less than the electrical conductivity of the metal layer 11. The metal included in the metal nitride layer 13 may be different from the metal included in the metal layer 11. The metal nitride layer 13 may include a metal that does not react with oxygen and remains stable, or include a metal that has higher oxidation reactivity than the metal included in the metal layer 11 but remains conductive even when the metal is oxidized.

[0066] The metal nitride layer 13 may include at least one of gallium (Ga), Mo, W, Zn, V, and Ti. For example, when the metal layer 11 includes W, the metal nitride layer 13 may include GaN; example embodiments are not limited thereto.

[0067] The metal nitride layer 13 may further include oxygen. The content (at%) of oxygen included in the metal nitride layer 13 may be greater than or equal to the content of oxygen included in the metal oxide layer 12. The oxygen included in the metal nitride layer 13 may be included by directly adding (e.g., injecting) an oxygen source when forming the metal nitride layer 13 and / or during a subsequent process such as forming the metal oxide layer 12. For example, when forming the oxide semiconductor layer 14 on the metal nitride layer 13 and / or manufacturing the oxide semiconductor layer 14 including Figure 1 In a process of manufacturing a semiconductor device or an electronic apparatus of the thin film structure 10 , oxygen may flow into the metal nitride layer 13 .

[0068] The cross-sectional area of ​​the metal nitride layer 13 may be greater than or equal to the cross-sectional area of ​​the metal oxide layer 12. The width of the metal nitride layer 13 may be greater than or equal to the width of the metal oxide layer 12. For example, a portion of the lower surface of the metal nitride layer 13 may be in contact with the metal oxide layer 12, and another portion of the lower surface of the metal nitride layer 13 may be in contact with the metal layer 11. In some example embodiments, the metal nitride layer 13 may surround the metal oxide layer 12.

[0069] The oxide semiconductor layer 14 may be disposed on the metal nitride layer 13. The oxide semiconductor layer 14 according to some example embodiments may include at least one oxide of at least one material selected from at least one of group 12, 13, and 14 elements such as, but not limited to, Zn, indium (In), Ga, Sn, cadmium (Cd), germanium (Ge), or Hf, and combinations thereof. For example, the oxide semiconductor layer 14 may include a Zn oxide-based material such as Zn oxide, In-Zn oxide, In-Ga-Zn oxide, etc. For example, the oxide semiconductor layer 14 may have a single-layer structure or a multi-layer structure.

[0070] In the thin film structure 10, interfaces among the metal layer 11, the metal oxide layer 12, the metal nitride layer 13, and the oxide semiconductor layer 14 may be unclear, have no fixed shape, or not exist.

[0071] The thin film structure 10 can be applied to a semiconductor device having a channel length of less than 1 μm, about 500 nm or less, or about 50 nm or less. To this end, the metal layer 11, the metal oxide layer 12, the metal nitride layer 13, and the oxide semiconductor layer 14 can be formed to have an ultra-thin thickness by an atomic layer deposition (ALD) method. The ALD method can be performed using a plasma enhanced chemical vapor deposition (PECVD) process and / or a low pressure CVD (LPCVD) process; however, the example embodiments are not limited thereto. The ALD method can be performed without using a sputtering process such as a physical vapor deposition (PVD) process.

[0072] Since the ALD method is performed at a higher temperature than the sputtering process and uses a material with high reactivity as a deposition material, other layers may be affected during the deposition of the target layer. For example, when the oxide semiconductor layer 14 is formed on the metal layer 11 or directly on the metal layer 11 by the ALD method, the oxygen source of the oxide semiconductor layer 14 may react with and / or diffuse to the metal layer 11 adjacent thereto, and the interface resistance may increase, such as in a conventional process.

[0073] The thin film structure 10 according to some example embodiments may include a metal oxide layer 12 and a metal nitride layer 13 between the metal layer 11 and the oxide semiconductor layer 14, thereby improving the performance of the semiconductor device. For example, due to the low reactivity of the metal nitride layer 13 to oxygen, the oxygen source may not pass through the metal nitride layer 13 or may not diffuse through the metal nitride layer 13, and therefore, during the process of forming the oxide semiconductor layer 14 and / or manufacturing a semiconductor device or electronic device including the thin film structure 10, the possibility of the reaction between the metal layer 11 and the oxygen source and / or the possibility of the influence occurring may be substantially prevented or reduced. Alternatively or additionally, the metal included in the metal nitride layer 13 may have a higher reactivity to oxygen than the metal included in the metal layer 11, and the movement or diffusion of oxygen may be restricted.

[0074] The thickness of the metal layer 11 may be about 20 nm or less. For example, the thickness of the metal layer 11 may be about 1 nm or more, about 3 nm or more, or about 5 nm or more, and may be about 15 nm or less, about 10 nm or less, or about 7 nm or less.

[0075] The thickness of the metal oxide layer 12 may be about 5 nm or less. For example, the thickness of the metal oxide layer 12 may be about 0.1 nm or more, about 0.5 nm or more, or about 1 nm or more, and may be about 3 nm or less, about 3.5 nm or less, about 4 nm or less, or about 5 nm or less. Alternatively, the thickness of the metal oxide layer 12 may be about 0.5 nm to about 3.5 nm.

[0076] The thickness of the metal nitride layer 13 may be about 10 nm or less. The thickness of the metal nitride layer 13 may be about 0.1 nm or more, about 0.3 nm or more, about 0.5 nm or more, about 0.8 nm or more, or about 1 nm or more, and may be about 8 nm or less, about 7 nm or less, about 6 nm or less, or about 5 nm or less.

[0077] The thickness of the oxide semiconductor layer 14 may be about 10 nm or less, about 8 nm or less, or about 7 nm or less.

[0078] The thickness of each of the metal layer 11 , the metal oxide layer 12 , the metal nitride layer 13 , and the oxide semiconductor layer 14 may refer to an average thickness.

[0079] The thickness of the metal layer 11, the metal oxide layer 12, the metal nitride layer 13, and the oxide semiconductor layer 14 can be measured from energy dispersive X-ray spectroscopy (EDS). More specifically, the thickness of the metal layer 11, the metal oxide layer 12, the metal nitride layer 13, and the oxide semiconductor layer 14 can be measured from the thickness of the region where the elements constituting each of the metal layer 11, the metal oxide layer 12, the metal nitride layer 13, and the oxide semiconductor layer 14 are detected. For example, when the metal oxide layer 12 includes tungsten oxide, the region from which tungsten and oxygen are simultaneously detected according to the EDS analysis result can be considered to be the thickness of the tungsten oxide. Alternatively or additionally, the region in which the tungsten content is sharply reduced and the oxygen content is sharply increased according to the EDS analysis result can be considered to be the thickness of the tungsten oxide.

[0080] The thin film structure 10 according to some example embodiments may have an appropriate thickness ratio between the metal layer 11, the metal oxide layer 12, the metal nitride layer 13, and the oxide semiconductor layer 14. Since the metal oxide layer 12 has a high resistance characteristic when its thickness is greater than or equal to a specific value, the characteristics of the semiconductor device may be degraded. For example, the density of the on-current flowing in the metal layer 11 and the oxide semiconductor layer 14 may drop sharply. The thickness of the metal nitride layer 13 may control the thickness of the metal oxide layer 12. For example, the greater the thickness of the metal nitride layer 13, the thinner the thickness of the metal oxide layer 12 may be. Since the greater thickness of the metal nitride layer 13 leads to an increased size of the thin film structure 10 or a semiconductor device including the thin film structure 10, the thickness of the metal nitride layer 13 may be at most twice the thickness of the oxide semiconductor layer 14.

[0081] The thickness of the metal oxide layer 12 may be less than the thickness of the metal layer 11. The thickness of the metal oxide layer 12 may be less than or equal to about 25% of the thickness of the metal layer 11, less than or equal to about 20% of the thickness of the metal layer 11, or less than or equal to about 18% of the thickness of the metal layer 11, and may be greater than or equal to 1% of the thickness of the metal layer 11.

[0082] The thickness of the metal oxide layer 12 may be at most about 5 times the thickness of the oxide semiconductor layer 14. The thickness of the metal oxide layer 12 may be at most about 3 times, about 2 times, about 1.5 times, about 1.0 times, or about 0.5 times the thickness of the oxide semiconductor layer 14, and may be greater than or equal to about 1%, about 5%, or about 10% of the thickness of the oxide semiconductor layer 14.

[0083] The thickness of the metal oxide layer 12 may be at most 10 times the thickness of the metal nitride layer 13. The thickness of the metal oxide layer 12 may be at most about 5 times, about 2.5 times, about 2 times, or about 1 times the thickness of the metal nitride layer 13, and may be at least about 0.05 times, about 0.1 times, or about 0.2 times the thickness of the metal nitride layer 13. Alternatively, the thickness of the metal oxide layer 12 may be about 0.2 times to about 2 times the thickness of the metal nitride layer 13.

[0084] FIG. 2A to FIG. 2C TEM images and EDS analysis results of thin film structures formed by using the ALD method according to some example embodiments are shown. More specifically, it is confirmed that the thin film structures according to various example embodiments sequentially include a metal layer including tungsten (W), a metal oxide layer including tungsten oxide (WOx), a metal nitride layer including GaON, and an oxide semiconductor layer including InGaZnO.

[0085] FIG. 2A to FIG. 2C TEM images and EDS analysis results are shown for a case where an oxide semiconductor layer containing InGaZnO having a thickness of 10 nm is formed on a metal layer containing W and the thickness of the metal oxide layer containing WOx is different from the thickness of the metal nitride layer containing GaON. More specifically, Figure 2A , Figure 2B and Figure 2C (i) TEM images and (ii) EDS analysis of thin film structures including metal nitride layers including GaON and having thicknesses of about 3 nm, about 5 nm, and about 10 nm, respectively, wherein the thickness of the metal oxide layer including WOx is controlled. Figure 2A , Figure 2B and Figure 2C As shown, in the thin film structure, the greater the thickness of the metal nitride layer containing GaON, the smaller the thickness of the metal oxide layer containing WOx. Therefore, when the thin film structure is formed by the ALD method, the thickness of the metal oxide layer can be adjusted to about 5nm or less by controlling the thickness of the metal nitride layer.

[0086] As a comparative example, Figure 3 TEM images and EDS analysis results are shown regarding a thin film structure in which an oxide semiconductor layer containing InGaZnO and having a thickness of 10 nm is formed on a metal layer containing W and includes a metal oxide layer containing WOx without a metal nitride layer containing GaON.

[0087] Reference Figure 3 The metal oxide layer of the thin film structure of the comparative example has Figure 2A , Figure 2B and Figure 2CThe average thickness of the metal oxide layer (e.g., WOx layer) is greater than about 5 nm. When the thickness of the metal oxide layer increases, the contact resistance between the metal layer and the oxide semiconductor layer also increases. This can be detrimental to the speed and / or other performance of the semiconductor device.

[0088] Figure 4 is a graph showing current-voltage (IV) characteristics of transistors according to examples and comparative examples. Each transistor may include Figure 2B , Figure 2C and Figure 3 A thin film structure manufactured by the same method as in, wherein the metal layer corresponds to the source electrode. W is used as the source / drain electrode, and the oxide semiconductor layer including IGZO is used as the channel layer of the transistor. The comparative example shows the IV characteristics of a transistor including a metal layer, a metal oxide layer and an oxide semiconductor layer, Example 1 shows the IV characteristics of a transistor including a metal layer, a metal oxide layer, a metal nitride layer having a thickness of about 5 nm and an oxide semiconductor layer, and Example 2 shows the IV characteristics of a transistor including a metal layer, a metal oxide layer, a metal nitride layer having a thickness of about 10 nm and an oxide semiconductor layer.

[0089] Reference Figure 4 , the IV characteristics of the transistors according to Examples 1 and 2 are more improved than the IV characteristics of the transistor according to the comparative example. Also, the IV characteristics of the transistor are improved according to the thickness of the metal nitride layer and the metal oxide layer.

[0090] Figure 5 is a diagram illustrating a semiconductor device 100 including a metal oxide layer 120 and a metal nitride layer 130 according to some example embodiments. Figure 5 The semiconductor device 100 may include a substrate 101, a first electrode 110 disposed on the substrate 101, a metal oxide layer 120 disposed on the first electrode 110, a metal nitride layer 130 disposed on the metal oxide layer 120, and an oxide semiconductor layer 140 disposed on the metal nitride layer 130.

[0091] The substrate 101 may be or may include an insulating substrate or a semiconductor substrate having an insulating layer formed thereon, or may be included in an insulating substrate or a semiconductor substrate having an insulating layer formed thereon. Alternatively, the substrate 101 may be, include, or be included in a semiconductor substrate. The semiconductor substrate may include, for example, one or more of Si, Ge, SiGe, and III-V semiconductor materials. The substrate 101 may be, for example, a silicon substrate having silicon oxide formed thereon; however, example embodiments are not limited thereto.

[0092] The first electrode 110, the metal oxide layer 120, the metal nitride layer 130, and the oxide semiconductor layer 140 may correspond to the above Figure 1 The film structure 10 is described.

[0093] For example, the first electrode 110 may include a metal material. The first electrode 110 may include at least one selected from W, Co, Ni, Fe, Ti, Mo, Cr, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Sn, V, Ru, Pt, Zn, and Mg. The first electrode 110 may be arranged spaced apart from the substrate 101.

[0094] The metal included in the metal oxide layer 120 may be the same as the metal included in the first electrode 110. The thickness of the metal oxide layer 120 may be smaller than the thickness of the first electrode 110. The thickness of the metal oxide layer 120 may be about 5 nm or less.

[0095] The content of oxygen included in the metal oxide layer 120 may vary as the distance from the oxide semiconductor layer 140 increases. For example, the content of oxygen included in the metal oxide layer 120 may decrease as the distance from the oxide semiconductor layer 140 increases. The interface between the first electrode 110 and the metal oxide layer 120 may be unclear, or may not exist, or may have no fixed shape. For example, the metal oxide layer 120 may be formed as a part of the first electrode 110. The metal oxide layer 120 may be discontinuously or continuously formed on the first electrode 110.

[0096] The electrical conductivity of the metal nitride layer 130 may be greater than that of the oxide semiconductor layer 140 and may be less than that of the first electrode 110. The metal included in the conductive metal nitride layer 130 may be different from the metal included in the first electrode 110. The metal nitride layer 130 may include a metal having low reactivity to oxygen and remaining stable, or a metal having higher oxidation reactivity than the metal included in the first electrode 110 but remaining conductive even when the metal is oxidized. The metal nitride layer 130 may include at least one of Ga, Mo, W, Zn, V, and Ti.

[0097] The metal nitride layer 130 may further include oxygen. The content (at%) of oxygen included in the metal nitride layer 130 may be greater than or equal to the content of oxygen included in the metal oxide layer 120. Alternatively or additionally, the content (at%) of oxygen included in the metal nitride layer 130 may be less than or equal to the content of oxygen included in the oxide semiconductor layer 140.

[0098] The thickness of the metal nitride layer 130 may be greater than or equal to the thickness of the metal oxide layer 120. For example, the thickness of the metal nitride layer 130 may be about 10 nm or less. Alternatively, the thickness of the metal nitride layer 130 may be about 0.1 nm to about 10 nm. The cross-sectional area of ​​the metal nitride layer 130 may be greater than or equal to the cross-sectional area of ​​the metal oxide layer 120. The width of the metal nitride layer 130 may be greater than or equal to the width of the metal oxide layer 120.

[0099] The oxide semiconductor layer 140 may be provided in the form of an ultrathin film. For example, the thickness of the oxide semiconductor layer 140 may be about 10 nm or less. The length of the oxide semiconductor layer 140 may be less than about 1 micron. The oxide semiconductor layer 140 according to some example embodiments may include one or more oxides of one or more materials selected from one or more of the elements of Groups 12, 13 and 14 (such as Zn, In, Ga, Sn, Cd, Ge or Hf and combinations thereof). For example, the oxide semiconductor layer 140 may include a material based on Zn oxide, such as Zn oxide, In-Zn oxide, In-Ga-Zn oxide, etc. For example, the oxide semiconductor layer 140 may have a single-layer structure or a multi-layer structure.

[0100] The oxide semiconductor layer 140 may be arranged in such a manner that a longitudinal direction thereof is a direction (Z-axis direction) perpendicular to the substrate 101. As used herein, the longitudinal direction may refer to a direction of a greater length of a component shown in the drawings.

[0101] The second electrode 170 may be disposed on the oxide semiconductor layer 140. The first electrode 110 and the second electrode 170 may be disposed to be spaced apart from each other in a direction perpendicular to the substrate 101 (Z-axis direction).

[0102] For example, the first electrode 110, the metal oxide layer 120, the metal nitride layer 130, the oxide semiconductor layer 140, and the second electrode 170 may be arranged in a row in a direction perpendicular to the substrate 101 or in a thickness direction (Z-axis direction) of the first electrode 110. The first electrode 110, the metal oxide layer 120, the metal nitride layer 130, and the oxide semiconductor layer 140 may be arranged sequentially without arranging other layers therebetween or between them.

[0103] The oxide semiconductor layer 140 may be arranged in such a manner that a longitudinal direction thereof is a direction (Z-axis direction) perpendicular to the substrate 101. In the present disclosure, the longitudinal direction may refer to a direction of a greater length of a component shown in the drawings.

[0104] The gate electrode 160 may be arranged on one side of the oxide semiconductor layer 140. The gate insulating layer 150 may be arranged between the oxide semiconductor layer 140 and the gate electrode 160. The gate electrode 160 may be arranged in such a manner that a longitudinal direction (Z-axis direction) thereof is a direction perpendicular to the substrate 101. The oxide semiconductor layer 140, the gate insulating layer 150, and the gate electrode 160 may be arranged in a row in a direction (X-axis direction) horizontal to the substrate 101.

[0105] The mold insulating layer 180 may be disposed on the substrate 101 to fill the empty space. The first electrode 110 may be disposed to be spaced apart from the substrate 101 by the mold insulating layer 180 .

[0106] As described above, in the semiconductor device 100 according to some example embodiments, the metal nitride layer 130 and the metal oxide layer 120 may be arranged between the first electrode 110 and the oxide semiconductor layer 140, and the thickness of the metal nitride layer 130 and the thickness of the metal oxide layer 120 may be controlled, for example, more controlled by a process of forming a thin film via ALD and / or subsequent processes.

[0107] Figure 6 is a diagram illustrating a semiconductor device 100a according to various example embodiments. Figure 6 In, by Figure 5 The parts denoted by the same reference numerals have the same Figure 5 Basically the same configuration and effects are described, so any redundant description will be omitted.

[0108] When compared Figure 5 and Figure 6 hour, Figure 6 The semiconductor device 100 a may include a first metal oxide layer 121 disposed between the first electrode 110 and the metal nitride layer 130 , and a second metal oxide layer 122 disposed between the oxide semiconductor layer 140 and the second electrode 170 .

[0109] The first metal oxide layer 121 may correspond to Figure 5 The metal oxide layer 120 is described.

[0110] The metal included in the second metal oxide layer 122 may be the same as the metal included in the second electrode 170. The content of oxygen included in the second metal oxide layer 122 may vary from the second electrode 170 toward the oxide semiconductor layer 140.

[0111] The thickness of the second metal oxide layer 122 may be about 5 nm or less. For example, the thickness of the second metal oxide layer 122 may be about 0.1 nm or more, about 0.5 nm or more, or about 1 nm or more, and may be about 3 nm or less, about 3.5 nm or less, about 4 nm or less, or about 5 nm or less. Alternatively, the thickness of the second metal oxide layer 122 may be about 0.5 nm to about 3.5 nm. The thickness of the second metal oxide layer 122 may refer to an average thickness. The thickness of the second metal oxide layer 122 may be the same as or different from the thickness of the first metal oxide layer 121 (e.g., greater than or less than the thickness of the first metal oxide layer 121).

[0112] The second metal oxide layer 122 may be formed in a process of forming the second electrode 170 on the oxide semiconductor layer 140 and / or in a process including Figure 6 The semiconductor device 100 a is formed during a post-processing process of the device.

[0113] Figure 7 is a diagram showing a semiconductor device 100b according to another embodiment. Figure 7 In, by Figure 6 The parts denoted by the same reference numerals have the same Figure 6 Basically the same configuration and effects are described, so any redundant description will be omitted.

[0114] When compared Figure 6 and Figure 7 hour, Figure 7 The semiconductor device 100 b may include a first metal nitride layer 131 disposed between the first metal oxide layer 121 and the oxide semiconductor layer 140 , and a second metal nitride layer 132 disposed between the oxide semiconductor layer 140 and the second metal oxide layer 122 .

[0115] The first metal nitride layer 131 may correspond to the above Figure 5 and Figure 6 The metal nitride layer 130 is described.

[0116] The electrical conductivity of the second metal nitride layer 132 may be greater than that of the oxide semiconductor layer 140 and may be less than that of the second electrode 170. The metal included in the second metal nitride layer 132 may be different from the metal included in the second electrode 170. The second metal nitride layer 132 may include a metal having low reactivity to oxygen and remaining stable, or a metal having higher oxidation reactivity than the metal included in the second electrode 170 but remaining conductive even when the metal is oxidized. The second metal nitride layer 132 may include at least one of Ga, Mo, W, Zn, V, and Ti.

[0117] The second metal nitride layer 132 may further include oxygen. The content (at%) of oxygen included in the second metal nitride layer 132 may be greater than or equal to the content of oxygen included in the second metal oxide layer 122. The oxygen in the second metal nitride layer 132 may be included during the formation of the second metal oxide layer 122. However, example embodiments are not limited thereto. The oxygen included in the oxide semiconductor layer 140 may be formed by heating the second metal nitride layer 132 to form the second metal oxide layer 122. Figure 7 The semiconductor device 100 b is moved and formed (eg, diffused) during a post-processing process.

[0118] The thickness of the second metal nitride layer 132 may be greater than or equal to the thickness of the second metal oxide layer 122. The thickness of the second metal nitride layer 132 may be at least twice the thickness of the second metal oxide layer 122. The greater the thickness of the second metal nitride layer 132, the smaller the thickness of the second metal oxide layer 122 may be. For example, the thickness of the second metal nitride layer 132 may be about 10 nm or less. Alternatively, the thickness of the second metal nitride layer 132 may be about 0.1 nm to about 10 nm.

[0119] The cross-sectional area of ​​the second metal nitride layer 132 may be greater than or equal to the cross-sectional area of ​​the second metal oxide layer 122. The width of the second metal nitride layer 132 may be greater than or equal to the width of the second metal oxide layer 122. For example, a portion of the upper surface of the second metal nitride layer 132 may contact the second metal oxide layer 122, and another portion of the upper surface of the second metal nitride layer 132 may contact the second electrode 170.

[0120] The second metal nitride layer 132 may control the thickness of the second metal oxide layer 122. For example, the greater the thickness of the second metal nitride layer 132, the thinner the thickness of the second metal oxide layer 122 may be. Therefore, the second metal nitride layer 132 may prevent or reduce the possibility and / or influence of an increase in contact resistance between the second electrode 170 and the oxide semiconductor layer 140.

[0121] The thickness of the second metal nitride layer 132 may be less than or equal to the thickness of the first metal nitride layer 131, or the thickness of the second metal oxide layer 122 may be less than or equal to the thickness of the first metal oxide layer 121. The first metal nitride layer 131 may be used to control the formation of the first metal oxide layer 121, and the second metal nitride layer 132 may be used to control the formation of the second metal oxide layer 122.

[0122] The first metal oxide layer 121 may be formed in a process of forming the oxide semiconductor layer 140 , a post-processing process of the semiconductor device 100 b , etc., and the second metal oxide layer 122 may be formed in a process of forming the second electrode 170 , a post-processing process of the semiconductor device 100 b , etc.

[0123] Figure 8 FIG. 1 is a diagram showing a semiconductor device 100 c according to another embodiment. Figure 8 In, by Figure 5 The parts denoted by the same reference numerals have the same Figure 5 Basically the same configuration and effects are described, so any redundant description will be omitted.

[0124] Figure 8 The semiconductor device 100c shown may include a first electrode 110, a metal oxide layer 120, a metal nitride layer 130, an oxide semiconductor layer 140, and a second electrode 170 arranged in a direction (Z-axis direction) perpendicular to the substrate 101. The gate insulating layer 150 may be arranged on the periphery of the oxide semiconductor layer 140, and the gate electrode 160 may be arranged on the periphery of the gate insulating layer 150. Since the gate electrode 160 is arranged on the periphery of the oxide semiconductor layer 140, the area where the gate electrode 160 and the oxide semiconductor layer 140 face each other may be increased, and the short channel effect may be suppressed.

[0125] Although not shown in the drawings, Figure 8 In the semiconductor device 100 c , a second metal oxide layer may be further disposed between the oxide semiconductor layer 140 and the second electrode 170 , or a second metal nitride layer may be further disposed between the oxide semiconductor layer 140 and the second metal oxide layer.

[0126] Fig. 9 is a diagram showing a semiconductor device 100 d according to another embodiment.

[0127] Reference Fig. 9 , the semiconductor device 100d may include a substrate 101, a first electrode 110 disposed on the substrate 101, and a second electrode 170 disposed spaced apart from the first electrode 110. The first electrode 110 and the second electrode 170 may be disposed spaced apart from each other in a direction (Z-axis direction) perpendicular to the substrate 101. Since the first electrode 110 and the second electrode 170 may correspond to the above Figure 1 The metal layer 11 is described, so the detailed description thereof is omitted.

[0128] The oxide semiconductor layer 140 may be arranged outside the space between the first electrode 110 and the second electrode 170. The oxide semiconductor layer 140 may include a first portion 140a parallel to the substrate 101, a second portion 140b bent from the first portion 140a in a direction perpendicular to the substrate 101, and a third portion 140c bent from the second portion 140b and extending in a direction opposite to the first portion 140a. The second portion 140b may be arranged on one side of the first electrode 110 and the second electrode 170, and the third portion 140c may be arranged to contact the second electrode 170. The oxide semiconductor layer 140 may correspond to the above description of Figure 1 The oxide semiconductor layer 14 is described.

[0129] The first metal nitride layer 131 may be disposed between the first electrode 110 and the second portion 140 b of the oxide semiconductor layer 140, and the first metal oxide layer 121 may be disposed between the first electrode 110 and the first metal nitride layer 131. In addition, the second metal nitride layer 132 may be disposed between the second electrode 170 and the second portion 140 b of the oxide semiconductor layer 140, and the second metal oxide layer 122 may be disposed between the second electrode 170 and the second metal nitride layer 132.

[0130] The first metal oxide layer 121 and the second metal oxide layer 122 may correspond to the above Figure 1 The metal oxide layer 12, the first metal nitride layer 131 and the second metal nitride layer 132 described above may correspond to Figure 1 The metal nitride layer 13 is described.

[0131] The gate electrode 160 may have a shape similar to that of the oxide semiconductor layer 140, and may be arranged spaced apart from the oxide semiconductor layer 140. In other words, the gate electrode 160 may include a first portion 160a parallel to the substrate 101, a second portion 160b bent from the first portion 160a in a direction perpendicular to the substrate 101, and a third portion 160c bent from the second portion 160b and extending in a direction opposite to the first portion 160a. The gate insulating layer 150 may be arranged between the oxide semiconductor layer 140 and the gate electrode 160.

[0132] Fig.10 is a diagram showing a semiconductor device 100 e according to another embodiment.

[0133] Fig.10 The semiconductor device 100 e shown in FIG. 1 may include a first electrode 110 , a metal oxide layer 120 disposed on the first electrode 110 , a metal nitride layer 130 disposed on the metal oxide layer 120 , and an oxide semiconductor layer 140 disposed on the metal nitride layer 130 .

[0134] The first electrode 110, the metal oxide layer 120, the metal nitride layer 130, and the oxide semiconductor layer 140 may correspond to the above Figure 1 The metal layer 11 , the metal oxide layer 12 , the metal nitride layer 13 , and the oxide semiconductor layer 14 are described, and thus any redundant description thereof will be omitted.

[0135] The width of the first electrode 110 may be greater than the width of the metal oxide layer 120. The surface of the first electrode 110 may be stepped by the metal oxide layer 120. The entire region of the oxide semiconductor layer 140 may be arranged to overlap the metal oxide layer 120 in a direction from the oxide semiconductor layer 140 to the first electrode 110.

[0136] The oxide semiconductor layer 140 may have a U-shaped cross section. The oxide semiconductor layer 140 may include a bottom 143 in contact with the metal nitride layer 130, a first vertical extension 141 extending from one end of the bottom 143 in a direction perpendicular to the first electrode 110 (Z-axis direction), and a second vertical extension 142 extending from the other end of the bottom 143 in a direction perpendicular to the first electrode 110 (Z-axis direction).

[0137] The first gate electrode 161 may be arranged spaced apart from the first vertical extension 141, and the second gate electrode 162 may be arranged spaced apart from the second vertical extension 142. The first gate insulating layer 151 may be arranged between the first vertical extension 141 and the first gate electrode 161, and the second gate insulating layer 152 may be arranged between the second vertical extension 142 and the second gate electrode 162.

[0138] The first gate electrode 161 and / or the second gate electrode 162 may extend in the second horizontal direction (Y-axis direction). The first gate electrode 161 and the second gate electrode 162 may be arranged to be spaced apart from each other. The first gate electrode 161 and / or the second gate electrode 162 may constitute a word line WL. The electrical signal input to the first gate electrode 161 may not correspond to the electrical signal input to the second gate electrode 162. The first gate electrode 161 may control the channel of the first vertical extension portion 141, and the second gate electrode 162 may control the channel of the second vertical extension portion 142.

[0139] The insulating liner 191 may be arranged between the first gate electrode 161 and the second gate electrode 162 arranged spaced apart from each other. The insulating liner 191 may be conformally arranged on the sidewalls of the first gate electrode 161 and the second gate electrode 162 facing each other and / or on the upper surface of the oxide semiconductor layer 140. The insulating liner 191 may include an upper surface arranged on the same plane as the first gate electrode 161 and the second gate electrode 162. The insulating liner 191 may include, for example, silicon nitride. The buried insulating layer 192 may fill the space between the first gate electrode 161 and the second gate electrode 162 arranged spaced apart from each other on the insulating liner 191. The buried insulating layer 192 may include, for example, silicon oxide. The upper insulating layer 193 may be arranged on the upper surface of the first gate electrode 161, the upper surface of the second gate electrode 162, and / or the upper surface of the buried insulating layer 192. The upper surface of the upper insulating layer 193 may be arranged at the same level as the upper surface of the mold insulating layer 180.

[0140] The second electrode 170 may be disposed on the oxide semiconductor layer 140. The second electrode 170 may be used as a landing pad. The second electrode 170 may include a first sub-electrode 171 and a second sub-electrode 172. The first sub-electrode 171 may be electrically connected to the first vertical extension portion 141. The second sub-electrode 172 may be electrically connected to the second vertical extension portion 142. The first sub-electrode 171 may not be electrically connected to the second sub-electrode 172.

[0141] The second electrode 170 may include an upper portion and a lower portion. The upper portion of the second electrode 170 may be a portion of the second electrode 170 disposed at a higher level than the upper surface of the mold insulating layer 180. The lower portion of the second electrode 170 may be a portion of the second electrode 170 disposed in a recess defined between the mold insulating layer 180 and the upper insulating layer 193.

[0142] In some example embodiments, the upper portion of the second electrode 170 may have a first width in the first horizontal direction (X-axis direction), and the lower portion of the second electrode 170 may have a second width smaller than the first width in the first horizontal direction (X-axis direction). The lower portion of the second electrode 170 may be disposed in the recess, and the upper portion of the second electrode 170 may be on the lower portion of the second electrode 170 and have a bottom surface disposed on the upper surface of the upper insulating layer 193 and the upper surface of the mold insulating layer 180. Therefore, the second electrode 170 may have a T-shaped vertical cross-section.

[0143] The bottom surface of the lower portion of the second electrode 170 may be in contact with the upper surface of the first vertical extension 141 and / or the second vertical extension 142. Both sidewalls of the lower portion of the second electrode 170 may be aligned with both sidewalls of the first vertical extension 141 and the second vertical extension 142. The bottom surface of the lower portion of the second electrode 170 may be arranged at a higher level than the upper surface of the first gate electrode 161 and / or the second gate electrode 162, and a portion of the sidewall of the lower portion of the second electrode 170 may be covered by the first gate insulating layer 151 and / or the second gate insulating layer 152.

[0144] A second electrode insulating layer 194 surrounding the periphery of the second electrode 170 may be disposed on upper surfaces of the mold insulating layer 180 and the upper insulating layer 193. The semiconductor device 100e may have a vertical channel transistor (VCT) structure including a vertical channel region extending in a direction perpendicular to the first electrode 110 (Z-axis direction).

[0145] Fig.11 FIG. 1 is a diagram showing a semiconductor device 100f according to another embodiment. Fig.11 In the Fig.10 Components denoted by the same reference numerals in the drawings have substantially the same configuration and operation effects, so detailed descriptions thereof are omitted.

[0146] When compared Fig.10 and Fig.11 When, including Fig.11 The metal nitride layer 130 in the semiconductor device 100f may be disposed on the entire upper surface of the first electrode 110. A bit line may be formed on the first electrode 110, and the metal nitride layer 130 may be disposed along the first electrode 110.

[0147] The width of the metal nitride layer 130 may be greater than the width of the metal oxide layer 120. In addition, the width of the metal nitride layer 130 may be greater than the width of the oxide semiconductor layer 140. The width of the oxide semiconductor layer 140 may refer to a width in contact with the metal nitride layer 130. The difference between the width of the metal nitride layer 130 and the width of the oxide semiconductor layer 140 may be greater than or equal to the difference between the width of the metal oxide layer 120 and the width of the oxide semiconductor layer 140.

[0148] The metal oxide layer 120 may be disposed between the first electrode 110 and the metal nitride layer 130. The surface of the first electrode 110 may form a step through the metal oxide layer 120. A partial region of the metal nitride layer 130 may be in contact with the metal oxide layer 120, and another partial region of the metal nitride layer 130 may be in contact with the first electrode 110. For example, a partial region of the metal nitride layer 130 in contact with the oxide semiconductor layer 140 may also be in contact with the metal oxide layer 120, and a partial region of the metal nitride layer 130 not in contact with the oxide semiconductor layer 140 may be in contact with the first electrode 110.

[0149] The thickness of the first electrode 110 may be about 20 nm or less. For example, the thickness of the first electrode 110 may be about 1 nm or more, about 3 nm or more, or about 5 nm or more, and may be about 15 nm or less, about 10 nm or less, or about 7 nm or less.

[0150] The thickness of the metal oxide layer 120 may be about 5 nm or less. For example, the thickness of the metal oxide layer 120 may be about 0.1 nm or more, about 0.5 nm or more, or about 1 nm or more, and may be about 3 nm or less, about 4 nm or less, or about 5 nm or less.

[0151] The thickness of the metal nitride layer 130 may be about 10 nm or less. The thickness of the metal nitride layer 130 may be about 0.1 nm or more, about 0.3 nm or more, about 0.5 nm or more, about 0.8 nm or more, or about 1 nm or more, and may be about 8 nm or less, about 7 nm or less, about 6 nm or less, or about 5 nm or less.

[0152] The thickness of the oxide semiconductor layer 140 may be about 10 nm or less, about 8 nm or less, or about 7 nm or less.

[0153] The first electrode 110 , the metal oxide layer 120 , the metal nitride layer 130 , and the oxide semiconductor layer 140 may have an appropriate thickness ratio.

[0154] The thickness of the metal oxide layer 120 may be less than the thickness of the first electrode 110. The thickness of the metal oxide layer 120 may be less than or equal to about 25% of the thickness of the first electrode 110, less than or equal to about 20% of the thickness of the first electrode 110, or less than or equal to about 18% of the thickness of the first electrode 110, and may be greater than or equal to 1% of the thickness of the first electrode 110.

[0155] The thickness of the metal oxide layer 120 may be at most about 5 times the thickness of the oxide semiconductor layer 140. The thickness of the metal oxide layer 120 may be at most about 3 times, about 2 times, about 1.5 times, about 1.0 times, or about 0.5 times the thickness of the oxide semiconductor layer 140, and may be greater than or equal to about 1% of the thickness of the oxide semiconductor layer 140.

[0156] The thickness of the metal oxide layer 120 may be at most 10 times the thickness of the metal nitride layer 130. The thickness of the metal oxide layer 120 may be at most about 5 times, about 2.5 times, about 2 times, or about 1 times the thickness of the metal nitride layer 130, and may be at least about 0.05 times, about 0.1 times, or about 0.2 times the thickness of the metal nitride layer 130. Alternatively, the thickness of the metal oxide layer 120 may be about 0.2 times to about 2 times the thickness of the metal nitride layer 130.

[0157] Fig.12 FIG. 1 is a diagram showing a semiconductor device 100g according to another embodiment. Fig.12 In the Fig.10 Components denoted by the same reference numerals in the drawings have substantially the same configuration and operation effects, so detailed descriptions thereof are omitted.

[0158] When compared Fig.10 and Fig.12 hour, Fig.12 The semiconductor device 100 g may include a first metal oxide layer 121 disposed between the first electrode 110 and the metal nitride layer 130 , and a second metal oxide layer 122 disposed between the oxide semiconductor layer 140 and the second electrode 170 .

[0159] The first metal oxide layer 121 may correspond to Fig.10 The metal oxide layer 120 is described, and thus a detailed description thereof is omitted.

[0160] The metal included in the second metal oxide layer 122 may be the same as the metal included in the second electrode 170. The content of oxygen included in the second metal oxide layer 122 may vary as the distance from the oxide semiconductor layer 140 increases. For example, the content of oxygen included in the second metal oxide layer 122 may decrease as the distance from the oxide semiconductor layer 140 increases. The thickness of the second metal oxide layer 122 may be about 5 nm or less. For example, the thickness of the second metal oxide layer 122 may be about 0.1 nm or more, about 0.5 nm or more, or about 1 nm or more, and may be about 3 nm or less, about 4 nm or less, or about 5 nm or less.

[0161] The second metal oxide layer 122 may be formed in a process of forming the second electrode 170 on the oxide semiconductor layer 140 or in a process including Fig.12 Therefore, the second metal oxide layer 122 may have a lower formation probability than the first metal oxide layer 121.

[0162] Fig.13 FIG. 1 is a diagram showing a semiconductor device 100h according to another embodiment. Fig.13 In the Fig.12 Components denoted by the same reference numerals in the drawings have substantially the same configuration and operation effects, so detailed descriptions thereof are omitted.

[0163] When compared Fig.12 and Fig.13 hour, Fig.13 The semiconductor device 100 h may include a first metal nitride layer 131 disposed between the first metal oxide layer 121 and the oxide semiconductor layer 140 , and a second metal nitride layer 132 disposed between the oxide semiconductor layer 140 and the second metal oxide layer 122 .

[0164] The first metal nitride layer 131 may correspond to Fig.10 and Fig.12 The metal nitride layer 130 is described, and thus a detailed description thereof is omitted.

[0165] The electrical conductivity of the second metal nitride layer 132 may be greater than that of the oxide semiconductor layer 140 and may be less than that of the second electrode 170. The metal included in the second metal nitride layer 132 may be different from the metal included in the second electrode 170. The second metal nitride layer 132 may include a metal that has low reactivity to oxygen and remains stable, or a metal that has higher oxidation reactivity than the metal included in the second electrode 170 but remains conductive even when the metal is oxidized.

[0166] The second metal nitride layer 132 may further include oxygen. The content (at%) of oxygen included in the second metal nitride layer 132 may be greater than or equal to the content of oxygen included in the second metal oxide layer 122. The oxygen in the second metal nitride layer 132 may be included during the formation of the second metal oxide layer 122. However, the present disclosure is not limited thereto. Fig.13 During a post-treatment process of the semiconductor device 100 h , oxygen included in the oxide semiconductor layer 140 may move and be included in the second metal nitride layer 132 .

[0167] The thickness of the second metal oxide layer 122 may be at most 10 times the thickness of the second metal nitride layer 132. The thickness of the second metal oxide layer 122 may be at most about 5 times, about 2.5 times, about 2 times, or about 1 times the thickness of the second metal nitride layer 132, and may be at least about 0.05 times, about 0.1 times, or about 0.3 times the thickness of the second metal nitride layer 132.

[0168] The cross-sectional area of ​​the second metal nitride layer 132 may be greater than or equal to the cross-sectional area of ​​the second metal oxide layer 122. The width of the second metal nitride layer 132 may be greater than or equal to the width of the second metal oxide layer 122. For example, a portion of the upper surface of the second metal nitride layer 132 may contact the second metal oxide layer 122, and another portion of the upper surface of the second metal nitride layer 132 may contact the second electrode 170.

[0169] The second metal nitride layer 132 may control the thickness of the second metal oxide layer 122. For example, the greater the thickness of the second metal nitride layer 132, the thinner the thickness of the second metal oxide layer 122 may be. Therefore, the second metal nitride layer 132 may prevent and / or reduce the possibility and / or influence of an increase in contact resistance between the second electrode 170 and the oxide semiconductor layer 140.

[0170] The thickness of the second metal nitride layer 132 may be less than or equal to the thickness of the first metal nitride layer 131, or the thickness of the second metal oxide layer 122 may be less than or equal to the thickness of the first metal oxide layer 121. The first metal nitride layer 131 may be used to control the formation of the first metal oxide layer 121, and the second metal nitride layer 132 may be used to control the formation of the second metal oxide layer 122.

[0171] The first metal oxide layer 121 may be formed in a process of forming the oxide semiconductor layer 140 or a post-processing process of the semiconductor device 100h, and the second metal oxide layer 122 may be formed in a process of forming the second electrode 170 or a post-processing process of the semiconductor device. Therefore, the thickness of the second metal oxide layer 122 may be less than or equal to the thickness of the first metal oxide layer 121.

[0172] Fig.14 FIG. 1 is a diagram showing a semiconductor device 100i according to another embodiment. Fig.14 In the Fig.10 Components denoted by the same reference numerals in the drawings have substantially the same configuration and operation effects, so detailed descriptions thereof are omitted.

[0173] When compared Fig.10 and Fig.14 When, including Fig.14The shape of the oxide semiconductor layer 140 in the semiconductor device 100i may be different from that included in Fig.10 The shape of the oxide semiconductor layer 140 in the semiconductor device 100e is different. The semiconductor device 100i may include a first oxide semiconductor layer 141 and a second oxide semiconductor layer 142. The first oxide semiconductor layer 141 may have an L-shaped cross-section, and the second oxide semiconductor layer 142 may have a shape symmetrical to the first oxide semiconductor layer 141 in the Z-axis direction. The first oxide semiconductor layer 141 and the second oxide semiconductor layer 142 may be separated from each other.

[0174] Each of the first oxide semiconductor layer 141 and the second oxide semiconductor layer 142 may be provided in such a manner that a longitudinal direction thereof is arranged in a direction (Z-axis direction) perpendicular to a substrate (not shown).

[0175] The metal oxide layer 120 may include a first sub-metal oxide layer 120a and a second sub-metal oxide layer 120b overlapping the first oxide semiconductor layer 141 and the second oxide semiconductor layer 142, respectively. The first sub-metal oxide layer 120a and the second sub-metal oxide layer 120b may be separated from each other. However, the present disclosure is not limited thereto. The first sub-metal oxide layer 120a and the second sub-metal oxide layer 120b may be connected to each other. For example, the thickness of the metal oxide layer in the region overlapping the first oxide semiconductor layer 141 and the second oxide semiconductor layer 142 in the thickness direction of the metal oxide layer may be greater than the thickness of the metal oxide layer in the region not overlapping the first oxide semiconductor layer 141 and the second oxide semiconductor layer 142.

[0176] Fig.15 1 is a diagram showing a semiconductor device 100j according to another embodiment. Fig.15 , the semiconductor device 100j may include a substrate 101, a first electrode 110 and a second electrode 170 arranged on the substrate 101 and spaced apart from each other. The first electrode 110 and the second electrode 170 may be arranged in a direction (X-axis direction) horizontal to the substrate 101 and spaced apart from each other. Since the first electrode 110 and the second electrode 170 may correspond to the above Figure 1 The metal layer 11 is described, so the detailed description thereof is omitted.

[0177] The oxide semiconductor layer 140 may be disposed between the first electrode 110 and the second electrode 170. The oxide semiconductor layer 140 may include a first portion 140a parallel to the substrate 101, a second portion 140b bent from the first portion 140a in a direction perpendicular to the substrate 101, and a third portion 140c bent from the second portion 140b and extending in a direction opposite to the first portion 140a. The first portion 140a may overlap a partial region of the first electrode 110 in the thickness direction of the substrate 101, and the third portion 140c may overlap a partial region of the second electrode 170 in the thickness direction of the substrate 101. The oxide semiconductor layer 140 may correspond to the above description of Figure 1 The oxide semiconductor layer 14 is described.

[0178] The first metal oxide layer 121 may be disposed between the first electrode 110 and the oxide semiconductor layer 140, and the first metal nitride layer 131 may be disposed between the first metal oxide layer 121 and the oxide semiconductor layer 140. The second metal oxide layer 122 may be disposed between the second electrode 170 and the oxide semiconductor layer 140, and the second metal nitride layer 132 may be disposed between the second metal oxide layer 122 and the oxide semiconductor layer 140.

[0179] The surface of the first electrode 110 may be stepped by the first metal oxide layer 121, and the first metal nitride layer 131 may be arranged to surround the side and upper surfaces of the first metal oxide layer 121. The oxide semiconductor layer 140 may be arranged on the side and upper surfaces of the first metal nitride layer 131.

[0180] In the thickness direction of the substrate 101, the overlap ratio between the first metal oxide layer 121 and the oxide semiconductor layer 140 may be different from the overlap ratio between the first metal nitride layer 131 and the oxide semiconductor layer 140. For example, the overlap ratio between the first metal oxide layer 121 and the oxide semiconductor layer 140 may be greater than the overlap ratio between the first metal nitride layer 131 and the oxide semiconductor layer 140.

[0181] The surface of the second electrode 170 may also be stepped by the second metal oxide layer 122, and the second metal nitride layer 132 may be arranged to surround the side and upper surfaces of the second metal oxide layer 122. The oxide semiconductor layer 140 may be arranged on the side and upper surfaces of the second metal nitride layer 132.

[0182] In the thickness direction of the substrate 101, the overlap ratio between the second metal oxide layer 122 and the oxide semiconductor layer 140 may be different from the overlap ratio between the second metal nitride layer 132 and the oxide semiconductor layer 140. For example, the overlap ratio between the second metal oxide layer 122 and the oxide semiconductor layer 140 may be greater than the overlap ratio between the second metal nitride layer 132 and the oxide semiconductor layer 140.

[0183] The first electrode 110, the first metal oxide layer 121, and the first metal nitride layer 131 may correspond to Figure 1 The metal layer 11, the metal oxide layer 12 and the metal nitride layer 13 described above, the second electrode 170, the second metal oxide layer 122 and the second metal nitride layer 132 may correspond to Figure 1 The metal layer 11, the metal oxide layer 12 and the metal nitride layer 13 are described.

[0184] In the following, about Figures 16 to 24 Methods of fabricating a semiconductor device according to some example embodiments are described.

[0185] Reference Fig.16 , a plurality of molded insulating layers 280 extending in the second horizontal direction (Y-axis direction) may be deposited on the first electrode 210 extending in the first horizontal direction (X-axis direction). The molded insulating layers 280 may be stacked in the vertical direction (Z-axis direction) to have a certain height. The plurality of molded insulating layers 280 and the first electrode 210 may form an opening 285.

[0186] Reference Fig.17 , a metal nitride layer 230 may be deposited on the first electrode 210. The metal nitride layer 230 may be deposited by using a selective ALD process and / or a PE-ALD process. The metal nitride layer 230 may have a thickness of about 10 nm or less. For example, the metal nitride layer 230 may have a thickness of about 2 nm to about 7 nm.

[0187] Reference Fig.18 The oxide semiconductor layer 240 may be deposited on the metal nitride layer 230 and the mold insulating layer 280. The oxide semiconductor layer 240 may be deposited by using a thermal ALD method (eg, a low pressure thermal ALD method) and / or a PE-ALD method. The oxide semiconductor layer 240 may have a U-shaped cross section.

[0188] exist Figure 17-Figure 20 Each film deposited in the process can be deposited in an in-situ manner, for example in the same furnace without opening the furnace door. Figure 17-Figure 20 Each film deposited in the process may be deposited in an in-situ manner, for example, in the same chamber without opening a chamber door. However, example embodiments are not limited thereto.

[0189] In the process of depositing the oxide semiconductor layer 240, an oxidation reaction may occur between the oxidant included in the precursor of the oxide semiconductor layer 240 and the first electrode 210, and the metal oxide layer 220 may be formed. Even when the first electrode 210 is oxidized, the formation of the metal oxide layer 220 may be limited by the metal nitride layer 230. For example, the thickness of the metal oxide layer 220 may be about 5 nm or less. Some of the oxygen included in the oxidant may remain in the metal nitride layer 230 when passing through the metal nitride layer 230, and the other may react with the first electrode 210 to form the metal oxide layer 220.

[0190] Reference Fig.19 , the gate insulating layer 250 may be deposited on the oxide semiconductor layer 240. Fig. 20 , the gate electrode 260 may be deposited on the gate insulating layer 250 .

[0191] Reference Fig.21 , can be Fig. 20 The gate insulating layer 250 and the gate electrode 260 of the structure shown in FIG. 1 are etched (such as anisotropic etching) to expose the bottom 243 of the oxide semiconductor layer 240. The gate electrode 260 may be divided into a first gate electrode 261 and a second gate electrode 262, and the gate insulating layer 250 may be divided into a first gate insulating layer 251 and a second gate insulating layer 252.

[0192] In addition, the gate electrode 260, the gate insulating layer 250, and the oxide semiconductor layer 240 may be etched in a direction to an upper portion of the mold insulating layer 280 to expose an upper surface of the mold insulating layer 280. The upper surface of the mold insulating layer 280, the upper surfaces of the first and second gate electrodes 261 and 262, and the upper surfaces of the first and second gate insulating layers 251 and 252 may be at the same level.

[0193] Reference Fig. 22 , when the gate electrode 260 is etched again, the level of the upper surfaces of the first gate electrode 261 and the second gate electrode 262 may be lower than the level of the upper surface of the mold insulating layer 280 .

[0194] Reference Fig. 22, the insulating liner 291 may be deposited on the surface of the bottom 243 of the oxide semiconductor layer 240 up to the level of the upper surface of the first gate electrode 261 and / or the second gate electrode 262. The buried insulating layer 292 may be filled in the insulating liner 291. The insulating liner 291 and the buried insulating layer 292 may not be distinguished from each other. The upper insulating layer 293 may be deposited on the upper surface of the first gate electrode 261 and / or the second gate electrode 262 and the upper surface of the insulating liner 291. The surface level of the upper insulating layer 293 may correspond to the level of the upper surface of the mold insulating layer 280, the upper surface of the oxide semiconductor layer 240, and the upper surfaces of the first gate insulating layer 251 and the second gate insulating layer 252.

[0195] Fig.23 Only show Fig. 22 The part corresponding to a unit of Fig.23 , an upper portion of the first oxide semiconductor layer 241 and an upper portion of the second oxide semiconductor layer 242 may be partially etched, and the second electrode 270 may be deposited on the first oxide semiconductor layer 241 and the second oxide semiconductor layer 242. After depositing the second electrode 270, a central portion of the second electrode 270 and an upper portion of the upper insulating layer 293 may be partially etched.

[0196] Reference Fig.24 , the second electrode insulating layer 294 may be deposited on a portion of an upper portion of the upper insulating layer 293 between the second electrodes 270 . The level of the upper surface of the second electrode insulating layer 294 may correspond to the level of the surface of the second electrode 270 .

[0197] Since the semiconductor device according to some example embodiments is of a microscopic size and has excellent electrical properties, it may be applied to an integrated circuit device having a high degree of integration.

[0198] The semiconductor device according to some example embodiments may be included in a transistor that constitutes a digital circuit and / or an analog circuit or is included in a digital circuit and / or an analog circuit. In some example embodiments, the semiconductor device may be used as a high voltage transistor and / or a low voltage transistor. For example, the semiconductor device according to some example embodiments may be included in a high voltage transistor constituting a peripheral circuit of a flash memory device, an electrically erasable programmable read-only memory (EEPROM) device, etc. (which is a non-volatile memory device operating at a high voltage).

[0199] Fig.25 is a circuit diagram of a complementary metal oxide semiconductor (CMOS) inverter 300 according to some example embodiments.

[0200] The CMOS inverter 300 may include a CMOS transistor 310. The CMOS transistor 310 may include a p-channel metal oxide semiconductor (PMOS) transistor 320 and an n-channel metal oxide semiconductor (NMOS) transistor 330 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 310 may include a Figures 5 to 15 Various example embodiments of one or more semiconductor devices are described.

[0201] Fig.26 is a circuit diagram of a CMOS static random access memory (SRAM) device 400 according to some example embodiments.

[0202] The CMOS SRAM device 400 may include a pair of driver transistors 410. Each of the pair of driver transistors 410 may include a PMOS transistor 420 and an NMOS transistor 430 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 400 may also include a pair of transmission transistors 440. A node (such as a source of the transmission transistor 440) may be cross-connected to a common node of the PMOS transistor 420 and the NMOS transistor 430 constituting the driver transistor 410. The power supply terminal Vdd may be connected to a node (such as a source of the PMOS transistor 420), and a ground terminal may be connected to a node (such as a source of the NMOS transistor 430). A word line WL may be connected to the gates of the pair of transmission transistors 440, a bit line BL, and an inverted bit line WL. The drains of the pair of pass transistors 440 may be connected respectively.

[0203] At least one of the driving transistor 410 and the transfer transistor 440 of the CMOS SRAM device 400 may include a transistor 410 according to the embodiment of the present invention. Figures 5 to 15 One or more semiconductor devices of various example embodiments described, for example, with respect to Figures 5 to 15 The same or different semiconductor devices described.

[0204] Fig. 27 is a circuit diagram of a CMOS NAND circuit 500 according to some example embodiments.

[0205] The CMOS NAND circuit 500 may include a pair of CMOS transistors that receive input signals different from each other. The CMOS NAND circuit 500 may include a pair of CMOS transistors that receive input signals different from each other. Figures 5 to 15 Various example embodiments of one or more semiconductor devices are described.

[0206] Fig.28 is a block diagram illustrating an electronic system 600 according to some example embodiments.

[0207] The electronic system 600 may include a memory 610 and a memory controller 620. The memory controller 620 may control the memory 610 to read data from the memory 610 and / or write data on the memory 610 in response to a request from the host 630. At least one of the memory 610 and the memory controller 620 may include a processor according to the information about the memory 610. Figures 5 to 15 Some example embodiments of semiconductor devices are described.

[0208] Fig.29 is a block diagram illustrating an electronic system 700 according to some example embodiments.

[0209] The electronic system 700 may constitute or include a wireless communication device and / or a device configured to send and / or receive information in a wireless environment, or be included in a wireless communication device and / or a device configured to send and / or receive information in a wireless environment. The electronic system 700 may include a controller 710, an input / output (I / O) device 720, a memory 730, and a wireless interface 740 connected to each other through a bus 750.

[0210] The controller 710 may include at least one of a microprocessor, a digital signal processor, and any other similar processor. The I / O device 720 may include at least one of a keypad, a keyboard, and a display. The memory 730 may be used to store instructions executed by the controller 710. For example, the memory 730 may be used to store user data. The electronic system 700 may use the wireless interface 740 to send / receive data through a wireless communication network. The wireless interface 740 may include an antenna and / or a wireless transceiver. The electronic system 700 may include a plurality of wireless interfaces 740 and a plurality of wireless interfaces 740. Figures 5 to 15 Various example embodiments of one or more semiconductor devices are described.

[0211] Since the semiconductor device according to some example embodiments has improved or excellent electrical performance due to its micro-sized structure, the semiconductor device may be applied to an integrated circuit device and have characteristics of one or more of miniaturization, low power consumption, and high performance.

[0212] A semiconductor device according to some example embodiments may control or help control formation of a metal oxide layer between an electrode and an oxide semiconductor layer by using a metal nitride layer.

[0213] By controlling the formation of the metal oxide layer on the electrode, the contact resistance of the semiconductor device can be controlled and / or improved (or reduced).

[0214] Such control of forming a metal oxide layer between an electrode and an oxide semiconductor by using a metal nitride layer can increase on-current density and scale down a semiconductor device. The electrical performance of the semiconductor device can be improved.

[0215] Any of the elements and / or functional blocks disclosed above may include or be implemented as: a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include electronic components, such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include electronic components such as a logic gate, and the logic gate includes at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0216] It should be understood that the various example embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each example embodiment and / or accompanying drawings should generally be considered to be applicable to other similar features and / or aspects in other embodiments. The example embodiments are not necessarily mutually exclusive. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0217] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0082887 filed in the Korean Intellectual Property Office on June 27, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: an oxide semiconductor layer; a first electrode and a second electrode, respectively adjacent to the oxide semiconductor layer and spaced apart from each other; a metal oxide layer between at least one of the first electrode and the second electrode and the oxide semiconductor layer; a metal nitride layer between the metal oxide layer and the oxide semiconductor layer; a gate electrode spaced apart from the oxide semiconductor layer; as well as A gate insulating layer is between the oxide semiconductor layer and the gate electrode. 2 . The semiconductor device according to claim 1 , wherein the metal nitride layer includes oxygen. 3 . The semiconductor device according to claim 1 , wherein at least one of a thickness of the metal oxide layer and a thickness of the metal nitride layer is smaller than a thickness of the oxide semiconductor layer. 4 . The semiconductor device according to claim 1 , wherein a thickness of the oxide semiconductor layer is 10 nm or less. The semiconductor device according to claim 1 , wherein the length of the oxide semiconductor layer is less than 1 micrometer. 6 . The semiconductor device according to claim 1 , wherein a thickness of the metal oxide layer is 5 nm or less. 7 . The semiconductor device according to claim 1 , wherein the metal oxide layer has a thickness of 0.5 nm to 3.5 nm. 8 . The semiconductor device according to claim 1 , wherein a thickness of the metal nitride layer is 10 nm or less. 9 . The semiconductor device according to claim 1 , wherein a thickness of the metal oxide layer is 0.2 to 2 times a thickness of the metal nitride layer. 10 . The semiconductor device according to claim 1 , wherein a thickness of the metal oxide layer is less than or equal to 25% of a thickness of the first electrode. 11 . The semiconductor device according to claim 1 , wherein the metal oxide layer includes a metal that is the same as a metal included in an electrode in contact with the metal oxide layer, the electrode being selected from the first electrode and the second electrode.

12. The semiconductor device according to claim 8, wherein the metal oxide layer includes at least one of W, Co, Ni, Fe, Ti, Mo, Cr, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Sn, V, Ru, Pt, Zn and Mg. 13 . The semiconductor device according to claim 12 , wherein the metal nitride layer comprises at least one of Ga, W, Zn, V, and Ti. 14 . The semiconductor device according to claim 1 , wherein a surface of at least one of the first electrode and the second electrode forms a step due to the metal oxide layer. 15 . The semiconductor device according to claim 1 , wherein a width of the metal nitride layer is greater than or equal to a width of the oxide semiconductor layer. 16 . The semiconductor device according to claim 1 , wherein a difference between a width of the oxide semiconductor layer and a width of the metal nitride layer is greater than or equal to a difference between the width of the oxide semiconductor layer and a width of the metal oxide layer. 17 . The semiconductor device according to claim 1 , wherein the first electrode, the metal oxide layer, the metal nitride layer, the oxide semiconductor layer, and the second electrode are arranged in this order in a thickness direction of the first electrode.

18. The semiconductor device according to claim 1, wherein the metal oxide layer comprises: a first metal oxide layer between the first electrode and the oxide semiconductor layer; and a second metal oxide layer between the second electrode and the oxide semiconductor layer, and The metal nitride layer is between the oxide semiconductor layer and at least one of the first metal oxide layer and the second metal oxide layer.

19. The semiconductor device according to claim 18, wherein the metal nitride layer comprises: a first metal nitride layer between the first metal oxide layer and the oxide semiconductor layer; and The second metal nitride layer is between the second metal oxide layer and the oxide semiconductor layer. 20 . The semiconductor device according to claim 18 , wherein a thickness of the first metal oxide layer is different from a thickness of the second metal oxide layer. 21 . The semiconductor device according to claim 1 , wherein if the oxide semiconductor layer and the metal oxide layer are in direct contact with each other, an interface resistance exists between the oxide semiconductor layer and the metal oxide layer.

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