Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof, and relates to the technical field of integrated circuits. The dielectric core is located on the side, away from the substrate, of the source; the channel layer is located between the dielectric core and the source electrode and covers the bottom surface and the side wall of the dielectric core, and the top surface of the channel layer is higher than the top surface of the dielectric core and forms a groove located above the dielectric core; the conductive plug is at least partially located in the groove, and the bottom surface of the conductive plug is lower than the top surface of the channel layer; the drain electrode is located between the channel layer and the conductive plug, and the side wall of the drain electrode is partially covered by the conductive plug, so that the performance and the reliability of the semiconductor device can be improved at least under the condition that the size of the semiconductor device is not increased.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the rapid development of semiconductor technology, the market has higher and higher requirements for the integration, performance and reliability of integrated circuits. The market's requirements for the number of integrated transistors per unit area are constantly increasing, requiring the use of smaller transistor structures and more compact design layouts, which brings challenges to improving the performance and reliability of semiconductor devices.

[0003] Therefore, how to improve the performance and reliability of semiconductor devices without increasing the volume of transistor structures has become one of the technical problems that need to be solved urgently. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device and a method for preparing the same in response to the problems in the above-mentioned background technology, which can at least improve the performance and reliability of the semiconductor device while ensuring that the volume of the semiconductor device does not increase.

[0005] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a semiconductor device, including a substrate, a source, a dielectric core, a channel layer, a conductive plug and a drain, wherein the source is located on the substrate; the dielectric core is located on the side of the source away from the substrate; the channel layer is located between the dielectric core and the source, and covers the bottom surface and side walls of the dielectric core, the top surface of the channel layer is higher than the top surface of the dielectric core and forms a groove above the dielectric core; the conductive plug is at least partially located in the groove, and the bottom surface of the conductive plug is lower than the top surface of the channel layer; the drain is located between the channel layer and the conductive plug, and the side walls of the drain are partially covered by the conductive plug.

[0006] In the semiconductor device in the above embodiment, a source electrode is arranged on a substrate, a dielectric core is arranged on a side of the source electrode facing away from the substrate, a channel layer is arranged between the dielectric core and the source electrode, and covers the bottom surface and side walls of the dielectric core, so as to form a U-shaped channel layer, and the top surface of the channel layer is higher than the top surface of the dielectric core and forms a groove located above the dielectric core, so that a conductive plug is arranged at least partially in the groove, so that the bottom surface of the conductive plug is lower than the top surface of the channel layer, and a drain electrode is arranged between the channel layer and the conductive plug, so that the side wall of the drain electrode is partially covered by the conductive plug, so as to increase the contact area between the drain electrode and the conductive plug without increasing the volume of the semiconductor device, and relatively increase the volume of the conductive plug, reduce the connection impedance between the conductive plug and the drain electrode, and improve the performance and reliability of the semiconductor device.

[0007] In some embodiments, the longitudinal cross-section of the conductive plug is "T"-shaped, and the bottom surface of the conductive plug contacts the top surface of the dielectric core, so that the conductive plug is partially located in a groove formed on the top surface of the channel layer and located above the dielectric core. The volume of the conductive plug is relatively increased without increasing the volume of the semiconductor device. This facilitates the formation of a drain electrode covered by a portion of the conductive plug on the side wall of the groove, thereby further increasing the contact area between the conductive plug and the drain electrode.

[0008] In some embodiments, the conductive plug also includes a first portion located in the groove, and a second portion located above the first portion; the semiconductor device also includes an interconnection column, which is located on the top surface of the second portion, and the vertical center line of the second portion is between the vertical center line of the first portion and the vertical center line of the interconnection column, so as to facilitate setting the specific position of the interconnection column on the conductive plug according to the actual needs of preparing the integrated circuit, thereby meeting the requirements of the integrated circuit integration and reducing the complexity and cost of the preparation process.

[0009] In some embodiments, the thickness of the drains on both sides of the conductive plug is equal, so that the size and performance of the drains on both sides of the conductive plug are kept consistent as much as possible, thereby improving the performance and reliability of the semiconductor device.

[0010] In some embodiments, the bottom surface of the conductive plug is lower than the bottom surface of the drain and extends into the dielectric core, thereby further increasing the volume of the conductive plug without increasing the volume of the semiconductor device, thereby reducing the connection impedance between the conductive plug and the drain; and, the conductive plug extends into the dielectric core, which can also reduce the complexity and cost of the preparation process in actual application scenarios.

[0011] In some embodiments, the semiconductor device further includes a gate dielectric layer and a gate conductive layer, wherein the gate conductive layer is located on the outer sidewall of the channel layer; the gate dielectric layer is located between the gate conductive layer and the channel layer, and the top surface of the gate dielectric layer is higher than the bottom surface of the conductive plug.

[0012] In some embodiments, a second aspect of the present disclosure provides a method for preparing a semiconductor device, comprising:

[0013] Providing a substrate, the substrate including a source electrode;

[0014] forming an intermediate layer on a side of the source electrode facing away from the substrate, wherein the intermediate layer includes a groove exposing a portion of the source electrode;

[0015] forming a channel layer covering the sidewalls of the trench and the exposed source;

[0016] A dielectric core is formed in the trench, wherein a top surface of the channel layer is higher than a top surface of the dielectric core and forms a recess located above the dielectric core;

[0017] forming a drain electrode on a sidewall of the groove;

[0018] A conductive plug is formed which is at least partially located in the groove, wherein the bottom surface of the conductive plug is lower than the top surface of the channel layer, and the side wall of the drain is partially covered by the conductive plug.

[0019] In some embodiments, forming a drain on a sidewall of the groove includes:

[0020] A drain electrode is formed covering the sidewalls of the groove and the top surface of the dielectric core.

[0021] In some embodiments, forming a drain on a sidewall of the groove includes:

[0022] forming a drain electrode material layer, wherein the drain electrode material layer conformally covers the sidewalls of the groove and the top surface of the dielectric core;

[0023] At least the drain electrode material layer on the top surface of the dielectric core is removed, and the drain electrode material layer remaining on the sidewall of the groove is used to form the drain.

[0024] In some embodiments, during the removal of the drain material layer on the top surface of the dielectric core, over-etching forms a recess toward the dielectric core; the conductive plug is partially located in the recess, thereby further increasing the volume of the conductive plug without increasing the volume of the semiconductor device, thereby reducing the connection impedance between the conductive plug and the drain; and, in the actual process, during the removal of the drain material layer on the top surface of the dielectric core, over-etching forms a recess toward the dielectric core, which can ensure that the drain material layer on the top surface of the dielectric core is completely removed, so that the drains on both sides of the conductive plug are isolated.

[0025] In some embodiments, forming a conductive plug at least partially within the recess includes:

[0026] forming a barrier layer, wherein the barrier layer covers the top surface of the dielectric core and the drain;

[0027] A conductive layer is formed to fill the groove; the barrier layer and the conductive layer are used to form a conductive plug together.

[0028] In the above embodiment, after forming a barrier layer covering the top surface of the dielectric core and the drain, a conductive layer filling the groove is formed to prevent metal ions between the conductive layers from entering the dielectric core and forming a current leakage channel, thereby improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1Shown is a schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0031] Figure 2 It is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained in step S20 in a method for preparing a semiconductor device provided in one embodiment of the present disclosure;

[0032] FIG3 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a gate conductive portion is formed in step S40 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0033] FIG4 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming an intermediate layer and an isolation layer in step S40 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0034] FIG5 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a gate conductive layer is formed in step S40 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0035] FIG6 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a gate dielectric layer is formed in step S40 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0036] FIG. 7 is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor structure obtained after a trench is formed in step S40 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0037] FIG8 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming an initial channel layer and a dielectric core in step S80 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0038] FIG9 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a drain material layer is formed in step S100 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0039] FIG10 is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor structure obtained after a drain electrode is formed in step S100 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0040] FIG11 is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor structure obtained after a conductive plug is formed in step S110 in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0041] FIG12 is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming an isolation structure in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0042] FIG13 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after forming an interconnect pillar in a method for preparing a semiconductor device provided in an embodiment of the present disclosure;

[0043] FIG14a is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor device provided in an embodiment of the present disclosure;

[0044] FIG14 b is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor device provided in another embodiment of the present disclosure;

[0045] FIG15 is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor device provided in yet another embodiment of the present disclosure;

[0046] FIG. 16 is a schematic diagram showing a longitudinal cross-sectional structure of a semiconductor device provided in yet another embodiment of the present disclosure.

[0047] Description of reference numerals:

[0048] 100, substrate; 1, first metal layer; 2, first barrier layer; 1211, gate conductive material layer; 10, source; 1000, stack; 20, dielectric core; 31, initial channel layer; 30, channel layer; 23, groove; 231, recess; 40, conductive plug; 41, first part; 42, second part; 401, barrier layer; 402, conductive layer; 403, isolation groove; 101, initial groove; 11, groove; 61, gate dielectric layer; 62, gate conductive layer; 51, drain material layer; 50, drain; 60, gate; 80, interlayer dielectric layer; 110, isolation structure; 111, first dielectric layer; 112, second dielectric layer; 90, interconnect pillar; 12, middle layer; 13, isolation layer; 121, gate conductive part; 122, isolation part. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0051] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0055] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0056] See also Figure 1 In some embodiments, a method for preparing a semiconductor device is provided, comprising: steps S20 to S110, wherein:

[0057] Step S20: providing a substrate, wherein the substrate includes a source electrode;

[0058] Step S40: forming an intermediate layer on a side of the source electrode facing away from the substrate, wherein the intermediate layer includes a groove exposing a portion of the source electrode;

[0059] Step S60: forming a channel layer covering the sidewalls of the trench and the exposed source;

[0060] Step S80: forming a dielectric core in the trench, wherein a top surface of the channel layer is higher than a top surface of the dielectric core and a recess is formed above the dielectric core;

[0061] Step S100: forming a drain on the sidewall of the groove;

[0062] Step S110: forming a conductive plug at least partially located in the groove, wherein the bottom surface of the conductive plug is lower than the top surface of the channel layer, and the sidewall of the drain is partially covered by the conductive plug.

[0063] In some embodiments, see Figure 2The material of the substrate 100 provided in step S20 may include, but is not limited to, semiconductor materials, insulating materials, conductor materials, or any combination thereof. The substrate 100 is a semiconductor structure that provides mechanical support and electrical properties for manufacturing semiconductor devices. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a III / V semiconductor substrate or a II / VI semiconductor substrate. Those skilled in the art may select the type of substrate 100 according to the type of transistor formed on the substrate 100, and therefore the type of substrate 100 should not limit the scope of protection of the present disclosure.

[0064] As an example, see Figure 2 On the substrate 100, along a direction away from the substrate 100, for example, in an OY direction, a first metal layer 1, a first barrier layer 2, a source electrode 10, an interlayer dielectric layer 80, and a gate conductive material layer 1211 are sequentially stacked. Chemical vapor deposition or physical vapor deposition (PVD) processes may be used to sequentially form the first metal layer 1, the first barrier layer 2, the source electrode 10, the interlayer dielectric layer 80, and the gate conductive material layer 1211. The chemical vapor deposition process may include but is not limited to atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and the like. One or more of the following methods may be used. For example, low-pressure chemical vapor deposition has good step coverage. The use of low-pressure chemical vapor deposition can increase the deposition rate and output and reduce process costs. Low-pressure chemical vapor deposition does not require a carrier gas and can reduce particle contamination.

[0065] As an example, see Figure 2 The material of the first metal layer 1 may include but is not limited to at least one of titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, etc. The material of the first barrier layer 2 may include but is not limited to at least one of a titanium nitride layer, a cobalt layer, a platinum layer, and a titanium tungsten layer. The material of the source electrode 10 may include but is not limited to at least one of a semiconductor material, a metal, and a metal silicide. The material of the interlayer dielectric layer 80 may include but is not limited to at least one of silicon dioxide, silicon nitride, silicon oxynitride, amorphous carbon, etc. The material of the gate conductive material layer 1211 may include but is not limited to at least one of indium tin oxide, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, etc.

[0066] In some embodiments, referring to FIG. 3 , the forming of the intermediate layer 12 in step S40 may include: patterning the gate conductive material layer 1211 to obtain a plurality of gate conductive portions 121 spaced apart along the OX direction. The patterning may include a Self-Aligned Double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process.

[0067] In some embodiments, referring to FIG. 4 , the formation of the intermediate layer 12 in step S40 may include: forming an isolation portion 122 in the gap between the gate conductive portions 121 adjacent along the OX direction, and the gate conductive portions 121 and the isolation portions 122 alternately arranged in sequence along the OX direction are used to jointly constitute the intermediate layer 12. For example, a deposition process or a spin on glass coating (SOG) process may be used to form the isolation portion 122 located between the gate conductive portions 121 adjacent along the OX direction. The material of the isolation portion 122 may include but is not limited to at least one of silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON).

[0068] In some embodiments, please continue to refer to FIG4 , after forming the isolation portion 122, a deposition process may be used to form an isolation layer 13 covering the intermediate layer 12. The material of the isolation layer 13 may include but is not limited to at least one of silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON).

[0069] In some embodiments, referring to FIG. 5 , the formation of the intermediate layer 12 in step S40 may include: forming a plurality of initial grooves 101 penetrating the isolation layer 13 and the plurality of gate conductive portions 121 along a direction perpendicular to the substrate 100, such as the OY direction, and the remaining gate conductive portions 121 constitute the gate conductive layer 62 arranged at intervals along the OX direction; the initial grooves 101 are located between the gate conductive layers 62 adjacent to each other along the OX direction. For example, a patterned photoresist layer (not shown) may be first formed on the top surface of the isolation layer 13, and the patterned photoresist layer includes an opening pattern (not shown) for defining the initial grooves 101; then, the patterned photoresist layer is used as a mask to etch the isolation layer 13 and the gate conductive portions 121, so as to obtain a plurality of initial grooves 101 penetrating the isolation layer 13 and the plurality of gate conductive portions 121 along the OY direction, and the remaining gate conductive portions 121 constitute the gate conductive layer 62 arranged at intervals along the OX direction.

[0070] In some embodiments, please refer to Figure 6, after forming the initial trench 101 and before forming the channel layer, it also includes: using a deposition process to form a gate dielectric material layer (not shown) covering the top surface of the remaining isolation layer 13, and the sidewalls and bottom surface of the initial trench 101; using a dry etching process to remove the gate dielectric material layer located on the top surface of the remaining isolation layer 13 and the bottom surface of the initial trench 101, and the remaining gate dielectric material layer is used to form a gate dielectric layer 61.

[0071] In some embodiments, referring to FIG. 7 , after forming the gate dielectric layer 61 and before forming the channel layer, a dry etching process can be used to remove the interlayer dielectric layer 80 exposed by the multiple initial grooves 101 and located between the gate dielectric layers 61 adjacent to each other along the OX direction, thereby obtaining multiple grooves 11 spaced apart along the OX direction and exposing a portion of the source 10 .

[0072] In some embodiments, referring to FIG. 8 , forming the channel layer 30 covering the sidewalls of the trench 11 and the exposed source 10 in step S60 may include: forming an initial channel layer 31 covering the top surface of the remaining isolation layer 13 , the sidewalls of the trench 11 , and the exposed source 10 using a deposition process.

[0073] In some embodiments, please continue to refer to FIG. 8 , forming the dielectric core 20 in the trench 11 in step S80 may include: using a deposition process or a spin on glass coating (SOG) process to form a dielectric material (not shown) that fills the trench 11; etching back the dielectric material to obtain a dielectric core 20 whose top surface is flush with the top surface of the gate conductive layer 62, and a groove 23 located above the dielectric core 20. The material of the dielectric core 20 may include but is not limited to at least one of silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON).

[0074] In some embodiments, referring to FIG. 9 , forming the drain 50 on the sidewall of the groove 23 in step S100 may include: using an ALD deposition process to form a drain material layer 51 conformally covering the exposed surface of the initial channel layer 31 and the top surface of the dielectric core 20. The material of the drain material layer 51 may include but is not limited to at least one of a semiconductor material, a metal, a metal silicide, and the like.

[0075] In some embodiments, referring to FIG. 10 , a dry etching process may be used to remove at least the drain material layer 51 located on the top surface of the remaining isolation layer 13 to obtain the drain 50 located in the groove 23 .

[0076] In some embodiments, referring to FIG. 10 , during the process of removing the drain material layer 51 located on the top surface of the remaining isolation layer 13 , the initial channel layer 31 located on the top surface of the remaining isolation layer 13 can be simultaneously removed to obtain the channel layer 30 , and obtain the drain 50 covering the sidewalls of the groove 23 and the top surface of the dielectric core 20 , thereby reducing the complexity and cost of the preparation process.

[0077] In some embodiments, referring to FIG. 10 , during the process of removing the drain material layer 51 located on the top surface of the remaining isolation layer 13 , the drain material layer 51 located on the top surface of the dielectric core 20 can be simultaneously removed, and the drain material layer 51 retained in the groove 23 and located on the side wall of the channel layer 30 is used to form the drain 50 .

[0078] In some embodiments, referring to FIG. 10 , during the removal of the drain material layer 51 located on the top surface of the remaining isolation layer 13 and the top surface of the dielectric core 20 , an over-etching may be performed to form a recess 231 toward the dielectric core 20 ; so that a conductive plug 40 prepared subsequently is partially located within the recess 231 , thereby further increasing the volume of the conductive plug 40 without increasing the volume of the semiconductor device, thereby reducing the connection impedance between the conductive plug 40 and the drain.

[0079] In some embodiments, referring to FIG. 11 , the step S110 of forming the conductive plug 40 at least partially located in the groove 23 includes: forming a barrier material layer (not shown) covering the top surface of the remaining isolation layer 13, the sidewall of the drain 50, and the top surface of the dielectric core 20 by a deposition process, and then forming a conductive material layer (not shown) on the exposed surface of the barrier material layer, wherein the conductive material layer and the barrier material layer at least fill the remaining gap of the groove 23; after the top surface of the conductive material layer is planarized, a part of the conductive material layer and a part of the barrier material layer located on the top surface of the remaining isolation layer 13 are removed by photolithography and etching processes, and the remaining conductive material layer is used to form the conductive layer 402, and the remaining barrier material layer is used to form the barrier layer 401, and the barrier layer 401 and the conductive layer 402 are used to form the conductive plug 40, thereby obtaining the conductive plug 40 and the isolation groove 403 arranged alternately along the OX direction. The barrier material layer can prevent metal ions from entering the dielectric core 20 during the formation of the conductive material layer to form a current leakage channel, thereby improving the performance and reliability of the semiconductor device.

[0080] Please continue to refer to Figure 11. The gate conductive layer 62 is located on the outer wall of the channel layer 30. The gate dielectric layer 61 is located between the gate conductive layer 62 and the channel layer 30. The top surface of the gate dielectric layer 61 is higher than the bottom surface of the conductive plug 40. The gate dielectric layer 61 and the gate conductive layer 62 are used to jointly form the gate 60.

[0081] In some embodiments, please continue to refer to FIG. 11 , the gate 60 may partially surround the channel layer 30 to relatively increase the contact area between the gate 60 and the channel layer 30 , thereby improving the performance and reliability of the device.

[0082] In some embodiments, the gate may circumferentially surround the channel layer to form a ring-gate structure, further increasing the contact area between the gate and the channel layer and improving the performance and reliability of the device.

[0083] In some embodiments, referring to FIG. 12 , a first dielectric layer 111 is formed on the sidewall of the isolation groove 403, and then a second dielectric layer 112 is formed in the isolation groove 403. The first dielectric layer 111 and the second dielectric layer 112 are used to jointly form an isolation structure 110, and the isolation structure 110 at least fills the isolation groove 403. A planarization process can be used to make the top surface of the isolation structure 110 flush with the top surface of the conductive plug 40. The material of the first dielectric layer 111 includes, but is not limited to, silicon nitride. The material of the second dielectric layer 112 includes, but is not limited to, silicon oxide. The isolation structure composed of the stack of silicon nitride and silicon oxide can alleviate the warping stress generated by the adjacent conductive plug 40 on the substrate 100.

[0084] In some embodiments, please refer to Figure 13, the conductive plug 40 also includes a first portion 41 located in the groove 23, and a second portion 42 located above the first portion 41; the semiconductor device also includes an interconnection column 90, and the interconnection column 90 is located on the top surface of the second portion 42, and the vertical center line 42a of the second portion 42 is between the vertical center line 41a of the first portion 41 and the vertical center line 90a of the interconnection column 90, so as to facilitate setting the specific position of the interconnection column 90 on the conductive plug 40 according to the actual needs of preparing the integrated circuit, while meeting the requirements of the integrated circuit integration, reducing the complexity and cost of the preparation process.

[0085] In some embodiments, please continue to refer to Figure 13, an atomic layer deposition (ALD) process is used to form a drain material layer 51 that conformally covers the exposed surface of the initial channel layer 31 and the top surface of the dielectric core 20, so that the thickness of the drain 50 on both sides of the conductive plug 40 is equal, so that the size and performance of the drain 50 on both sides of the conductive plug 40 are kept as consistent as possible, thereby improving the performance and reliability of the semiconductor device.

[0086] In some embodiments, please refer to Figure 14a, a semiconductor device is provided, including a substrate 100, a source 10, a dielectric core 20, a channel layer 30, a conductive plug 40 and a drain, the source 10 is located on the substrate 100; the dielectric core 20 is located on the side of the source 10 away from the substrate 100; the channel layer 30 is located between the dielectric core 20 and the source 10, and covers the bottom surface and side walls of the dielectric core 20, the top surface of the channel layer 30 is higher than the top surface of the dielectric core 20 and forms a groove 23 located above the dielectric core 20; the conductive plug 40 is at least partially located in the groove 23, and the bottom surface of the conductive plug 40 is lower than the top surface of the channel layer 30; the drain is located between the channel layer 30 and the conductive plug 40, and the side walls of the drain are partially covered by the conductive plug 40.

[0087] For example, please continue to refer to Figure 14a. By setting the source 10 on the substrate 100, the dielectric core 20 is located on the side of the source 10 away from the substrate 100, and the channel layer 30 is located between the dielectric core 20 and the source 10, and covers the bottom surface and side walls of the dielectric core 20, a U-shaped channel layer 30 is formed, the top surface of the channel layer 30 is higher than the top surface of the dielectric core 20 and forms a groove 23 located above the dielectric core 20, so that the conductive plug 40 is at least partially located in the groove 23, so that the bottom surface of the conductive plug 40 is lower than the top surface of the channel layer 30, and the drain 50 is set between the channel layer 30 and the conductive plug 40, so that the side wall of the drain 50 is partially covered by the conductive plug 40.

[0088] In some embodiments, please continue to refer to Figure 14a. The longitudinal section of the conductive plug 40 is "T"-shaped, and the bottom surface of the conductive plug 40 contacts the top surface of the dielectric core 20, so that the conductive plug 40 is partially located in the groove 23 formed on the top surface of the channel layer 30 and located above the dielectric core 20. Without increasing the volume of the semiconductor device, the volume of the conductive plug 40 is relatively increased; it is convenient to form a drain covered by a portion of the conductive plug 40 on the side wall of the groove 23, and further increase the contact area between the conductive plug 40 and the drain.

[0089] In some embodiments, please continue to refer to Figure 14a, the conductive plug 40 also includes a first part 41 located in the groove 23, and a second part 42 located above the first part 41; the semiconductor device also includes an interconnection column 90, the interconnection column 90 is located on the top surface of the second part 42, and the vertical center line 42a of the second part 42 is between the vertical center line 41a of the first part 41 and the vertical center line 90a of the interconnection column 90, so as to facilitate setting the specific position of the interconnection column 90 on the conductive plug 40 according to the actual needs of preparing the integrated circuit, while meeting the requirements of the integrated circuit integration, reducing the complexity and cost of the preparation process.

[0090] In some embodiments, please refer to FIG. 14b. The differences between FIG. 14a and FIG. 14b include: in FIG. 14a, the bottom surface of the conductive plug 40 contacts the top surface of the dielectric core 20, and the drain 50 is located on the outer sidewall of the conductive plug 40; in FIG. 14b, the drain 50 includes a first portion 50a located between the bottom surface of the conductive plug 40 and the source 10, and a second portion 50b located on the outer sidewall of the conductive plug 40. Compared with FIG. 14a, FIG. 14b increases the contact area between the conductive plug 40 and the drain 50, which can reduce the connection impedance between the conductive plug 40 and the drain 50.

[0091] In some embodiments, referring to FIG. 15 , the bottom surface of the conductive plug 40 is lower than the bottom surface of the drain 50 and extends into the dielectric core 20, so that the volume of the conductive plug 40 is further increased without increasing the volume of the semiconductor device, thereby reducing the connection impedance between the conductive plug 40 and the drain; and the conductive plug 40 extends into the dielectric core 20, which can also reduce the complexity and cost of the preparation process in actual application scenarios.

[0092] In some embodiments, please continue to refer to Figure 14a, Figure 14b or Figure 15, the thickness of the drain 50 on both sides of the conductive plug 40 is equal, so that the size and performance of the drain on both sides of the conductive plug 40 are kept consistent as much as possible, thereby improving the performance and reliability of the semiconductor device.

[0093] In some embodiments, please continue to refer to FIG. 14a, FIG. 14b or FIG. 15, the semiconductor device further includes a gate dielectric layer 61 and a gate conductive layer 62, the gate conductive layer 62 is located on the outer sidewall of the channel layer 30; the gate dielectric layer 61 is located between the gate conductive layer 62 and the channel layer 30, and the top surface of the gate dielectric layer 61 is higher than the bottom surface of the conductive plug 40. The gate dielectric layer 61 and the gate conductive layer 62 are used to form a gate 60 together.

[0094] In some embodiments, the gate may partially surround the channel layer to relatively increase the contact area between the gate and the channel layer, thereby improving the performance and reliability of the device.

[0095] In some embodiments, the gate may circumferentially surround the channel layer to form a ring-gate structure, further increasing the contact area between the gate and the channel layer and improving the performance and reliability of the device.

[0096] Please continue to refer to FIG. 15 and FIG. 16. The difference between FIG. 16 and FIG. 15 is that in FIG. 16, the drain electrode 50 is located outside the groove 23 and between the bottom surface of the conductive plug 40 and the top surface of the channel layer 30. Compared with FIG. 16, FIG. 15 at least achieves an increase in the contact area between the drain electrode 50 and the conductive plug 40 without increasing the volume of the semiconductor device, and relatively increases the volume of the conductive plug 40, reduces the connection impedance between the conductive plug 40 and the drain electrode 50, and improves the performance and reliability of the semiconductor device.

[0097] In some embodiments, a memory is provided, comprising the semiconductor device in any embodiment of the present application.

[0098] In some embodiments, a memory is provided, including a memory manufactured using the semiconductor device manufacturing method in any embodiment of the present application.

[0099] In some embodiments, an electronic device is provided, comprising the semiconductor device in any one of the embodiments of the present application.

[0100] In some embodiments, an electronic device is provided, comprising the memory in any embodiment of the present application.

[0101] The aforementioned electronic devices include, but are not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems and vehicle-mounted DVDs, etc. Financial terminal products include ATM machines and self-service terminals, etc.

[0102] Please note that for the sake of simplicity of the specification, in the structural schematic diagrams given in the embodiments below, unless the corresponding cross-sectional structural schematic diagrams are given separately, other structural schematic diagrams of different perspectives of structures related to the inventive points of the embodiments of the present disclosure can refer to each other.

[0103] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A source electrode, located on the substrate; a dielectric core, located on a side of the source electrode facing away from the substrate; A channel layer is located between the dielectric core and the source electrode and covers the bottom surface and sidewalls of the dielectric core, wherein the top surface of the channel layer is higher than the top surface of the dielectric core and forms a groove located above the dielectric core; a conductive plug, at least partially located in the groove, wherein a bottom surface of the conductive plug is lower than a top surface of the channel layer; The drain is located between the channel layer and the conductive plug, and a sidewall of the drain is partially covered by the conductive plug.

2. The semiconductor device according to claim 1, wherein: The longitudinal section of the conductive plug is T-shaped, and the bottom surface of the conductive plug contacts the top surface of the dielectric core.

3. The semiconductor device according to claim 1, wherein: The conductive plug further includes a first portion located in the groove, and a second portion located above the first portion; the semiconductor device further includes: The interconnection column is located on the top surface of the second part, and the vertical center line of the second part is between the vertical center line of the first part and the vertical center line of the interconnection column.

4. The semiconductor device according to claim 1, wherein: The drain electrodes on both sides of the conductive plug have the same thickness.

5. The semiconductor device according to claim 1, wherein: The bottom surface of the conductive plug is lower than the bottom surface of the drain and extends into the dielectric core.

6. The semiconductor device according to claim 1, wherein: Also includes: A gate conductive layer, located on an outer sidewall of the channel layer; A gate dielectric layer is located between the gate conductive layer and the channel layer, and a top surface of the gate dielectric layer is higher than a bottom surface of the conductive plug.

7. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate includes a source electrode; forming an intermediate layer on a side of the source electrode facing away from the substrate, wherein the intermediate layer includes a groove exposing a portion of the source electrode; forming a channel layer covering the sidewalls of the trench and the exposed source; forming a dielectric core in the trench, wherein a top surface of the channel layer is higher than a top surface of the dielectric core and forms a recess above the dielectric core; forming a drain electrode on a sidewall of the groove; A conductive plug is formed which is at least partially located in the groove, wherein the bottom surface of the conductive plug is lower than the top surface of the channel layer, and the sidewall of the drain is partially covered by the conductive plug.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: A drain is formed on the sidewall of the groove, comprising: forming a drain electrode covering the sidewalls of the groove and the top surface of the dielectric core; or A drain electrode is formed covering the sidewall of the groove, and a bottom surface of the conductive plug contacts a top surface of the dielectric core.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: During the removal of the drain material layer on the top surface of the dielectric core, over-etching forms a recess toward the dielectric core; the conductive plug is partially located in the recess.

10. The method for preparing a semiconductor device according to claim 7, wherein: Forming a conductive plug at least partially within the recess comprises: forming a barrier layer, wherein the barrier layer covers the top surface of the dielectric core and the drain; A conductive layer is formed to fill the groove; the barrier layer and the conductive layer are used to jointly constitute the conductive plug.

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