Driving circuit, DC-DC converter and driving method

Abstract

The invention discloses a driving circuit, a DC-DC converter and a driving method. The driving circuit comprises a detection unit, a first delay control unit, a first driving unit, a second delay control unit and a second driving unit, the detection unit generates a detection signal based on the detection voltage and a preset voltage; the first delay control unit generates a first delay control signal based on the detection signal and the first driving signal; the first driving unit generates a second driving signal for driving the second transistor based on the first delay control signal and the control signal; the second delay control unit generates a second delay control signal based on the second driving signal; the second driving unit generates the first driving signal based on the second delay control signal and the control signal. According to the driving circuit, the DC-DC converter and the driving method, self-adaptive dead zone control can be added to the first transistor and the second transistor, the dead zone time can be more flexibly adapted and adjusted, and the driving circuit can be compatible with an external transistor with wider-range grid charge.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a driving circuit, a DC-DC converter and a driving method. Background Art

[0002] For DC-DC control, we cannot make specific predictions because the gate charge of the off-chip MOS tubes used by customers can range from a few nC to tens of nC. Although the chip has some dead time processing to prevent the upper and lower tubes from being turned on at the same time and thus burning the chip, the use of MOS tubes with a large range of unknown gate charges in the periphery still poses a risk of penetration.

[0003] The common method to prevent the penetration is as follows: the first driving signal HO and the second driving signal LO are detected inside the chip, and the dead time is considered according to the feedback signal generated after the detection.

[0004] For MOS tubes with unknown gate charges, the first drive signal HO and the second drive signal LO may flip very slowly or very quickly; and the feedback signal has a fixed logic transmission, which is very easy to be out of synchronization with the first drive signal HO and the second drive signal LO, resulting in the effective levels of the first drive signal HO and the second drive signal LO overlapping, and then a penetration phenomenon occurs, thereby burning the chip.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a driving circuit, a DC-DC converter and a driving method, which can set up a delay, ensure sufficient dead time and prevent the chip from burning.

[0007] In order to achieve the above-mentioned purpose, a specific embodiment of the present invention provides a driving circuit for driving a first transistor and a second transistor, wherein the first end of the first transistor and the second end of the second transistor are connected to form a detection point, and the driving circuit includes: a first delay control unit, a first driving unit, a second delay control unit and a second driving unit.

[0008] The first delay control unit is connected to the detection point and the control end of the first transistor to generate a first delay control signal based on the detection voltage of the detection point and the first drive signal of the control end of the first transistor; the first drive unit is connected to the output end of the first delay control unit, the control end of the second transistor and the control signal to generate a second drive signal for driving the second transistor based on the first delay control signal and the control signal; the second delay control unit is connected to the control end of the second transistor to generate a second delay control signal based on the second drive signal; the second drive unit is connected to the output end of the second delay control unit, the control end of the first transistor and the control signal to generate the first drive signal based on the second delay control signal and the control signal.

[0009] In one or more embodiments of the present invention, the driving circuit also includes a detection unit, which is connected to a detection point and a preset voltage to generate a detection signal based on the detection voltage of the detection point and the preset voltage. The first delay control unit is connected to the output end of the detection unit and the control end of the first transistor to generate a first delay control signal based on the detection signal and the first drive signal of the control end of the first transistor. The detection unit includes a comparator, a first input end of the comparator is connected to the detection point, and a second input end of the comparator is used to receive a preset voltage.

[0010] In one or more embodiments of the present invention, the preset voltage is a threshold voltage of the first transistor or the second transistor.

[0011] In one or more embodiments of the present invention, the first delay control unit includes a first logic module and a first delay module, the first input end of the first logic module is connected to the detection point, the second input end of the first logic module is connected to the control end of the first transistor, the first logic module is used to perform logical operations on the detection voltage of the detection point and the first drive signal, the output end of the first logic module is connected to the input end of the first delay module, and the output end of the first delay module is used to output a first delay control signal.

[0012] In one or more embodiments of the present invention, the first driving unit includes a first inverter and a second logic module, the input end of the first inverter is used to receive a control signal, the first input end of the second logic module is connected to the output end of the first inverter, the second input end of the second logic module is used to receive a first delayed control signal, the output end of the second logic module is connected to the control end of the second transistor, and the second logic module is used to perform a logic operation on the inverted signal generated by the first inverter and the first delayed control signal to generate a second driving signal.

[0013] In one or more embodiments of the present invention, the second delay control unit includes a second inverter and a second delay module, the input end of the second inverter is connected to the control end of the second transistor, the output end of the second inverter is connected to the input end of the second delay module, and the output end of the second delay module is used to output a second delay control signal.

[0014] In one or more embodiments of the present invention, the second driving unit includes a third logic module, a first input terminal of the third logic module is connected to the control signal, a second input terminal of the third logic module is used to receive a second delayed control signal, an output terminal of the third logic module is connected to the control terminal of the first transistor, and the third logic module is used to perform logical operations on the control signal and the second delayed control signal to generate a first driving signal.

[0015] In one or more embodiments of the present invention, the driving circuit further includes a third delay module, an input end of the third delay module is used to receive a control signal, and an output end of the third delay module is used to generate a characterization signal characterizing the minimum on-time of the first transistor.

[0016] The invention also discloses a DC-DC converter, comprising the driving circuit.

[0017] The present invention also discloses a driving method for driving a first transistor and a second transistor, wherein a first end of the first transistor and a second end of the second transistor are connected to form a detection point. Based on the driving circuit, the driving method includes:

[0018] Generate a first delayed control signal based on a detection voltage at the detection point and a first driving signal at the control terminal of the first transistor, wherein a first edge of the first delayed control signal has a first delay time with a first edge of the control signal;

[0019] Generate a second drive signal for driving the second transistor based on the first delayed control signal and the control signal, wherein the first edge of the control signal is used to generate a first edge of the second drive signal, and the second edge of the first delayed control signal is used to generate a second edge of the second drive signal;

[0020] Generate a second delayed control signal based on the second driving signal, wherein a first edge of the second delayed control signal and a first edge of the second driving signal have a first delay time;

[0021] The first driving signal is generated based on the second delayed control signal and the control signal. The first edge of the second delayed control signal is used to generate the first edge of the first driving signal. The second edge of the control signal is used to generate the second edge of the first driving signal.

[0022] In one or more embodiments of the present invention, a delay time between the second edge of the first delayed control signal and the second edge of the control signal is greater than a second delay time.

[0023] Compared with the prior art, the drive circuit, DC-DC converter and drive method of the present invention detect the detection point through the detection unit, and cooperate with the delay control of the first delay control unit and the second delay control unit to enable the first drive unit and the second drive unit to generate corresponding drive signals, thereby adding adaptive dead zone control to the first transistor and the second transistor, and can more flexibly adapt to and adjust the dead zone time, so as to be compatible with external transistors with a wider range of gate charges. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 FIG. 4 is a circuit schematic diagram of a driving circuit in an embodiment.

[0026] Figure 2 FIG. 4 is a timing diagram of various signals in a driving circuit in an embodiment. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0029] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0030] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0031] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0032] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.

[0033] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0034] like Figure 1 As shown, a driving circuit in an embodiment of the present invention is used to drive a first transistor M1 and a second transistor M2, and the first end of the first transistor M1 and the second end of the second transistor M2 are connected to form a detection point P. The driving circuit includes: a detection unit 10, a first delay control unit 20, a first driving unit 30, a second delay control unit 40 and a second driving unit 50. In one embodiment, the first transistor M1 and the second transistor M2 are N-channel MOS transistors, the first end of the first transistor M1 and the first end of the second transistor M2 are sources, the second end of the first transistor M1 and the second end of the second transistor M2 are drains, and the control end of the first transistor M1 and the control end of the second transistor M2 are gates. In other embodiments, the first transistor M1 and / or the second transistor M2 are P-channel MOS transistors.

[0035] The detection unit 10 is connected to the detection point P and the preset voltage Vth to generate a detection signal SW_REG based on the detection voltage SW at the detection point P and the preset voltage Vth.

[0036] The first delay control unit 20 is connected to the output terminal of the detection unit 10 and the control terminal of the first transistor M1 to generate a first delay control signal HS_BBM based on the detection signal SW_REG and the first driving signal HO of the control terminal of the first transistor M1.

[0037] The first driving unit 30 is connected to the output terminal of the first delay control unit 20 , the control terminal of the second transistor M2 and the control signal PWM to generate a second driving signal LO for driving the second transistor M2 based on the first delay control signal HS_BBM and the control signal PWM.

[0038] The second delay control unit 40 is connected to the control terminal of the second transistor M2 to generate a second delay control signal LO_BBM based on the second driving signal LO.

[0039] The second driving unit 50 is connected to the output terminal of the second delay control unit 40 , the control terminal of the first transistor M1 , and the control signal PWM to generate the first driving signal HO based on the second delay control signal LO_BBM and the control signal PWM.

[0040] In one embodiment, the detection unit 10 includes a comparator CMP, a first input terminal of the comparator CMP is connected to the detection point P, and a second input terminal of the comparator CMP is used to receive a preset voltage Vth. The preset voltage Vth is a threshold voltage of the first transistor M1 or the second transistor M2. Preferably, the preset voltage Vth is a threshold voltage of the first transistor M1, and the threshold voltage is about 0.5 V. When the detection voltage SW at the detection point P is greater than the preset voltage Vth, the detection signal SW_REG is a high level, and when the detection voltage SW at the detection point P is less than the preset voltage Vth, the detection signal SW_REG is a low level.

[0041] The first delay control unit 20 includes a first logic module 21 and a first delay module 22. The first input end of the first logic module 21 is connected to the output end of the detection unit 10, and the second input end of the first logic module 21 is connected to the control end of the first transistor M1. The first logic module 21 is used to perform a logic operation on the detection signal SW_REG and the first drive signal HO. The output end of the first logic module 21 is connected to the input end of the first delay module 22. The output end of the first delay module 22 is used to output the first delay control signal HS_BBM. In one embodiment, the first logic module 21 is a NOR gate NOR, and the NOR gate NOR performs a logic operation and a non-logic operation on the detection signal SW_REG and the first drive signal HO to generate a logic signal HO_REG. The first delay module 22 delays the rising edge of the logic signal HO_REG to generate the first delay control signal HS_BBM. In other embodiments, the first delay module 22 can also delay the falling edge or be used to perform rising edge delay and falling edge delay.

[0042] The first delay control unit 20 can adjust its own delay time based on the trimming code TRIM. In one embodiment, the first delay module 22 can adjust its own rising edge delay time under the control of the trimming code TRIM, thereby controlling the dead time.

[0043] The first driving unit 30 includes a first inverter NOT1 and a second logic module 31, wherein the input end of the first inverter NOT1 is used to receive the control signal PWM, the first input end of the second logic module 31 is connected to the output end of the first inverter NOT1, the second input end of the second logic module 31 is used to receive the first delayed control signal HS_BBM, the output end of the second logic module 31 is connected to the control end of the second transistor M2, and the second logic module 31 is used to perform a logic operation on the inverted signal generated by the first inverter NOT1 and the first delayed control signal HS_BBM to generate the second driving signal LO. In one embodiment, the second logic module 31 is a first AND gate AND1, the first inverter NOT1 is used to invert the control signal PWM, and the first AND gate AND1 performs an AND logic operation on the inverted signal of the control signal PWM and the first delayed control signal HS_BBM to generate the second driving signal LO.

[0044] The second delay control unit 40 includes a second inverter NOT2 and a second delay module 41, the input end of the second inverter NOT2 is connected to the control end of the second transistor M2, the output end of the second inverter NOT2 is connected to the input end of the second delay module 41, and the output end of the second delay module 41 is used to output the second delay control signal LO_BBM. In one embodiment, the second inverter NOT2 is used to invert the second drive signal LO, and the second delay module 41 is used to delay the rising edge of the inverted signal of the second drive signal LO to generate the second delay control signal LO_BBM. In other embodiments, the second delay module 41 can also delay the falling edge or be used to delay the rising edge and the falling edge.

[0045] The second delay control unit 40 adjusts its own delay time based on the trimming code TRIM. In one embodiment, the second delay module 41 can adjust its own delay time under the control of the trimming code TRIM, thereby controlling the dead time.

[0046] The second driving unit 50 includes a third logic module, a first input end of the third logic module is connected to the control signal PWM, a second input end of the third logic module is used to receive the second delayed control signal LO_BBM, an output end of the third logic module is connected to the control end of the first transistor M1, and the third logic module is used to perform a logic operation on the control signal PWM and the second delayed control signal LO_BBM to generate the first driving signal HO. In one embodiment, the third logic module is a second AND gate AND2, and the second AND gate AND2 is used to perform an AND logic operation on the control signal PWM and the second delayed control signal LO_BBM to generate the first driving signal HO.

[0047] like Figure 2 As shown, when the control signal PWM flips to a high level, the second drive signal LO flips to a low level, and the second transistor M2 is turned off. At the same time, after the second drive signal LO is inverted and the rising edge is delayed in the second delay control unit 40, the second delayed control signal LO_BBM flips to a high level. The first delay time here is recorded as t1. At this time, the high-level second delayed control signal LO_BBM is ANDed with the high-level control signal PWM, the first drive signal HO flips to a high level, and the first transistor M1 is turned on.

[0048] When the first drive signal HO flips to a high level, the logic signal HO_REG and the first delay control signal HS_BBM flip to a low level; the first transistor M1 is turned on, causing the detection voltage SW of the detection point P to rise, and when the detection voltage SW is greater than the preset voltage Vth, the detection signal SW_REG flips to a high level, the logic signal HO_REG and the first delay control signal HS_BBM continue to maintain a low level, and the second drive signal LO continues to maintain a low level.

[0049] When the control signal PWM flips to a low level, the first drive signal HO flips to a low level, the first transistor M1 is turned off, and the detection voltage SW drops. When the detection voltage SW drops to a preset voltage Vth, the detection signal SW_REG flips to a low level, and the logic signal HO_REG flips to a high level. The time for the detection voltage SW to drop to the preset voltage Vth is recorded as tk; after the rising edge delay of the first delay module 22, the first delayed control signal HS_BBM flips to a high level, and the second delay time here is recorded as t2. An AND logic operation is performed on the inverted signal of the control signal PWM and the high-level first delayed control signal HS_BBM, the second drive signal LO flips to a high level, and the second transistor M2 is turned on.

[0050] Depend on Figure 2 It can be seen that the setting of the first delay time t1 and the second delay time t2 can ensure sufficient dead time to prevent the first transistor M1 and the second transistor M2 from being connected, and the first delay time t1 and the second delay time t2 can be flexibly adjusted as needed, thereby flexibly adjusting the dead time.

[0051] The externally arranged first transistor M1 and second transistor M2 will result in different conversion rates of the first drive signal HO and the second drive signal LO. If the intermediate value of the first drive signal HO or the second drive signal LO, i.e., 1 / 2*HO or 1 / 2*LO, is used as the detection value for feedback, it is easy to cause the first transistor M1 and the second transistor M2 to be connected. In one embodiment, by setting the threshold voltage of the first transistor M1 or the second transistor M2 to a preset voltage Vth, the subsequent logic flip will be triggered only when the detection voltage SW at the detection point P rises and falls to the threshold voltage, ensuring that the second transistor M2 is turned on after the first transistor M1 is fully turned off. In other embodiments, if the conversion rates of the first drive signal HO and the second drive signal LO are not considered, the detection unit 10 may not be set.

[0052] like Figure 1 As shown, the driving circuit also includes a third delay module 60, the input end of the third delay module 60 is used to receive the control signal PWM, and the output end of the third delay module 60 is used to generate a characterization signal TON_MIN characterizing the minimum on-time of the first transistor M1. In one embodiment, the third delay module 60 delays the rising edge of the control signal PWM to generate the characterization signal TON_MIN, and the delay time is also t1. Through the monitoring of the characterization signal TON_MIN by the subsequent circuit, the minimum on-time of the first transistor M1 can be obtained, and the appropriate minimum on-time ensures that the first transistor M1 can work normally. In other embodiments, the third delay module 60 can also delay the falling edge as needed or be used for rising edge delay and falling edge delay.

[0053] Depend on Figure 2 and Figure 1 It can be seen that since a delay module (such as the second delay module 41) is provided in the driving circuit, when the control signal PWM is flipped to a high level, the first driving signal HO is not immediately flipped to a high level, but the first driving signal HO is flipped to a high level after a delay time t1, so a delay error will be generated when testing the minimum on-time of the first transistor M1. Therefore, a third delay module 60 is provided to delay the rising edge of the control signal PWM, and the characterization signal TON_MIN is flipped to a high level after a delay of t1 after the control signal PWM is flipped to a high level, thereby offsetting this part of the delay error and obtaining an accurate minimum on-time of the first transistor M1.

[0054] The present invention also discloses a DC-DC converter, comprising the above-mentioned drive circuit, a first transistor M1, a second transistor M2, an inductor L, a first capacitor C1 and a second capacitor C2, wherein the first end of the inductor L is connected to the detection point P, the second end of the inductor L is connected to the first end of the second capacitor C2 to form an output end VOUT, the second end of the second capacitor C2 is connected to a ground voltage, the first end of the first capacitor C1 is connected to the second end of the first transistor M1 to form an input end VIN connected to a power supply voltage, and the second end of the first capacitor C1 is connected to the ground voltage.

[0055] The present invention also discloses a driving method for driving a first transistor M1 and a second transistor M2, wherein a first end of the first transistor M1 and a second end of the second transistor M2 are connected to form a detection point P. Based on the above driving circuit, the driving method includes:

[0056] The first delay control unit 20 generates a first delay control signal HS_BBM based on the detection voltage SW at the detection point P and the first drive signal HO at the control end of the first transistor M1, and there is a first delay time t1 between the first edge (falling edge) of the first delay control signal HS_BBM and the first edge (rising edge) of the control signal PWM. In one embodiment, there is a delay time greater than the second delay time t2 between the second edge (rising edge) of the first delay control signal HS_BBM and the second edge (falling edge) of the control signal PWM.

[0057] The second drive signal LO for driving the second transistor M2 is generated by the first drive unit 30 based on the first delayed control signal HS_BBM and the control signal PWM. The first edge (rising edge) of the control signal PWM is used to generate the first edge (falling edge) of the second drive signal LO, and the second edge (rising edge) of the first delayed control signal HS_BBM is used to generate the second edge (rising edge) of the second drive signal LO.

[0058] The second delay control unit 40 generates a second delay control signal LO_BBM based on the second driving signal LO, and a first delay time t1 exists between a first edge (rising edge) of the second delay control signal LO_BBM and a first edge (falling edge) of the second driving signal LO.

[0059] The first drive signal HO is generated by the second drive unit 50 based on the second delayed control signal LO_BBM and the control signal PWM, the first edge (rising edge) of the second delayed control signal LO_BBM is used to generate the first edge (rising edge) of the first drive signal HO, and the second edge (falling edge) of the control signal PWM is used to generate the second edge (falling edge) of the first drive signal HO.

[0060] Further, in one embodiment, a detection unit 10 is provided, and a detection signal is generated by the detection unit 10 based on the detection voltage SW of the detection point P and the preset voltage Vth; and then a first delay control unit 20 generates a first delay control signal HS_BBM based on the detection signal SW_REG and the first drive signal HO at the control end of the first transistor M1. For specific methods, please refer to the circuit description part.

[0061] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0062] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A driving circuit for driving a first transistor and a second transistor, wherein a first end of the first transistor and a second end of the second transistor are connected to form a detection point, characterized in that: The driving circuit comprises: A first delay control unit is connected to the detection point and the control terminal of the first transistor to generate a first delay control signal based on the detection voltage of the detection point and the first drive signal of the control terminal of the first transistor; a first driving unit connected to an output terminal of the first delay control unit, a control terminal of the second transistor and a control signal, so as to generate a second driving signal for driving the second transistor based on the first delay control signal and the control signal; a second delay control unit connected to the control terminal of the second transistor to generate a second delay control signal based on the second driving signal; and The second driving unit is connected to the output terminal of the second delay control unit, the control terminal of the first transistor and the control signal to generate a first driving signal based on the second delay control signal and the control signal.

2. The driving circuit according to claim 1, characterized in that: The driving circuit also includes a detection unit, which is connected to a detection point and a preset voltage to generate a detection signal based on the detection voltage at the detection point and the preset voltage. The first delay control unit is connected to the output end of the detection unit and the control end of the first transistor to generate a first delay control signal based on the detection signal and a first drive signal at the control end of the first transistor. The detection unit includes a comparator, a first input end of the comparator is connected to the detection point, and a second input end of the comparator is used to receive a preset voltage.

3. The driving circuit according to claim 2, characterized in that: The preset voltage is a threshold voltage of the first transistor or the second transistor.

4. The driving circuit according to claim 1, characterized in that: The first delay control unit includes a first logic module and a first delay module, the first input end of the first logic module is connected to the detection point, the second input end of the first logic module is connected to the control end of the first transistor, the first logic module is used to perform logical operations on the detection voltage of the detection point and the first drive signal, the output end of the first logic module is connected to the input end of the first delay module, and the output end of the first delay module is used to output a first delay control signal.

5. The driving circuit according to claim 1, characterized in that: The first driving unit includes a first inverter and a second logic module, the input end of the first inverter is used to receive a control signal, the first input end of the second logic module is connected to the output end of the first inverter, the second input end of the second logic module is used to receive a first delayed control signal, the output end of the second logic module is connected to the control end of the second transistor, and the second logic module is used to perform a logic operation on the inverted signal generated by the first inverter and the first delayed control signal to generate a second driving signal.

6. The driving circuit according to claim 1, characterized in that: The second delay control unit includes a second inverter and a second delay module, the input end of the second inverter is connected to the control end of the second transistor, the output end of the second inverter is connected to the input end of the second delay module, and the output end of the second delay module is used to output a second delay control signal.

7. The driving circuit according to claim 1, characterized in that: The second driving unit includes a third logic module, a first input end of the third logic module is connected to the control signal, a second input end of the third logic module is used to receive a second delayed control signal, an output end of the third logic module is connected to the control end of the first transistor, and the third logic module is used to perform logical operations on the control signal and the second delayed control signal to generate a first driving signal.

8. The driving circuit according to claim 1, characterized in that: The driving circuit further includes a third delay module, an input end of the third delay module is used to receive a control signal, and an output end of the third delay module is used to generate a characterization signal characterizing a minimum on-time of the first transistor.

9. A DC-DC converter, characterized in that: The invention comprises a driving circuit as claimed in any one of claims 1 to 8.

10. A driving method for driving a first transistor and a second transistor, wherein a first end of the first transistor and a second end of the second transistor are connected to form a detection point, characterized in that: Based on the driving circuit according to any one of claims 1 to 8, the driving method comprises: Generate a first delayed control signal based on a detection voltage at the detection point and a first driving signal at the control terminal of the first transistor, wherein a first edge of the first delayed control signal has a first delay time with a first edge of the control signal; Generate a second drive signal for driving the second transistor based on the first delayed control signal and the control signal, wherein the first edge of the control signal is used to generate a first edge of the second drive signal, and the second edge of the first delayed control signal is used to generate a second edge of the second drive signal; Generate a second delayed control signal based on the second driving signal, wherein a first edge of the second delayed control signal and a first edge of the second driving signal have a first delay time; The first driving signal is generated based on the second delayed control signal and the control signal. The first edge of the second delayed control signal is used to generate the first edge of the first driving signal. The second edge of the control signal is used to generate the second edge of the first driving signal. 11 . The driving method according to claim 10 , wherein a delay time between the second edge of the first delayed control signal and the second edge of the control signal is greater than a second delay time.

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