A Class E Differential Colpitts Oscillator

Abstract

The present invention belongs to the field of electronic components, and in particular, relates to a class-E differential colpitts oscillator, comprising a first MOS tube M1, a second MOS tube M2, a first inductor L1 to a sixth inductor L6, a first capacitor C1 to a fourth capacitor C4, a first switch capacitor array SCA1 and a second switch capacitor array SCA2. The present invention enables the oscillator to oscillate at the high frequency peak of a two-port network, thereby achieving a larger size of inductor and capacitor values, avoiding the deterioration of phase noise and tuning range in traditional structures, and significantly improving the energy efficiency of the oscillator by using a class-E structure, while also achieving a differential colpitts oscillator, and achieving a drain-gate voltage gain greater than 1 in the two-port network, which helps to reduce the noise coefficient of the oscillator.

Description

Technical Field

[0001] The invention relates to the field of electronic components, and in particular to a class-E differential Colpitts oscillator. Background Art

[0002] In modern RF communication systems, the quality of the local oscillator (LO) signal directly affects the wireless communication data rate and bit error rate. As the generator of the local oscillator signal, the performance of the voltage-controlled oscillator (VCO) directly affects the quality of the local oscillator signal. In the millimeter wave frequency band, as the operating frequency increases, the quality factor of passive devices will significantly decrease, especially in the V band. Passive devices with low quality factors seriously deteriorate the phase noise of the voltage-controlled oscillator, and parasitic capacitance seriously deteriorates the tuning range of the voltage-controlled oscillator. Ultimately, the V-band voltage-controlled oscillator faces a serious performance trade-off between the phase noise tuning range and power consumption, which deteriorates the overall performance (FoM) of the oscillator. Traditional cross-coupled transistor structure oscillators need to reduce the size of inductors and capacitors to oscillate at higher frequencies, but smaller inductor size will lead to a lower inductor quality factor, thereby deteriorating the oscillator phase noise; smaller capacitor size will make the oscillator more sensitive to parasitic capacitance, thereby deteriorating the tuning range. Summary of the invention

[0003] The object of the present invention is to overcome the deficiencies of the prior art and provide a class-E differential Colpitts oscillator, which can make the oscillator oscillate at the high frequency peak of the two-port network, thereby achieving larger inductor and capacitor values ​​and suppressing the deterioration of phase noise and tuning range.

[0004] The object of the present invention is achieved by the following technical solutions: A class E differential colpitts oscillator, comprising a first MOS transistor M1, a second MOS transistor M2, a first inductor L1 to a sixth inductor L6, a first capacitor C1 to a fourth capacitor C4, a first switch capacitor array SCA1 and a second switch capacitor array SCA2;

[0005] The drain of the first MOS transistor M1 is connected to the first end of the first switch capacitor array SCA1, and the second end of the first switch capacitor array SCA1 is connected to the drain of the second MOS transistor M2;

[0006] The gate of the first MOS transistor M1 is connected to the first end of the second switch capacitor array SCA2, and the second end of the second switch capacitor array SCA2 is connected to the gate of the second MOS transistor M2;

[0007] The source of the first MOS tube M1 is connected to the source of the second MOS tube M2 through the fifth inductor L5 and the sixth inductor L6 in sequence; the common end of the fifth inductor L5 and the sixth inductor L6 is grounded;

[0008] A second inductor L2 is connected between the gate and drain of the first MOS transistor M1; a fourth inductor L4 is connected between the gate and drain of the second MOS transistor M2;

[0009] The first end of the first capacitor C1 is connected to the first end of the first switched capacitor array SCA1, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second end of the first switched capacitor array SCA1;

[0010] The first end of the fourth capacitor C4 is connected to the second end of the third capacitor C3, the second end of the fourth capacitor C4 is connected to the gate of the second MOS transistor M2, and the first end of the third capacitor C3 is connected to the gate of the first MOS transistor M1; a control voltage port V is also connected between the first end of the fourth capacitor C4 and the second end of the third capacitor C3. CTRL ; Adjust the control voltage port V CTRL The voltage changes the capacitance value of the two varactors (variable capacitors) C3 and C4.

[0011] Preferably, the first end of the first inductor L1 is connected to the first end of the first switched capacitor array SCA1, the second end of the first inductor L1 is connected to the first end of the third inductor L3, and the second end of the third inductor L3 is connected to the second end of the first switched capacitor array SCA1; a VDD power supply port is also connected between the second end of the first inductor L1 and the first end of the third inductor L3.

[0012] Preferably, the first switch capacitor array SCA1 includes a switch array unit, one end of the switch array unit is connected to the first end of the first switch capacitor array SCA1, and the other end of the switch array unit is connected to the second end of the first switch capacitor array SCA1. The second switch capacitor array SCA2 includes three switch array units in parallel, one end of each switch array unit is connected to the first end of the second switch capacitor array SCA2, and the other end of each switch array unit is connected to the second end of the second switch capacitor array SCA2. The switch array unit includes a capacitor, a switch, and a capacitor connected in series in sequence.

[0013] The beneficial effects of the present invention are as follows: the present invention enables the oscillator to oscillate at the high frequency peak of the two-port network, thereby achieving a larger inductor and capacitor value, and solving the deterioration of the phase noise and tuning range of the traditional structure. The class-E structure of the present invention significantly improves the energy efficiency of the oscillator, and also realizes a differential Colpitts oscillator, and at the same time realizes a drain-gate voltage gain greater than 1 in the two-port network, which helps to reduce the noise coefficient of the oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural schematic diagram of the present invention;

[0015] Figure 2 It is a schematic diagram of the structure of the oscillator two-port network resonant circuit;

[0016] Figure 3 It is a schematic diagram of the equivalent two-port network model of the oscillator;

[0017] Figure 4 It is a schematic diagram of Z parameter analysis of equivalent two-port network;

[0018] Figure 5 is the normalized frequency contour plot of the oscillator;

[0019] Figure 6 It is a schematic diagram of the voltage and current waveform of the oscillator transistor and the energy efficiency simulation curve;

[0020] Figure 7 is the oscillator ISF function and the transistor transconductance (G M ) and channel conductance (G DS ) Schematic diagram;

[0021] Figure 8 This is a graph showing the relationship between the oscillator phase noise PN and the comprehensive performance FoM at a frequency offset of 10MHz and the frequency. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0023] like Figure 1 As shown, a class E differential Colpitts oscillator includes a first MOS transistor M1, a second MOS transistor M2, a first inductor L1 to a sixth inductor L6, a first capacitor C1 to a fourth capacitor C4, a first switch capacitor array SCA1 and a second switch capacitor array SCA2;

[0024] The drain of the first MOS transistor M1 is connected to the first end of the first switch capacitor array SCA1, and the second end of the first switch capacitor array SCA1 is connected to the drain of the second MOS transistor M2;

[0025] The gate of the first MOS transistor M1 is connected to the first end of the second switch capacitor array SCA2, and the second end of the second switch capacitor array SCA2 is connected to the gate of the second MOS transistor M2;

[0026] The source of the first MOS tube M1 is connected to the source of the second MOS tube M2 through the fifth inductor L5 and the sixth inductor L6 in sequence; the common end of the fifth inductor L5 and the sixth inductor L6 is grounded;

[0027] A second inductor L2 is connected between the gate and drain of the first MOS transistor M1; a fourth inductor L4 is connected between the gate and drain of the second MOS transistor M2;

[0028] The first end of the first capacitor C1 is connected to the first end of the first switched capacitor array SCA1, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second end of the first switched capacitor array SCA1;

[0029] The first end of the fourth capacitor C4 is connected to the second end of the third capacitor C3, the second end of the fourth capacitor C4 is connected to the gate of the second MOS transistor M2, and the first end of the third capacitor C3 is connected to the gate of the first MOS transistor M1; a power supply port V is also connected between the first end of the fourth capacitor C4 and the second end of the third capacitor C3. CTRL ;

[0030] The first end of the first inductor L1 is connected to the first end of the first switched capacitor array SCA1, the second end of the first inductor L1 is connected to the first end of the third inductor L3, and the second end of the third inductor L3 is connected to the second end of the first switched capacitor array SCA1; a power supply port is also connected between the second end of the first inductor L1 and the first end of the third inductor L3.

[0031] The invented class-E differential colpitts oscillator structure includes a pair of NMOS (M1 and M2), the first inductor L1 to the sixth inductor L6, fixed capacitors (C1 and C2), variable capacitors (C3 and C4) and switched capacitor arrays (SCA1 and SCA2). Through the coupling between the first inductor and the fourth inductor and the second inductor and the third inductor, a two-port network is realized between the drain and gate of the transistor, achieving a drain-gate voltage gain greater than 1, which helps to reduce the noise coefficient of the oscillator. At the same time, the two-port network realizes a class-E oscillator structure, which improves the energy efficiency of the oscillator, wherein the oscillator energy efficiency is defined as:

[0032]

[0033] Where P DC represents the oscillator DC power consumption, represents the transistor transient voltage waveform, Represents the transistor transient current waveform.

[0034] like Figure 2 As shown, the structure of the two-port network resonant circuit of the oscillator is shown, where the influence of the fifth and sixth inductors at the source end is ignored to simplify the model. SCA1 and the first and second capacitors are equivalent to capacitor C D1 and C D2 , SCA2 and the third and fourth variable capacitors are equivalent to capacitor CG1 and C G2 Considering the influence of transistor parasitic capacitance, the parasitic capacitance C of the source and drain of the first MOS tube P1 , the parasitic capacitance C of the gate-source terminal of the first MOS tube P3 , the parasitic capacitance C of the source and drain of the second MOS tube P2 , the parasitic capacitance C of the gate-source terminal of the second MOS tube P4 .

[0035] Since the entire oscillator structure is a differential structure and is completely symmetrical, the equivalent two-port network model of any differential structure is as follows: Figure 3 As shown, P1 is the drain terminal of the transistor, P2 is the gate terminal of the transistor, the transistor refers to M1 or M2, and the first and third inductors are both L D (L1=L3=L D ), the second and fourth inductors are both L G (L2=L4=L G ), the mutual inductance generated by the coupling between inductors is M ( ), k represents the coupling coefficient, and the equivalent drain capacitance is C D (C D1 =C D2 =C D ), the equivalent gate capacitance is C G (C G1 =C G2 =C G ), the parasitic capacitance is C P (C P1 =C P2 =C P3 =C P4 =C P ), the transistor transconductance is G m , the output resistance is 1 / G ds .

[0036] For the two-port network of the present application, there are two impedance peaks, the low-frequency impedance peak corresponds to a 0-degree phase, and the high-frequency impedance peak corresponds to a 180-degree phase; the traditional oscillator adopts a cross-coupled transistor structure, requiring the resonant cavity to provide a 0-degree phase to maintain oscillation, and the oscillator oscillates at a low frequency ( ); Traditional cross-coupled oscillators can oscillate at higher frequencies by reducing the size of inductors and capacitors, but smaller inductor size will lead to a decrease in the inductor quality factor, thereby deteriorating the oscillator phase noise; smaller capacitor size will make the oscillator more sensitive to parasitic capacitance, thereby deteriorating the tuning range;

[0037] The structure of the present application adopts a non-cross-coupling connection mode, by directly connecting the feedback inductor across the drain and gate of the transistor, so that the resonant cavity provides a 180-degree phase to maintain oscillation, thereby making the oscillator oscillate at a high frequency ( ), larger inductor and capacitor values ​​can be used to avoid the degradation of phase noise caused by small inductor values ​​and the degradation of tuning range caused by small capacitors;

[0038] like Figure 4 As shown in the figure, the equivalent two-port network structure of the oscillator and the Z parameter analysis; from the figure, it can be seen that the traditional two-port network cross-coupled oscillator requires the two ports to provide 0 degrees (Z 21 ) phase, the present invention directly connects the feedback inductor across the drain and gate of the transistor, requiring two ports to provide 180 degrees (Z 21 ) phase to maintain oscillation. 21 Amplitude higher than Z 11 ( ), the subscript H represents the high frequency peak, thereby achieving a drain-gate voltage gain greater than 1 (A V = V G / V D , A V >1), reducing the oscillator noise.

[0039] like Figure 5 As shown in the figure, it is the normalized frequency contour map of the oscillator. Compared with the traditional Class B cross-coupled oscillator, the operating frequency is The oscillation frequency of the two-port network is 31% higher than that of the traditional Class B oscillator. Without considering the parasitic capacitance, the ±15% C D and C G The capacitance tuning range will bring a 15% frequency variation range to both the traditional structure and the present structure. Considering the influence of parasitic capacitance (assuming C P =30%C G =30%C D ), the tuning range of the traditional structure will be significantly reduced to 9.4%, while the tuning range of the present structure is slightly reduced to 12.1%. Compared with the traditional structure, the tuning range is increased by 29%.

[0040] In the embodiment of the present application, the first and third inductors are implemented by the highest aluminum metal layer (AP layer), and the inductor line width is 9 μm. The second inductor and the fourth to sixth inductors are implemented by the thickest copper metal layer (M10 layer), wherein the second and fourth inductors have a line width of 9 μm, and the fifth and sixth inductors have a line width of 5.4 μm. By reducing the power supply (V DD ) and ground (V SS ) to reduce the impact of the common-mode loop on oscillator noise.

[0041] like Figure 6 The figure shows the voltage and current waveforms of the oscillator transistor and the energy efficiency simulation curve. The traditional Class E oscillator achieves completely staggered transistor voltage and current by controlling the tube current and voltage waveforms, and can theoretically achieve 100% oscillator energy efficiency; however, as the frequency increases, the influence of transistor parasitic capacitance increases significantly, and the traditional Class E structure cannot accurately achieve waveform misalignment. The oscillator of the present application achieves transistor voltage and current waveform misalignment through a structure similar to that of the Class E oscillator, thereby enhancing the oscillator energy efficiency, and ultimately achieves an energy efficiency of 71.4% in the V band.

[0042] like Figure 7 As shown, the oscillator ISF function and transistor transconductance (G M ) and channel conductance (G DS ), the Colpitts structure makes the maximum value of the channel conductance correspond to the zero point of the ISF function, thereby reducing the oscillator phase noise.

[0043] In the embodiment of the present application, the oscillator of the present invention is manufactured using a 40nm CMOS process, and the area of ​​the chip core module is 0.23 mm × 0.2 mm (0.046 mm 2 The chip power supply voltage is constant at 0.5V, and the power consumption is 5.5–10.5mW. The oscillator output signal is first down-converted by the mixer (where the LO signal is set at 45GHz and generated by the signal generator), and then the phase noise of the mixer intermediate frequency output signal is tested by a phase noise analyzer.

[0044] Figure 8 The relationship between the oscillator phase noise PN and the comprehensive performance FoM at a 10MHz frequency offset is shown, where the lowest phase noise is –124.9dBc / Hz, the chip power consumption is 5.5mW, and the corresponding highest FoM is 192.3 dBc / Hz. The overall tuning frequency range of the oscillator is 47.28–58.41GHz, and the relative tuning range is 21.1%.

[0045] The above is a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A class E differential colpitts oscillator, characterized in that: It includes a first MOS transistor M1, a second MOS transistor M2, a first inductor L1 to a sixth inductor L6, a first capacitor C1 to a fourth capacitor C4, a first switch capacitor array SCA1 and a second switch capacitor array SCA2; The drain of the first MOS transistor M1 is connected to the first end of the first switch capacitor array SCA1, and the second end of the first switch capacitor array SCA1 is connected to the drain of the second MOS transistor M2; The gate of the first MOS transistor M1 is connected to the first end of the second switch capacitor array SCA2, and the second end of the second switch capacitor array SCA2 is connected to the gate of the second MOS transistor M2; The source of the first MOS tube M1 is connected to the source of the second MOS tube M2 through the fifth inductor L5 and the sixth inductor L6 in sequence; the common end of the fifth inductor L5 and the sixth inductor L6 is grounded; A second inductor L2 is connected between the gate and drain of the first MOS transistor M1; a fourth inductor L4 is connected between the gate and drain of the second MOS transistor M2; The first end of the first capacitor C1 is connected to the first end of the first switched capacitor array SCA1, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second end of the first switched capacitor array SCA1; The first end of the fourth capacitor C4 is connected to the second end of the third capacitor C3, the second end of the fourth capacitor C4 is connected to the gate of the second MOS transistor M2, and the first end of the third capacitor C3 is connected to the gate of the first MOS transistor M1; a control voltage port V is also connected between the first end of the fourth capacitor C4 and the second end of the third capacitor C3. CTRL ; The first end of the first inductor L1 is connected to the first end of the first switched capacitor array SCA1, the second end of the first inductor L1 is connected to the first end of the third inductor L3, and the second end of the third inductor L3 is connected to the second end of the first switched capacitor array SCA1; a VDD power supply port is also connected between the second end of the first inductor L1 and the first end of the third inductor L3.

2. A Class-E differential Colpitts oscillator according to claim 1, characterized in that: The first MOS transistor M1 and the second MOS transistor M2 are both NMOS transistors.

3. A Class-E differential Colpitts oscillator according to claim 1, characterized in that: The first capacitor C1 and the second capacitor C2 are fixed capacitors.

4. A Class-E differential Colpitts oscillator according to claim 1, characterized in that: The third capacitor C3 and the fourth capacitor C4 are variable capacitors.

5. The class-E differential Colpitts oscillator according to claim 1, characterized in that: The first switched capacitor array SCA1 includes a switch array unit, one end of the switch array unit is connected to the first end of the first switched capacitor array SCA1, and the other end of the switch array unit is connected to the second end of the first switched capacitor array SCA1.

6. A Class-E differential Colpitts oscillator according to claim 1, characterized in that: The second switch capacitor array SCA2 includes three parallel switch array units, one end of each switch array unit is connected to the first end of the second switch capacitor array SCA2, and the other end of each switch array unit is connected to the second end of the second switch capacitor array SCA2.

7. A Class E differential Colpitts oscillator according to claim 5 or 6, characterized in that: The switch array unit includes a capacitor, a switch and a capacitor connected in series in sequence.

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