Logic power supply circuit for solving gain climbing problem of power amplifier

Abstract

The invention discloses a logic power supply circuit for solving the gain climbing problem of a power amplifier, and the circuit comprises a logic circuit which is used for receiving an enable signal and generating an output control signal; the power supply circuit is used for generating voltage signals with different voltage values; the switching circuit is used for outputting bias voltage according to the output control signal and the voltage signals with different voltage values, the gain climbing problem of the power amplifier is solved, the throughput can be obviously improved in the application of a communication base station system, and the communication quality is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a logic power supply circuit that solves the gain climbing problem of a power amplifier. Background Art

[0002] At present, RF power amplifiers are widely used in mobile terminals, communication base stations and IoT consumer products. As an indispensable device in these application scenarios, the performance of the power amplifier largely determines the scope and conditions of use of the product. Due to the large power consumption and chip area of ​​the power amplifier, the power amplifier will generate heat and uneven heat distribution when it is powered on.

[0003] When the power amplifier is powered on, the temperature of the RF amplifier tube inside the chip rises quickly, while the temperature of the bias tube changes less. The gain of the RF amplifier tube will slowly increase with the temperature rise of the amplifier tube and eventually reach stability. This phenomenon of slow signal ramping when the power amplifier is powered on will affect the throughput in communication base station system applications. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a logic power supply circuit for solving the gain climbing problem of a power amplifier, which solves the gain climbing problem of the power amplifier.

[0005] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: a logic power supply circuit for solving the gain climbing problem of a power amplifier, comprising:

[0006] Logic circuit: used to receive the enable signal and generate the output control signal;

[0007] Power supply circuit: used to generate voltage signals with different voltage values;

[0008] Switching circuit: used to output bias voltage according to output control signal and voltage signals of different voltage values.

[0009] Further: the logic circuit includes an IO module, the Vin terminal of the IO module is used to receive an enable signal EN, the Vp terminal of the IO module is respectively connected to the Vin terminal of the first phase converter and the Vin terminal of the buffer, the Vout terminal of the first phase converter outputs a control signal en; the Vout terminal of the buffer outputs a control signal enp; the Vn terminal of the IO module is connected to the Vin terminal of the second phase converter, and the Vout terminal of the second phase converter outputs a control signal enn;

[0010] The logic circuit also includes a first delay module, a Vin end of the first delay module receives a control signal enp, a Vout end of the first delay module is respectively connected to the Vin end of the third isochronous device and the Vin end of the second delay module, the Vout ends of the second delay modules are connected to the Vin end of the fourth isochronous device, the Vout end of the third isochronous device is respectively connected to the Vin2 end of the first XOR gate and the Vin1 end of the second XOR gate, the Vin1 end of the first XOR gate receives the output control signal enp, the Vout end of the first XOR gate is connected to the Vin end of the fifth isochronous device, and the Vout end of the fifth isochronous device outputs a control signal en1; the Vin2 end of the second XOR gate is connected to the Vout end of the fourth isochronous device, the Vout end of the second XOR gate is connected to the Vin end of the sixth isochronous device, and the Vout end of the sixth isochronous device outputs a control signal en2; the Vout end of the fourth isochronous device is also connected to the Vin end of the seventh isochronous device, and the Vout end of the seventh isochronous device outputs a control signal en3.

[0011] Further: when the enable signal EN is at a high level, the control signal en outputs a high level, the control signal enp outputs a high level, the control signal enn outputs a low level, the control signal en1 and the control signal en2 output pulse signals with different timings, and the control signal en3 outputs a delayed step signal.

[0012] Further: the IO module includes a field effect transistor M1, the gate of the field effect transistor M1 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to one end of the resistor R1, the other end of the resistor R1 serves as the Vin end of the IO module, the source of the field effect transistor M1 serves as the VSS end of the IO module, the drain of the field effect transistor M1 is respectively connected to one end of the resistor R4 and the gate of the field effect transistor M2, the drain of the field effect transistor M1 also serves as the Vn end of the IO module, the other end of the resistor R4 serves as the VDD end of the IO module, the other end of the resistor R4 is also connected to one end of the resistor R5, the other end of the resistor R5 is connected to the drain of the field effect transistor M2, the drain of the field effect transistor M2 serves as the Vp end of the IO module, the other end of the resistor R3 is also connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the source of the field effect transistor M2.

[0013] Further: the first phase converter, the second phase converter, the third phase converter, the fourth phase converter, the fifth phase converter, the sixth phase converter and the seventh phase converter have the same structure. The first phase converter includes a field effect transistor M3, the gate of the field effect transistor M3 is connected to one end of the resistor R7, the other end of the resistor R7 serves as the Vin end of the first phase converter, the source of the field effect transistor M3 serves as the VSS end of the first phase converter, the drain of the field effect transistor M3 is respectively connected to one end of the resistor R8 and the gate of the field effect transistor M4, the other end of the resistor R8 serves as the VDD end of the first phase converter IO, the other end of the resistor R8 is also connected to one end of the resistor R9, the other end of the resistor R9 is connected to the drain of the field effect transistor M4, the drain of the field effect transistor M4 serves as the Vout end of the first phase converter, the other end of the resistor R7 is also connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the source of the field effect transistor M4.

[0014] Further: the buffer includes a field effect transistor M5, the gate of the field effect transistor M5 serves as the Vin terminal of the buffer, the gate of the field effect transistor M5 is also connected to the gate of the field effect transistor M6, the source of the field effect transistor M5 serves as the VSS terminal of the buffer, the source of the field effect transistor M5 is also connected to the source of the field effect transistor M6, the source of the field effect transistor M7 and the source of the field effect transistor M8, the drain of the field effect transistor M5 is respectively connected to the drain of the field effect transistor M6, the gate of the field effect transistor M7, the gate of the field effect transistor M8 and one end of the resistor R10, the other end of the resistor R10 serves as the VDD terminal of the buffer, the other end of the resistor R10 is also connected to one end of the resistor R11, the other end of the resistor R11 serves as the Vout terminal of the buffer, and the other end of the resistor R11 is also connected to the drain of the field effect transistor M7 and the drain of the field effect transistor M8.

[0015] Further: the first delay module and the second delay module have the same structure, the first delay module includes a field effect transistor M9, the source of the field effect transistor M9 serves as the VSS end of the first delay module, the gate of the field effect transistor M9 is respectively connected to one end of the resistor R12 and one end of the capacitor C1, the other end of the resistor R12 serves as the Vin end of the first delay module, the other end of the capacitor C1 is respectively connected to one end of the capacitor C2 and the source of the field effect transistor M10, the other end of the capacitor C2 is respectively connected to one end of the resistor R13 and the gate of the field effect transistor M10, the other end of the resistor R13 is respectively connected to the drain of the field effect transistor M9 and one end of the resistor R14, the other end of the resistor R14 serves as the VDD end of the first delay module, the other end of the resistor R14 is also connected to one end of the resistor R15, the other end of the resistor R15 is connected to the drain of the field effect transistor M10, and the drain of the field effect transistor M10 also serves as the Vout end of the first delay module.

[0016] Further: the first XOR gate and the second XOR gate have the same structure, the first XOR gate includes a field effect transistor M11, the source of the field effect transistor M11 serves as the VSS terminal of the first XOR gate, the source of the field effect transistor M11 is also connected to the source of the field effect transistor M12 and the source of the field effect transistor M13, the gate of the field effect transistor M11 serves as the Vin1 terminal of the first XOR gate, the gate of the field effect transistor M11 is also connected to the gate of the field effect transistor M18, the source of the field effect transistor M18 serves as the VSS terminal of the first XOR gate, The VSS end of the first XOR gate, the drain of the field effect tube M11 is respectively connected to one end of the resistor R16, the drain of the field effect tube M12 and the gate of the field effect tube M13, the other end of the resistor R16 serves as the VDD end of the first XOR gate, the other end of the resistor R16 is also connected to one end of the resistor R17, the other end of the resistor R17 is respectively connected to the drain of the field effect tube M13 and the gate of the field effect tube M14, the drain of the field effect tube M14 serves as the VSS end of the first XOR gate The drain of the field effect tube M14 is also connected to the drain of the field effect tube M15, the source of the field effect tube M15 serves as the Vout terminal of the first XOR gate, the source of the field effect tube M15 is also connected to one end of the resistor R19, the other end of the resistor R19 serves as the first VDD terminal of the first XOR gate, the gate of the field effect tube M15 is respectively connected to one end of the resistor R18 and the source of the field effect tube M16, the other end of the resistor R18 serves as the second VDD terminal of the first XOR gate, The drain of the field effect transistor M16 is connected to the source of the field effect transistor M14, the gate of the field effect transistor M16 is respectively connected to one end of the resistor R20 and the drain of the field effect transistor M17, the other end of the resistor R20 serves as the third VDD end of the first XOR gate, the source of the field effect transistor M17 is connected to the drain of the field effect transistor M18, the gate of the field effect transistor M17 is connected to the gate of the field effect transistor M12, and the gate of the field effect transistor M12 also serves as the Vin2 end of the first XOR gate.

[0017] Further: the power supply circuit receives a VBIAS voltage, and after the VBIAS voltage passes through diodes of different numbers and different areas, a voltage value signal out1, a voltage value signal out2 and a voltage value signal out3 are generated, and the voltage value signal out1, the voltage value signal out2 and the voltage value signal out3 are used to provide voltage signals of different steps to the output voltage VB;

[0018] The larger the diode area, the higher the voltage value generated after passing through the diode, and the more diodes passed, the smaller the voltage value generated;

[0019] The power supply circuit further generates a power supply signal VDD1 and a power supply signal VVD2 , wherein the power supply signal VDD1 and the power supply signal VVD2 are used to supply power to each logic unit in the logic circuit and control the power consumption of the logic unit.

[0020] Further: the switch circuit includes a first switch tube SW1, a second switch tube SW2, a third switch tube SW3, a fourth switch tube SW4 and a fifth switch tube SW5; the first switch tube SW1 transmits the voltage signal out1 to the VB terminal according to the timing of the control signal en1; the second switch tube SW2 transmits the voltage signal out2 to the VB terminal according to the timing of the control signal en2; the third switch tube SW3 transmits the voltage signal out3 to the VB terminal according to the timing of the control signal en3; the fourth switch tube SW4 receives the control signal en, the fifth switch tube SW5 receives the control signal enn, and the fourth switch tube SW4 and the fifth switch tube SW5 adopt a series-parallel structure to ensure fast opening and closing of the signal; the VB terminal is used to output a bias voltage.

[0021] The beneficial effects of the present invention are:

[0022] 1. For the gain climbing problem caused by heat generation or uneven heat distribution of the power amplifier, the logic power supply circuit can solve this problem by compensating the bias voltage of the power amplifier;

[0023] 2. The present application proposes a logic power supply circuit structure that can achieve compensation effects of arbitrary time width and signal strength, greatly improving flexibility and meeting more usage scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the logic power supply circuit structure for solving the gain climbing problem of the power amplifier;

[0025] Figure 2 It is a topological structure diagram of the logic circuit;

[0026] Figure 3 It is the schematic diagram of the IO module and the corresponding block diagram;

[0027] Figure 4 It is the principle diagram of the phase converter and the corresponding block diagram;

[0028] Figure 5 It is the principle diagram of the delay module and the corresponding block diagram;

[0029] Figure 6 It is the buffer schematic diagram and corresponding block diagram;

[0030] Figure 7 It is the XOR gate schematic diagram and corresponding block diagram;

[0031] Figure 8 It is the topological structure diagram of the power supply circuit;

[0032] Fig. 9 It is the topological structure diagram of the switching circuit;

[0033] Fig.10 A schematic diagram of a power amplifier using the logic power supply circuit described in this application;

[0034] Fig.11 It is the timing diagram of each signal in the logic circuit;

[0035] Fig.12 is the output bias voltage timing diagram;

[0036] Fig.13 It is a schematic diagram of gain climbing phenomenon;

[0037] Fig.14 This is a schematic diagram of the no-gain climbing phenomenon;

[0038] Fig.15 A schematic diagram of improving the gain climbing phenomenon by using the logic power supply circuit described in this application. DETAILED DESCRIPTION

[0039] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0040] like Figure 1 As shown, in one embodiment of the present invention, a logic power supply circuit for solving the gain climbing problem of a power amplifier includes:

[0041] Logic circuit: used to receive the enable signal and generate the output control signal;

[0042] Power supply circuit: used to generate voltage signals with different voltage values;

[0043] Switching circuit: used to output bias voltage according to output control signal and voltage signals of different voltage values.

[0044] like Figure 2As shown, the logic circuit includes an IO module, the Vin terminal of the IO module is used to receive an enable signal EN, the Vp terminal of the IO module is respectively connected to the Vin terminal of the first phase converter and the Vin terminal of the buffer, the Vout terminal of the first phase converter outputs a control signal en; the Vout terminal of the buffer outputs a control signal enp; the Vn terminal of the IO module is connected to the Vin terminal of the second phase converter, and the Vout terminal of the second phase converter outputs a control signal enn;

[0045] The logic circuit also includes a first delay module, a Vin end of the first delay module receives a control signal enp, a Vout end of the first delay module is respectively connected to the Vin end of the third isochronous device and the Vin end of the second delay module, the Vout ends of the second delay modules are connected to the Vin end of the fourth isochronous device, the Vout end of the third isochronous device is respectively connected to the Vin2 end of the first XOR gate and the Vin1 end of the second XOR gate, the Vin1 end of the first XOR gate receives the output control signal enp, the Vout end of the first XOR gate is connected to the Vin end of the fifth isochronous device, and the Vout end of the fifth isochronous device outputs a control signal en1; the Vin2 end of the second XOR gate is connected to the Vout end of the fourth isochronous device, the Vout end of the second XOR gate is connected to the Vin end of the sixth isochronous device, and the Vout end of the sixth isochronous device outputs a control signal en2; the Vout end of the fourth isochronous device is also connected to the Vin end of the seventh isochronous device, and the Vout end of the seventh isochronous device outputs a control signal en3.

[0046] When the enable signal EN arrives, the logic circuit will output control signals en, enn, en1, en2 and en3 to control the corresponding switch tubes in the switch circuit. The specific control process is: when the enable signal EN is at a high level, the control signal en outputs a high level, the control signal enp outputs a high level, the control signal enn outputs a low level, the control signal en1 and the control signal en2 output pulse signals with different timings, and the control signal en3 outputs a delayed step signal.

[0047] like Figure 3As shown, the IO module includes a field effect transistor M1, a gate of the field effect transistor M1 is connected to one end of a resistor R3, the other end of the resistor R3 is connected to one end of a resistor R1, the other end of the resistor R1 serves as a Vin end of the IO module, the source of the field effect transistor M1 serves as a VSS end of the IO module, the drain of the field effect transistor M1 is respectively connected to one end of a resistor R4 and a gate of a field effect transistor M2, the drain of the field effect transistor M1 also serves as a Vn end of the IO module, the other end of the resistor R4 serves as a VDD end of the IO module, the other end of the resistor R4 is also connected to one end of a resistor R5, the other end of the resistor R5 is connected to the drain of the field effect transistor M2, the drain of the field effect transistor M2 serves as a Vp end of the IO module, the other end of the resistor R3 is also connected to one end of a resistor R2, and the other end of the resistor R2 is connected to the source of the field effect transistor M2.

[0048] The working principle of the IO module is that when Vin is at a high level, the drain of the field effect tube M1 outputs a low level, that is, Vn is a low level, and the drain of the field effect tube M2 is a high level, that is, Vp is a high level. The IO module can output two inverted signals.

[0049] like Figure 4 As shown, the first phase converter, the second phase converter, the third phase converter, the fourth phase converter, the fifth phase converter, the sixth phase converter and the seventh phase converter have the same structure. The first phase converter includes a field effect transistor M3, the gate of the field effect transistor M3 is connected to one end of the resistor R7, the other end of the resistor R7 serves as the Vin end of the first phase converter, the source of the field effect transistor M3 serves as the VSS end of the first phase converter, the drain of the field effect transistor M3 is respectively connected to one end of the resistor R8 and the gate of the field effect transistor M4, the other end of the resistor R8 serves as the VDD end of the first phase converter IO, the other end of the resistor R8 is also connected to one end of the resistor R9, the other end of the resistor R9 is connected to the drain of the field effect transistor M4, the drain of the field effect transistor M4 serves as the Vout end of the first phase converter, the other end of the resistor R7 is also connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the source of the field effect transistor M4.

[0050] In this embodiment, all phase comparators are composed of two inverters. The working principle diagram shows that when Vin is at a high level, the drain of the field effect tube M3 is at a low level, and the drain of the field effect tube M4 is at a high level. The phase comparator mainly plays two roles in this design: 1. Isolation of front and rear signals; 2. By increasing the VDD supply voltage of the phase comparator, the output voltage of the phase comparator can be increased, thereby providing a high-level control voltage to the switch tube.

[0051] like Figure 5As shown, the buffer includes a field effect transistor M5, the gate of the field effect transistor M5 serves as the Vin terminal of the buffer, the gate of the field effect transistor M5 is also connected to the gate of the field effect transistor M6, the source of the field effect transistor M5 serves as the VSS terminal of the buffer, the source of the field effect transistor M5 is also connected to the source of the field effect transistor M6, the source of the field effect transistor M7 and the source of the field effect transistor M8, the drain of the field effect transistor M5 is respectively connected to the drain of the field effect transistor M6, the gate of the field effect transistor M7, the gate of the field effect transistor M8 and one end of a resistor R10, the other end of the resistor R10 serves as the VDD terminal of the buffer, the other end of the resistor R10 is also connected to one end of a resistor R11, the other end of the resistor R11 serves as the Vout terminal of the buffer, and the other end of the resistor R11 is also connected to the drain of the field effect transistor M7 and the drain of the field effect transistor M8.

[0052] The buffer is used to improve the driving capability of the control circuit. The field effect transistor M5 and the field effect transistor M6 are connected in parallel, and the field effect transistor M7 and the field effect transistor M8 are connected in parallel. The output voltages Vout and Vin are kept in phase.

[0053] like Figure 6 As shown, the first delay module and the second delay module have the same structure. The first delay module includes a field effect transistor M9, the source of the field effect transistor M9 serves as the VSS end of the first delay module, the gate of the field effect transistor M9 is respectively connected to one end of the resistor R12 and one end of the capacitor C1, the other end of the resistor R12 serves as the Vin end of the first delay module, the other end of the capacitor C1 is respectively connected to one end of the capacitor C2 and the source of the field effect transistor M10, the other end of the capacitor C2 is respectively connected to one end of the resistor R13 and the gate of the field effect transistor M10, the other end of the resistor R13 is respectively connected to the drain of the field effect transistor M9 and one end of the resistor R14, the other end of the resistor R14 serves as the VDD end of the first delay module, the other end of the resistor R14 is also connected to one end of the resistor R15, the other end of the resistor R15 is connected to the drain of the field effect transistor M10, and the drain of the field effect transistor M10 also serves as the Vout end of the first delay module.

[0054] The working principle of the delay module is that the input signal Vin passes through the RC charging and discharging circuit formed by the resistor R12, the capacitor C1, the resistor R13, and the capacitor C2 to realize the signal delay function, and a two-stage inverter is used to realize the same phase of Vout and Vin.

[0055] like Figure 7As shown, the first XOR gate and the second XOR gate have the same structure, the first XOR gate includes a field effect transistor M11, the source of the field effect transistor M11 serves as the VSS terminal of the first XOR gate, the source of the field effect transistor M11 is also connected to the source of the field effect transistor M12 and the source of the field effect transistor M13, the gate of the field effect transistor M11 serves as the Vin1 terminal of the first XOR gate, the gate of the field effect transistor M11 is also connected to the gate of the field effect transistor M18, the source of the field effect transistor M18 serves as the Vin2 terminal of the first XOR gate, The drain of the field effect tube M11 is respectively connected to one end of the resistor R16, the drain of the field effect tube M12 and the gate of the field effect tube M13, the other end of the resistor R16 serves as the VDD end of the first XOR gate, the other end of the resistor R16 is also connected to one end of the resistor R17, the other end of the resistor R17 is respectively connected to the drain of the field effect tube M13 and the gate of the field effect tube M14, the drain of the field effect tube M14 serves as the VSS end of the first XOR gate. The drain of the field effect tube M14 is also connected to the drain of the field effect tube M15, the source of the field effect tube M15 serves as the Vout terminal of the first XOR gate, the source of the field effect tube M15 is also connected to one end of the resistor R19, the other end of the resistor R19 serves as the first VDD terminal of the first XOR gate, the gate of the field effect tube M15 is respectively connected to one end of the resistor R18 and the source of the field effect tube M16, the other end of the resistor R18 serves as the second VDD terminal of the first XOR gate, and the The drain of the field effect tube M16 is connected to the source of the field effect tube M14, the gate of the field effect tube M16 is respectively connected to one end of the resistor R20 and the drain of the field effect tube M17, the other end of the resistor R20 serves as the third VDD end of the first XOR gate, the source of the field effect tube M17 is connected to the drain of the field effect tube M18, the gate of the field effect tube M17 is connected to the gate of the field effect tube M12, and the gate of the field effect tube M12 also serves as the Vin2 end of the first XOR gate.

[0056] The working principle of the XOR gate is as follows: when Vin1=0 and Vin2=0, Vout=0; when Vin1=0 and Vin2=1, Vout=1; when Vin1=1 and Vin2=0, Vout=1; when Vin1=1 and Vin2=1, Vout=0; where "0" represents a low potential and "1" represents a high potential.

[0057] like Figure 8As shown, the power supply circuit receives a VBIAS voltage, and after the VBIAS voltage passes through diodes of different numbers and different areas, a voltage value signal out1, a voltage value signal out2 and a voltage value signal out3 are generated, and the voltage value signal out1, the voltage value signal out2 and the voltage value signal out3 are used to provide voltage signals of different steps to the output voltage VB;

[0058] The larger the diode area, the higher the voltage value generated after passing through the diode, and the more diodes passed, the smaller the voltage value generated;

[0059] The power supply circuit further generates a power supply signal VDD1 and a power supply signal VVD2 , wherein the power supply signal VDD1 and the power supply signal VVD2 are used to supply power to each logic unit in the logic circuit and control the power consumption of the logic unit.

[0060] In this embodiment, the voltage value signal out1, the voltage value signal out2 and the voltage value signal out3 are arranged in order of voltage value as out1>out2>out3;

[0061] like Fig. 9 As shown, the switch circuit includes a first switch tube SW1, a second switch tube SW2, a third switch tube SW3, a fourth switch tube SW4 and a fifth switch tube SW5; the first switch tube SW1 transmits the voltage signal out1 to the VB terminal according to the timing of the control signal en1; the second switch tube SW2 transmits the voltage signal out2 to the VB terminal according to the timing of the control signal en2; the third switch tube SW3 transmits the voltage signal out3 to the VB terminal according to the timing of the control signal en3; the fourth switch tube SW4 receives the control signal en, and the fifth switch tube SW5 receives the control signal enn. The fourth switch tube SW4 and the fifth switch tube SW5 adopt a series-parallel structure to ensure fast opening and closing of the signal; the VB terminal is used to output a bias voltage.

[0062] The working principle of the switching circuit is as follows: the three voltage signals out1, out2 and out3 can be transmitted to the VB port respectively through the switch tubes SW1, SW2 and SW3 according to the timing of the three control signals en1, en2 and en3, thereby completing the final output of the VB bias voltage that changes with time. The switch tubes SW4 and SW5 adopt a series and parallel structure to ensure the rapid opening and closing of the signal.

[0063] like Fig.10 FIG. 1 is a schematic diagram of a power amplifier using the logic power supply circuit described in this embodiment. Fig.10 The power amplifier shown in the figure is used for simulation experiment. In this simulation experiment, the timing diagram of each signal of the logic circuit is as follows Fig.11The output bias voltage timing diagram is shown in Fig.12 shown; through Fig.11 and Fig.12 It can be seen that the circuit can generate the required timing voltage waveform, and then obtain the bias voltage waveform that changes with time, thereby improving the gain climbing phenomenon;

[0064] like Fig.13 and Fig.14 As shown in the figure, there are schematic diagrams of gain climbing phenomenon and no gain climbing phenomenon, respectively. The yellow is the EN enable signal, and the light blue is the output signal of the amplifier. When the EN enable signal is turned on, if there is a gain climbing phenomenon, the output signal of the amplifier will show a slow rising trend, and will not immediately reach the maximum value and remain stable. The power amplifier with this phenomenon will affect the throughput in the communication application of the base station;

[0065] like Fig.15 As shown, it is a schematic diagram of using the logic power supply circuit recorded in the present application to improve the gain climbing phenomenon. The logic power supply circuit recorded in the present application is used to control the bias voltage of the power amplifier over time, so that the gain climbing phenomenon caused by heat in the power amplifier can be adaptively improved with the time-varying bias voltage.

[0066] By utilizing the logic power supply circuit structure proposed in this application, it is possible to realize pulse signals of arbitrary timing and adjustment of arbitrary VB voltage. Moreover, it is highly adaptable to power amplifiers of various application scenarios, not only for the power amplifier structure described in this article, but also for a wider range of usage scenarios.

[0067] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A logic power supply circuit for solving the gain climbing problem of a power amplifier, characterized in that: include: Logic circuit: used to receive the enable signal and generate the output control signal; Power supply circuit: used to generate voltage signals with different voltage values; Switching circuit: used to output bias voltage according to output control signal and voltage signals of different voltage values.

2. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 1, characterized in that: The logic circuit includes an IO module, wherein the Vin terminal of the IO module is used to receive an enable signal EN, the Vp terminal of the IO module is respectively connected to the Vin terminal of the first phase converter and the Vin terminal of the buffer, the Vout terminal of the first phase converter outputs a control signal en; the Vout terminal of the buffer outputs a control signal enp; the Vn terminal of the IO module is connected to the Vin terminal of the second phase converter, and the Vout terminal of the second phase converter outputs a control signal enn; The logic circuit also includes a first delay module, a Vin end of the first delay module receives a control signal enp, a Vout end of the first delay module is respectively connected to the Vin end of the third isochronous device and the Vin end of the second delay module, the Vout ends of the second delay modules are connected to the Vin end of the fourth isochronous device, the Vout end of the third isochronous device is respectively connected to the Vin2 end of the first XOR gate and the Vin1 end of the second XOR gate, the Vin1 end of the first XOR gate receives the output control signal enp, the Vout end of the first XOR gate is connected to the Vin end of the fifth isochronous device, and the Vout end of the fifth isochronous device outputs a control signal en1; the Vin2 end of the second XOR gate is connected to the Vout end of the fourth isochronous device, the Vout end of the second XOR gate is connected to the Vin end of the sixth isochronous device, and the Vout end of the sixth isochronous device outputs a control signal en2; the Vout end of the fourth isochronous device is also connected to the Vin end of the seventh isochronous device, and the Vout end of the seventh isochronous device outputs a control signal en3.

3. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 2, characterized in that: When the enable signal EN is high, the control signal en outputs a high level, the control signal enp outputs a high level, the control signal enn outputs a low level, the control signal en1 and the control signal en2 output pulse signals with different timings, and the control signal en3 outputs a delayed step signal.

4. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 2, characterized in that: The IO module includes a field effect transistor M1, a gate of the field effect transistor M1 is connected to one end of a resistor R3, the other end of the resistor R3 is connected to one end of a resistor R1, the other end of the resistor R1 serves as a Vin end of the IO module, the source of the field effect transistor M1 serves as a VSS end of the IO module, the drain of the field effect transistor M1 is respectively connected to one end of a resistor R4 and a gate of a field effect transistor M2, the drain of the field effect transistor M1 also serves as a Vn end of the IO module, the other end of the resistor R4 serves as a VDD end of the IO module, the other end of the resistor R4 is also connected to one end of a resistor R5, the other end of the resistor R5 is connected to a drain of the field effect transistor M2, the drain of the field effect transistor M2 serves as a Vp end of the IO module, the other end of the resistor R3 is also connected to one end of a resistor R2, the other end of the resistor R2 is connected to the source of the field effect transistor M2.

5. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 2, characterized in that: The first phase converter, the second phase converter, the third phase converter, the fourth phase converter, the fifth phase converter, the sixth phase converter and the seventh phase converter have the same structure. The first phase converter includes a field effect transistor M3, the gate of the field effect transistor M3 is connected to one end of the resistor R7, the other end of the resistor R7 serves as the Vin end of the first phase converter, the source of the field effect transistor M3 serves as the VSS end of the first phase converter, the drain of the field effect transistor M3 is respectively connected to one end of the resistor R8 and the gate of the field effect transistor M4, the other end of the resistor R8 serves as the VDD end of the first phase converter IO, the other end of the resistor R8 is also connected to one end of the resistor R9, the other end of the resistor R9 is connected to the drain of the field effect transistor M4, the drain of the field effect transistor M4 serves as the Vout end of the first phase converter, the other end of the resistor R7 is also connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the source of the field effect transistor M4.

6. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 2, characterized in that: The buffer includes a field effect transistor M5, a gate of the field effect transistor M5 serving as a Vin terminal of the buffer, the gate of the field effect transistor M5 being also connected to a gate of the field effect transistor M6, a source of the field effect transistor M5 serving as a VSS terminal of the buffer, the source of the field effect transistor M5 being also connected to a source of the field effect transistor M6, a source of the field effect transistor M7 and a source of the field effect transistor M8, a drain of the field effect transistor M5 being respectively connected to a drain of the field effect transistor M6, a gate of the field effect transistor M7, a gate of the field effect transistor M8 and one end of a resistor R10, the other end of the resistor R10 serving as a VDD terminal of the buffer, the other end of the resistor R10 being also connected to one end of a resistor R11, the other end of the resistor R11 serving as a Vout terminal of the buffer, the other end of the resistor R11 being also connected to a drain of the field effect transistor M7 and a drain of the field effect transistor M8.

7. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 2, characterized in that: The first delay module and the second delay module have the same structure. The first delay module includes a field effect transistor M9, the source of the field effect transistor M9 serves as the VSS terminal of the first delay module, the gate of the field effect transistor M9 is respectively connected to one end of the resistor R12 and one end of the capacitor C1, the other end of the resistor R12 serves as the Vin terminal of the first delay module, the other end of the capacitor C1 is respectively connected to one end of the capacitor C2 and the source of the field effect transistor M10, the other end of the capacitor C2 is respectively connected to one end of the resistor R13 and the gate of the field effect transistor M10, the other end of the resistor R13 is respectively connected to the drain of the field effect transistor M9 and one end of the resistor R14, the other end of the resistor R14 serves as the VDD terminal of the first delay module, the other end of the resistor R14 is also connected to one end of the resistor R15, the other end of the resistor R15 is connected to the drain of the field effect transistor M10, and the drain of the field effect transistor M10 also serves as the Vout terminal of the first delay module.

8. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 2, characterized in that: The first XOR gate and the second XOR gate have the same structure. The first XOR gate includes a field effect transistor M11. The source of the field effect transistor M11 serves as the VSS terminal of the first XOR gate. The source of the field effect transistor M11 is also connected to the source of the field effect transistor M12 and the source of the field effect transistor M13. The gate of the field effect transistor M11 serves as the Vin1 terminal of the first XOR gate. The gate of the field effect transistor M11 is also connected to the gate of the field effect transistor M18. The source of the field effect transistor M18 serves as the Vin2 terminal of the first XOR gate. The drain of the field effect tube M11 is respectively connected to one end of the resistor R16, the drain of the field effect tube M12 and the gate of the field effect tube M13, the other end of the resistor R16 serves as the VDD end of the first XOR gate, the other end of the resistor R16 is also connected to one end of the resistor R17, the other end of the resistor R17 is respectively connected to the drain of the field effect tube M13 and the gate of the field effect tube M14, the drain of the field effect tube M14 serves as the VSS end of the first XOR gate. The drain of the field effect tube M14 is also connected to the drain of the field effect tube M15, the source of the field effect tube M15 serves as the Vout terminal of the first XOR gate, the source of the field effect tube M15 is also connected to one end of the resistor R19, the other end of the resistor R19 serves as the first VDD terminal of the first XOR gate, the gate of the field effect tube M15 is respectively connected to one end of the resistor R18 and the source of the field effect tube M16, the other end of the resistor R18 serves as the second VDD terminal of the first XOR gate, and the The drain of the field effect tube M16 is connected to the source of the field effect tube M14, the gate of the field effect tube M16 is respectively connected to one end of the resistor R20 and the drain of the field effect tube M17, the other end of the resistor R20 serves as the third VDD end of the first XOR gate, the source of the field effect tube M17 is connected to the drain of the field effect tube M18, the gate of the field effect tube M17 is connected to the gate of the field effect tube M12, and the gate of the field effect tube M12 also serves as the Vin2 end of the first XOR gate.

9. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 2, characterized in that: The power supply circuit receives a VBIAS voltage, and after the VBIAS voltage passes through diodes of different numbers and different areas, it generates a voltage value signal out1, a voltage value signal out2, and a voltage value signal out3, and the voltage value signal out1, the voltage value signal out2, and the voltage value signal out3 are used to provide voltage signals of different steps to the output voltage VB; The larger the diode area, the higher the voltage value generated after passing through the diode, and the more diodes passed, the smaller the voltage value generated; The power supply circuit further generates a power supply signal VDD1 and a power supply signal VVD2 , wherein the power supply signal VDD1 and the power supply signal VVD2 are used to supply power to each logic unit in the logic circuit and control the power consumption of the logic unit.

10. The logic power supply circuit for solving the gain climbing problem of a power amplifier according to claim 9, characterized in that: The switch circuit includes a first switch tube SW1, a second switch tube SW2, a third switch tube SW3, a fourth switch tube SW4 and a fifth switch tube SW5; the first switch tube SW1 transmits the voltage signal out1 to the VB terminal according to the timing of the control signal en1; the second switch tube SW2 transmits the voltage signal out2 to the VB terminal according to the timing of the control signal en2; the third switch tube SW3 transmits the voltage signal out3 to the VB terminal according to the timing of the control signal en3; the fourth switch tube SW4 receives the control signal en, and the fifth switch tube SW5 receives the control signal enn. The fourth switch tube SW4 and the fifth switch tube SW5 adopt a series-parallel structure to ensure fast opening and closing of the signal; the VB terminal is used to output a bias voltage.

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