Millimeter wave low-noise amplifier

Abstract

The invention provides a millimeter wave low-noise amplifier which comprises a first-stage amplifying circuit, a second-stage amplifying circuit and a third-stage amplifying circuit, the signal output end of the first-stage amplifying circuit is connected with the signal input end of the second-stage amplifying circuit, and the signal output end of the third-stage amplifying circuit is connected with the signal output end of the third-stage amplifying circuit. The signal output end of the second-stage amplification circuit is connected with the signal input end of the third-stage amplification circuit; according to the low-noise amplifier, the transformer is matched with the transmission line inductor and the transmission line plate capacitor in a combined mode, loss of a passive matching circuit is reduced, and meanwhile large-bandwidth output of the low-noise amplifier is achieved; a cascode amplification structure is adopted, the transformer is combined with a transmission line plate capacitor and a transmission line inductor for impedance matching, and broadband, high-gain amplification and low-noise signal output can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of millimeter wave integrated circuit design, and in particular to a millimeter wave low noise amplifier. Background Art

[0002] RF integrated circuits have different performance requirements and technical difficulties in different fields and at different operating frequencies. In practice, in order to meet the requirements of cost performance, operating frequency, etc., many manufacturing processes have emerged, such as BJT, HEMT, BiMOS, CMOS, etc. Although BJT has the advantages of speed and precision, it is not suitable for large-scale integration. HTEM has a high electron saturation velocity and an operating frequency of up to submillimeter waves. It is mostly used for high speed and high power. Like BJT, it is suitable for digital integrated circuits. In previous designs, although CMOS has the advantage of low cost, due to process limitations, its cutoff frequency is low and the noise is large, which is not suitable for the design of RF circuits. However, with the advancement of science and technology and the improvement of microelectronics process technology, the frequency characteristics of CMOS transistors have gradually improved, which has greatly stimulated the use of CMOS in the RF field. Compared with GaAs, BiCMOS and other processes, CMOS processes have the advantages of high integration, lowest cost, and easy integration with digital circuits, providing better conditions for realizing the productization of modules.

[0003] In RF circuit design, the low noise amplifier is a key component of the receiver. Its performance directly affects the sensitivity of the entire receiver. For the low noise amplifier, noise factor, gain, etc. are its important indicators. The low noise amplifier receives weak signals from the antenna and amplifies the weak signals. In order to reduce the impact of the subsequent circuit noise on the noise of the entire system, the LNA needs to provide sufficient gain, which is particularly important for the down-conversion circuit. Therefore, how to achieve high gain and low noise has always been a problem that needs to be solved in the design of low noise amplifiers (LNA).

[0004] Low-noise amplifier designs generally use common source, common gate, common source and common gate structures. Common source amplifiers have good gain and noise performance, but have narrow bandwidth; common gate amplifiers have broadband characteristics, better linearity and isolation, but their gain is smaller than that of common source structures; and common source and common gate structures are composed of stacked common source tubes and common gate tubes, which is equivalent to a two-stage amplifier. The gain is significantly better than that of common source and common gate amplifiers, so they are used in high-gain amplifier designs, but they require a higher power supply voltage, and their noise is significantly greater than that of common source amplifiers, and have narrowband characteristics. Therefore, using common source and common gate structures to achieve high gain and low noise is also a problem that needs to be solved.

[0005] In RF circuit design, impedance matching and the rational application of passive components help reduce the noise figure. Impedance matching is a very important design in the circuit, and inductors are important passive components in RF circuits, playing a key role in impedance matching. However, with the development of technology, on-chip integrated transformers have gradually shown their advantages over traditional inductors, especially in broadband matching.

[0006] In summary, the disclosed low-noise amplifier has room for improvement in the following aspects: (1) transformer matching is used to increase bandwidth while easily introducing excessive insertion loss, causing noise degradation; (2) it is difficult to achieve a large bandwidth using traditional LC (L is inductance, C is capacitance) matching; (3) the common source and common gate structure is difficult to achieve both high gain and low noise at the same time while achieving high gain. Summary of the invention

[0007] The present invention aims to at least solve the technical problems existing in the prior art, and in particular innovatively proposes a millimeter wave low noise amplifier.

[0008] In order to achieve the above-mentioned object of the present invention, the present invention provides a millimeter wave low noise amplifier, the low noise amplifier comprises: a first-stage amplifier circuit, a second-stage amplifier circuit, and a third-stage amplifier circuit, the signal output end of the first-stage amplifier circuit is connected to the signal input end of the second-stage amplifier circuit, and the signal output end of the second-stage amplifier circuit is connected to the signal input end of the third-stage amplifier circuit;

[0009] The first-stage amplifier circuit includes: a first input matching capacitor, a second input matching capacitor, an input transformer, a first common-source transistor, a second common-source transistor, a first common-source neutralizing capacitor, a second common-source neutralizing capacitor, a first common-source common-gate inductor, a second common-source common-gate inductor, a first common-gate transistor, a second common-gate transistor, a first common-gate neutralizing capacitor, a second common-gate neutralizing capacitor, a first interstage transformer, a first interstage inductor, and a second interstage inductor; the input transformer includes: an input transformer primary coil P1 and an input transformer secondary coil S1; the first interstage transformer includes: a first interstage transformer primary coil P2 and a first interstage transformer secondary coil S2; the specific connection method is:

[0010] The radio frequency signal as an input signal is connected to the primary coil P1 of the input transformer, one end of the first input matching capacitor is connected to the first end of the primary coil P1 of the input transformer, the other end of the first input matching capacitor is grounded, one end of the second input matching capacitor is connected to the second end of the primary coil P1 of the input transformer, the other end of the second input matching capacitor is grounded, the first end of the secondary coil S1 of the input transformer is connected to the gate of the first common source transistor and one end of the first common source neutralizing capacitor, the second end of the secondary coil S1 of the input transformer is connected to the gate of the second common source transistor and one end of the second common source neutralizing capacitor, the drain of the first common source transistor is connected to one end of the first common source common gate inductor and the other end of the second common source neutralizing capacitor, the drain of the second common source transistor is connected to one end of the second common source common gate inductor and the other end of the first common source neutralizing capacitor, the source of the first common source transistor is grounded, and the source of the second common source transistor is grounded; The other end of the first common-source common-gate inductor is connected to the source of the first common-gate transistor, the other end of the second common-source common-gate inductor is connected to the source of the second common-gate transistor, the gate of the first common-gate transistor is connected to one end of the first common-gate neutralizing capacitor, the other end of the first common-gate neutralizing capacitor is connected to the drain of the second common-gate transistor and the second end of the primary coil P2 of the first interstage transformer; the gate of the second common-gate transistor is connected to one end of the second common-gate neutralizing capacitor, the other end of the second common-gate neutralizing capacitor is connected to the drain of the first common-gate transistor and the first end of the primary coil P2 of the first interstage transformer; the first end of the secondary coil S2 of the first interstage transformer is connected to one end of the first interstage inductor, the second end of the secondary coil S2 of the first interstage transformer is connected to one end of the second interstage inductor, the other end of the first interstage inductor is connected to the input end of the second-stage amplifier circuit, and the other end of the second interstage inductor is connected to the input end of the second input amplifier circuit;

[0011] The second stage amplifier circuit includes: a third common source transistor, a fourth common source transistor, a third common source neutralization capacitor, a fourth common source neutralization capacitor, a third common source common gate inductor, a fourth common source common gate inductor, a third common gate transistor, a fourth common gate transistor, a third common gate neutralization capacitor, a fourth common gate neutralization capacitor, a second interstage transformer, a third interstage inductor, and a fourth interstage inductor; the second interstage transformer includes: a second interstage transformer primary coil P3 and a second interstage transformer secondary coil S3; the specific connection method is:

[0012] The first input end of the differential input of the second-stage amplifier circuit is connected to the gate of the third common-source transistor and one end of the third common-source neutralizing capacitor, and the second input end of the differential input of the second-stage amplifier circuit is connected to the gate of the fourth common-source transistor and one end of the fourth common-source neutralizing capacitor; the drain of the third common-source transistor is connected to one end of the third common-source common-gate inductor and the other end of the fourth common-source neutralizing capacitor, and the drain of the fourth common-source transistor is connected to one end of the fourth common-source common-gate inductor and the other end of the third common-source neutralizing capacitor; the source of the third common-source transistor is grounded, and the source of the fourth common-source transistor is grounded; the other end of the third common-source common-gate inductor is connected to the source of the third common-gate transistor, and the other end of the fourth common-source common-gate inductor is connected to the source of the fourth common-gate transistor, and the third common-source transistor is grounded. The gate of the gate transistor is connected to one end of the third common-gate neutralizing capacitor, and the other end of the third common-gate neutralizing capacitor is connected to the drain of the fourth common-gate transistor and the second end of the primary coil P3 of the second interstage transformer; the gate of the fourth common-gate transistor is connected to one end of the fourth common-gate neutralizing capacitor, and the other end of the fourth common-gate neutralizing capacitor is connected to the drain of the third common-gate transistor and the first end of the primary coil P3 of the second interstage transformer, the first end of the secondary coil S3 of the second interstage transformer is connected to one end of the third interstage inductor, the second end of the secondary coil S3 of the second interstage transformer is connected to one end of the fourth interstage inductor, the other end of the third interstage inductor is connected to the input end of the third-stage amplifier circuit, and the other end of the fourth interstage inductor is connected to the input end of the third input amplifier circuit;

[0013] The third-stage amplifier circuit includes: a fifth common-source transistor, a sixth common-source transistor, a fifth common-source neutralization capacitor, a sixth common-source neutralization capacitor, a fifth common-source common-gate inductor, a sixth common-source common-gate inductor, a fifth common-gate transistor, a sixth common-gate transistor, a fifth common-gate neutralization capacitor, a sixth common-gate neutralization capacitor, an output transformer XF4, a first output matching capacitor, and a second output matching capacitor; the output transformer includes: an output transformer primary coil P4 and an output transformer secondary coil S4; the specific connection method is:

[0014] The first input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the fifth common-source transistor and one end of the fifth common-source neutralizing capacitor, and the second input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the sixth common-source transistor and one end of the sixth common-source neutralizing capacitor; the drain of the fifth common-source transistor is connected to one end of the fifth common-source common-gate inductor and the other end of the sixth common-source neutralizing capacitor, the drain of the sixth common-source transistor is connected to one end of the sixth common-source common-gate inductor and the other end of the fifth common-source neutralizing capacitor, the source of the fifth common-source transistor is grounded, and the source of the sixth common-source transistor is grounded; the other end of the fifth common-source common-gate inductor is connected to the source of the fifth common-gate transistor, and the other end of the sixth common-source common-gate inductor is connected to the source of the sixth common-gate transistor. The gate of the fifth common-gate transistor is connected to one end of the fifth common-gate neutralization capacitor, and the other end of the fifth common-gate neutralization capacitor is connected to the drain of the sixth common-gate transistor and the second end of the output transformer primary coil P4; the gate of the sixth common-gate transistor is connected to one end of the sixth common-gate neutralization capacitor, and the other end of the sixth common-gate neutralization capacitor is connected to the drain of the fifth common-gate transistor and the first end of the output transformer primary coil P4; the first end of the output transformer secondary coil S4 is connected to one end of the first output matching capacitor, the second end of the output transformer secondary coil S4 is connected to one end of the second output matching capacitor, the other ends of the first output matching capacitor and the second output matching capacitor are both grounded, and the output transformer secondary coil S4 outputs a radio frequency signal.

[0015] Further, one or any combination of the first input matching capacitor, the second input matching capacitor, the first output matching capacitor, and the second output matching capacitor is a transmission line flat plate capacitor, and one or any combination of the first interstage inductor, the second interstage inductor, the third interstage inductor, and the fourth interstage inductor is a transmission line inductor.

[0016] The use of transmission line flat capacitors and transmission line inductors has better effects than general capacitors and inductors.

[0017] Furthermore, the transmission line flat plate capacitor has a width of 4.5 um and a length of 15 um.

[0018] Furthermore, the transmission line planar capacitor is drawn using metal layers M4 and M5.

[0019] Furthermore, the inner diameter of the transmission line inductor is 20 um, and the metal line width is 3.5 um.

[0020] Furthermore, the transmission line inductor is drawn using high-layer metal.

[0021] Furthermore, the first, second, third, fourth, fifth and sixth common-source transistors and the first, second, third, fourth, fifth and sixth common-gate transistors are all MOS tubes of CMOS process.

[0022] Furthermore, the turns ratio of the first interstage transformer is 1:2, and the turns ratio of the input transformer, the second interstage transformer, and the output transformer is 1:1.

[0023] Furthermore, the input transformer, the first interstage transformer, the second interstage transformer, and the output transformer all have center taps.

[0024] In summary, due to the adoption of the above technical solution, the present invention can achieve high gain and low noise at the same time while increasing bandwidth. The specific beneficial effects are:

[0025] (1) The transformer is used to match the inductor and capacitor, which reduces the loss of the passive matching circuit and realizes the wide bandwidth output of the low-noise amplifier;

[0026] (2) The common-source and common-gate amplifier structure is adopted, and the impedance matching is performed by combining the transformer with capacitors and inductors to achieve broadband, high-gain amplification and low-noise signal output.

[0027] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0029] Figure 1 This is a schematic diagram of the structure of Example 1 of the present invention.

[0030] Figure 2 This is a comparison diagram of the return loss (S11) parameters of the capacitors in the PDK library and the transmission line flat plate capacitors used in Example 1 of the present invention.

[0031] Figure 3 This is a comparison chart of the noise factors (NF) of capacitors, inductors, and transmission line plate capacitors and transmission line inductors in the PDK library used in Example 1 of the present invention.

[0032] Figure 4 This is a comparison diagram of the inductance and transmission line inductance gains in the PDK library used in Example 1 of the present invention. DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0034] A schematic diagram of the structure of a millimeter wave low noise amplifier provided in Example 1 of the present invention is shown in FIG. Figure 1 As shown, there are a first-stage amplifier circuit, a second-stage amplifier circuit and a third-stage amplifier circuit; the signal output end of the first-stage amplifier circuit is connected to the signal input end of the second-stage amplifier circuit, and the signal output end of the second-stage amplifier circuit is connected to the signal input end of the third-stage amplifier circuit. First, the low-noise amplifier of the present application abandons the ordinary transformer matching, and adopts the transformer and the transmission line flat capacitor and the transmission line inductor to perform impedance matching, thereby increasing the flexibility of the design; the transmission line inductor is used to weaken the parasitic capacitance in the chip layout, reduce the additional loss caused by the parasitic capacitance, and improve the gain; while realizing the return loss broadband design, a lower noise signal amplification is achieved, and a common source and common gate amplifier structure is adopted to achieve high gain amplification and low noise output.

[0035] The first-stage amplifier circuit includes: a first input matching capacitor C1P, a second input matching capacitor C1N, an input transformer XF1, a first common-source transistor M1P, a second common-source transistor M1N, a first common-source neutralizing capacitor CM1, a second common-source neutralizing capacitor CM2, a first common-source common-gate inductor LM1, a second common-source common-gate inductor LN1, a first common-gate transistor M2P, a second common-gate transistor M2N, a first common-gate neutralizing capacitor CM3, a second common-gate neutralizing capacitor CM4, a first interstage transformer XF2, a first interstage inductor LM2, and a second interstage inductor LN2;

[0036] The input transformer XF1 includes: an input transformer primary coil P1 and an input transformer secondary coil S1; the first inter-stage transformer XF2 includes: a first inter-stage transformer primary coil P2 and a first inter-stage transformer secondary coil S2;

[0037] The input transformer XF1 forms a coupled resonance with the first input matching capacitor C1P and the second input matching capacitor C1N. The input matching capacitor increases the parasitic capacitance value of the transformer, realizes a strong coupled resonance with the transformer, and realizes a wide bandwidth matching of the low noise amplifier. The first input matching capacitor is equal to the second input matching capacitor; the first input matching capacitor and the second input matching capacitor are both transmission line planar capacitors, both are drawn with metal layers M4 and M5, with a width of 4.5um and a length of 15um;

[0038] The first common-source transistor M1P and the second common-source transistor M1N adopt a finger interpolation structure to reduce parasitic resistance, and a single finger (interpolation finger) is 0.04um; the first common-source transistor M1P and the second common-source transistor M1N are connected to the source of the first common-gate transistor M2P and the second common-gate transistor M2N through the first common-source common-gate inductor LM1 and the second common-source common-gate inductor LN1, and there is a parasitic capacitance between the drain of the common-source transistor and the source of the common-gate transistor. The common-source common-gate inductors LM1 and LN1 are increased to resonate with the parasitic capacitance to achieve the purpose of reducing circuit noise; the first common-gate transistor M2P and the second common-gate transistor M2N also adopt an interpolation structure, and a single finger is 0.04um; the inner diameter of the first common-source common-gate inductor LM1 and the second common-source common-gate inductor LN1 is 20um, and they are drawn with high-layer metal, and the metal line width is 3.5um;

[0039] The first common-gate neutralization capacitor CM3 and the second common-gate neutralization capacitor CM4 both have a capacitance of 19f, which can compensate for the influence of the gate-drain capacitance of the MOS tube, suppress the Miller effect, and improve the stability and gain of the circuit.

[0040] The first interstage transformer XF2 is a differential transformer. The two input ends of the first interstage transformer XF2 are respectively connected to the drains of the first common-gate transistor M2P and the second common-gate transistor M2N, and the two output ends are respectively connected to the first-stage transmission line inductors LM2 and LN2. The transmission line inductors LM2 and LN2 are interstage matching between the first-stage amplifier circuit and the second-stage amplifier circuit. The transmission line inductors LM2 and LN2 are drawn with high-layer metal in the PDK library to reduce losses. In order to reduce the area, bending processing is adopted; the transmission line inductors reduce the passive matching losses and increase the flexibility of the design, optimize the interstage matching performance, and realize high-gain broadband design; the first interstage transformer XF2 adopts a turns ratio of 1:2 structure and is drawn with high-layer metal and sub-high-layer metal;

[0041] The second stage amplifier circuit includes: a third common source transistor M3P, a fourth common source transistor M3N, a third common source neutralization capacitor CM5, a fourth common source neutralization capacitor CM6, a third common source common gate inductor LM2, a fourth common source common gate inductor LN2, a third common gate transistor M4P, a third common gate transistor M4N, a third common gate neutralization capacitor CM7, a fourth common gate neutralization capacitor CM8, a second interstage transformer XF3, a third interstage inductor LM3, and a fourth interstage inductor LN3; the interstage transformer XF3 includes: a transformer primary coil P3, a transformer secondary coil S3,;

[0042] The gates of the third common-source transistor M3P and the fourth common-source transistor M3N are connected to the first-stage transmission line inductors LM2 and LN1, and the drains of the third common-source transistor M3P and the fourth common-source transistor M3N are connected to the third common-source common-gate inductor LM3 and the fourth common-source common-gate inductor LN3. The third common-source common-gate inductor LM3 and the fourth common-source common-gate inductor LN3 have a line width of 4um and an inductance of 100p. Metal isolation rings are added around the inductors to isolate substrate noise; the third common-source common-gate inductor LM3 and the fourth common-source common-gate inductor LN3 are connected to the source terminals of the third common-gate transistor M4P and the fourth common-gate transistor M4N. The third common-gate transistor M4P and the fourth common-gate transistor M4N both adopt an interpolation structure to reduce the parasitic resistance of the MOS tube;

[0043] The third common-gate transistor M4P and the fourth common-gate transistor M4N are respectively connected to the differential input end of the second interstage transformer XF3, and the differential output end of the second interstage transformer is connected to the third transmission line inductor LM4 and the fourth transmission line inductor LN4, thereby increasing the secondary coil inductance of the second interstage transformer, using an independent transmission line inductor, and increasing the flexibility of transformer design;

[0044] The design of the third-stage amplifier is equivalent to that of the second-stage, and a first output matching capacitor C2P and a second output matching capacitor C2N are added to the secondary coil of the output transformer. The capacitance of the first output matching capacitor C2P and the second output matching capacitor C2N are both 20f. The output matching capacitor increases the parasitic capacitance value of the transformer, achieves strong coupling resonance with the transformer, and adjusts the output matching of the low-noise amplifier.

[0045] For the design of millimeter-wave low-noise amplifiers, the return loss is less than -10dB, and the corresponding frequency range is greater than 4GHz, which meets the broadband design requirements. For the design of three-stage low-noise amplifiers, the noise figure is less than 7dB and the gain is greater than 20dB, which meets the high gain and low noise design requirements of low-noise amplifiers. Figure 2 to Figure 4 It can be seen that the low noise amplifier designed in the present invention can achieve high gain and low noise at the same time while increasing the bandwidth.

[0046] Figure 2 This is a comparison diagram of the return loss (S11) parameters of the capacitors in the PDK library and the transmission line flat capacitors in Example 1 of the present invention. The dotted line is the return loss diagram using the capacitors in the PDK, and the solid line is the return loss diagram using the transmission line flat capacitors; it can be seen from the figure that the use of transmission line flat capacitors can achieve a wider bandwidth when the return loss is -10dB;

[0047] Figure 3This is a comparison diagram of the noise coefficient (NF) of capacitors, inductors, and transmission line flat capacitors and transmission line inductors in the PDK library in Example 1 of the present invention, wherein the dotted line is the noise coefficient diagram of capacitors and inductors in the PDK library, and the solid line is the noise coefficient diagram of transmission line flat capacitors and transmission line inductors; it can be seen that the noise coefficient of transmission line flat capacitors and transmission line inductors is obviously lower than that of capacitors and inductors in the PDK library, and within the frequency band, the maximum change of the noise coefficient is 0.35dB;

[0048] Figure 4 This is a gain comparison diagram of the inductor and transmission line inductor in the PDK library used in Example 1 of the present invention, wherein the dotted line is the gain diagram using the inductor in the PDK library, and the solid line is the gain diagram using the transmission line inductor. It can be seen that the gain using the transmission line inductor is significantly higher than the gain value using the inductor in the PDK library; the transmission line inductor has low loss, so compared with the inductor in the PDK library, the gain of the low noise amplifier can be improved.

[0049] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A millimeter wave low noise amplifier, characterized in that: The low noise amplifier comprises: a first-stage amplifier circuit, a second-stage amplifier circuit, and a third-stage amplifier circuit, wherein the signal output end of the first-stage amplifier circuit is connected to the signal input end of the second-stage amplifier circuit, and the signal output end of the second-stage amplifier circuit is connected to the signal input end of the third-stage amplifier circuit; The first-stage amplifier circuit includes: a first input matching capacitor, a second input matching capacitor, an input transformer, a first common-source transistor, a second common-source transistor, a first common-source neutralizing capacitor, a second common-source neutralizing capacitor, a first common-source common-gate inductor, a second common-source common-gate inductor, a first common-gate transistor, a second common-gate transistor, a first common-gate neutralizing capacitor, a second common-gate neutralizing capacitor, a first interstage transformer, a first interstage inductor, and a second interstage inductor; the input transformer includes: an input transformer primary coil P1 and an input transformer secondary coil S1; the first interstage transformer includes: a first interstage transformer primary coil P2 and a first interstage transformer secondary coil S2; the specific connection method is: The RF signal as the input signal is connected to the primary coil P1 of the input transformer, one end of the first input matching capacitor is connected to the first end of the primary coil P1 of the input transformer, the other end of the first input matching capacitor is grounded, one end of the second input matching capacitor is connected to the second end of the primary coil P1 of the input transformer, the other end of the second input matching capacitor is grounded, the first end of the secondary coil S1 of the input transformer is connected to the gate of the first common source transistor and one end of the first common source neutralizing capacitor, the second end of the secondary coil S1 of the input transformer is connected to the gate of the second common source transistor and one end of the second common source neutralizing capacitor, the first The drain of the common-source transistor is connected to one end of the first common-source common-gate inductor and the other end of the second common-source neutralizing capacitor, the drain of the second common-source transistor is connected to one end of the second common-source common-gate inductor and the other end of the first common-source neutralizing capacitor, the source of the first common-source transistor is grounded, and the source of the second common-source transistor is grounded; the other end of the first common-source common-gate inductor is connected to the source of the first common-gate transistor, the other end of the second common-source common-gate inductor is connected to the source of the second common-gate transistor, the gate of the first common-gate transistor is connected to one end of the first common-gate neutralizing capacitor, and the other end of the first common-gate neutralizing capacitor is connected to the drain of the second common-gate transistor, The second end of the primary coil P2 of the first interstage transformer is connected; the gate of the second common-gate transistor is connected to one end of the second common-gate neutralizing capacitor, and the other end of the second common-gate neutralizing capacitor is connected to the drain of the first common-gate transistor and the first end of the primary coil P2 of the first interstage transformer; the first end of the secondary coil S2 of the first interstage transformer is connected to one end of the first interstage inductor, the second end of the secondary coil S2 of the first interstage transformer is connected to one end of the second interstage inductor, the other end of the first interstage inductor is connected to the input end of the second stage amplifier circuit, and the other end of the second interstage inductor is connected to the input end of the second input amplifier circuit; The second stage amplifier circuit includes: a third common source transistor, a fourth common source transistor, a third common source neutralization capacitor, a fourth common source neutralization capacitor, a third common source common gate inductor, a fourth common source common gate inductor, a third common gate transistor, a fourth common gate transistor, a third common gate neutralization capacitor, a fourth common gate neutralization capacitor, a second interstage transformer, a third interstage inductor, and a fourth interstage inductor; the second interstage transformer includes: a second interstage transformer primary coil P3 and a second interstage transformer secondary coil S3; the specific connection method is: The first input end of the differential input of the second-stage amplifier circuit is connected to the gate of the third common-source transistor and one end of the third common-source neutralizing capacitor, and the second input end of the differential input of the second-stage amplifier circuit is connected to the gate of the fourth common-source transistor and one end of the fourth common-source neutralizing capacitor; the drain of the third common-source transistor is connected to one end of the third common-source common-gate inductor and the other end of the fourth common-source neutralizing capacitor, and the drain of the fourth common-source transistor is connected to one end of the fourth common-source common-gate inductor and the other end of the third common-source neutralizing capacitor; the source of the third common-source transistor is grounded, and the source of the fourth common-source transistor is grounded; the other end of the third common-source common-gate inductor is connected to the source of the third common-gate transistor, and the other end of the fourth common-source common-gate inductor is connected to the source of the fourth common-gate transistor, and the third common-source transistor is grounded. The gate of the gate transistor is connected to one end of the third common-gate neutralizing capacitor, and the other end of the third common-gate neutralizing capacitor is connected to the drain of the fourth common-gate transistor and the second end of the primary coil P3 of the second interstage transformer; the gate of the fourth common-gate transistor is connected to one end of the fourth common-gate neutralizing capacitor, and the other end of the fourth common-gate neutralizing capacitor is connected to the drain of the third common-gate transistor and the first end of the primary coil P3 of the second interstage transformer, the first end of the secondary coil S3 of the second interstage transformer is connected to one end of the third interstage inductor, the second end of the secondary coil S3 of the second interstage transformer is connected to one end of the fourth interstage inductor, the other end of the third interstage inductor is connected to the input end of the third-stage amplifier circuit, and the other end of the fourth interstage inductor is connected to the input end of the third input amplifier circuit; The third-stage amplifier circuit includes: a fifth common-source transistor, a sixth common-source transistor, a fifth common-source neutralization capacitor, a sixth common-source neutralization capacitor, a fifth common-source common-gate inductor, a sixth common-source common-gate inductor, a fifth common-gate transistor, a sixth common-gate transistor, a fifth common-gate neutralization capacitor, a sixth common-gate neutralization capacitor, an output transformer XF4, a first output matching capacitor, and a second output matching capacitor; the output transformer includes: an output transformer primary coil P4 and an output transformer secondary coil S4; the specific connection method is: The first input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the fifth common-source transistor and one end of the fifth common-source neutralizing capacitor, and the second input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the sixth common-source transistor and one end of the sixth common-source neutralizing capacitor; the drain of the fifth common-source transistor is connected to one end of the fifth common-source common-gate inductor and the other end of the sixth common-source neutralizing capacitor, the drain of the sixth common-source transistor is connected to one end of the sixth common-source common-gate inductor and the other end of the fifth common-source neutralizing capacitor, the source of the fifth common-source transistor is grounded, and the source of the sixth common-source transistor is grounded; the other end of the fifth common-source common-gate inductor is connected to the source of the fifth common-gate transistor, and the other end of the sixth common-source common-gate inductor is connected to the source of the sixth common-gate transistor. The gate of the fifth common-gate transistor is connected to one end of the fifth common-gate neutralization capacitor, and the other end of the fifth common-gate neutralization capacitor is connected to the drain of the sixth common-gate transistor and the second end of the output transformer primary coil P4; the gate of the sixth common-gate transistor is connected to one end of the sixth common-gate neutralization capacitor, and the other end of the sixth common-gate neutralization capacitor is connected to the drain of the fifth common-gate transistor and the first end of the output transformer primary coil P4; the first end of the output transformer secondary coil S4 is connected to one end of the first output matching capacitor, the second end of the output transformer secondary coil S4 is connected to one end of the second output matching capacitor, the other ends of the first output matching capacitor and the second output matching capacitor are both grounded, and the output transformer secondary coil S4 outputs a radio frequency signal.

2. A millimeter wave low noise amplifier according to claim 1, characterized in that: One or any combination of the first input matching capacitor, the second input matching capacitor, the first output matching capacitor, and the second output matching capacitor is a transmission line flat plate capacitor, and one or any combination of the first inter-stage inductor, the second inter-stage inductor, the third inter-stage inductor, and the fourth inter-stage inductor is a transmission line inductor.

3. A millimeter wave low noise amplifier according to claim 2, characterized in that: The transmission line flat plate capacitor has a width of 4.5 um and a length of 15 um.

4. A millimeter wave low noise amplifier according to claim 2, characterized in that: The transmission line planar capacitor is drawn using metal layers M4 and M5.

5. A millimeter wave low noise amplifier according to claim 2, characterized in that: The inner diameter of the transmission line inductor is 20um, and the metal line width is 3.5um.

6. A millimeter wave low noise amplifier according to claim 2, characterized in that: The transmission line inductor is drawn using high-layer metal.

7. The millimeter wave low noise amplifier according to claim 1, characterized in that: The first, second, third, fourth, fifth and sixth common-source transistors and the first, second, third, fourth, fifth and sixth common-gate transistors are all MOS tubes of CMOS process.

8. The millimeter wave low noise amplifier according to claim 1, characterized in that: The turns ratio of the first interstage transformer is 1:2, and the turns ratio of the input transformer, the second interstage transformer, and the output transformer is 1:

1.

9. The millimeter wave low noise amplifier according to claim 1, characterized in that: The input transformer, the first interstage transformer, the second interstage transformer, and the output transformer all have center taps.

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