Signal transmission system and signal transmission method

Abstract

The invention relates to a signal transmission system and a signal transmission method. The signal transmission system includes: a first transmission circuit operating on a first work clock signal having a first phase, a second transmission circuit operating on a second work clock signal having a second phase, the first phase being different from the second phase; and a multi-phase clock signal generation circuit coupled to the first transmission circuit and the second transmission circuit for generating the first work clock signal and the second work clock signal.

Description

Technical Field

[0001] The present invention relates to a signal transmission system and a signal transmission method, and in particular to a signal transmission system and a signal transmission method capable of reducing power ripple. Background Art

[0002] The existing signal transmission system includes multiple transmission circuits, each of which receives a working clock signal and operates according to the working clock signal. These working clock signals have the same phase, so they will perform logic level conversion at the same time, that is, they will generate rising edges or falling edges at the same time. However, such a mechanism will cause power ripples in the power signal of the entire system, which may affect the operation of the entire signal transmission system or generate signal noise. Summary of the invention

[0003] An object of the present invention is to provide a signal transmission system capable of reducing power ripple.

[0004] An embodiment of the present invention discloses a signal transmission system, comprising: a first transmission circuit, operating on a first working clock signal with a first phase; a second transmission circuit, operating on a second working clock signal with a second phase, wherein the first phase is different from the second phase; and a multi-phase clock signal generating circuit, coupling the first transmission circuit and the second transmission circuit, for generating the first working clock signal and the second working clock signal.

[0005] An embodiment of the present invention discloses a signal transmission system, comprising: a plurality of transmission circuits, each receiving one of a plurality of working clock signals, the working clock signals having different phases; and a multi-phase clock signal generating circuit, coupled to the transmission circuits, for generating the working clock signals. In one embodiment, the number of the transmission circuits is greater than 2.

[0006] According to the aforementioned embodiment, different transmission circuits can be operated according to working clock signals with different phases, so that the working clock signals will not undergo logic level conversion at the same time, thereby improving the power ripple problem in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A block diagram of a signal transmission system according to an embodiment of the present invention is shown.

[0008] Figure 2 Shows Figure 1 A schematic diagram of the working clock signal used by the signal transmission system shown.

[0009] Figure 3 , Figure 4as well as Figure 5 A block diagram of a signal transmission system according to various embodiments of the present invention is shown.

[0010] Figure 6 for Figure 5 An exemplary circuit of a PRBS (pseudorandom binary sequence) generator is shown in FIG.

[0011] Figure 7 A flow chart of a signal transmission method according to an embodiment of the present invention is shown.

[0012] Explanation of symbols

[0013] 100 signal transmission system

[0014] 101 Multi-phase Clock Signal Generating Circuit

[0015] 301PLL Circuit

[0016] PI_1 first phase interpolation circuit

[0017] PI_2 Second Phase Interpolation Circuit

[0018] TC_1 first transmission circuit

[0019] TC_2 Second transmission circuit

[0020] TC_1a, TC_2a, TC_ka transmission circuits

[0021] 501 Random Clock Signal Generator Circuit

[0022] 600 Linear Feedback Shift Register

[0023] 601 XOR Logic Gate DETAILED DESCRIPTION

[0024] The present invention will be described below with multiple embodiments. Please note that the "first", "second" and similar descriptions in the following description are only used to define different elements, parameters, data, signals or steps. They are not used to limit their order. For example, the first device and the second device can be different devices with the same structure.

[0025] Figure 1 FIG. 4 is a block diagram of a signal transmission system according to an embodiment of the present invention. Figure 1As shown, the signal transmission system 100 includes a multi-phase clock signal generating circuit 101, a first transmission circuit TC_1 and a second transmission circuit TC_2. The first transmission circuit TC_1 operates on a first working clock signal CLK_1 having a first phase. The second transmission circuit TC_2 operates on a second working clock signal CLK_2 having a second phase, wherein the first phase is different from the second phase. In one embodiment, the first transmission circuit TC_1 samples data according to the rising edge or the falling edge of the first working clock signal CLK_1, and the second transmission circuit TC_2 samples data according to the rising edge or the falling edge of the second working clock signal CLK_2.

[0026] The multi-phase clock signal generating circuit 101 is coupled to the first transmission circuit TC_1 and the second transmission circuit TC_2 to generate the first working clock signal CLK_1 and the second working clock signal CLK_2. In one embodiment, the first transmission circuit TC_1 and the second transmission circuit TC_2 are transmission circuits on different channels or lanes. In addition, in one embodiment, the first working clock signal CLK_1 and the second working clock signal CLK_2 are received by drivers in the first transmission circuit TC_1 and the second transmission circuit TC_2, respectively, and the drivers respectively operate on the first working clock signal CLK_1 and the second working clock signal CLK_2, that is, they operate in response to the rising edge, falling edge or logic level of the first working clock signal CLK_1 and the second working clock signal CLK_2, respectively.

[0027] Figure 2 Shows Figure 1 The schematic diagram of the working clock signal used by the signal transmission system shown in FIG. Figure 2 As shown, the first working clock signal CLK_1 and the second working clock signal CLK_2 have different phases. In one embodiment, the first working clock signal CLK_1 and the second working clock signal CLK_2 have the same clock frequency and working cycle, but have different phases. By doing so, the rising edge and the falling edge of the first working clock signal CLK_1 and the second working clock signal CLK_2 can be made to occur at different times, thereby improving the power ripple problem in the prior art.

[0028] In addition, Figure 1 In the embodiment, two transmission circuits are used for illustration. However, the signal transmission system of the present invention may include more than two transmission circuits. For example, in one embodiment, the signal transmission system provided by the present invention includes M transmission circuits (M>2). In such an embodiment, the M working clock signals used by the M transmission circuits all have different phases. Figure 2As shown, the M working clock signals CLK_1, CLK_2…CLK_M all have different phases. In such an embodiment, the signal transmission system provided by the present invention can be simply illustrated as: a signal transmission system, comprising: a plurality of transmission circuits, each receiving one of a plurality of working clock signals, and the working clock signals have different phases; and a multi-phase clock signal generating circuit, coupled to the transmission circuits, for generating the working clock signals. However, please note that the signal transmission system provided by the present invention is not limited to the working clock signals used by all transmission circuits having different phases, and the working clock signals used by some transmission circuits may have different phases, but the working clock signals used by some transmission circuits may have the same phase. Such an architecture can also be applied to the following other embodiments.

[0029] Figure 1 The multi-phase clock signal generating circuit 101 shown can be implemented by various circuits. Figure 3 , Figure 4 as well as Figure 5 FIG. 1 is a block diagram of a signal transmission system according to different embodiments of the present invention. Figure 3 In the embodiment of FIG. 1 , the multi-phase clock signal generating circuit 101 is a PLL (Phase-locked loop) circuit 301. Figure 3 As shown, the multi-phase clock signal generating circuit 101 is used to generate a plurality of clock signals PH0, PH1 ... PH(N-1) with different phases, and then two of the clock signals PH0, PH1 ... PH(N-1) can be taken as working clock signals CLK_1, CLK_2.

[0030] And in Figure 4In an embodiment of the invention, the multi-phase clock signal generating circuit 101 includes a PLL circuit 301, a first phase interpolation circuit PI_1, and a second phase interpolation circuit PI_2. In such an embodiment, the clock signals PH0, PH1, ... PH(N-1) generated by the PLL circuit 301 are used as candidate clock signals. The first phase interpolation circuit PI_1 generates a first working clock signal CLK_1 according to at least one first candidate clock signal among the candidate clock signals, and the second phase interpolation circuit PI_2 generates a second working clock signal CLK_2 according to at least one second candidate clock signal among the candidate clock signals. The first phase interpolation circuit PI_1 and the second phase interpolation circuit PI_2 can be circuits of various forms. In an embodiment, the first phase interpolation circuit PI_1 and the second phase interpolation circuit PI_2 have adjustable current sources, which can be adjusted to determine the phases of the working clock signals output by the first phase interpolation circuit PI_1 and the second phase interpolation circuit PI_2. Other detailed structures of the phase interpolation circuit have been disclosed in the prior art. For example, US Pat. No. US8564352 describes the phase interpolation circuit in detail, so they will not be described here in detail.

[0031] exist Figure 5 In an embodiment of the present invention, the multi-phase clock signal generating circuit 101 includes a random clock signal generating circuit 501, which is used to generate a random clock signal, that is, to generate a plurality of random clock signals with different phases. In an embodiment, the random clock signal generating circuit 501 is a PRBS (pseudorandom binary sequence) generator. The PRBS generator is used to randomly generate 0 or 1 in a value cycle.

[0032] Figure 6 for Figure 5 An exemplary circuit of a PRBS generator is shown in FIG. Figure 6 In the embodiment of FIG. 5 , the random clock signal generating circuit 501 is a linear feedback shift register 600 (LFSR), which can be used as a PRBS generator. Figure 6As shown, the linear feedback shift register 600 includes registers L_1, L_2, L_3, L_4, L_5, L_6 and L_7, which correspond to the equation X7+X6+1=0. The linear feedback shift register 600 takes the output linear function as input, that is, the output is processed by the XOR logic gate 601 as input, and then shifts the number of bits in the registers L_1, L_2, L_3, L_4, L_5, L_6 and L_7. The initial value in the registers L_1, L_2, L_3, L_4, L_5, L_6 and L_7 is called a "seed". Figure 6 For example, the seed is 0000001. The detailed operation of the linear feedback shift register 600 is known to those skilled in the art, so it will not be described here. Please also note that the PRBS generator may include Figure 6 In addition to the above-mentioned embodiments, the multi-phase clock signal generating circuit 101 can also be other circuits that can generate clock signals with different phases. For example, the multi-phase clock signal generating circuit 101 can be a delay chain circuit.

[0033] Please refer to Figure 5 After the random clock signal generating circuit 501 generates multiple clock signals with different phases, these clock signals can be directly used as working clock signals for different transmission circuits. In one embodiment, after selecting one of the clock signals generated by the random clock signal generating circuit 501, the working clock signals for different transmission circuits are generated according to the selected clock signal. Figure 5 For example, the random clock signal generating circuit 501 generates N clock signals, and then selects the clock signal with phase j to generate the working clock signal for different transmission circuits. Figure 5 In the embodiment of , there are K transmission circuits TC_1a, TC_2a ... TC_Ka, and these transmission circuits have phase j, phase j+1, phase j+2 ... phase j+k respectively. Adjacent phases have a predetermined phase difference respectively. For example, phase j and phase j+1 have a predetermined phase difference, and phase j+k-1 and phase j+k also have a predetermined phase difference.

[0034] According to the aforementioned embodiments, a signal transmission method can be obtained. Figure 7 A flow chart of a signal transmission method according to an embodiment of the present invention is shown, which is used in a signal transmission system and includes the following steps:

[0035] Step 701

[0036] Generate a first working clock signal with a first phase (eg Figure 2The first working clock signal CLK_1 shown).

[0037] Step 703

[0038] Generate a second working clock signal with a second phase (eg Figure 2 The second working clock signal CLK_2 shown).

[0039] The first phase is different from the second phase.

[0040] Step 705

[0041] A first transmission circuit (eg Figure 1 The first transmission circuit TC_1) shown runs on a first working clock signal.

[0042] Step 707

[0043] A second transmission circuit (eg Figure 1 The second transmission circuit TC_2 shown runs on a second working clock signal.

[0044] According to the aforementioned embodiment, different transmission circuits can be operated according to working clock signals with different phases, so that the working clock signals will not undergo logic level conversion at the same time, thereby improving the power ripple problem in the prior art.

[0045] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A signal transmission system, comprising: A first transmission circuit operates on a first working clock signal with a first phase: a second transmitting circuit operating on a second working clock signal having a second phase, wherein the first phase is different from the second phase; and A multi-phase clock signal generating circuit is coupled to the first transmitting circuit and the second transmitting circuit, and is used for generating the first working clock signal and the second working clock signal. 2 . The signal transmission system as claimed in claim 1 , wherein the first transmission circuit and the second transmission circuit are transmission circuits of different channels or paths.

3. The signal transmission system as claimed in claim 1, wherein the drivers in the first transmission circuit and the second transmission circuit receive the first working clock signal and the second working clock signal respectively, and operate on the first working clock signal and the second working clock signal respectively.

4. The signal transmission system as claimed in claim 1, wherein the multi-phase clock signal generating circuit is a phase-locked loop circuit.

5. The signal transmission system as claimed in claim 1, wherein the multi-phase clock signal generating circuit comprises: a phase-locked loop circuit for generating a plurality of candidate clock signals, wherein the plurality of candidate clock signals have different phases; a first phase interpolation circuit, coupled to the phase-locked loop circuit and the first transmission circuit, for generating the first working clock signal according to at least one first candidate clock signal among the plurality of candidate clock signals; A second phase interpolation circuit is coupled to the phase-locked loop circuit and the second transmission circuit, and is used to generate the second working clock signal according to at least one second candidate clock signal among the plurality of candidate clock signals. 6 . The signal transmission system as claimed in claim 1 , wherein the multi-phase clock signal generating circuit comprises a random clock signal generating circuit.

7. The signal transmission system as claimed in claim 6, wherein the random clock signal generating circuit is a pseudo-random binary number sequence generator.

8. The signal transmission system as claimed in claim 1, wherein the multi-phase clock signal generating circuit is a delay line circuit.

9. A signal transmission system, comprising: A plurality of transmission circuits, each receiving one of a plurality of working clock signals, wherein the plurality of working clock signals have different phases; and A multi-phase clock signal generating circuit is coupled to the plurality of transmitting circuits to generate the plurality of working clock signals.

10. The signal transmission system of claim 9, wherein the number of the plurality of transmission circuits is greater than 2.

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