An LDO circuit and method for preventing overcharging of residual power hot-swap output under no-load

Abstract

The invention discloses an LDO circuit and method for preventing overcharging of residual power hot-swap output under no-load, comprising a comparator and a pulse signal generating module; the pulse signal generating module is connected to the comparator and connected to a low static power consumption circuit through a PMOS tube; a first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage, and outputs a driving voltage through an NMOS tube and the low static power consumption circuit; a second PMOS tube generates and controls an output voltage based on an external input voltage and a driving voltage; a comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module; the pulse signal generating module generates a second voltage signal based on the third voltage signal; a pulse signal is generated by the comparator and the pulse signal generating module to modulate the gate of the second PMOS tube, so as to prevent overcharging of the output voltage when the external input voltage residual power hot-swap is powered on under no-load.

Description

Technical Field

[0001] The present invention relates to the technical field of power management chips, and in particular to an LDO circuit and method for preventing overcharging of residual power hot-swap output under no-load conditions. Background Art

[0002] See also Figure 2 , Figure 2 FIG. 1 is a static power consumption LDO circuit in the prior art. Figure 2 As shown, the circuit may include a circuit input terminal, a circuit output terminal and a ground terminal, a first amplifier, a second amplifier, a third amplifier, a PMOS tube M3 and an output sampling module.

[0003] Among them, when the voltage of the external input terminal is lower than the preset voltage of the output terminal, the voltage of the output terminal of the circuit will decrease as the voltage of the input terminal of the circuit decreases. At this time, the first sampling signal decreases, the gate voltage of M1 increases, the gate voltage of M3 decreases, and the PMOS tube M3 is in a linear region; the third amplifier outputs the gate voltage of M4 based on the drain voltage of M2 and the output terminal voltage, and makes the source voltage of M4 change with the output terminal voltage and have the same value; at this time, the PMOS tube M2 is in a linear region, and the gate, drain and source voltages of the PMOS tube M2 are equal to the gate, drain and source voltages of the PMOS tube M3, respectively, and the current IM2 of the PMOS tube M2 and the current IM3 of the PMOS tube M3 are in a mirror relationship, and the mirror relationship is:

[0004]

[0005] The preset output terminal voltage is greater than or equal to the first reference signal, IM2 is the current of the PMOS tube M2, IM3 is the current of the PMOS tube M3, (W / L)M2 is the width-to-length ratio of the PMOS tube M2, and (W / L)M3 is the width-to-length ratio of the PMOS tube M3; so that when the input terminal voltage is lower than the preset output terminal voltage, the current of the PMOS tube M2 is:

[0006]

[0007] This avoids the increase in circuit static power consumption caused by current mirror mismatch.

[0008] Those skilled in the art know that the above has very high application value in the field of low power consumption and lithium batteries, which is manifested as: when VIN is low, M2 is limited by M4, and the static power consumption of the circuit will not increase due to current mirror mismatch. In order to improve the response speed and load capacity of the second-stage amplifier of the low-power LDO currently on the market, under normal circumstances, the load current of the second stage is: using a P-tube current mirror to copy the current of the power tube; but the above-mentioned prior art has the following disadvantages:

[0009] Under no-load conditions, when VIN is low, the overall current is small, that is, the response speed of the op amp is slow, and VOUT overcharge problems will occur, including:

[0010] When VIN is slowly started, VOUT will be overcharged;

[0011] In the case of hot swapping with residual power in VIN, VOUT will be overcharged. Summary of the invention

[0012] In view of the above-mentioned deficiencies in the current power management chip technology field, the present invention provides an LDO circuit and method for preventing overcharging of the output voltage when hot-plugging the residual power under no-load condition, so as to prevent the overcharging problem of the output voltage when hot-plugging the residual power of the external input voltage under no-load condition and powering on.

[0013] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0014] An LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition comprises: a first amplifier, a first NMOS tube, a second PMOS tube, a low static power consumption circuit, a fourth PMOS tube, a first voltage-dividing sampling resistor and a second voltage-dividing sampling resistor, and an external input voltage , External reference voltage and output voltage ; The first amplifier is connected to the low static power consumption circuit through the NMOS tube, the first voltage-dividing sampling resistor and the second voltage-dividing sampling resistor are connected to the low static power consumption circuit and generate a feedback voltage, characterized in that it also includes a comparator and a pulse signal generating module; wherein the comparator is connected to the low static power consumption circuit through the second PMOS tube, the pulse signal generating module is connected to the comparator and connected to the low static power consumption circuit through the fourth PMOS tube, the first amplifier outputs a first voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the first NMOS tube and the low static power consumption circuit, the second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal, and the second voltage signal is input to the gate of the second PMOS tube through the fourth PMOS tube; the pulse signal is generated by the comparator and the pulse signal generating module to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load.

[0015] According to one aspect of the present invention, the first NMOS tube is a common source amplifier, the source is grounded, the drain is connected to the drain of the fourth PMOS tube and the low static power consumption circuit, the gate is connected to the output end of the first amplifier, and outputs a driving voltage based on the first voltage signal and the bias current provided by the low static power consumption; the source of the second PMOS tube is connected to the external input voltage, the gate is connected to the drain of the fourth PMOS tube, and the drain is connected to the first voltage divider sampling resistor and the comparator.

[0016] According to one aspect of the present invention, the low static power consumption circuit includes a first PMOS tube, a third PMOS tube and a second amplifier, the source of the first PMOS tube is connected to an external input voltage, the gate is connected to the gate of the second PMOS tube, and the drain is connected to the source of the third PMOS tube; the source of the third PMOS tube is connected to the drain of the first PMOS tube and the input of the second amplifier, the gate is connected to the output of the second amplifier, and the drain is connected to the drain of the fourth PMOS tube and the drain of the first NOMS tube.

[0017] According to one aspect of the present invention, the LDO circuit further includes a current limiting resistor, and the current limiting resistor is located between the source of the first PMOS tube and the external input voltage.

[0018] According to one aspect of the present invention, the second amplifier and the third PMOS tube form a follower, and based on the output voltage, the drain voltage of the first PMOS tube is controlled to follow the output voltage, thereby avoiding an increase in circuit static power consumption due to current mirror mismatch.

[0019] According to one aspect of the present invention, a loop formed by the first amplifier, the first NMOS tube, the bias current provided by the low static power consumption circuit, the second PMOS tube, the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor constitutes a negative feedback loop, one end of the first voltage-dividing sampling resistor is connected to the low static power consumption circuit and the drain of the second PMOS tube, the other end of the first voltage-dividing sampling resistor is connected to one end of the second voltage-dividing sampling resistor and outputs a feedback voltage signal; the other end of the second voltage-dividing sampling resistor is grounded; the negative feedback loop makes the reference voltage consistent with the feedback voltage, and then sets the output voltage through the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor, and the output voltage is:

[0020] .

[0021] According to one aspect of the present invention, the gate of the fourth PMOS tube is connected to the pulse signal generating module, the drain is connected to the drain of the first NMOS tube and the low static power consumption circuit, and the source is connected to the external input voltage, serving as a switch controller to control the driving voltage.

[0022] A method for preventing residual power hot-swap output overcharging under no-load conditions, the method comprising the following steps: the first amplifier outputs a first voltage signal based on an external reference voltage and a feedback voltage, and outputs a driving voltage through a first NMOS tube and a low static power consumption circuit; the second PMOS tube generates and controls the output voltage based on an external input voltage and the driving voltage; the comparator compares the external input voltage and the output voltage and outputs a third voltage signal to a pulse signal generating module; the pulse signal generating module generates a second voltage signal based on the third voltage signal; the second voltage signal is input to the gate of the second PMOS tube through a fourth PMOS tube.

[0023] According to one aspect of the present invention, the comparator is internally a comparator with an offset voltage, that is, the comparator output flip voltage point is: ; When the external input voltage is unplugged under no-load hot-swap conditions, before the external input voltage is higher than the comparator flip voltage point, the third voltage signal output by the comparator is a high level signal; when the external input voltage is lower than the comparator flip voltage point, the third voltage signal output by the comparator flips to a low level.

[0024] According to one aspect of the present invention, when the external input voltage is hot-plugged and powered on, the comparator inverts the output third voltage signal to a high level based on the external input voltage being greater than the comparator flip voltage point, and the pulse signal generating module generates a pulse second voltage signal with an effective level of a low level based on the rising edge of the third voltage signal. The fourth PMOS tube is turned on and pulls up the gate drive voltage based on the low-level pulse second voltage signal, and the power tube is turned off at the same time, thereby preventing the output voltage from being overcharged; after the pulse second voltage signal recovers from a low level to a high level, the fourth PMOS tube is no longer controlled to be turned on, and the output voltage is only adjusted by the negative feedback operational amplifier.

[0025] According to one aspect of the present invention, the no-load hot-swap condition includes a situation where no load is connected, and a situation where the load is connected to the output voltage but the switch turns off the load.

[0026] Advantages of the present invention: The present invention is connected to the comparator through the pulse signal generating module and the low static power consumption circuit through the PMOS tube. The first amplifier outputs a voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the NMOS tube and the low static power consumption circuit. The second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS tube through the fourth PMOS tube; the comparator and the pulse signal generating module generate a pulse signal to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A circuit structure diagram of an LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to the present invention;

[0029] Figure 2 A circuit structure diagram of the prior art of an LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition as described in the present invention;

[0030] Figure 3 This is a no-load hot-swap simulation effect diagram of an LDO circuit for preventing overcharging of residual power hot-swap output under no-load according to the present invention;

[0031] Figure 4 It is an effect diagram of the static current of an LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to the present invention as a function of external input voltage;

[0032] Figure 5 This is a no-load hot-swap simulation effect diagram of an LDO circuit without a comparison circuit and a pulse signal generating module for preventing overcharging of residual power hot-swap output under no-load conditions as described in the present invention;

[0033] Figure 6 FIG2 is a second embodiment of an LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to the present invention;

[0034] Figure 7 FIG3 is an embodiment of an LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to the present invention;

[0035] Figure 8 FIG4 is a fourth embodiment of an LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] Embodiment 1:

[0038] like Figure 1 As shown, an LDO circuit to prevent overcharging of residual power hot-swap output under no-load condition, the circuit comprises: a first amplifier, , , low static power circuit, , ,switch , comparator, pulse signal generation module, external power supply, ground voltage GND, reference voltage and external output voltage The first amplifier is based on an external reference voltage and feedback voltage , output voltage control signal . It is a common source amplifier, with the source connected to ground and the drain connected to The drain and the low static power consumption circuit, the gate is connected to the output end of the first amplifier, and based on and low quiescent power consumption provide bias current, output drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to The drain and source of the low static power circuit are connected to the external input voltage , as a switch controller to control the drive voltage . The source is connected to the external input voltage, and the gate is connected to The drain is connected to the and comparators, Based on external input voltage and internal signals Control output voltage size. One end is connected to the low static power consumption circuit and The drain, The other end of the connection One end of the feedback voltage signal ; The other end of the first amplifier is grounded. , bias current provided by low static power circuit, , and The loop formed forms a negative feedback loop, which makes the reference voltage and feedback voltage Agree, then pass and Setting the Output Voltage , the output voltage is: The comparator has an internal offset voltage The comparator output flip voltage point is: + The comparator is based on the external input voltage Compare with the comparator flip voltage point and output The pulse signal generating module is based on , generating a switch control signal , pass Input to The low static power consumption circuit comprises , and the second amplifier, The source is connected to the external input voltage , gate access The gate and drain are connected The source of Source access The drain of the second amplifier is connected to the input of the second amplifier, the gate is connected to the output of the second amplifier, and the drain is connected to The drain and The drain of the second amplifier and Form a follower buffer based on the output voltage control The drain voltage follows the output voltage , avoiding the increase of circuit static power consumption caused by current mirror mismatch.

[0039] In the no-load hot-swap external input voltage unplug condition, if the external input voltage is removed Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs is a high level signal; if the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator inversion voltage point, the comparator output If the external input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the drive voltage , the comparator is based on the external input voltage is greater than the comparator flip voltage point, making the output Inverted to high level, the pulse signal generating module is based on The rising edge of the , the switch Based on the low level pulse Turn on and pull up the gate drive voltage , and turn off the power tube at the same time, thereby avoiding the output voltage Overcharge occurs. When the pulse signal After the low level is restored to the high level, the fourth PMOS tube is no longer controlled to be turned on, and the output voltage is regulated only by the negative feedback amplifier. The no-load hot-swap condition includes a situation where no load is connected, and a situation where the load is connected to the output voltage but the switch turns off the load.

[0040] like Figure 3 As shown, Under the condition of inconsistent hot plug speed, When removing After that, it is powered by the input capacitor. Since the static power consumption of LDO is small and constant under no-load condition, The performance is uniform power loss, the above hot plug overcharge, when When the residual power is higher than 3.24V, the negative feedback amplifier is still in normal regulation state, so unchanged; when When it is lower than 3.24V, Begin to follow The above simulation effect diagram shows the change of the decline Power on at 3uS speed, No overcharging occurred.

[0041] like Figure 5 As shown, Residual power hot-swap conditions and Figure 3 However, due to the lack of comparison circuit and pulse signal generation module, the circuit response speed is slow. After overcharging occurs, the power tube remains in the off state until Falling to preset After that, negative feedback releases the power tube, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0042] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0043] Advantages of the present invention: The present invention is connected to the comparator through the pulse signal generating module and the low static power consumption circuit through the PMOS tube. The first amplifier outputs a voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the NMOS tube and the low static power consumption circuit. The second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS tube through the fourth PMOS tube; the comparator and the pulse signal generating module generate a pulse signal to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load.

[0044] Embodiment 2:

[0045] like Figure 6 As shown, an LDO circuit to prevent overcharging of residual power hot-swap output under no-load condition, the circuit comprises: a first amplifier, , , low static power circuit, , ,switch , comparator, pulse signal generation module, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage In this embodiment, a clamp circuit is also added. The first amplifier is based on an external reference voltage and feedback voltage , output voltage control signal . A common source amplifier, wherein the source is grounded, the drain is connected to the drain and the low static power consumption circuit, the gate is connected to the output end of the first amplifier, and based on and low quiescent power consumption provide bias current, output gate drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to The drain and source of the low static power circuit are connected to the external input voltage , as a switch controller to control the drive voltage . The source is connected to the external input voltage, and the gate is connected to The drain is connected to the and comparators, Based on external input voltage and internal signals Control output voltage size. One end is connected to the low static power consumption circuit and The drain, The other end of the connection One end of the feedback voltage signal ; The other end of the first amplifier is grounded. , bias current provided by low static power circuit, , and The loop formed forms a negative feedback loop, which makes the reference voltage and feedback voltage Agree, then pass and Setting the Output Voltage , the output voltage is: The comparator has an internal offset voltage The comparator output flip voltage point is: + The comparator is based on the external input voltage Compare with the comparator flip voltage point and output The pulse signal generating module is based on , generating a switch control signal and , pass Input to The clamping circuit is connected to the pulse signal generating module, based on To control The low static power consumption circuit includes a current limiting resistor , , and the second amplifier, The source is connected to the current limiting resistor , gate access The gate and drain are connected The source of Source access The drain of the second amplifier, the gate of the second amplifier, the drain of the second amplifier The drain and The drain of the second amplifier and Form a follower buffer based on the output voltage control The drain voltage follows the output voltage , avoiding the increase of circuit static power consumption caused by current mirror mismatch.

[0046] When the external input voltage is removed during no-load hot-swap conditions, Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs is a high level signal; if the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator flip voltage point, the comparator output If the external input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the gate drive voltage , the comparator is based on the external input voltage is greater than the comparator flip voltage point, making the output Inverted to high level, the pulse signal generating module is based on The rising edge of the ,exist During the high level period, the clamp circuit is turned on, then is pulled low and shuts down , which is beneficial to the upper Tube pull up The pulse signal generation module is based on The rising edge of the , the switch Based on the low level pulse Turn on and pull up the gate drive voltage , and turn off the power tube at the same time, thereby avoiding the output voltage Overcharge occurs. When the pulse signal After the low level is restored to the high level, the fourth PMOS tube is no longer controlled to be turned on, and the output voltage is regulated only by the negative feedback amplifier. The no-load hot-swap condition includes a situation where no load is connected, and a situation where the load is connected to the output voltage but the switch turns off the load.

[0047] like Figure 3 As shown, Under the condition of inconsistent hot plug speed, When removing After that, it is powered by the input capacitor. Since the static power consumption of LDO is small and constant under no-load condition, The performance is uniform power loss, the above hot plug overcharge, when When the residual power is higher than 3.24V, the negative feedback amplifier is still in normal regulation state, so unchanged; when When it is lower than 3.24V, Begin to follow The above simulation effect diagram shows the change of the decline Power on at 3uS speed, No overcharging occurred.

[0048] like Figure 5 As shown, Residual power hot-swap conditions and Figure 3 However, due to the lack of comparison circuit and pulse signal generation module, the circuit response speed is slow. After overcharging occurs, the power tube remains in the off state until Falling to preset After that, negative feedback releases the power tube, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0049] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0050] Advantages of the present invention: The present invention is connected to the comparator through the pulse signal generating module and the low static power consumption circuit through the PMOS tube. The first amplifier outputs a voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the NMOS tube and the low static power consumption circuit. The second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS tube through the fourth PMOS tube; the comparator and the pulse signal generating module generate a pulse signal to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load.

[0051] Embodiment three:

[0052] like Figure 7 As shown, an LDO circuit to prevent overcharging of residual power hot-swap output under no-load condition, the circuit comprises: a first amplifier, , , low static power circuit, , ,switch , comparator, pulse signal generation module, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage In this embodiment, a clamp circuit is added and the description of the pulse signal generating module is expanded. The first amplifier is based on an external reference voltage and feedback voltage , output voltage control signal . It is a common source amplifier, with the source connected to ground and the drain connected to The drain and the low static power consumption circuit, the gate is connected to the output end of the first amplifier, and based on and low quiescent power consumption provide bias current, output gate drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to The drain and source of the low static power circuit are connected to the external input voltage , as a switch controller to control the drive voltage . The source is connected to the external input voltage, and the gate is connected to The drain is connected to the and comparators, Based on external input voltage and internal signals Control output voltage size. One end is connected to the low static power consumption circuit and The drain, The other end of the connection One end of the feedback voltage signal ; The other end of the first amplifier is grounded. , bias current provided by low static power circuit, , and The loop formed forms a negative feedback loop, which makes the reference voltage and feedback voltage Agree, then pass and Setting the Output Voltage , the output voltage is: The comparator has an internal offset voltage The comparator output flip voltage point is: + The comparator is based on the external input voltage Compare with the comparator flip voltage point and output The pulse signal generating module is based on , generating a switch control signal , pass Input to The low static power consumption circuit comprises , and the second amplifier, The source is connected to the external input voltage , gate access The gate and drain are connected The source of Source access The drain of the second amplifier is connected to the input of the second amplifier, the gate is connected to the output of the second amplifier, and the drain is connected to The drain and The drain. and A current limiting resistor can be connected between the The second amplifier and Form a follower buffer based on the output voltage control The drain voltage follows the output voltage , avoiding the increase of circuit static power consumption caused by current mirror mismatch.

[0053] The clamping circuit comprises: , and , The gate voltage signal , drain access The source of , Drain output voltage signal , gate access voltage signal , The other side of the When it is high level, On, and Pulled down.

[0054] The pulse signal generating module specifically comprises: , , , , , , , The output signal of the comparator Do , The gate input signal of based on , , , output Voltage; Capacitance Access The drain is connected to ground. connect , which plays a delaying role; Gate access The drain and source are connected , drain access The source of The other end of the ground, the voltage signal Do The gate input voltage signal; when When it is high level, If conduction Pulled down.

[0055] When the external input voltage is removed during no-load hot-swap conditions, Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs is a high level signal; if the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator inversion voltage point, the comparator output Reverse to low level. , , Du Yin is low level and in the cut-off state, and , is high level, Controlled by the first amplifier. If the external input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the gate drive voltage , and in the The external input voltage starts to rise. If the comparator flip voltage is greater than the comparator flip voltage, the output Reverse to high level; when When a high level is input to the pulse signal generating module, , , On, and When conducting, based on , , Generates a falling edge. On, and If it is still at the falling edge of high level, , Conductivity; Voltage based on , and Flips to low level, and the switch Open, Pull up to . On, and During the falling edge of high level, If conduction The voltage is pulled low, the aforementioned The common source amplifier is cut off, and the acceleration amplifier is pulled high ;switch , The three work together to increase the gate drive voltage. , and turn off the power tube at the same time, thereby avoiding the output voltage Overcharge occurs. The voltage at the falling edge makes After the deadline, stop Pull down ;when Continue to decrease to of + * back, If the deadline is The voltage returns to a high level, The switch is turned off. Reduce to low level and , After shutdown, there is no additional circuit affecting the normal operation of the negative feedback amplifier. based on , , During the falling edge, It appears as a pulse signal from high-low-high; It is a pulse pull-down of off-on-off status.

[0056] like Figure 3 As shown, Under the condition of inconsistent hot plug speed, When removing After that, it is powered by the input capacitor. Since the static power consumption of LDO is small and constant under no-load condition, The performance is uniform power loss, the above hot plug overcharge, when When the residual power is higher than 3.24V, the negative feedback amplifier is still in normal regulation state, so unchanged; when When it is lower than 3.24V, Begin to follow The above simulation effect diagram shows the change of the decline Power on at 3uS speed, No overcharging occurred.

[0057] like Figure 4 As shown, the horizontal axis is , the vertical axis is the static current of the entire LDO circuit. =3.25V, Maximum, maximum is 0.955uA; normal =4.3V, =656nA.

[0058] like Figure 5 As shown, Residual power hot-swap conditions and Figure 3 However, due to the lack of comparison circuit and pulse signal generation module, the circuit response speed is slow. After overcharging occurs, the power tube remains in the off state until Falling to preset After that, negative feedback releases the power tube, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0059] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0060] Advantages of the present invention: The present invention is connected to the comparator through the pulse signal generating module and the low static power consumption circuit through the PMOS tube. The first amplifier outputs a voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the NMOS tube and the low static power consumption circuit. The second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS tube through the fourth PMOS tube; the comparator and the pulse signal generating module generate a pulse signal to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load.

[0061] Embodiment 4:

[0062] like Figure 8 As shown, an LDO circuit to prevent overcharging of residual power hot-swap output under no-load condition, the circuit comprises: a first amplifier, , , low static power circuit, , ,switch , comparator, pulse signal generation module, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage The first amplifier is based on an external reference voltage and feedback voltage , output voltage control signal In this embodiment, the description of the pulse signal generating module is expanded. It is a common source amplifier, with the source connected to ground and the drain connected to The drain and the low static power consumption circuit, the gate is connected to the output end of the first amplifier, and based on and low quiescent power consumption provide bias current, output gate drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to The drain and source of the low static power circuit are connected to the external input voltage , as a switch controller to control the drive voltage . The source is connected to the external input voltage, and the gate is connected to The drain is connected to the and comparators, Based on external input voltage and internal signals Control output voltage size. One end is connected to the low static power consumption circuit and The drain, The other end of the connection One end of the feedback voltage signal ; The other end of the first amplifier is grounded. , bias current provided by low static power circuit, , and The loop formed forms a negative feedback loop, which makes the reference voltage and feedback voltage Agree, then pass and Setting the Output Voltage , the output voltage is: The comparator has an internal offset voltage The comparator output flip voltage point is: + The comparator is based on the external input voltage Compare with the comparator flip voltage point and output The pulse signal generating module is based on , generating a switch control signal , pass Input to The low static power consumption circuit comprises , and the second amplifier, The source is connected to the external input voltage , gate access The gate and drain are connected The source of Source access The drain of the second amplifier is connected to the input of the second amplifier, the gate is connected to the output of the second amplifier, and the drain is connected to The drain and The drain. and A current limiting resistor can be connected between the The second amplifier and Form a follower buffer based on the output voltage control The drain voltage follows the output voltage , avoiding the increase of circuit static power consumption caused by current mirror mismatch.

[0063] The pulse signal generating module specifically comprises: , Inverter , , , NOR gate, , and The inverter Output termination , The other end of NOR gate, The other end of the NOR gate is connected to the ground, and the output end of the NOR gate is connected to the inverter. , inverter Output termination The output signal of the comparator Do The gate input voltage, based on and , output voltage signal . As an inverter The input of the inverter and one of the inputs of the NOR gate based on and , the output voltage passes After getting , Make another input of NOR, and After NOR , go through After getting ,Depend on Control the switch .

[0064] When the external input voltage is removed during no-load hot-swap conditions, Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs is a high level signal; if the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator inversion voltage point, the comparator output Reverse to low level, then If turned on, is pulled high, and is low level, is high level, If the external input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the gate drive voltage , while At the beginning of the rise process, If the comparator output voltage is greater than the comparator flip voltage point, Invert to high level.

[0065] when A high level is input to the pulse signal generating module, then By Pulled down. based on , Current limiting and as input, then through and Current limiting and delay, and Compared to It is manifested as a slow increase from a low level to a high level; at this time is low level, and When the rising edge of is still at a low level, The signal turns high. based on High level output low level , then the switch Open, The voltage is pulled up to , shut down the power tube, thus avoiding Overcharge occurs. After the rising edge is at a high level, NOR makes The signal changes from high level to low level, After the inverter, it is high level, the switch Cut-off, no additional circuit affects the normal operation of the negative feedback amplifier. After being pulled down, During the rising edge of It appears as a low-level active pulse signal from high-low-high.

[0066] like Figure 3 As shown, Under the condition of inconsistent hot plug speed, When removing After that, it is powered by the input capacitor. Since the static power consumption of LDO is small and constant under no-load condition, The performance is uniform power loss, the above hot plug overcharge, when When the residual power is higher than 3.24V, the negative feedback amplifier is still in normal regulation state, so unchanged; when When it is lower than 3.24V, Begin to follow The above simulation effect diagram shows the change of the decline Power on at 3uS speed, No overcharging occurred.

[0067] like Figure 5 As shown, Residual power hot-swap conditions and Figure 3 However, due to the lack of comparison circuit and pulse signal generation module, the circuit response speed is slow. After overcharging occurs, the power tube remains in the off state until Falling to preset After that, negative feedback releases the power tube, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0068] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0069] Advantages of the present invention: The present invention is connected to the comparator through the pulse signal generating module and the low static power consumption circuit through the PMOS tube. The first amplifier outputs a voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the NMOS tube and the low static power consumption circuit. The second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS tube through the fourth PMOS tube; the comparator and the pulse signal generating module generate a pulse signal to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load.

[0070] Embodiment five:

[0071] like Figure 1 As shown, a method for preventing overcharging of residual power hot-swap output under no-load condition is provided. This embodiment is based on the LDO circuit of embodiment 1. The specific method steps of this embodiment are as follows: S1: unplugging the external input voltage under no-load hot-swap condition, removing the external input voltage Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs It is a high level signal.

[0072] S2: the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator inversion voltage point, the comparator output Invert to low level.

[0073] S3: External input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the gate drive voltage , the comparator is based on the external input voltage is greater than the comparator flip voltage point, making the output Inverted to high level, the pulse signal generating module is based on The rising edge of the , the switch Based on the low level pulse Turn on and pull up the gate drive voltage , and turn off the power tube at the same time, thereby avoiding the output voltage Overcharge occurs.

[0074] S4: When the pulse signal After the low level is restored to the high level, the fourth PMOS tube is no longer controlled to be turned on, and the output voltage is regulated only by the negative feedback amplifier. The no-load hot-swap condition includes a situation where no load is connected, and a situation where the load is connected to the output voltage but the switch turns off the load.

[0075] A new embodiment of the LDO circuit structure can be obtained by replacing and changing part of the structure of the LDO circuit in this embodiment. The new embodiment has the same function and effect.

[0076] For example, in the second embodiment, a clamping circuit is added, based on the newly added , to control judgment Whether it is clamped.

[0077] For example, in the third embodiment, a clamping circuit is added, and the description of the pulse signal generating module is expanded. The clamping circuit includes: , and , The gate voltage signal , drain access The source of , Drain output voltage signal , gate access voltage signal , The other side of the When it is high level, On, and The pulse signal generating module specifically comprises: , , , , , , , The output signal of the comparator Do , The gate input signal of based on , , , output Voltage; Capacitance Access The drain is connected to ground. connect , which plays a delaying role; Gate access The drain and source are connected , drain access The source of The other end of the ground, the voltage signal Do The gate input voltage signal; when When it is high level, If conduction In no-load hot-swap conditions, if the external input voltage is removed, Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs is a high level signal; if the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator inversion voltage point, the comparator output Reverse to low level. , , Du Yin is low level and in the cut-off state, and , is high level, Controlled by the first amplifier. If the external input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the gate drive voltage , and in the The external input voltage starts to rise. If the comparator flip voltage is greater than the comparator flip voltage, the output Reverse to high level; when When a high level is input to the pulse signal generating module, , , On, and When conducting, based on , , Generates a falling edge. On, and If it is still at the falling edge of high level, , Conductivity; Voltage based on , and Flips to low level, and the switch Open, Pull up to . On, and During the falling edge of high level, If conduction The voltage is pulled low, the aforementioned The common source amplifier is cut off, and the acceleration amplifier is pulled high ;switch , The three work together to increase the gate drive voltage. , and turn off the power tube at the same time, thereby avoiding the output voltage Overcharge occurs. The voltage at the falling edge makes After the deadline, stop Pull down ;when Continue to decrease to of + * back, If the deadline is The voltage returns to a high level, The switch is turned off. Reduce to low level and , After shutdown, there is no additional circuit affecting the normal operation of the negative feedback amplifier. based on , , During the falling edge, It appears as a pulse signal from high-low-high; It is a pulse pull-down of off-on-off status.

[0078] For example, in the fourth embodiment, the description of the pulse signal generating module is expanded. The pulse signal generating module specifically includes: , Inverter , , , NOR gate, , and The inverter Output termination , The other end of NOR gate, The other end of the NOR gate is connected to the ground, and the output end of the NOR gate is connected to the inverter. , inverter Output termination The output signal of the comparator Do The gate input voltage, based on and , output voltage signal . As an inverter The input of the inverter and one of the inputs of the NOR gate based on and , the output voltage passes After getting , Make another input of NOR, and After NOR , go through After getting ,Depend on Control the switch . In the no-load hot-swap condition, if the external input voltage is removed, Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs is a high level signal; if the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator inversion voltage point, the comparator output Reverse to low level, then If turned on, is pulled high, and is low level, is high level, If the external input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the gate drive voltage , while At the beginning of the rise process, If the comparator output voltage is greater than the comparator flip voltage point, Inverts to high level. A high level is input to the pulse signal generating module, then By Pulled down. based on , Current limiting and as input, then through and Current limiting and delay, and Compared to It is manifested as a slow increase from a low level to a high level; at this time is low level, and When the rising edge of is still at a low level, The signal turns high. based on High level output low level , then the switch Open, The voltage is pulled up to , shut down the power tube, thus avoiding Overcharge occurs. After the rising edge is at a high level, NOR makes The signal changes from high level to low level, After the inverter, it is high level, the switch Cut-off, no additional circuit affects the normal operation of the negative feedback amplifier. After being pulled down, During the rising edge of It appears as a low-level active pulse signal from high-low-high.

[0079] like Figure 3 As shown, Under the condition of inconsistent hot plug speed, When removing After that, it is powered by the input capacitor. Since the static power consumption of LDO is small and constant under no-load condition, The performance is uniform power loss, the above hot plug overcharge, when When the residual power is higher than 3.24V, the negative feedback amplifier is still in normal regulation state, so unchanged; when When it is lower than 3.24V, Begin to follow The above simulation effect diagram shows the change of the decline Power on at 3uS speed, No overcharging occurred.

[0080] like Figure 5 As shown, Residual power hot-swap conditions and Figure 3However, due to the lack of comparison circuit and pulse signal generation module, the circuit response speed is slow. After overcharging occurs, the power tube remains in the off state until Falling to preset After that, negative feedback releases the power tube, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0081] Advantages of the present invention: The present invention is connected to the comparator through the pulse signal generating module and the low static power consumption circuit through the PMOS tube. The first amplifier outputs a voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the NMOS tube and the low static power consumption circuit. The second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS tube through the fourth PMOS tube; the comparator and the pulse signal generating module generate a pulse signal to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load.

[0082] Embodiment six:

[0083] like Figure 1 As shown, an LDO circuit to prevent overcharging of residual power hot-swap output under no-load condition, the circuit comprises: a first amplifier, , , low static power circuit, , ,switch , comparator, pulse signal generation module, external power supply, ground voltage GND, reference voltage and external output voltage The first amplifier is based on an external reference voltage and feedback voltage , output voltage control signal . It is a common source amplifier, with the source connected to ground and the drain connected to The drain and the low static power consumption circuit, the gate is connected to the output end of the first amplifier, and based on and low quiescent power consumption provide bias current, output drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to The drain and source of the low static power circuit are connected to the external input voltage , as a switch controller to control the drive voltage . The source is connected to the external input voltage, and the gate is connected to The drain is connected to the and comparators, Based on external input voltage and internal signals Control output voltage size. One end is connected to the low static power consumption circuit and The drain, The other end of the connection One end of the feedback voltage signal ; The other end of the first amplifier is grounded. , bias current provided by low static power circuit, , and The loop formed forms a negative feedback loop, which makes the reference voltage and feedback voltage Agree, then pass and Setting the Output Voltage , the output voltage is: The comparator has an internal offset voltage The comparator output flip voltage point is: + The comparator is based on the external input voltage Compare with the comparator flip voltage point and output The pulse signal generating module is based on , generating a switch control signal , pass Input to The low static power consumption circuit comprises , and the second amplifier, The source is connected to the external input voltage , gate access The gate and drain are connected The source of Source access The drain of the second amplifier is connected to the input of the second amplifier, the gate is connected to the output of the second amplifier, and the drain is connected to The drain and The drain. and A current limiting resistor can be connected between the The second amplifier and Form a follower buffer based on the output voltage control The drain voltage follows the output voltage , avoiding the increase of circuit static power consumption caused by current mirror mismatch.

[0084] In the no-load hot-swap external input voltage unplug condition, if the external input voltage is removed Power supply, then the external input voltage The power is supplied by the charge stored in the external input capacitor and gradually decreases with time. When the external input voltage is higher than the comparator flip voltage point, the comparator outputs is a high level signal; if the external input voltage Lower than the preset output voltage , the negative feedback loop pulls down the gate drive voltage , so that the power tube is fully turned on, and the output voltage Follows external input voltage When the external input voltage is less than the comparator inversion voltage point, the comparator output If the external input voltage When hot-swap power is applied, the negative feedback loop starts to pull up the drive voltage , the comparator is based on the external input voltage is greater than the comparator flip voltage point, making the output Inverted to high level, the pulse signal generating module is based on The rising edge of the , the switch Based on the low level pulse Turn on and pull up the gate drive voltage , and turn off the power tube at the same time, thereby avoiding the output voltage Overcharge occurs. When the pulse signal After the low level is restored to the high level, the fourth PMOS tube is no longer controlled to be turned on, and the output voltage is regulated only by the negative feedback amplifier. The no-load hot-swap condition includes a situation where no load is connected, and a situation where the load is connected to the output voltage but the switch turns off the load.

[0085] like Figure 3 As shown, Under the condition of inconsistent hot plug speed, When removing After that, it is powered by the input capacitor. Since the static power consumption of LDO is small and constant under no-load condition, The performance is uniform power loss, the above hot plug overcharge, when When the residual power is higher than 3.24V, the negative feedback amplifier is still in normal regulation state, so unchanged; when When it is lower than 3.24V, Begin to follow The above simulation effect diagram shows the change of the decline Power on at 3uS speed, No overcharging occurred.

[0086] like Figure 5 As shown, Residual power hot-swap conditions and Figure 3 However, due to the lack of comparison circuit and pulse signal generation module, the circuit response speed is slow. After overcharging occurs, the power tube remains in the off state until Falling to preset After that, negative feedback releases the power tube, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0087] By changing part of the structure in this embodiment, the new embodiment can obtain the same function and effect.

[0088] Advantages of the present invention: The present invention is connected to the comparator through the pulse signal generating module and the low static power consumption circuit through the PMOS tube. The first amplifier outputs a voltage signal based on the external reference voltage and the feedback voltage, and outputs a driving voltage through the NMOS tube and the low static power consumption circuit. The second PMOS tube generates and controls the output voltage based on the external input voltage and the driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS tube through the fourth PMOS tube; the comparator and the pulse signal generating module generate a pulse signal to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load.

[0089] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. An LDO circuit for preventing residual power hot-swap output overcharging under no-load conditions, comprising: a first amplifier, a first NMOS tube, a second PMOS tube, a low static power consumption circuit, a fourth PMOS tube, a first voltage-dividing sampling resistor And the second voltage divider sampling resistor , and the external input voltage , External reference voltage and output voltage The first amplifier is connected to the low static power consumption circuit through an NMOS tube, and the first voltage-dividing sampling resistor and the second voltage-dividing sampling resistor are connected to the low static power consumption circuit and generate a feedback voltage, characterized in that: It also includes a comparator and a pulse signal generating module; wherein the comparator is connected to the low static power consumption circuit through a second PMOS tube, the pulse signal generating module is connected to the comparator and is connected to the low static power consumption circuit through a fourth PMOS tube, the first amplifier outputs a first voltage signal based on an external reference voltage and a feedback voltage, and outputs a driving voltage through a first NMOS tube and the low static power consumption circuit, the second PMOS tube generates and controls the output voltage based on an external input voltage and a driving voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generating module, the pulse signal generating module is based on The third voltage signal generates a second voltage signal, and the second voltage signal is input to the gate of the second PMOS tube through the fourth PMOS tube; a pulse signal is generated by the comparator and the pulse signal generating module to modulate the gate of the second PMOS tube to prevent the output voltage from being overcharged when the external input voltage is residual and hot-swapped under no-load; the gate of the fourth PMOS tube is connected to the pulse signal generating module, the drain is connected to the drain of the first NMOS tube and the low static power consumption circuit, and the source is connected to the external input voltage, as a switch controller to control the driving voltage; the comparator is a comparator with an offset voltage inside, that is, the comparator output flip voltage point is: ; When the external input voltage is unplugged in the no-load hot-swap condition, before the external input voltage is higher than the comparator flip voltage point, the third voltage signal output by the comparator is a high-level signal; when the external input voltage is lower than the comparator flip voltage point, the third voltage signal output by the comparator flips to a low level; the no-load hot-swap condition includes the situation where no load is connected, and the situation where the load is hung on the output voltage but the switch turns off the load.

2. According to claim 1, a LDO circuit for preventing residual power hot-swap output overcharging under no-load condition, characterized in that: The first NMOS tube is a common source amplifier, the source of which is grounded, the drain of which is connected to the drain of the fourth PMOS tube and the low static power consumption circuit, the gate of which is connected to the output end of the first amplifier, and outputs a driving voltage based on the first voltage signal and the bias current provided by the low static power consumption; the source of the second PMOS tube is connected to the external input voltage, the gate of which is connected to the drain of the fourth PMOS tube, and the drain of which is connected to the first voltage-dividing sampling resistor and the comparator.

3. According to claim 1, a LDO circuit for preventing residual power hot-swap output overcharging under no-load condition, characterized in that: The low static power consumption circuit includes a first PMOS tube, a third PMOS tube and a second amplifier, wherein the source of the first PMOS tube is connected to an external input voltage, the gate is connected to the gate of the second PMOS tube, and the drain is connected to the source of the third PMOS tube; the source of the third PMOS tube is connected to the drain of the first PMOS tube and the input end of the second amplifier, the gate is connected to the output end of the second amplifier, and the drain is connected to the drain of the fourth PMOS tube and the drain of the first NMOS tube.

4. The LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to claim 3, characterized in that: The LDO circuit further includes a current limiting resistor, which is located between the source of the first PMOS tube and the external input voltage.

5. The LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to claim 3, characterized in that: The second amplifier and the third PMOS tube form a follower, and based on the output voltage, the drain voltage of the first PMOS tube is controlled to follow the output voltage, thereby avoiding an increase in static power consumption of the circuit due to current mirror mismatch.

6. The LDO circuit for preventing overcharging of residual power hot-swap output under no-load condition according to claim 1, characterized in that: The loop formed by the first amplifier, the first NMOS tube, the bias current provided by the low static power consumption circuit, the second PMOS tube, the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor constitutes a negative feedback loop, one end of the first voltage-dividing sampling resistor is connected to the low static power consumption circuit and the drain of the second PMOS tube, the other end of the first voltage-dividing sampling resistor is connected to one end of the second voltage-dividing sampling resistor and outputs a feedback voltage signal; the other end of the second voltage-dividing sampling resistor is grounded; the negative feedback loop makes the reference voltage consistent with the feedback voltage, and then sets the output voltage through the first sampling voltage-dividing resistor and the second sampling voltage-dividing resistor, and the output voltage is: 。 7. A method for preventing overcharging of residual hot-swap output under no-load conditions, implemented based on the LDO circuit described in any one of claims 1 to 6, characterized in that: The method comprises the following steps: the first amplifier outputs a first voltage signal based on an external reference voltage and a feedback voltage, and outputs a driving voltage through a first NMOS tube and a low static power consumption circuit; the second PMOS tube generates and controls an output voltage based on an external input voltage and a driving voltage; the comparator compares the external input voltage and the output voltage and outputs a third voltage signal to a pulse signal generating module; the pulse signal generating module generates a second voltage signal based on the third voltage signal, and the second voltage signal is input to a gate of the second PMOS tube through a fourth PMOS tube; the comparator is a comparator with an offset voltage inside, that is, the comparator output flip voltage point is: ; When the external input voltage is unplugged in the no-load hot-swap condition, before the external input voltage is higher than the comparator flip voltage point, the third voltage signal output by the comparator is a high-level signal; when the external input voltage is lower than the comparator flip voltage point, the third voltage signal output by the comparator flips to a low level; the no-load hot-swap condition includes the situation where no load is connected, and the situation where the load is hung on the output voltage but the switch turns off the load.

8. A method for preventing overcharging of residual power hot-swap output under no-load condition according to claim 7, characterized in that: When the external input voltage is hot-plugged and powered on, the comparator inverts the output third voltage signal to a high level based on the external input voltage being greater than the comparator flip voltage point, and the pulse signal generating module generates a pulse second voltage signal with an effective level of a low level based on the rising edge of the third voltage signal. The fourth PMOS tube is turned on and pulls up the gate drive voltage based on the low-level pulse second voltage signal, and the power tube is turned off at the same time, thereby avoiding overcharging of the output voltage; after the pulse second voltage signal recovers from a low level to a high level, the fourth PMOS tube is no longer controlled to be turned on, and the output voltage is only adjusted by the negative feedback operational amplifier.

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