Successive approximation-pipeline hybrid analog-to-digital converter and time sequence control method

Abstract

The invention discloses a successive approximation-pipeline hybrid analog-to-digital converter and a time sequence control method. The successive approximation-pipeline hybrid analog-to-digital converter comprises a first-stage analog-to-digital converter, a residual amplifier, a second-stage analog-to-digital converter and a sequential circuit module, the sequential circuit module is used for sequentially acquiring a sampling clock signal and a first mark signal quantized by the first-stage analog-to-digital converter from the sequential output end of the first-stage analog-to-digital converter, and acquiring a second mark signal quantized by the second-stage analog-to-digital converter from the sequential output end of the second-stage analog-to-digital converter; an amplification clock signal is generated according to the sampling clock signal, the first mark signal and the second mark signal, and the amplification clock signal is output to a time sequence control end of the residual amplifier; and the residual amplifier is used for performing residual amplification according to the amplified clock signal. According to the invention, the error rate of the successive approximation-pipeline hybrid analog-to-digital converter is reduced, and the linearity can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of analog integrated circuit design, and in particular to a successive approximation-pipeline hybrid analog-to-digital converter and a timing control method. Background Art

[0002] The successive approximation-pipeline hybrid analog-to-digital converter is widely used in the field of wired and wireless communications because it has the low power consumption of the successive approximation analog-to-digital converter and the high throughput and low noise of the pipeline analog-to-digital converter.

[0003] The difference between the successive approximation-pipeline hybrid analog-to-digital converter and the traditional pipeline analog-to-digital converter (Pipeline Analog to Digital Converter, Pipeline ADC) is that each stage adopts a successive approximation structure. Since the use of additional comparators and subtraction circuits is avoided, the power consumption and area are guaranteed to be small, and the circuit complexity of the analog-to-digital converter is reduced. At the same time, due to the reduction in the total number of stages, it is also beneficial for the analog-to-digital converter to achieve higher linearity. Compared with the traditional successive approximation analog-to-digital converter (Successive Approximation Register Analog to Digital Converter, referred to as SAR ADC), the speed and accuracy are greatly improved. However, in the existing successive approximation-pipeline hybrid analog-to-digital converter, the asynchronous clocks of the first SAR ADC and the second SAR ADC are included respectively, and the clock of the inter-stage amplifier is also included. If the timing design does not match, there are problems of high bit error rate and low linearity. Summary of the invention

[0004] The present invention provides a successive approximation-pipeline hybrid analog-to-digital converter and a timing control method, so as to reduce the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improve the linearity.

[0005] In a first aspect, an embodiment of the present invention provides a successive approximation-pipeline hybrid analog-to-digital converter, the successive approximation-pipeline hybrid analog-to-digital converter comprising a first-stage analog-to-digital converter, a residual amplifier, a second-stage analog-to-digital converter and a timing circuit module; an input end of the first-stage analog-to-digital converter is connected to an input signal, an output end of the first-stage analog-to-digital converter is connected to an input end of the residual amplifier, and an output end of the residual amplifier is connected to an input end of the second-stage analog-to-digital converter;

[0006] The timing circuit module is connected to the timing output terminal of the first-stage analog-to-digital converter, the timing control terminal of the residual amplifier, and the timing output terminal of the second-stage analog-to-digital converter respectively; the timing circuit module is used to sequentially obtain a sampling clock signal and a first flag signal of quantization completed by the first-stage analog-to-digital converter from the timing output terminal of the first-stage analog-to-digital converter, obtain a second flag signal of quantization completed by the second-stage analog-to-digital converter from the timing output terminal of the second-stage analog-to-digital converter, generate an amplified clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplified clock signal to the timing control terminal of the residual amplifier;

[0007] The residual amplifier is used to perform residual amplification on the input signal after quantization by the first-stage analog-to-digital converter according to the amplified clock signal.

[0008] In a second aspect, an embodiment of the present invention further provides a timing control method for a successive approximation-pipeline hybrid analog-to-digital converter, and the timing control method for the successive approximation-pipeline hybrid analog-to-digital converter is applied to the successive approximation-pipeline hybrid analog-to-digital converter described in any embodiment of the present invention, comprising:

[0009] A sampling clock signal and a first flag signal indicating that the first-stage analog-to-digital converter has completed quantization are sequentially obtained from the timing output end of the first-stage analog-to-digital converter, and a second flag signal indicating that the second-stage analog-to-digital converter has completed quantization is obtained from the timing output end of the second-stage analog-to-digital converter; an amplified clock signal is generated according to the sampling clock signal, the first flag signal, and the second flag signal, and the amplified clock signal is output to the timing control end of the residual amplifier.

[0010] The present invention provides a successive approximation-pipeline hybrid analog-to-digital converter and a timing control method. The successive approximation-pipeline hybrid analog-to-digital converter includes a first-stage analog-to-digital converter, a residual amplifier, a second-stage analog-to-digital converter and a timing circuit module. The timing circuit module obtains a sampling clock signal, a first flag signal of quantization completion of the first-stage analog-to-digital converter and a second flag signal of quantization completion of the second-stage analog-to-digital converter, thereby determining that the sampling of the first-stage analog-to-digital converter is completed according to the sampling clock signal, determining that the quantization of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter are completed according to the first flag signal and the second flag signal, and obtaining a sampling clock signal, a first flag signal of quantization completion of the first-stage analog-to-digital converter and a timing control method. The signal and the second flag signal generate an amplifying clock signal, and determine that the residual amplifier can perform residual amplification, so that the residual amplifier performs residual amplification after the first-stage analog-to-digital converter completes sampling and the first-stage analog-to-digital converter and the second-stage analog-to-digital converter complete quantization, thereby avoiding the bit error problem caused by the residual amplifier starting to work before the first-stage analog-to-digital converter completes quantization, and also avoiding the problem that the residual amplifier has not performed residual amplification yet after the first-stage analog-to-digital converter completes quantization very early, thereby reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is the overall timing diagram of a traditional successive approximation-pipeline hybrid analog-to-digital converter.

[0012] Figure 2 A schematic structural diagram of a successive approximation-pipeline hybrid analog-to-digital converter provided in an embodiment of the present invention.

[0013] Figure 3 A schematic diagram of the structure of another successive approximation-pipeline hybrid analog-to-digital converter provided in an embodiment of the present invention.

[0014] Figure 4 A schematic diagram of the structure of a first sequential circuit provided in an embodiment of the present invention.

[0015] Figure 5 A partial timing diagram of a successive approximation-pipeline hybrid analog-to-digital converter provided in an embodiment of the present invention.

[0016] Figure 6 A schematic diagram of the structure of a second sequential circuit provided in an embodiment of the present invention.

[0017] Figure 7 An overall timing diagram of a successive approximation-pipeline hybrid analog-to-digital converter provided in an embodiment of the present invention.

[0018] Figure 8 A schematic diagram of the structure of a third sequential circuit provided in an embodiment of the present invention.

[0019] Fig. 9 A flowchart of a timing control method for a successive approximation-pipeline hybrid analog-to-digital converter provided by an embodiment of the present invention.

[0020] Fig.10 A flowchart of another timing control method of a successive approximation-pipeline hybrid analog-to-digital converter provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0022] In the prior art, in the field of wired and wireless communications, the RF direct sampling scheme uses an analog to digital converter (ADC) to directly sample high-frequency signals to replace the traditional down-mixing structure. Due to the wide application of this structure, medium and high-precision ADCs with gigahertz speeds have become one of the hot research directions. The pipeline structure analog to digital converter is a conventional choice under this speed and precision. However, with the development and progress of technology, the design of pipeline analog to digital converters under nanometer-level technology has become increasingly difficult due to its parallel design method and the gain problem of operational amplifiers that are highly dependent on gate length. The difference between the successive approximation-pipeline hybrid analog to digital converter and the traditional pipeline ADC is that each stage adopts a successive approximation structure. By avoiding the use of additional comparators and subtraction circuits, the power consumption and area are guaranteed to be small, and the circuit complexity of the ADC is reduced. At the same time, due to the reduction in the total number of stages, it is also beneficial for the ADC to achieve higher linearity. Compared with the traditional SAR ADC, the speed and precision are greatly improved. In addition, this structure also retains the potential to further improve the speed by using a time interleaving structure. This structure breaks the limitation that the successive approximation register (SAR) analog-to-digital converter cannot be used in high sampling rate and high resolution scenarios, while still maintaining good power consumption efficiency and being relatively simple to design under nanoscale technology.

[0023] In a successive approximation-pipeline hybrid analog-to-digital converter, timing design is particularly important because the overall successive approximation-pipeline hybrid analog-to-digital converter includes asynchronous clocks for the first SAR ADC and the second SAR ADC, as well as the clock for the inter-stage amplifier. If the timing design does not match, the bit error rate of the chip will increase in extreme environments.

[0024] The architecture of the traditional successive approximation-pipeline hybrid ADC samples in half a cycle and amplifies in half a cycle, so the overall timing is split in half. The ADC with the successive approximation-pipeline architecture can also be designed using this timing. Figure 1 This is the overall timing diagram of the traditional successive approximation-pipeline hybrid analog-to-digital converter, such as Figure 1 As shown, φ1 is the overall sampling timing signal of the traditional successive approximation-pipeline hybrid analog-to-digital converter, and φ2 is the working timing signal of the interstage amplifier of the traditional successive approximation-pipeline hybrid analog-to-digital converter. In the sampling timing signal diagram of φ1, the S / H stage at time T1 is the sampling stage of the successive approximation-pipeline hybrid analog-to-digital converter, and in the working timing signal diagram of φ2, the residual amplification stage at time T2 is the residual amplification stage of the interstage amplifier of the successive approximation-pipeline hybrid analog-to-digital converter. The second-stage SAR quantization in φ2 is the quantization stage of the second SAR ADC. One cycle of φ1 and φ2 is T1+T2 time. The quantization stage of the first SAR ADC is located after the sampling stage and before the residual amplification stage of the interstage amplifier, that is, the first-stage SAR quantization in φ1, wherein the residual amplification time is the second-stage sampling time.

[0025] However, there are three potential problems with the traditional successive approximation-pipeline hybrid analog-to-digital converter: 1. The architecture of the successive approximation-pipeline hybrid analog-to-digital converter requires a duty cycle that is not 50% (usually a 12.5% ​​input reference signal). If this timing is used, an additional signal with a duty cycle of 50% is required to control the overall circuit. 2. If a fixed duty cycle is used, the residual amplifier may start working before the first-stage SAR ADC has completed quantization. The residual amplification error will lead to an increase in the bit error rate. 3. If the first-stage SAR ADC completes its work very early, there will be a certain amount of idle time. The first-stage SAR does not work, and the residual amplifier does not work, which may reduce the linearity of the overall ADC.

[0026] Therefore, the embodiment of the present invention proposes a successive approximation-pipeline hybrid analog-to-digital converter, which can reduce the bit error rate and improve the linearity.

[0027] Figure 2 A schematic diagram of a successive approximation-pipeline hybrid analog-to-digital converter according to an embodiment of the present invention is provided. Figure 2The successive approximation-pipeline hybrid analog-to-digital converter includes a first-stage analog-to-digital converter 110, a residual amplifier 120, a second-stage analog-to-digital converter 130 and a timing circuit module 140; the input end of the first-stage analog-to-digital converter 110 is connected to the input signal, the output end of the first-stage analog-to-digital converter 110 is connected to the input end of the residual amplifier 120, and the output end of the residual amplifier 120 is connected to the input end of the second-stage analog-to-digital converter 130.

[0028] The timing circuit module 140 is respectively connected to the timing output end of the first-stage analog-to-digital converter 110, the timing control end of the residual amplifier 120, and the timing output end of the second-stage analog-to-digital converter 130; the timing circuit module 140 is used to sequentially obtain the sampling clock signal and the first flag signal quantized by the first-stage analog-to-digital converter 110 from the timing output end of the first-stage analog-to-digital converter 110, obtain the second flag signal quantized by the second-stage analog-to-digital converter 130 from the timing output end of the second-stage analog-to-digital converter 130, and generate an amplified clock signal according to the sampling clock signal, the first flag signal and the second flag signal, and output the amplified clock signal to the timing control end of the residual amplifier 120.

[0029] The residual amplifier 120 is used to perform residual amplification on the input signal after quantization by the first-stage analog-to-digital converter 110 according to the amplified clock signal.

[0030] The first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 are SAR ADCs. The first-stage analog-to-digital converter 110 quantizes the input signal by the asynchronous clock control of the first-stage analog-to-digital converter 110, and the second-stage analog-to-digital converter 130 quantizes the input signal by the asynchronous clock control of the second-stage analog-to-digital converter 130. The sampling clock signal is the sampling clock of the successive approximation-pipeline hybrid analog-to-digital converter as a whole. When the sampling clock signal is at a high level, the first-stage analog-to-digital converter 110 performs sampling. When the sampling clock signal changes from a high level to a low level, the sampling of the first-stage analog-to-digital converter is completed. Therefore, whether the sampling of the first-stage analog-to-digital converter is completed can be determined according to the sampling clock signal. When the quantization of the first-stage analog-to-digital converter 110 is completed, the asynchronous clock of the first-stage analog-to-digital converter 110 changes from a high level to a low level, and a high-level first flag signal is generated at this time. When the first flag signal is at a high level, it is determined that the quantization of the first-stage analog-to-digital converter 110 is completed; when the asynchronous clock of the second-stage analog-to-digital converter 130 changes from a high level to a low level, a high-level second flag signal is generated at this time. When the second flag signal is at a high level, the quantization of the second-stage analog-to-digital converter 130 is completed.

[0031] Specifically, the timing circuit module 140 is connected to the timing output terminal of the first-stage analog-to-digital converter 110, the timing control terminal of the residual amplifier 120, and the timing output terminal of the second-stage analog-to-digital converter 130, respectively. The timing circuit module 140 can sequentially obtain the sampling clock signal and the first flag signal from the timing output terminal of the first-stage analog-to-digital converter 110, and obtain the second flag signal from the timing output terminal of the second-stage analog-to-digital converter 130, thereby determining that the sampling of the first-stage analog-to-digital converter 110 is completed according to the sampling clock signal, and determining that the quantization of the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 is completed according to the first flag signal and the second flag signal, thereby determining that the residual amplifier 120 can perform residual amplification according to the sampling clock signal, the first flag signal and the second flag signal, thereby generating an amplified clock signal. Optionally, when the sampling clock signal is obtained to be low level, and the first flag signal and the second flag signal are obtained, that is, when the sampling of the first-stage analog-to-digital converter 110 is completed, and the quantization of the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 is completed, the amplified clock signal is generated. After the amplification clock signal is generated, the residual amplifier 120 performs residual amplification on the input signal after quantization by the first-stage analog-to-digital converter 110 according to the amplification clock signal, thereby avoiding the bit error problem caused by the residual amplifier 120 starting to work before the first-stage analog-to-digital converter 110 completes quantization. At the same time, it also avoids the problem that the first-stage analog-to-digital converter 110 completes quantization very early but the residual amplifier 120 has not yet performed residual amplification. This achieves the goal of reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0032] In addition, the amplification clock signal of the residual amplifier 120 is determined by the sampling clock signal, the first flag signal, and the second flag signal, so as to ensure that the residual amplifier 120 starts working immediately after the first-stage analog-to-digital converter 110 completes quantization, which not only avoids the problem of bit errors caused by the failure of the first-stage analog-to-digital converter 110 to complete quantization in the first half of the sampling clock signal in the traditional 50% duty cycle clock control method, but also ensures that the residual amplifier 120 starts working immediately after the first-stage analog-to-digital converter 110 completes quantization, thus saving cycle time and reducing the bandwidth pressure of the residual amplifier 120. At the same time, the second-stage analog-to-digital converter 130 quantizes the input signal with the sampling clock signal controlled by the asynchronous clock of the second-stage analog-to-digital converter 130, and uses the second flag signal of the completion of quantization of the second-stage analog-to-digital converter 130 as a condition for generating the amplification clock signal of the residual amplifier 120, so as to ensure that the residual amplifier 120 is turned on only after both the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 complete their work. Therefore, the successive approximation-pipeline hybrid analog-to-digital converter in the implementation of the present invention does not require an additional clock, and the internal functions complete the closed loop without bit errors.

[0033] The embodiment of the present invention provides a successive approximation-pipeline hybrid analog-to-digital converter, which includes a first-stage analog-to-digital converter, a residual amplifier, a second-stage analog-to-digital converter and a timing circuit module. The timing circuit module obtains a sampling clock signal, a first flag signal of quantization completion of the first-stage analog-to-digital converter and a second flag signal of quantization completion of the second-stage analog-to-digital converter, thereby determining that the sampling of the first-stage analog-to-digital converter is completed according to the sampling clock signal, and determining that the quantization of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter are completed according to the first flag signal and the second flag signal, so that the sampling of the first-stage analog-to-digital converter is completed according to the sampling clock signal, and the quantization of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter are completed according to the sampling clock signal. The first flag signal and the second flag signal determine that the residual amplifier can perform residual amplification, thereby generating an amplification clock signal, so that the residual amplifier performs residual amplification on the input signal after quantization by the first-stage analog-to-digital converter according to the amplification clock signal, thereby avoiding the bit error problem caused by the residual amplifier starting to work before the first-stage analog-to-digital converter has completed quantization, and also avoiding the problem that the first-stage analog-to-digital converter has completed quantization very early but the residual amplifier has not yet performed residual amplification, thereby reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0034] Figure 3 A structural diagram of another successive approximation-pipeline hybrid analog-to-digital converter provided by an embodiment of the present invention, see Figure 3 The timing circuit module 140 includes a first timing circuit 141 and a second timing circuit 142; the input end of the first timing circuit 141 is respectively connected to the timing output end of the first-stage analog-to-digital converter 110 and the timing output end of the second-stage analog-to-digital converter 130, and the output end of the first timing circuit 141 is connected to the input end of the second timing circuit 142; the first timing circuit 141 is used to obtain a sampling clock signal, a first flag signal, and a second flag signal, and generate an intermediate timing signal according to the sampling clock signal, the first flag signal, and the second flag signal, and send the intermediate timing signal to the second timing circuit 142.

[0035] The input end of the second timing circuit 142 is also connected to the timing output end of the first-stage analog-to-digital converter 110, and the output end of the second timing circuit 142 is connected to the timing control end of the residual amplifier 120. The second timing circuit 142 is used to generate an amplified clock signal according to the first flag signal and the intermediate timing signal, and output the amplified clock signal to the timing control end of the residual amplifier 120.

[0036] Specifically, when the first timing circuit 141 obtains the sampling clock signal as a low level and obtains the first flag signal and the second flag signal, that is, the first-stage analog-to-digital converter 110 completes sampling and the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 complete quantization, the intermediate timing signal is immediately generated. When the second timing circuit 142 obtains the intermediate timing signal or the first flag signal, it generates an amplified clock signal, thereby realizing the generation of the amplified clock signal according to the first flag signal and the intermediate timing signal, ensuring that the residual amplifier 120 starts working immediately at the next moment after the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 complete quantization, which not only avoids the problem of the first-stage analog-to-digital converter 110 not completing quantization in the first half of the sampling clock signal that may occur in the traditional 50% duty cycle clock control method, resulting in bit errors, but also ensures that the residual amplifier 120 starts working immediately after the first-stage analog-to-digital converter 110 completes quantization, saving cycle time and reducing the bandwidth pressure of the residual amplifier 120.

[0037] Furthermore, Figure 4 A schematic diagram of the structure of a first sequential circuit provided by an embodiment of the present invention, Figure 5 Partial timing diagram of the successive approximation-pipeline hybrid analog-to-digital converter provided by the embodiment of the present invention, refer to Figure 3-Figure 5 The first timing circuit 141 includes a three-input AND gate 1411 and a NOT gate 1412, the first input end of the three-input AND gate 1411 is connected to the first flag signal CMPOK_SAR1, the second input end of the three-input AND gate 1411 is connected to the second flag signal CMPOK_SAR2, the third input end of the three-input AND gate 1411 is connected to the output end of the NOT gate 1412, and the output end of the three-input AND gate 1411 is connected to the input end of the second timing circuit 142; the input end of the NOT gate 1412 is connected to the sampling clock signal CLK_SAMPLE.

[0038] Among them, the three-input AND gate 1411 will output high only when all inputs are high. Only when the first flag signal CMPOK_SAR1 and the second flag signal CMPOK_SAR2 are both high and the sampling clock signal CLK_SAMPLE is low, the three-input AND gate 1411 will output a high-level intermediate timing signal CLK_SAMPLE2, thereby greatly reducing the bit error rate caused by the metastable state of the comparator in the first-stage analog-to-digital converter 110, and also saving cycle time to reduce the bandwidth pressure of the residual amplifier 120.

[0039] Specifically, the NOT gate 1412 can reverse the high and low states of the input. When the sampling clock signal CLK_SAMPLE is at a low level, a high level signal can be output to the third input terminal of the three-input AND gate 1411 through the NOT gate 1412. The first flag signal CMPOK_SAR1 is at a high level after the first-stage analog-to-digital converter 110 completes quantization, and the second flag signal CMPOK_SAR2 is at a high level after the second-stage analog-to-digital converter 130 completes quantization. Therefore, when the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 are both quantized and the successive approximation-pipeline hybrid analog-to-digital converter sampling is completed, the three-input AND gate 1411 can generate an intermediate timing signal CLK_SAMPLE2, and then generate a reset clock signal and an amplification clock signal according to the intermediate timing signal CLK_SAMPLE2, so that the residual amplifier 120 is reset and the residual is amplified.

[0040] Optional, such as Figure 4 As shown, the first timing circuit 141 also includes a delay unit 1413; the input end of the delay unit 1413 is connected to the first flag signal CMPOK_SAR1 quantized by the first-stage analog-to-digital converter 110, and the output end of the delay unit 1413 is connected to the first input end of the three-input AND gate 1411; the delay unit 1413 is used to delay the first flag signal CMPOK_SAR1 for a preset time and input it to the first input end of the three-input AND gate 1411.

[0041] Specifically, the delay unit 1413 delays the first flag signal CMPOK_SAR1 by a preset time and then inputs it to the first input terminal of the three-input AND gate 1411. For example, the preset time is 30*10 -12 By delaying the first flag signal CMPOK_SAR1 by a preset time and inputting it to the first input terminal of the three-input AND gate 1411, after the first timing circuit 141 receives the first flag signal CMPOK_SAR1, the three-input AND gate 1411 delays the preset time to generate the intermediate timing signal CLK_SAMPLE2, thereby further ensuring that the first-stage analog-to-digital converter 110 generates an amplified clock signal after quantization is completed, so that the residual amplifier 120 performs residual amplification, and further ensuring that the successive approximation-pipeline hybrid analog-to-digital converter will not have bit errors.

[0042] Furthermore, Figure 6 A schematic diagram of the structure of a second sequential circuit provided in an embodiment of the present invention, referring to Figure 3 and Figure 6The second timing circuit 142 includes an OR gate 1421, a first input terminal of the OR gate 1421 is connected to the first flag signal CMPOK_SAR1, a second input terminal of the OR gate 1421 is connected to the output terminal generated by the first timing circuit 141, and an output terminal of the OR gate 1421 is connected to the timing control terminal of the residual amplifier 120.

[0043] Specifically, the first input terminal of the OR gate 1421 is connected to the first flag signal CMPOK_SAR1, and the second input terminal of the OR gate 1421 is connected to the intermediate timing signal CLK_SAMPLE2. When all inputs of the OR gate 1421 are low, the output is low. Then, when the first flag signal CMPOK_SAR1 is high, or the intermediate timing signal CLK_SAMPLE2 is high, or the first flag signal CMPOK_SAR1 and the intermediate timing signal CLK_SAMPLE2 are both high, the output terminal of the OR gate 1421 outputs a high-level amplified clock signal CLK_AMP to the residual. The timing control end of the amplifier 120 enables the residual amplifier 120 to perform residual amplification on the input signal after quantization by the first-stage analog-to-digital converter 110 according to the amplification clock signal CLK_AMP, thereby avoiding the bit error problem caused by the residual amplifier 120 starting to work before the first-stage analog-to-digital converter 110 has not completed quantization, and also avoiding the problem that the first-stage analog-to-digital converter 110 has completed quantization very early but the residual amplifier 120 has not yet performed residual amplification, thereby reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0044] Furthermore, Figure 7 The overall timing diagram of the successive approximation-pipeline hybrid analog-to-digital converter provided by the embodiment of the present invention is further referred to Figure 3 and Figure 7 The timing circuit module 140 includes a third timing circuit 143; a first input end of the third timing circuit 143 is connected to the timing output end of the first-stage analog-to-digital converter 110, and a second input end of the third timing circuit 143 is connected to the output end of the first timing circuit 141; the third timing circuit 143 is used to generate a reset clock signal CLK_AMP_RST according to the intermediate mark signal CLK5 and the intermediate timing signal CLK_SAMPLE2 of the quantization process of the first-stage analog-to-digital converter 110, and output the reset clock signal CLK_AMP_RST to the timing control end of the residual amplifier 120; wherein the intermediate mark signal CLK5 of the quantization process of the first-stage analog-to-digital converter 110 is generated at the last rising edge in one cycle of the asynchronous clock signal CLK_ASY_SAR1 of the first-stage analog-to-digital converter 110; the residual amplifier 120 is used to reset according to the reset clock signal CLK_AMP_RST.

[0045] Among them, the intermediate flag signal CLK5 of the quantization process of the first-stage analog-to-digital converter 110 is generated at the last rising edge in one cycle of the asynchronous clock signal of the first-stage analog-to-digital converter 110, that is, the intermediate flag signal CLK5 is a latched signal of the last rising edge in one cycle of the asynchronous clock signal of the first-stage analog-to-digital converter 110.

[0046] Specifically, the first input terminal of the third timing circuit 143 is connected to the timing output terminal of the first-stage analog-to-digital converter 110, and is used to obtain the intermediate mark signal CLK5 of the quantization process of the first-stage analog-to-digital converter 110. The second input terminal of the third timing circuit 143 and the output terminal of the first timing circuit 141 are used to obtain the intermediate timing signal CLK_SAMPLE2. Figure 7 The third timing circuit 143 generates a reset clock signal CLK_AMP_RST through the intermediate flag signal CLK5 and the intermediate timing signal CLK_SAMPLE2, so that the reset clock signal CLK_AMP_RST and the amplified clock signal CLK_AMP do not overlap at all, thereby preventing the amount of information stored on the capacitor of the first-stage analog-to-digital converter 110 from being released by the reset circuit of the residual amplifier 120. The specific principle is that the reset circuit of the residual amplifier 120 is turned off at the rising edge of the last asynchronous clock of the first-stage analog-to-digital converter 110, and the residual amplifier 120 has completed the reset.

[0047] Furthermore, Figure 8 A schematic diagram of the structure of the third sequential circuit provided by an embodiment of the present invention, see Figure 8 The third timing circuit 143 includes a NOR gate 1431, a first input end of the NOR gate 1431 is connected to the intermediate mark signal CLK5 of the quantization process of the first-stage analog-to-digital converter 110, and a second input end of the NOR gate is connected to the output end of the first timing circuit 141; the third timing circuit 143 is used to generate a reset clock signal CLK_AMP_RST according to the intermediate mark signal CLK5 and the intermediate timing signal CLK_SAMPLE2 of the quantization process of the first-stage analog-to-digital converter 110, and output the reset clock signal CLK_AMP_RST to the timing control end of the residual amplifier 120.

[0048] The NOR gate 1431 will have a high output only when all inputs are low. When the intermediate flag signal CLK5 and the intermediate timing signal CLK_SAMPLE2 of the quantization process of the first-stage analog-to-digital converter 110 are both low, the third timing circuit 143 generates a reset clock signal CLK_AMP_RST.

[0049] Specifically, in order to avoid the reset clock signal CLK_AMP_RST and the amplified clock signal CLK_AMP from overlapping, it is necessary to reset the clock signal CLK_AMP_RST to a high level when the amplified clock signal CLK_AMP is at a low level, thereby ensuring that the reset and residual amplification of the residual amplifier 120 are performed in a time-sharing manner, and preventing the amount of information stored on the capacitor of the first-stage analog-to-digital converter 110 from being released by the reset circuit of the residual amplifier 120.

[0050] In addition, if Figure 2 and Figure 7As shown, the reset clock signal CLK_AMP_RST and the amplified clock signal CLK_AMP of the residual amplifier 120 do not overlap, which can prevent the amount of information stored on the capacitor of the first-stage analog-to-digital converter 110 from being released by the reset circuit of the residual amplifier 120. The specific principle is that the reset circuit of the residual amplifier 120 is turned off at the rising edge time t1 of the last asynchronous clock of the first-stage analog-to-digital converter 110, and the residual amplifier 120 has been reset. When the first-stage analog-to-digital converter 110 is quantized, a high-level first flag signal CMPOK_SAR1 is generated. The first flag signal CMPOK_SAR1 and the intermediate timing signal CLK_SAMPLE2 can be passed through the OR gate 1421 to make the amplified clock signal CLK_AMP start to rise at time t2, generating a high-level amplified clock signal CLK_AMP, and the residual amplification of the residual amplifier 120 begins. During the residual amplification process of the residual amplifier 120, the amplified clock signal CLK_AMP is at a high level. For example, at time t3 during the residual amplification process of the residual amplifier 120, the amplified clock signal CLK_AMP, the first flag signal CMPOK_SAR1, the second flag signal CMPOK_SAR2, the intermediate timing signal CLK_SAMPLE2 and the intermediate flag signal CLK5 are all at a high level. By controlling the working timing of the residual amplifier 120, it can be ensured that the residual amplifier 120 starts working immediately at the next moment after the first-stage analog-to-digital converter 110 completes quantization. It not only avoids the problem of bit errors caused by the failure of the first-stage analog-to-digital converter 110 to complete quantization in the first half of the sampling clock signal CLK_SAMPLE that may occur in the traditional 50% duty cycle clock control method, but also ensures that the residual amplifier 120 starts working immediately after the first-stage analog-to-digital converter 110 completes quantization, thereby reducing the bandwidth pressure of the residual amplifier 120. At the same time, an asynchronous signal CLK_ASY_SAR2 is added to control the operation of the second-stage analog-to-digital converter 130. The second flag signal CMPOK_SAR2 indicating the completion of quantization of the second-stage analog-to-digital converter 130 is added to the three-input AND gate 1411, so that the residual amplifier 120 can be ensured to be turned on only after the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 have completed their work. Therefore, the successive approximation-pipeline hybrid analog-to-digital converter of the embodiment of the present invention does not require an additional clock, and the internal functions complete the closed loop without bit errors, thereby reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0051] The embodiment of the present invention provides a successive approximation-pipeline hybrid analog-to-digital converter, thereby avoiding the bit error problem caused by the residual amplifier starting to work before the first-stage analog-to-digital converter has completed quantization, and also avoiding the problem that the first-stage analog-to-digital converter has completed quantization very early but the residual amplifier has not yet performed residual amplification. This reduces the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improves the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0052] The embodiment of the present invention further provides a timing control method for a successive approximation-pipeline hybrid analog-to-digital converter. The timing control method for the successive approximation-pipeline hybrid analog-to-digital converter is applied to the successive approximation-pipeline hybrid analog-to-digital converter in any embodiment of the present invention. Fig. 9 A flowchart of a timing control method for a successive approximation-pipeline hybrid analog-to-digital converter provided by an embodiment of the present invention, see Fig. 9 , the timing control method of the successive approximation-pipeline hybrid analog-to-digital converter includes:

[0053] S110, sequentially obtaining a sampling clock signal and a first flag signal indicating that the first-stage analog-to-digital converter has completed quantization from a timing output terminal of the first-stage analog-to-digital converter, and obtaining a second flag signal indicating that the second-stage analog-to-digital converter has completed quantization from a timing output terminal of the second-stage analog-to-digital converter.

[0054] Specifically, refer to Figure 2 , according to the sampling clock signal, it is determined that the sampling of the first-stage analog-to-digital converter 110 is completed, and according to the first flag signal and the second flag signal, it is determined that the quantization of the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 is completed, so that according to the sampling clock signal, the first flag signal and the second flag signal, it can be determined that the residual amplifier 120 can perform residual amplification, thereby generating an amplified clock signal.

[0055] S120 , generating an amplified clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and outputting the amplified clock signal to a timing control terminal of the residual amplifier.

[0056] Specifically, when the sampling clock signal is obtained to be at a low level, and the first flag signal and the second flag signal are obtained, that is, the sampling of the first-stage analog-to-digital converter 110 is completed, and the quantization of the first-stage analog-to-digital converter 110 and the second-stage analog-to-digital converter 130 is completed, an amplification clock signal is generated. After the amplification clock signal is generated, the residual amplifier 120 performs residual amplification on the input signal after the quantization of the first-stage analog-to-digital converter 110 is completed according to the amplification clock signal, thereby avoiding the problem of the residual amplifier 120 starting to work before the quantization of the first-stage analog-to-digital converter 110 is completed, and also avoiding the problem that the residual amplifier 120 has not performed residual amplification when the first-stage analog-to-digital converter 110 is quantized very early, and ensures that the residual amplifier 120 starts to work immediately the next moment after the first-stage analog-to-digital converter 110 completes quantization, thereby reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0057] The embodiment of the present invention provides a timing control method for a successive approximation-pipeline hybrid analog-to-digital converter. By acquiring a sampling clock signal, a first flag signal indicating that the first-stage analog-to-digital converter has completed quantization, and a second flag signal indicating that the second-stage analog-to-digital converter has completed quantization, the sampling completion of the first-stage analog-to-digital converter is determined according to the sampling clock signal, and the quantization completion of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter is determined according to the first flag signal and the second flag signal. Therefore, it can be determined according to the sampling clock signal, the first flag signal and the second flag signal that the residual amplifier can perform residual amplification, thereby generating an amplified clock signal, so that the residual amplifier performs residual amplification on the input signal after quantization by the first-stage analog-to-digital converter has completed according to the amplified clock signal, thereby avoiding the problem of the residual amplifier starting to work before the first-stage analog-to-digital converter has completed quantization, and also avoiding the problem of the residual amplifier not performing residual amplification when the first-stage analog-to-digital converter has completed quantization very early, thereby reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0058] Furthermore, Fig.10 A flowchart of another method for controlling the timing of a successive approximation-pipeline hybrid analog-to-digital converter provided by an embodiment of the present invention, see Fig.10 , generating an amplified clock signal according to the sampling clock signal, the first flag signal and the second flag signal, including:

[0059] S210 , generating an intermediate timing signal according to a sampling clock signal, a first flag signal, and a second flag signal.

[0060] Specifically, refer to Figure 3-Figure 5Only when the first flag signal CMPOK_SAR1 and the second flag signal CMPOK_SAR2 are both high and the sampling clock signal CLK_SAMPLE is low, the three-input AND gate 1411 will output a high intermediate timing signal CLK_SAMPLE2. The intermediate timing signal can be used to generate non-overlapping amplified clock signals and reset clock signals, thereby greatly reducing the bit error rate caused by the metastable state of the comparator in the first-stage analog-to-digital converter 110, and also saving cycle time to reduce the bandwidth pressure of the residual amplifier 120.

[0061] S220 , generating an amplified clock signal according to the first flag signal and the intermediate timing signal, and outputting the amplified clock signal to a timing control terminal of the residual amplifier.

[0062] Specifically, refer to Figure 3 and Figure 6 When the first flag signal CMPOK_SAR1 is at a high level, or when the intermediate timing signal CLK_SAMPLE2 is at a high level, or when both the first flag signal CMPOK_SAR1 and the intermediate timing signal CLK_SAMPLE2 are at a high level, the output end of the OR gate 1421 outputs a high-level amplified clock signal CLK_AMP to the timing control end of the residual amplifier 120, so that the residual amplifier 120 performs residual amplification on the input signal after quantization by the first-stage analog-to-digital converter 110 according to the amplified clock signal CLK_AMP, thereby avoiding the bit error problem caused by the residual amplifier 120 starting to work before the first-stage analog-to-digital converter 110 is quantized, and also avoiding the problem that the residual amplifier 120 has not performed residual amplification when the first-stage analog-to-digital converter 110 is quantized very early, thereby reducing the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improving the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0063] Optionally, after the intermediate timing signal is generated according to the sampling clock signal, the first flag signal and the second flag signal, the method further includes:

[0064] A reset clock signal is generated according to an intermediate mark signal and an intermediate timing signal of a quantization process of a first-stage analog-to-digital converter, and the reset clock signal is output to a timing control terminal of a residual amplifier.

[0065] Specifically, refer to Figure 3 and Figure 7, a reset clock signal CLK_AMP_RST is generated by the intermediate flag signal CLK5 and the intermediate timing signal CLK_SAMPLE2, and the residual amplifier 120 is reset according to the reset clock signal CLK_AMP_RST. The reset clock signal CLK_AMP_RST and the amplified clock signal CLK_AMP of the residual amplifier 120 do not overlap at all, thereby preventing the amount of information stored on the capacitor of the first-stage analog-to-digital converter 110 from being released by the reset circuit of the residual amplifier 120.

[0066] The embodiment of the present invention provides a timing control method for a successive approximation-pipeline hybrid analog-to-digital converter, thereby avoiding the bit error problem caused by the residual amplifier starting to work before the first-stage analog-to-digital converter in the successive approximation-pipeline hybrid analog-to-digital converter has completed quantization. At the same time, it also avoids the problem that the first-stage analog-to-digital converter has completed quantization very early but the residual amplifier has not yet performed residual amplification. This reduces the bit error rate of the successive approximation-pipeline hybrid analog-to-digital converter and improves the linearity of the successive approximation-pipeline hybrid analog-to-digital converter.

[0067] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A successive approximation-pipeline hybrid analog-to-digital converter, characterized in that: The successive approximation-pipeline hybrid analog-to-digital converter comprises a first-stage analog-to-digital converter, a residual amplifier, a second-stage analog-to-digital converter and a timing circuit module; the input end of the first-stage analog-to-digital converter is connected to an input signal, the output end of the first-stage analog-to-digital converter is connected to the input end of the residual amplifier, and the output end of the residual amplifier is connected to the input end of the second-stage analog-to-digital converter; The timing circuit module is connected to the timing output terminal of the first-stage analog-to-digital converter, the timing control terminal of the residual amplifier, and the timing output terminal of the second-stage analog-to-digital converter respectively; the timing circuit module is used to sequentially obtain a sampling clock signal and a first flag signal of quantization completed by the first-stage analog-to-digital converter from the timing output terminal of the first-stage analog-to-digital converter, obtain a second flag signal of quantization completed by the second-stage analog-to-digital converter from the timing output terminal of the second-stage analog-to-digital converter, generate an amplified clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplified clock signal to the timing control terminal of the residual amplifier; The residual amplifier is used to perform residual amplification on the input signal after quantization by the first-stage analog-to-digital converter according to the amplified clock signal.

2. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 1, characterized in that: The sequential circuit module includes a first sequential circuit and a second sequential circuit; The input end of the first sequential circuit is connected to the timing output end of the first-stage analog-to-digital converter and the timing output end of the second-stage analog-to-digital converter respectively, and the output end of the first sequential circuit is connected to the input end of the second sequential circuit; The first sequential circuit is used to obtain the sampling clock signal, the first flag signal and the second flag signal, generate an intermediate sequential signal according to the sampling clock signal, the first flag signal and the second flag signal, and send the intermediate sequential signal to the second sequential circuit; The input end of the second timing circuit is also connected to the timing output end of the first-stage analog-to-digital converter, and the output end of the second timing circuit is connected to the timing control end of the residual amplifier. The second timing circuit is used to generate the amplified clock signal according to the first flag signal and the intermediate timing signal, and output the amplified clock signal to the timing control end of the residual amplifier.

3. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 2, characterized in that: The first sequential circuit includes a three-input AND gate and a NOT gate, wherein the first input of the three-input AND gate is connected to the first flag signal, the second input of the three-input AND gate is connected to the second flag signal, the third input of the three-input AND gate is connected to the output of the NOT gate, and the output of the three-input AND gate is connected to the input of the second sequential circuit; the input of the NOT gate is connected to the sampling clock signal.

4. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 3, characterized in that: The first sequential circuit further includes a delay unit; The input end of the delay unit is connected to the first flag signal quantized by the first-stage analog-to-digital converter, and the output end of the delay unit is connected to the first input end of the three-input AND gate; The delay unit is used to delay the first flag signal by a preset time and then input the first flag signal to the first input terminal of the three-input AND gate.

5. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 3, characterized in that: The second timing circuit includes an OR gate, a first input end of the OR gate is connected to the first flag signal, a second input end of the OR gate is connected to an output end generated by the first timing circuit, and an output end of the OR gate is connected to a timing control end of the residual amplifier.

6. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 2, characterized in that: The sequential circuit module includes a third sequential circuit; The first input end of the third sequential circuit is connected to the sequential output end of the first-stage analog-to-digital converter, and the second input end of the third sequential circuit is connected to the output end of the first sequential circuit; The third timing circuit is used to generate a reset clock signal according to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter and the intermediate timing signal, and output the reset clock signal to the timing control terminal of the residual amplifier; wherein the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter is generated at the last rising edge in one cycle of the asynchronous clock signal of the first-stage analog-to-digital converter; The residual amplifier is used for being reset according to the reset clock signal.

7. The successive approximation-pipeline hybrid analog-to-digital converter according to claim 6, characterized in that: The third sequential circuit comprises a NOR gate, a first input end of the NOR gate is connected to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter, and a second input end of the NOR gate is connected to the output end of the first sequential circuit; The third timing circuit is used to generate the reset clock signal according to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter and the intermediate timing signal, and output the reset clock signal to the timing control terminal of the residual amplifier.

8. A timing control method for a successive approximation-pipeline hybrid analog-to-digital converter, characterized in that: The timing control method of the successive approximation-pipeline hybrid analog-to-digital converter is applied to the successive approximation-pipeline hybrid analog-to-digital converter according to any one of claims 1 to 7, and the timing control method comprises: Acquire a sampling clock signal and a first flag signal indicating that quantization of the first-stage analog-to-digital converter is completed from a timing output terminal of the first-stage analog-to-digital converter, and acquire a second flag signal indicating that quantization of the second-stage analog-to-digital converter is completed from a timing output terminal of the second-stage analog-to-digital converter; An amplified clock signal is generated according to the sampling clock signal, the first flag signal and the second flag signal, and the amplified clock signal is output to a timing control terminal of the residual amplifier.

9. The timing control method of the successive approximation-pipeline hybrid analog-to-digital converter according to claim 8, characterized in that: The step of generating an amplified clock signal according to the sampling clock signal, the first flag signal and the second flag signal comprises: generating the intermediate timing signal according to the sampling clock signal, the first flag signal and the second flag signal; The amplified clock signal is generated according to the first flag signal and the intermediate timing signal, and the amplified clock signal is output to the timing control terminal of the residual amplifier.

10. The timing control method of the successive approximation-pipeline hybrid analog-to-digital converter according to claim 8, characterized in that: After generating the intermediate timing signal according to the sampling clock signal, the first flag signal and the second flag signal, the method further includes: A reset clock signal is generated according to the intermediate flag signal of the quantization process of the first-stage analog-to-digital converter and the intermediate timing signal, and the reset clock signal is output to the timing control terminal of the residual amplifier.

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