16-bit PWM-DAC digital-to-analog conversion circuit and digital-to-analog converter
Through dual-channel parallel conversion and quantization superposition technology, the problem of signal bandwidth compression of PWM-DAC at high resolution is solved, and the balance between high resolution and wide bandwidth is achieved, circuit design is simplified, and power consumption and complexity are reduced.
Patent Information
- Application Number
- CN202411286924.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2024-12-27
AI Technical Summary
When existing PWM-DACs achieve high resolution, the signal bandwidth is compressed, making it difficult to maintain high resolution in a wide bandwidth range, and the circuit design is high, and the power consumption and area occupies a large amount.
Using a dual-channel parallel conversion scheme, 16-bit numbers are divided into high 8-bit and low 8-bit, and quantized superposition and ripple suppression are achieved through latched full adder and second-order active low-pass filter to achieve high resolution and Balance of wide bandwidth simplifies circuit design.
It improves signal bandwidth and conversion speed, reduces circuit complexity and power consumption, and achieves high-resolution digital-to-analog conversion performance.
Smart Images
Figure CN119210459A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of signal processing, and in particular to a 16-bit PWM-DAC digital-to-analog conversion circuit and a digital-to-analog converter. Background Art
[0002] The digital-to-analog converter (DAC) is a signal processing circuit that converts digital quantities into analog quantities. There are different design frameworks according to different performance requirements. The typical resistor type, capacitor type and current type have a strong reliance on accurate reference voltage or current in design. In the circuit design process, it is much easier to achieve accurate clock pulse width duty cycle by controlling the timing and frequency division of the clock circuit than to accurately control a voltage or current analog quantity.
[0003] Therefore, a DAC digital-to-analog converter based on pulse width modulation (PWM) technology has been derived from the prior art. The pulse width duty cycle of the output clock is controlled by the input digital code, and the output clock signal is filtered to achieve the output of the corresponding analog quantity, thereby completing the conversion. This type of DAC has the advantages of robustness, reliability, simplicity and low cost, and is mostly used in power conversion, LED brightness control, motor control and some signal conditioning circuits. However, for typical PWM-DAC implementation schemes, the need to obtain high-resolution performance comes at the expense of high clock frequency. Therefore, it is very challenging to achieve high resolution within a relatively wide bandwidth. Summary of the invention
[0004] The present invention provides a 16-bit PWM-DAC digital-to-analog conversion circuit and a digital-to-analog converter that help to reasonably improve speed and precision performance, and can solve at least one of the above technical problems.
[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:
[0006] A 16-bit PWM-DAC digital-to-analog conversion circuit includes a 16-bit pulse width modulator, a high- and low-bit PWM quantizer, and a second-order active low-pass filter;
[0007] The 16-bit pulse width modulator is used to convert the input 16-bit digital data into a pulse width modulation PWM signal, including two dual 8-bit PWM modulation conversion channels, namely a high 8-bit PWM modulation conversion channel and a low 8-bit PWM modulation conversion channel, and the two channels have the same counting clock, reset control and register enable;
[0008] The input ends of the high and low bit PWM quantizers are respectively connected to the output ends of the high 8-bit PWM modulation conversion channel and the low 8-bit PWM modulation conversion channel, and the output ends of the high and low bit PWM quantizers are connected to the signal input end of the second-order active low-pass filter.
[0009] Furthermore, the basic unit constituting the high 8-bit PWM modulation conversion channel or the low 8-bit PWM modulation conversion channel is a one-bit latch full adder, and the one-bit latch full adder is composed of two D flip-flops and one full adder;
[0010] The two D flip-flops are respectively an input-level D flip-flop and an intermediate-level D flip-flop. The input-level D flip-flop is used to latch and update the input single-bit digital. The control pin Dlat enables the update of the synchronous digital input pin D. The intermediate-level D flip-flop is used to count up according to the input code. The counting clock CK comes from the system clock.
[0011] The full adder is used to perform binary addition operation on the addition overflow code Ci from the low position and the counting code of the current position, and according to whether the current input digital number is logic "1", a system clock cycle is superimposed on the final pulse width after PWM modulation, that is, the pulse width of the output pin Co, thereby realizing the modification of the pulse width duty cycle of PWM modulation according to the digital weight.
[0012] Furthermore, the duty cycle of the low 8-bit digital number after being modulated by the low 8-bit PWM modulation conversion channel is amplified 256 times relative to the pulse width modulation based on the 16-bit principle. The output PWM signal is scaled by the high and low-bit PWM quantizers in proportion to each other, and then superimposed with the PWM signal output by the high 8-bit digital number through the high 8-bit PWM modulation conversion channel to restore the equivalent 16-bit PWM pulse width modulation.
[0013] Furthermore, the 16-bit pulse width modulator is divided into 8 bits high and 8 bits low, which are latched into dual channels for synchronous parallel modulation conversion. The 16-bit pulse width modulator outputs two high and low modulation signals, namely PWMH and PWML. The PWMH represents the output after the high 8-bit input is digitally modulated, and the PWML represents the output after the low 8-bit input is digitally modulated. The output characteristics of the PWMH and PWML are consistent. The two outputs are simultaneously input into the high and low PWM quantizers for quantization superposition, and finally output VPWM, which is the final output of the 16-bit pulse width modulator.
[0014] Furthermore, the high- and low-bit PWM quantizer includes two groups of logic buffers and a resistor-capacitor network, the two groups of logic buffers are respectively connected to the high 8-bit PWM modulation conversion channel and the low 8-bit PWM modulation conversion channel, each group of logic buffers includes multiple logic inverters, the resistor-capacitor network includes Rh, Rl, Rf, Cs and Cf, the two groups of logic buffers respectively differentiate the PWML and PWMH signals into PWMLb and PWMHb signals, and use the reverse superposition of the signals to eliminate the DC component of the ripple, and then suppress some high-order harmonics through the bandpass filter composed of Rf and Cs and the low-pass filter composed of Rf and Cf, which is equivalent to introducing additional harmonic suppression poles into the second-order active low-pass filter of the output stage, and realizing the quantization superposition of the signal at the same time.
[0015] Furthermore, the two groups of PWM signals output by the two dual 8-bit PWM modulation conversion channels are respectively connected in series with weighted resistors Rh and Rl before short-circuiting. Rh represents the resistor connected in series with the high 8-bit PWM signal, and Rl represents the resistor connected in series with the low 8-bit PWM signal. The ratio between the two is: Rl=256*Rh.
[0016] Furthermore, the second-order active low-pass filter includes an amplifier, and the amplifier and the logic inverter are powered by the same driving power supply.
[0017] A digital-to-analog converter comprises the 16-bit PWM-DAC digital-to-analog conversion circuit.
[0018] The beneficial effects of the present invention are embodied in:
[0019] 1. The present invention analyzes the problems that occur in the high-resolution conversion process of traditional PWM-DAC, and proposes dual-channel parallel conversion to address the problem that high resolution will inevitably lead to compression of signal bandwidth. On this basis, the idea of four-channel parallel conversion is divided to effectively improve the signal bandwidth and reasonably balance the contradiction between resolution and signal bandwidth in the application of electronic equipment, thereby improving the performance of traditional PWM-DAC. At the same time, the present invention simplifies the complexity of circuit design. Taking the 16-bit PWM-DAC digital-to-analog conversion circuit of the present application as an example, it not only achieves the guarantee of high resolution, but also improves the signal bandwidth.
[0020] 2. In the present invention, a simple digital timing circuit framework generates high-resolution PWM, and the channel division can be realized through the cascade of unit latch full adders, and the circuit implementation is simple; subsequently, a simple resistor network is used to realize the superposition quantization and active ripple suppression of the PWM signal output by multiple channels, reducing the design difficulty and complexity of the final output stage low-pass filter. In this way, the circuit complexity is optimized, providing feasibility for reducing power consumption and area. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.
[0022] Figure 1 It is a schematic diagram of a 16-bit PWM-DAC digital-to-analog conversion circuit according to an embodiment of the present invention.
[0023] Figure 2 1 is a circuit diagram of a 16-bit pulse width modulator according to an embodiment of the present invention.
[0024] Figure 3 It is a structural schematic diagram of a one-bit latch full adder according to an embodiment of the present invention.
[0025] Figure 4 Schematic diagram of a circuit of a high-low bit PWM quantizer according to an embodiment of the present invention.
[0026] Figure 5 4 is a circuit diagram of a second-order active low-pass filter according to an embodiment of the present invention.
[0027] Figure 6 It is a structural block diagram of a computer device according to an embodiment of the present invention.
[0028] The components in the accompanying drawings are marked as follows: 100, 16-bit pulse width modulator; 1001, one-bit latch full adder; 110, high and low-bit PWM quantizer; 1101, logic inverter; 120, second-order active low-pass filter; 1201, amplifier. DETAILED DESCRIPTION
[0029] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0030] It should be noted that the meaning of "and / or" in the full text includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, "plurality" means more than two.
[0031] It should be noted that those skilled in the art can understand that all or part of the steps implemented in the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When hardware is used for implementation, the components such as those mentioned in the accompanying drawings can be implemented in whole or in part by purchasing standard parts or modified parts. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).
[0032] See also Figure 1 , an embodiment of the present invention provides a 16-bit PWM-DAC digital-to-analog conversion circuit, including a 16-bit pulse width modulator 100, a high- and low-bit PWM quantizer 110, and a second-order active low-pass filter 120;
[0033] The 16-bit pulse width modulator 100 is used to convert the input 16-bit digital data into a pulse width modulation PWM signal, including two dual 8-bit PWM modulation conversion channels, namely a high 8-bit PWM modulation conversion channel and a low 8-bit PWM modulation conversion channel, and the two channels have the same counting clock, reset control and register enable;
[0034] The input end of the high-low bit PWM quantizer 110 is respectively connected to the output end of the high 8-bit PWM modulation conversion channel and the low 8-bit PWM modulation conversion channel, and the output end of the high-low bit PWM quantizer 110 is connected to the signal input end of the second-order active low-pass filter 120.
[0035] According to the Fourier analysis of the general PWM signal, under steady-state conditions, the Fourier series of the PWM signal is as follows:
[0036]
[0037] Among them, A0 is the DC component, which is equal to the peak-to-peak amplitude Vp of the PWM rectangular pulse signal multiplied by the duty cycle (D), that is, A0=Vp*D, which represents the required DAC output.
[0038] The other higher-order terms in the equation, as the (n)-order harmonic components in the series, will cause errors in the final DAC conversion accuracy, and their magnitudes are as follows:
[0039]
[0040] When the duty cycle D = 0.5, the error introduced by the first-order harmonic is the largest: A1 = Vp / π.
[0041] In the filtering process of DAC, high-order harmonics can be suppressed by a high-order low-pass filter. Assuming an (m)-order low-pass filter with a cutoff frequency (f C ), the amplitude of the higher-order harmonics of the PWM rectangular wave will be suppressed to the first-order harmonic amplitude after filtering:
[0042] A1_lpf=A1*(fc / fp) ∧m
[0043] Most PWM signal generators can be controlled by a microcontroller using the system clock CLK. A counter counts and resets when a specified limit is reached to determine the PWM period and frequency.
[0044] Its duty cycle will be based on the weight of the number of bits of the input digital, and another level set by the register determines when the PWM output switches from a high level to a low level.
[0045] Based on the above design principle, the present invention proposes a simple 16-bit pulse width modulator 100, such as Figure 2 As shown, through Figure 3 The one-bit latch full adder 1001 shown in the figure can be cascaded to realize a PWM pulse width modulator with any resolution. For example, a 16-bit resolution PWM only needs to cascade 16 units of the one-bit latch full adder 1001, and the PWM cycle count is reset by connecting the overflow output pin of the highest bit count to the overflow input terminal of the lowest bit full adder.
[0046] The above-mentioned 16-bit pulse width modulator 100 has the following radiation frequency and minimum duty cycle characteristics:
[0047] Frequency: f P =f CLK / (2 ^N ), where f CLKis the system clock, N is the counting depth (in bit), and the counting depth required in the present invention should be 16 bits in principle;
[0048] Minimum duty cycle: D min =1 / (2 ^N ), which determines the minimum resolution of the DAC, but due to the residual harmonic components after filtering, the ripple of the output result will exceed this resolution, thereby reducing the effective bit (ENOB) of the DAC.
[0049] Based on the above description, the minimum resolution or ripple rate is defined as follows:
[0050]
[0051] Define relative filter bandwidth: BW = f C / f CLK .
[0052] The above minimum resolution is divided by the peak-to-peak value Vp of the PWM and normalized to obtain the effective number of bits (ENOB) of the PWM-DAC, as shown in the following equation:
[0053] ENOB S = -log(SR / V P ) / log(2)
[0054] in,
[0055] From the above analysis, we can know that if we want to meet the 16-bit resolution PWM-DAC, N = 16, assuming that the system clock f CLK =16MHz, f PWM =250Hz, after a third-order filter, the available bandwidth is less than 4Hz. Here, the actual limitations of the filter have not been considered. Therefore, the inherent limitations of the traditional PWM-DAC framework cannot reasonably balance wide bandwidth and high resolution in practical applications.
[0056] Based on the above limitations, a dual-channel PWM technology is proposed, which degrades the high-resolution design of 16-bit PWM into two 8-bit PWM processing channels (same counting clock, same peak-to-peak value, same channel resolution), converting high and low 8-bit digital codes respectively. Then, the output results of the two channels are quantized and ripple suppressed through the weighted superposition principle, such as Figure 1 The 16-bit PWM-DAC digital-to-analog conversion circuit shown.
[0057] Similarly, based on the above analysis, the total ripple rate of the dual-channel 16-bit PWM modulation DAC can be obtained as follows:
[0058]
[0059] Where, BW = f C / f CLK .
[0060] It should be noted that the denominator of the first term on the right side of the above equation has been changed to the traditional square, which has the effect of increasing the original bandwidth by 256 times (based on PWM-DAC at 16-bit resolution), that is, from 4Hz to 1KHz (assuming the counting clock frequency is 16MHz).
[0061] It should also be noted that, optionally, as an extension of the present embodiment, the above bandwidth enhancement principle can also be used to weightedly superimpose 4-channel 4-bit PWM into 16-bit PWM, and quantize and superimpose the digital codes of each channel according to the weights of the digital codes through the resistor network of the high and low bit PWM quantizer 110 to achieve the purpose of increasing the bandwidth.
[0062] See also Figure 2-Figure 3 In this embodiment, the basic unit constituting the high 8-bit PWM modulation conversion channel or the low 8-bit PWM modulation conversion channel is a one-bit latch full adder 1001, and the one-bit latch full adder 1001 is composed of two D flip-flops and a full adder;
[0063] The two D flip-flops are respectively an input-level D flip-flop and an intermediate-level D flip-flop. The input-level D flip-flop is used to latch and update the input single-bit digital. The control pin Dlat enables the update of the synchronous digital input pin D. The intermediate-level D flip-flop is used to count up according to the input code. The counting clock CK comes from the system clock.
[0064] The full adder is used to perform binary addition operation on the addition overflow code Ci from the low position and the counting code of the current position, and according to whether the current input digital number is logic "1", a system clock cycle is superimposed on the final pulse width after PWM modulation, that is, the pulse width of the output pin Co, thereby realizing the modification of the pulse width duty cycle of PWM modulation according to the digital weight.
[0065] In this embodiment, the storage state of any bit register of the channel is controllable, and the control of the data update Dlatch pin and the reset RST pin of the two channels are synchronously connected respectively. At the same time, the two channels are based on the same counting clock CK.
[0066] See also Figure 1-Figure 2In this embodiment, the duty cycle of the low 8-bit digital number after being modulated by the low 8-bit PWM modulation conversion channel is amplified 256 times relative to the pulse width modulation on the 16-bit principle. The output PWM signal is scaled by the high and low bit PWM quantizer 110 in proportion, and then superimposed with the PWM signal output by the high 8-bit digital number through the high 8-bit PWM modulation conversion channel to restore the equivalent 16-bit PWM pulse width modulation.
[0067] In the present application, the 16-bit pulse width modulator 100 mainly realizes dual-channel PWM modulation of the high and low 8-bit digital numbers of the input 16-bit digital number D<15:0>. In particular, the minimum resolution pulse width corresponding to the least significant bit updating of the traditional 16-bit single channel PWM needs 2 ^16 The system clock cycle Tclk is 50ns, that is, it takes 3.277ms for the lowest input digital bit to be updated to the PWM output response. With the same system clock, dual-channel modulation converts the high and low 8-bit digital bits in parallel, and the conversion time required for digital update output is only 12.8us, which reduces the update time by 256 times. The process of increasing the speed of dual-channel PWM conversion also amplifies the pulse width duty cycle of the low 8 bits by 256 times. Therefore, the high and low PWM quantizers 110 need to perform weighted superposition.
[0068] See also Figure 2 In this embodiment, the 16-bit pulse width modulator 100 is divided into 8 bits high and 8 bits low, respectively, which are latched into dual channels for synchronous parallel modulation conversion. The 16-bit pulse width modulator 100 outputs two high and low modulation signals, namely PWMH and PWML. The PWMH represents the output after the high 8-bit input is digitally modulated, and the PWML represents the output after the low 8-bit input is digitally modulated. The output characteristics of the PWMH and PWML are consistent, such as frequency, minimum duty cycle, etc. The two outputs are simultaneously input to the high and low PWM quantizers 110 for quantization superposition, and finally output VPWM. The VPWM is the final output of the 16-bit pulse width modulator 100, and the spectrum characteristics are consistent with the traditional 16-bit pulse width modulation, but the conversion speed is 256 times that of the traditional one;
[0069] For an 8-bit PWM modulation channel, just press the high and low bits of the input digital, and count the overflow from the low bit to the high bit, such as Figure 2 Cascading can be easily achieved;
[0070] The dual channels divide the 16-bit input digital D<15:0> into the upper 8 bits D<15:08> and the lower 8 bits D<7:0> for parallel modulation. From the output PWM modulation effect, it is equivalent to the duty cycle of the lower 8 bits being amplified 256 times.
[0071] See also Figure 4In this embodiment, the high-low bit PWM quantizer 110 includes two sets of logic buffers and resistor-capacitor networks to achieve high-low bit PWM quantization superposition and active ripple suppression;
[0072] Two groups of logic buffers are respectively connected to the upper 8-bit PWM modulation conversion channel and the lower 8-bit PWM modulation conversion channel, each group of logic buffers includes a plurality of logic inverters 1101, the resistor-capacitor network includes Rh, Rl, Rf, Cs and Cf, the two groups of logic buffers respectively differentiate the PWML and PWMH signals into two signals PWMLb and PWMHb, and use the reverse superposition of the signals to eliminate the DC component of the ripple, and then suppress part of the high-order harmonics through the band-pass filter formed by Rf and Cs and the low-pass filter formed by Rf and Cf, which is equivalent to the second-order active low-pass filter 120 of the output stage to introduce additional harmonic suppression poles, and realize the quantized superposition of the signals at the same time;
[0073] The high- and low-bit PWM quantizer 110 performs active ripple suppression on the PWMH to preliminarily suppress high-frequency ripples, which is equivalent to adding an additional noise reduction pole to the output-stage low-pass filter, thereby reducing the difficulty of designing the output-stage low-pass filter. For this embodiment, the output filter can use the general second-order active low-pass filter 120 to meet the design requirements.
[0074] See also Figure 2 and Figure 4 In this embodiment, the two groups of PWM signals output by the two dual 8-bit PWM modulation conversion channels are respectively connected in series with weight resistors Rh and Rl before being short-circuited. Rh represents the resistor connected in series with the high 8-bit PWM signal, and Rl represents the resistor connected in series with the low 8-bit PWM signal. The ratio relationship between the two is: Rl = 256*Rh. To meet 16-bit high precision, the resistance deviation of Rl or Rh should be controlled below 0.3%;
[0075] Before superimposing the PWM signals output by the two dual 8-bit PWM modulation conversion channels, the high-low PWM quantizer 110 first scales the PWM signal generated by the low 8-bit PWM modulation conversion channel by 256 times relative to the PWM signal generated by the high 8-bit PWM modulation conversion channel.
[0076] In the present application, after the high and low bits are converted in parallel, the 16-bit PWM conversion can be expanded to a 4-channel 4-bit PWM modulator parallel conversion through the weighted superposition principle. The conversion speed will be further improved, and the corresponding quantization superposition circuit will also reallocate the ratio weights of the resistors according to the channel duty cycle scaling multiple. The PWM signals output by different channels are scaled by the resistance ratio and then superimposed to achieve equivalent 16-bit pulse width modulation.
[0077] See also Figure 5 In this embodiment, the second-order active low-pass filter 120 includes an amplifier 1201, and the amplifier 1201 and the logic inverter 1101 are powered by the same driving power supply;
[0078] The DC component A0 of the PWM signal is Vp*D, where D is the duty cycle and Vp is the amplitude of the PWMH or PWML, which is derived from the driving power supply of the logic inverter 1101. Therefore, in order to improve the final accuracy of the digital-to-analog converter, the stability of the driving power supply should also be ensured. Similarly, the amplifier 1201 should also have the same stability. This embodiment is powered by the same driving power supply.
[0079] The second-order active low-pass filter 120 serves as the low-pass filter stage of the PWM-DAC, providing a simple second-order low-pass active filtering solution. A matching high-order harmonic suppression blocking frequency fc can be adjusted through a simple RC network, and the ripple peak-to-peak value of the analog output voltage of the final digital-to-analog conversion can be suppressed within the required minimum resolution voltage range, thereby achieving the high-resolution performance target of this application.
[0080] It should be noted that, as a complete DAC analog-to-digital conversion circuit, the circuit implementation part of this embodiment also includes the implementation of a low-pass filter. Optionally, the filter type can be a simple passive RC filter or an active filter. The above-mentioned second-order active low-pass filter 120 is used in the description of this embodiment to simply achieve the performance requirements of the circuit.
[0081] Similarly, based on the circuit implementation area of RC filtering, the area occupied by RC will be relatively large. In different usage scenarios, such as some signal conditioning circuits or sensor circuits, switched capacitors can also be considered for filtering.
[0082] An embodiment of the present invention further provides a digital-to-analog converter, comprising the 16-bit PWM-DAC digital-to-analog conversion circuit.
[0083] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor executes the circuit or digital-to-analog converter as described above.
[0084] See also Figure 6 An embodiment of the present invention further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the above-mentioned circuit or digital-to-analog converter.
[0085] It is understandable that the system, device and storage medium provided in the embodiments of the present invention correspond to the circuit or digital-to-analog converter provided in the embodiments of the present invention, and the explanation, examples and beneficial effects of the relevant contents can refer to the corresponding parts in the above-mentioned circuit or digital-to-analog converter.
[0086] In summary, the present invention provides a 16-bit PWM-DAC digital-to-analog conversion circuit, which can be implemented on a digital-to-analog converter. The 16-bit PWM-DAC digital-to-analog conversion circuit includes a 16-bit pulse width modulator, a high- and low-bit PWM quantizer, and a second-order active low-pass filter.
[0087] Among them, the 16-bit pulse width modulator converts the high and low 8-bit digital numbers input in parallel, and the required conversion speed is increased by 256 times compared with the traditional 16-bit PWM modulation conversion, which effectively improves the communication bandwidth of the signal; in order to improve the resolution of the conversion, a simple high and low-bit PWM quantizer and an active ripple suppression circuit are proposed to effectively control the ripple of the final output analog quantity and suppress it within the minimum resolution voltage range required for 16 bits, thereby realizing the high-resolution performance of the embodiment.
[0088] This embodiment, based on a thorough analysis of the inherent limitations of the traditional PWM-DAC, proposes a simple dual-channel conversion technology, combined with simple quantization and ripple suppression technology, to achieve a reasonable improvement in the speed and accuracy performance of this type of digital converter.
[0089] It should be understood that the examples and implementation modes described herein are for illustrative purposes only and are not intended to limit the present invention. Those skilled in the art may make various modifications or changes based on the examples and implementation modes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. 16-bit PWM-DAC digital-to-analog conversion circuit, characterized in that: It includes a 16-bit pulse width modulator (100), a high- and low-bit PWM quantizer (110), and a second-order active low-pass filter (120); The 16-bit pulse width modulator (100) is used to convert an input 16-bit digital number into a pulse width modulation (PWM) signal, and comprises two dual 8-bit PWM modulation conversion channels, namely a high 8-bit PWM modulation conversion channel and a low 8-bit PWM modulation conversion channel, wherein the two channels have the same counting clock, reset control and register enable; The input end of the high-low bit PWM quantizer (110) is respectively connected to the output end of the high 8-bit PWM modulation conversion channel and the low 8-bit PWM modulation conversion channel, and the output end of the high-low bit PWM quantizer (110) is connected to the signal input end of the second-order active low-pass filter (120).
2. The 16-bit PWM-DAC digital-to-analog conversion circuit according to claim 1, characterized in that: The basic unit constituting the high 8-bit PWM modulation conversion channel or the low 8-bit PWM modulation conversion channel is a one-bit latch full adder (1001), and the one-bit latch full adder (1001) is composed of two D flip-flops and a full adder; The two D flip-flops are respectively an input-level D flip-flop and an intermediate-level D flip-flop. The input-level D flip-flop is used to latch and update the input single-bit digital. The control pin Dlat enables the update of the synchronous digital input pin D. The intermediate-level D flip-flop is used to count up according to the input code. The counting clock CK comes from the system clock. The full adder is used to perform binary addition operation on the addition overflow code Ci from the low position and the counting code of the current position, and according to whether the current input digital number is logic "1", a system clock cycle is superimposed on the final PWM modulated pulse width, that is, the pulse width of the output pin Co, thereby realizing the modification of the PWM modulated pulse width duty cycle according to the digital weight.
3. The 16-bit PWM-DAC digital-to-analog conversion circuit according to claim 1, characterized in that: The duty cycle of the low 8-bit digital code after being modulated by the low 8-bit PWM modulation conversion channel is amplified by 256 times relative to the pulse width modulation on the 16-bit principle. The output PWM signal is scaled by the high and low bit PWM quantizer (110) in proportion to each other, and then superimposed with the PWM signal output by the high 8-bit digital code through the high 8-bit PWM modulation conversion channel to restore the equivalent 16-bit PWM pulse width modulation.
4. The 16-bit PWM-DAC digital-to-analog conversion circuit according to claim 1, characterized in that: The 16-bit pulse width modulator (100) is divided into high and low 8 bits, respectively, which are latched into dual channels for synchronous parallel modulation conversion. The 16-bit pulse width modulator (100) outputs two high and low modulation signals, namely PWMH and PWML. The PWMH represents the output after the high 8-bit input is digitally modulated, and the PWML represents the output after the low 8-bit input is digitally modulated. The output characteristics of the PWMH and PWML are consistent. The two outputs are simultaneously input into the high and low PWM quantizers (110) for quantization and superposition, and finally output VPWM, which is the final output of the 16-bit pulse width modulator (100).
5. The 16-bit PWM-DAC digital-to-analog conversion circuit according to claim 4, characterized in that: The high-low bit PWM quantizer (110) comprises two groups of logic buffers and a resistor-capacitor network. The two groups of logic buffers are respectively connected to the high 8-bit PWM modulation conversion channel and the low 8-bit PWM modulation conversion channel. Each group of logic buffers comprises a plurality of logic inverters (1101). The resistor-capacitor network comprises Rh, Rl, Rf, Cs and Cf. The two groups of logic buffers respectively differentiate the PWML and PWMH signals into two signals, PWMLb and PWMHb. The reverse superposition of the signals is used to eliminate the DC component of the ripple. The bandpass filter formed by Rf and Cs and the low-pass filter formed by Rf and Cf are used to suppress part of the high-order harmonics. The second-order active low-pass filter (120) which is equivalent to the output stage introduces additional harmonic suppression poles, and simultaneously realizes the quantization superposition of the signals.
6. The 16-bit PWM-DAC digital-to-analog conversion circuit according to claim 1, characterized in that: The two groups of PWM signals output by the two dual 8-bit PWM modulation conversion channels are respectively connected in series with weighted resistors Rh and Rl before short-circuiting. Rh represents the resistance connected in series with the high 8-bit PWM signal, and Rl represents the resistance connected in series with the low 8-bit PWM signal. The ratio between the two is: Rl=256*Rh.
7. The 16-bit PWM-DAC digital-to-analog conversion circuit according to claim 5, characterized in that: The second-order active low-pass filter (120) comprises an amplifier (1201), and the amplifier (1201) and the logic inverter (1101) are powered by the same driving power supply.
8. A digital-to-analog converter, characterized in that It comprises a 16-bit PWM-DAC digital-to-analog conversion circuit as claimed in any one of claims 1 to 7.