Coding method and device, computer equipment and storage medium
By using encoding lookup table instead of encoding operation in dual binary turbo encoding, the problem of high complexity of turbo encoding calculation is solved, and a more efficient encoding process is achieved, suitable for real-time communication systems and reduce resource consumption.
Patent Information
- Application Number
- CN202411259892.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2024-12-27
AI Technical Summary
Dual binary turbo encoding has high computational complexity in high-speed data transmission scenarios, resulting in increased latency, unable to meet the needs of real-time communication systems, and has high power consumption and hardware costs for resource-constrained devices.
Through the pre-configured encoding lookup table, the target verification bit pair is queried based on the target register status and information to be encoded, instead of encoding operation, simplifying the encoding process and improving encoding efficiency.
It greatly reduces the computational complexity and delay of encoding, improves encoding efficiency, is suitable for real-time communication systems, and reduces resource consumption.
Smart Images
Figure CN119210471A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular, to a coding method, apparatus, computer device and storage medium. Background Art
[0002] Currently, duobinary turbo coding is an efficient forward error correction coding technology widely used in communication systems to improve the reliability of data transmission. The core idea of turbo coding is to increase the redundancy of the coding by cascading two or more encoders in parallel, combined with an interleaver, so that the errors that may be introduced during the transmission process can be corrected more effectively at the receiving end. In the context of duobinary turbo coding, the component encoder is usually each of the two or more encoders that constitute the turbo encoder.
[0003] In turbo coding, each component encoder usually generates a check bit pair by performing a modulo-2 addition operation (i.e., XOR operation) on the input bit stream and the contents of the shift register based on a recursive systematic convolutional code. Specifically, each bit of the input bit stream is XORed with the bit at the corresponding position in the component encoder's shift register, and the generated bit is output as the check bit. This process is performed according to the encoder's generating polynomial and the length of the register.
[0004] However, since each input bit needs to be XORed with multiple bits in the shift register, this results in high computational complexity. In high-speed data transmission scenarios, this computational complexity will significantly increase the encoding delay and may not meet the needs of real-time communication systems. In addition, for resource-constrained devices, such as mobile devices or low-power devices, this high computational complexity will also bring additional power consumption and hardware costs.
[0005] Meanwhile, digital signal processors are often used to process high-speed data streams, such as audio and video encoding / decoding. The architecture of digital signal processors optimizes the efficient execution of specific types of calculations, such as fast Fourier transforms and digital filtering. However, the complexity and latency characteristics of turbo coding may not match the efficient processing capabilities of digital signal processors, especially in scenarios that require real-time processing. The hardware resources of digital signal processors may not be sufficient to support the highly complex turbo coding algorithm, resulting in low coding efficiency. Summary of the invention
[0006] The embodiments of the present application provide a coding method, apparatus, computer device and storage medium.
[0007] A first aspect of an embodiment of the present application provides an encoding method, comprising:
[0008] Acquire target information to be encoded, and determine a target register state of a component encoder where the target information to be encoded is located;
[0009] Determine, according to the target register state, a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables; wherein each of the encoding lookup tables is constructed according to the information to be encoded, the register state and a check bit pair corresponding to the information to be encoded;
[0010] Determine a target check bit pair corresponding to the target information to be encoded from the target encoding lookup table based on the target information to be encoded;
[0011] An encoding result of the target information to be encoded is determined based on the target check bit pair.
[0012] In an optional embodiment of the present application, the process of constructing the encoding lookup table includes the following steps:
[0013] determining different first register states according to the historical states of each register in the component encoder;
[0014] Determining different first information to be encoded according to the historical information to be encoded;
[0015] Inputting each of the first register states and each of the first information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded;
[0016] For each state of the first register, a first coding lookup table is constructed according to each pair of the first information to be encoded and the corresponding first check bit.
[0017] In an optional embodiment of the present application, the step of inputting each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded includes:
[0018] Inputting each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial to obtain a second register state;
[0019] The second register state is input into a pre-configured first output polynomial and a pre-configured second output polynomial respectively to obtain the first check bit pair corresponding to each of the first information to be encoded.
[0020] In an optional embodiment of the present application, after determining different first information to be encoded according to the historical information to be encoded, the method further includes:
[0021] Interleaving each of the first information to be encoded to obtain second information to be encoded corresponding to each of the first information to be encoded;
[0022] Inputting each of the first register states and each of the second information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a second check bit pair corresponding to each of the first information to be encoded;
[0023] For each state of the first register, a second encoding lookup table is constructed according to each pair of the first information to be encoded and the corresponding second check bit.
[0024] In an optional embodiment of the present application, determining a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables according to the target register state includes:
[0025] According to the target register state, a first target encoding lookup table and a second target encoding lookup table corresponding to the target register state are determined from a plurality of pre-configured first encoding lookup tables and second encoding lookup tables respectively.
[0026] In an optional embodiment of the present application, the first information to be encoded is a combination of information bit pairs, and the inputting of each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded includes:
[0027] For each of the information bit pair combinations, obtaining a first group of information bit pairs of the current information bit pair combination, inputting the first group of information bit pairs and the current first register state into a pre-configured feedback branch polynomial to obtain a third register state;
[0028] Inputting the third register state into a preconfigured output polynomial to obtain a third check bit pair corresponding to the first group of information bit pairs, and updating the current first register state to the third register state;
[0029] For the remaining groups of information bit pairs in the current information bit pair combination, the steps of obtaining the corresponding third check bit pairs and updating the current first register state are performed, and the third check bit pairs corresponding to each group of information bit pairs in the current information bit pair combination are combined to form a first check bit pair corresponding to the current information bit pair combination.
[0030] In an optional embodiment of the present application, the method further includes:
[0031] The current first register state updated by the last group of information bit pairs in the current information bit pair combination is used as a fourth register state corresponding to the current information bit pair combination, wherein the fourth register state is used to cooperate with the new information bit pair combination to generate a new first check bit pair.
[0032] A second aspect of the embodiments of the present application provides an encoding device, including:
[0033] An acquisition module, used for acquiring target information to be encoded, and determining a target register state of a component encoder where the target information to be encoded is located;
[0034] A first determination module is used to determine a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables according to the target register state; wherein each encoding lookup table is constructed according to information to be encoded, a register state and a check bit pair corresponding to the information to be encoded;
[0035] A second determination module is used to determine a target check bit pair corresponding to the target information to be encoded from the target encoding lookup table based on the target information to be encoded;
[0036] The third determination module is used to determine the encoding result of the target information to be encoded based on the target check bit pair.
[0037] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above encoding methods when executing the computer program.
[0038] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, characterized in that when the computer program is executed by a processor, the steps of any of the above encoding methods are implemented.
[0039] The above technical solution provided by the embodiment of the present application has at least some or all of the following advantages compared with the prior art:
[0040] The encoding method described in the embodiment of the present application obtains target information to be encoded, and determines the target register state of the component encoder where the target information to be encoded is located; determines the target encoding lookup table corresponding to the target register state from multiple pre-configured encoding lookup tables according to the target register state; wherein each of the encoding lookup tables is constructed according to the information to be encoded, the register state and the check bit pair corresponding to the information to be encoded; determines the target check bit pair corresponding to the target information to be encoded from the target encoding lookup table based on the target information to be encoded; determines the encoding result of the target information to be encoded based on the target check bit pair, and can construct a encoding lookup table in advance according to each of the information to be encoded and the check bit pair under each of the register states, so that in the actual encoding process, the encoding lookup table can be queried according to the current register state and the current information to be encoded to obtain the check bit pair corresponding to the current information to be encoded, and the encoding operation is replaced by the table lookup method, thereby eliminating the encoding operation of the current information to be encoded, thereby greatly improving the encoding efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0042] Figure 1 A flowchart of an encoding method provided for one embodiment of the present application;
[0043] Figure 2 A flowchart of step 200 in the encoding method provided in one embodiment of the present application;
[0044] Figure 3 A flowchart of step 230 in the encoding method provided in one embodiment of the present application;
[0045] Figure 4 A schematic diagram of the structure of a duo-binary turbo encoder in a digital video broadcast satellite return channel protocol provided by one embodiment of the present application;
[0046] Figure 5 A schematic diagram of the structure of a component encoder provided by an embodiment of the present application;
[0047] Figure 6 A schematic diagram of an encoding method provided for one embodiment of the present application;
[0048] Figure 7 A schematic diagram of a device structure provided for an embodiment of the present application;
[0049] Figure 8 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION
[0050] In the process of implementing the present application, the inventors found that the current encoding method has a large amount of computation and a long encoding time.
[0051] In response to the above problems, an encoding method, apparatus, computer device and storage medium are provided in the embodiments of the present application. By looking up a table, the target check bit pair corresponding to the information to be encoded is obtained, thereby eliminating the encoding operation process and improving the encoding efficiency.
[0052] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.
[0053] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0054] See also Figure 1 The encoding method provided in the embodiment of the present application includes the following steps 100 to 400:
[0055] Step 100: Acquire target information to be encoded, and determine a target register state of a component encoder where the target information to be encoded is located.
[0056] The target information to be encoded is the original data to be sent to the channel in the communication system. The target information to be encoded can be text, image, audio or video data, which needs to be encoded before transmission to adapt to the characteristics of the channel and ensure reliable transmission of data. The encoding process may include quantization, channel coding, encryption and other steps, aiming to reduce transmission errors, protect data privacy or improve data transmission efficiency.
[0057] The component encoder is used to encode the target information to be encoded to increase the redundancy of the data. This redundancy can help the receiving end detect and correct errors in a channel with noise or other interference, thereby improving the reliability of data transmission.
[0058] In a component encoder, the target register state is the current value of the data or information stored in the register at a specified time. When processing the target information to be encoded, the target register state is updated according to the rules and algorithms of the component encoder. The target register state ensures the accuracy of the encoding process and the reliability of the encoded output.
[0059] Step 200: Determine a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables according to the target register state; wherein each encoding lookup table is constructed based on information to be encoded, a register state and a check bit pair corresponding to the information to be encoded.
[0060] Among them, one target register state corresponds to at least one target coding lookup table, that is, one target register state can correspond to one target coding lookup table or multiple target coding lookup tables. In essence, the number of target coding lookup tables corresponding to one target register state depends on the number of check bit pairs outputted corresponding to a target information to be encoded.
[0061] Step 300: Determine a target check bit pair corresponding to the target information to be encoded from the target encoding lookup table based on the target information to be encoded.
[0062] Among them, based on the correspondence between the information to be encoded and the check bit pair in the target coding lookup table, the target information to be encoded is used as the search index of the target coding lookup table to obtain the target check bit pair corresponding to the information to be encoded.
[0063] Step 400: Determine the encoding result of the target information to be encoded based on the target check bit pair.
[0064] The target check bit pair is a part of the output of the coding algorithm. The coding algorithm combines the target information to be encoded with the target check bit pair according to a specific coding rule and structure to form an encoded codeword as a coding result.
[0065] The encoding method of the present application determines the target encoding lookup table according to the target register state, and then determines the target check bit pair corresponding to the target information to be encoded from the target encoding lookup table according to the target information to be encoded. The encoding operation process is replaced by table lookup, thereby eliminating the encoding operation process and improving the encoding efficiency.
[0066] In an optional embodiment of the present application, see Figure 2 In the above step 200, the process of constructing the encoding lookup table includes the following steps 210-240:
[0067] Step 210: Determine different first register states according to the historical states of the registers of the component encoder.
[0068] The number of registers in the component encoder is determined by the encoding rule. Assuming that the number of registers is n, each register has only two states, 0 and 1, and all possible register states are 2 nThe number of encoding lookup tables that a component encoder needs to generate is 2 n When n is 2, the register states include the following four types: [0,0], [0,1], [1,0], and [1,1].
[0069] Step 220: Determine different first information to be encoded according to the historical information to be encoded.
[0070] Wherein, in the case where the first information to be encoded is an information bit pair, when the number of information bit pairs is N, there are a total of 2 possible information bit pairs. 2N That is, if N is 4, the possible information bit pairs are [01 11 10 10], a total of 8 bits, and all possible information bit pairs are 2 8 kind.
[0071] Step 230: Input each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded.
[0072] Step 240: For each state of the first register, construct a first coding lookup table according to each first information to be coded and the corresponding first check bit pair. The first coding lookup table is constructed according to the correspondence between the first information to be coded and the first check bit pair in the first register state.
[0073] The present application pre-encodes each possible information to be encoded under all possible register states to obtain the check bit pairs corresponding to each information to be encoded under each register state, and constructs a coding lookup table according to each information to be encoded and the check bit pairs under each register state, so that in the actual coding process, the coding lookup table can be queried according to the current register state and the current information to be encoded to obtain the check bit pairs corresponding to the current information to be encoded, and the table lookup is used instead of the coding operation to achieve the purpose of fast coding speed and high efficiency.
[0074] In an optional embodiment of the present application, see Figure 3 Step 230, inputting each of the first register states and each of the first information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded, includes steps 231-232:
[0075] Step 231: Input each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial to obtain a second register state.
[0076] Step 232: Input the second register state into a pre-configured first output polynomial and a pre-configured second output polynomial respectively to obtain a first check bit pair corresponding to each of the first information to be encoded.
[0077] by Figure 4 Taking the dual binary turbo encoder in the digital video broadcast satellite return channel protocol as an example, the component encoder uses a dual binary cyclic recursive systematic convolutional code, and the feedback branch polynomial is g(x)=1+x 3 +x 4 , the first output polynomial is f 1 (x) = 1 + x + x 2 +x 4 , the second output polynomial f 2 (x) = 1 + x 2 +x 3 +x 4 , where the component encoder structure is as follows Figure 5 As shown, the number of shift registers is 4.
[0078] When the first information to be encoded is an information bit pair (A 0 ,B 0 ), the process of encoding by the component encoder 1 comprises the following steps:
[0079] Initialize registers: Ensure that the registers are initially set to zero. 1 ,S 2 ,S 3 ,S 4 ]=[0,0,0,0].
[0080] Input information bit pair (A 0 ,B 0 ): A 0 ,B 0 As input, it is fed into component encoder 1.
[0081] Apply feedback polynomial: Use the specified feedback branch polynomial g(x)=1+x 3 +x 4 , calculate the second register state according to the current first register state and the input information bit pair.
[0082] Generate check bit Y 0 :Apply the first output polynomial f 1 (x) = 1 + x + x 2 +x 4 , based on the second register state, calculate the check bit Y 0 .
[0083] Generate check bits W0 : Use the second output polynomial f 2 (x) = 1 + x 2 +x 3 +x 4 , based on the second register state, calculate the check bit W 0 .
[0084] Update register state: based on the second register state, update the first register state to prepare for the next input of the information bit pair.
[0085] Output check bit pair (Y 0 ,W 0 ): The calculated check bit pair (Y 0 ,W 0 ) as the first check bit pair.
[0086] The present application applies feedback polynomials and output polynomials to ensure the accuracy of the encoding results and the reliability of data transmission. After outputting the check bit pair, the second register state will be used for encoding subsequent information bit pairs to form a continuous encoding process.
[0087] In an optional embodiment of the present application, after determining different first information to be encoded according to the historical information to be encoded, the method further includes:
[0088] Interleaving is performed on each of the first information to be encoded to obtain second information to be encoded corresponding to each of the information to be encoded. Interleaving is performed on each of the first information to be encoded to improve the anti-interference capability of the system by rearranging the bit sequence of the first information to be encoded.
[0089] Input each of the first register states and each of the second information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a second check bit pair corresponding to each of the first information to be encoded. The second information to be encoded is encoded to obtain a second check bit pair, which further increases data redundancy to cope with potential transmission errors.
[0090] For each of the first register states, a second coding lookup table is constructed according to each of the first information to be coded and the corresponding second check bit pairs. The second coding lookup table is constructed according to the correspondence between the first information to be coded and the second check bit pairs in the first register state.
[0091] by Figure 4 As an example, the dual binary turbo encoder in the digital video broadcast satellite return channel protocol shown in FIG. 1 is used, the first information to be encoded may be N pairs of information bit pairs, denoted as [(A 0 ,B0 ),(A 1 ,B 1 ),…,(A N ,B N )], N is a multiple of 4, and each time an information bit pair is input (A n ,B n ), (A n ,B n ) is sent to component encoder 1 for encoding, and the check bit pair (Y1 n ,W1 n ), the input information bit pair (A n ,B n ) is interleaved by the interleaver and sent to the component encoder 2 for encoding to obtain the check bit pair (Y2 n ,W2 n ), and then check the bit pair (Y1 n ,W1 n ) and (Y2 n ,W2 n ) After puncturing, the target bit rate code is output as the encoding result.
[0092] The present application constructs a first coding lookup table and a second coding lookup table to obtain the correspondence between the first information to be encoded and the first check bit pair and the second check bit pair, so that in the actual encoding process, the first check bit pair and the second check bit pair can be obtained only by looking up the table of the target information to be encoded, which is equivalent to performing two rounds of encoding and interleaving on the information to be encoded, and can effectively combat random and burst errors in the channel, ensure that the receiving end can accurately restore the original data, and improve the efficiency and reliability of data transmission.
[0093] In an optional embodiment of the present application, step 200, determining a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables according to the target register state, includes:
[0094] According to the target register state, a first target encoding lookup table and a second target encoding lookup table corresponding to the target register state are determined from a plurality of pre-configured first encoding lookup tables and second encoding lookup tables, wherein the number of the target encoding lookup tables is consistent with the number of the component encoders.
[0095] The present application determines the first target coding lookup table and the second target coding lookup table according to the target register state, so as to query the first check bit pair and the second check bit pair from the first target coding lookup table and the second target coding respectively according to the target information to be encoded, which is equivalent to encoding the information to be encoded in component encoder 1, and first interleaving the information to be encoded and then encoding it in component encoder 2. While simplifying the encoding process of the target information to be encoded, it can also improve the accuracy of data transmission.
[0096] In an optional embodiment of the present application, the first information to be encoded is a combination of information bit pairs, and step 230, inputting each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded, includes:
[0097] For each of the information bit pair combinations, a first group of information bit pairs of the current information bit pair combination is obtained, and the first group of information bit pairs and the current first register state are input into a pre-configured feedback branch polynomial to obtain a second register state, wherein the number of the information bit pairs determines the depth of each coding lookup table, and when the number of information bit pairs is N, the depth of the coding lookup table is 2 2N .
[0098] The second register state is input into a preconfigured output polynomial to obtain a third check bit pair corresponding to the first group of information bit pairs, and the current first register state is updated to the second register state.
[0099] For the remaining groups of information bit pairs in the current information bit pair combination, the steps of obtaining the corresponding third check bit pairs and updating the current first register state are performed, and the third check bit pairs corresponding to each group of information bit pairs in the current information bit pair combination are combined to form a first check bit pair corresponding to the current information bit pair combination.
[0100] The initial state of the register is zero, that is, [S 1 ,S 2 ,S 3 ,S 4 ]=[0,0,0,0], and the first information to be encoded is an information bit pair combination [(A 0 ,B 0 ),(A 1 ,B 1 ),(A 2 ,B 2 ),(A 3 ,B 3 )] as an example, the following steps are used to combine information bits [(A0 ,B 0 ),(A 1 ,B 1 ),(A 2 ,B 2 ),(A 3 ,B 3 )] corresponding to the first check bit pair:
[0101] [S 1 ,S 2 ,S 3 ,S 4 ]=[0,0,0,0] and the first group of information bit pairs (A 0 ,B 0 ) is input into the component encoder 1 for encoding, and the first group of check bit pairs (Y) corresponding to the first group of information bit pairs are calculated according to the feedback polynomial and the output polynomial. 0 ,W 0 ). and update the status of the register.
[0102] For the remaining information bit pairs (A 1 ,B 1 ),(A 2 ,B 2 ),(A 3 ,B 3 ) Repeat the above steps in sequence, and update the check bit pair (Y 1 ,W 1 ), (Y 2 ,W 2 ), (Y 3 ,W 3 ) and the status of the registers.
[0103] When all information bit pairs are encoded, the final register state is recorded as [S 1 ',S 2 ',S 3 ',S 4 ']. This indicates that the encoding process is complete, and the first check bit pair and the final register state obtained are [(Y 0 ,W 0 ), (Y 1 ,W 1 ), (Y 2 ,W 2 ), (Y 3 ,W 3 )][S 1 ',S 2 ',S 3 ',S 4 '].
[0104] The present application combines input information bit pairs and generates a coding lookup table based on the relationship between the input information bit pairs and register states and the output check bit pairs derived from the component encoder generating polynomial. For the information bit pair combinations containing multiple groups of input information bit pairs, the corresponding multiple groups of output check bit pairs are obtained by looking up the table. This not only saves the encoding calculation process, but also realizes parallel encoding of multiple groups of bit pairs, thereby improving encoding efficiency.
[0105] In an optional embodiment of the present application, the method further includes:
[0106] The current first register state updated by the last group of information bit pairs of the current information bit pair combination is used as a fourth register state corresponding to the current information bit pair combination, wherein the fourth register state is used to cooperate with a new information bit pair combination to generate a new first check bit pair.
[0107] See also Figure 6 , when the number of registers is 4 and the input information bit pair combination is 8, the register state [S 1 ,S 2 ,S 3 ,S 4 ] is traversed as [0,0,0,0], [0,0,0,1], …, [1,1,1,1], which are recorded as 0, 1, 2, …, 15 respectively. Each register state corresponds to a coding lookup table; the number of registers determines the number of coding lookup tables.
[0108] Set the register to the initial state of 0, that is, [S 1 ,S 2 ,S 3 ,S 4 ]=[0,0,0,0], input the information bit pair combination to be encoded [(A 0 ,B 0 ),(A 1 ,B 1 ),(A 2 ,B 2 ),(A 3 ,B 3 )], complete the encoding of the four information bit pairs, and obtain the check bit pair and register status [(Y 0 ,W 0 ), (Y 1 ,W 1 ), (Y 2 ,W 2 ), (Y 3 ,W 3 )][S 1 ',S 2 ',S 3 ',S4 '], traverse the input from [(0,0), (0,0), (0,0), (0,0)] to [(1,1), (1,1), (1,1), (1,1)], a total of 2 8 The value is recorded as 0 to 255 as the input index, corresponding to 256 groups of outputs, and a 256*12-bit encoding lookup table is obtained, recorded as encoding lookup table LUT[0]. Each input index corresponds to a group of 12-bit outputs, the first 8 bits are used as the output check bit sequence, and the last 4 bits are used as the encoded register state.
[0109] Traverse the register status from 0 to 15, repeat the operation in the previous step, and obtain a total of 15 lookup tables, represented as LUT[0] to LUT
[15] .
[0110] When the register state is [0,0,0,0], the encoding lookup table LUT[0] can be as shown in Table 1 below.
[0111] Table 1
[0112]
[0113] When the register state is [0, 0, 0, 1], the encoding lookup table LUT[1] can be as shown in Table 2 below.
[0114] Table 2
[0115]
[0116] When the register state is [1,1,1,1], the encoding lookup table LUT
[15] can be as shown in Table 3 below.
[0117] Table 3
[0118]
[0119] There are 16 lookup tables in total, one-to-one corresponding to all possible register states (the number of registers is 4, so there are 16 states in total). The number of indexes of the input and output of the encoding lookup table is related to the number of bit pairs of parallel encoding. The number of parallel bit pairs is N, and the number of traversing all inputs is 2 2N , N = 4, then the number of indexes is 2 8 The output of the coding lookup table is N groups of check bit pairs and S end , S end =[S 1 ',S 2 ',S 3 ',S 4 '].
[0120] Input 4 pairs of information bits [(A 0 ,B0 ),(A 1 ,B 1 ),(A 2 ,B 2 ),(A 3 ,B 3 )], and the register status S before the current encoding start , S start =[S 1 ,S 2 ,S 3 ,S 4 ].
[0121] By S start The value of is used as the lookup table index s to obtain the target encoding lookup table LUT[s].
[0122] Input information bit pair [(A 0 ,B 0 ),(A 1 ,B 1 ),(A 2 ,B 2 ),(A 3 ,B 3 )] as the search index, and obtain the output corresponding to the index of the target encoding lookup table LUT[s] [(Y 0 ,W 0 ), (Y 1 ,W 1 ), (Y 2 ,W 2 ), (Y 3 ,W 3 )][S 1 ',S 2 ',S 3 ',S 4 '].
[0123] [S 1 ',S 2 ',S 3 ',S 4 '] as the S of the next moment start , repeat the above process for the next group of 4 pairs of information bits until all information bit pairs are encoded.
[0124] The present application ensures accurate encoding of input information bit pairs by setting the register initial state to zero, while maintaining the consistency and systematicness of the encoding process by updating the register state, and provides necessary data for subsequent interleaving and transmission by providing information bit pairs, check bit pairs, and the register state at the end of encoding.
[0125] In an optional embodiment of the present application, the target coding information may be stored in the form of a symmetric triangular matrix. Correspondingly, the target coding information in the form of a symmetric triangular matrix may be processed as follows:
[0126] For each iterative calculation in the reflection transformation of the target symmetric matrix, determining a first target matrix operation expression for the current iterative calculation;
[0127] Converting the first target matrix operation into a second target matrix operation expression, wherein the variables of the second target matrix operation expression include the target symmetric matrix, a preset transformation matrix column vector, and a preset process calculation column vector;
[0128] Dividing the target symmetric matrix into a plurality of target vectors;
[0129] Each of the target vectors is stored in a different single core in the processor respectively, and the target elements corresponding to each of the target vectors in the preset transformation matrix column vector and the preset process calculation column vector are stored in the single core corresponding to the target vector; in the different single cores, each of the target vectors and the target elements is operated in parallel according to the second target matrix operation expression, and the matrix composed of the results of the different single core operations is used as the result of the current iterative calculation.
[0130] In an optional embodiment of the present application, the second target matrix operation expression includes: a first multiplication operation between the preset transformation matrix column vector and the conjugate transpose of the preset process calculation column vector; a second multiplication operation between the preset process calculation column vector and the conjugate transpose of the preset transformation matrix column vector; and a subtraction operation between the target symmetric matrix and the first multiplication operation result and the second multiplication operation result.
[0131] In an optional embodiment of the present application, in the different single cores, performing parallel operations on each of the target vectors and the target elements according to the second target matrix operation expression includes:
[0132] For each target vector in a single core, the following computations are performed in parallel:
[0133] Determine the first calculation element vectors in the preset transformation matrix column vector corresponding to the current target vector, the second calculation element vectors in the conjugate transpose of the preset transformation matrix column vector corresponding to the current target vector, the third calculation element vectors in the preset process calculation column vector corresponding to the current target vector, and the fourth calculation element vectors in the conjugate transpose of the preset process calculation column vector corresponding to the current target vector;
[0134] Performing a multiplication operation on the first calculation element vector and the fourth calculation element vector to obtain a first multiplication operation matrix;
[0135] Performing a multiplication operation on the third calculation element vector and the second calculation element vector to obtain a second multiplication operation matrix;
[0136] The current target vector performs a subtraction operation on the first multiplication operation matrix and the second multiplication operation matrix to obtain a result of the current single-core operation.
[0137] In an optional embodiment of the present application, when the target vector is a row vector, determining the first calculation element vectors in the preset transformation matrix column vector corresponding to the current target vector, the second calculation element vectors in the conjugate transpose of the preset transformation matrix column vector corresponding to the current target vector, the third calculation element vectors in the preset process calculation column vector corresponding to the current target vector, and the fourth calculation element vectors in the conjugate transpose of the preset process calculation column vector corresponding to the current target vector, includes:
[0138] In the case where the current target vector is a vector composed of elements of the nth row of the target symmetric matrix, the first calculated element vector includes the nth element in the preset transformation matrix column vector; the second calculated element vector includes the nth element to the last element in the conjugate transpose of the preset transformation matrix column vector; the third calculated element vector includes the nth element in the preset process calculation column vector; and the fourth calculated element vector includes the nth element to the last element in the conjugate transpose of the preset process calculation column vector.
[0139] In an optional embodiment of the present application, when the target vector is a column vector, the process of determining the target elements in the preset transformation matrix column vector and the preset process calculation column vector respectively corresponding to the current target vector includes:
[0140] In the case where the current target vector is a vector composed of the elements of the nth column of the target symmetric matrix, the first calculation element vector includes the nth element to the last element in the preset transformation matrix column vector; the second calculation element vector includes the nth element in the conjugate transpose of the preset transformation matrix column vector; the third calculation element vector includes the nth element to the last element in the preset process calculation column vector; and the fourth calculation element vector includes the nth element in the conjugate transpose of the preset process calculation column vector.
[0141] In an optional embodiment of the present application, it also includes:
[0142] Determining, according to the number of the single cores and the order of the target alignment matrix, the target vector corresponding to the single core for each iteration calculation;
[0143] When the number of the single cores is less than the order of the target alignment matrix, the number of the target vectors corresponding to the single cores calculated in each iteration exceeds one.
[0144] In an optional embodiment of the present application, it also includes:
[0145] While performing parallel operations on the target vectors and the target elements, a next target vector corresponding to a next operation in the single core is determined, and the next target vector is stored in the single core.
[0146] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
[0147] See also Figure 7 , an embodiment of the present application provides a coding device 700, including:
[0148] An acquisition module 710 is used to acquire target information to be encoded and determine a target register state of a component encoder where the target information to be encoded is located;
[0149] A first determination module 720 is used to determine a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables according to the target register state; wherein each encoding lookup table is constructed according to information to be encoded, a register state and a check bit pair corresponding to the information to be encoded;
[0150] A second determination module 730 is used to determine a target check bit pair corresponding to the target information to be encoded from the target encoding lookup table based on the target information to be encoded;
[0151] The third determination module 740 is configured to determine the encoding result of the target information to be encoded based on the target check bit pair.
[0152] In an optional embodiment of the present application, in the first determination module, the process of constructing the encoding lookup table includes the following steps:
[0153] determining different first register states according to the historical states of the registers of the component encoder;
[0154] Determining different first information to be encoded according to the historical information to be encoded;
[0155] Inputting each of the first register states and each of the first information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded;
[0156] For each state of the first register, a first coding lookup table is constructed according to each pair of the first information to be encoded and the corresponding first check bit.
[0157] In an optional embodiment of the present application, the first determining module is further configured to:
[0158] Inputting each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial to obtain a second register state;
[0159] The second register state is input into a pre-configured first output polynomial and a pre-configured second output polynomial respectively to obtain a first check bit pair corresponding to each of the first information to be encoded.
[0160] In an optional embodiment of the present application, the first determining module is further configured to:
[0161] Interleaving each of the first information to be encoded to obtain second information to be encoded corresponding to each of the first information to be encoded;
[0162] Inputting each of the first register states and each of the second information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a second check bit pair corresponding to each of the first information to be encoded;
[0163] For each state of the first register, a second encoding lookup table is constructed according to each pair of the first information to be encoded and the corresponding second check bit.
[0164] In an optional embodiment of the present application, the first determining module is further configured to:
[0165] According to the target register state, a first target encoding lookup table and a second target encoding lookup table corresponding to the target register state are determined from a plurality of pre-configured first encoding lookup tables and second encoding lookup tables respectively.
[0166] In an optional embodiment of the present application, the information to be encoded is a combination of information bit pairs, and the first determining module is further used to:
[0167] For each of the information bit pair combinations, obtaining a first group of information bit pairs of the current information bit pair combination, inputting the first group of information bit pairs and the current first register state into a pre-configured feedback branch polynomial to obtain a third register state;
[0168] Inputting the third register state into a preconfigured output polynomial to obtain a third check bit pair corresponding to the first group of information bit pairs, and updating the current first register state to the third register state;
[0169] For the remaining groups of information bit pairs in the current information bit pair combination, the steps of obtaining the corresponding third check bit pairs and updating the current first register state are performed, and the third check bit pairs corresponding to each group of information bit pairs in the current information bit pair combination are combined to form a first check bit pair corresponding to the current information bit pair combination.
[0170] In an optional embodiment of the present application, the first determining module is further configured to:
[0171] The current first register state updated by the last group of information bit pairs of the current information bit pair combination is used as a fourth register state corresponding to the current information bit pair combination, wherein the fourth register state is used to cooperate with a new information bit pair combination to generate a new first check bit pair.
[0172] The encoding device of the present application first traverses the input first information bit pair combination to be encoded and the initial state of the register before encoding according to the generating polynomial of the component encoder, and obtains the output check bit pair combination of the dimension of the input traversal number multiplied by the initial state traversal number. Each group of input and the initial state of the register corresponds to a unique group of output check bit pair combinations, and a coding lookup table is generated based on this correspondence, so that the encoding process of the component encoder is to input a group of information bit pair combinations of the current node parallel encoding number and the initial state of the register of the node, and the output check bit pair combination and the register state after the encoding are completed can be confirmed by the table lookup method, thereby achieving the purpose of eliminating the calculation of the encoding process and high encoding efficiency of parallel encoding.
[0173] For the specific definition of the above-mentioned device 700, please refer to the definition of the encoding method above, which will not be repeated here. Each module in the above-mentioned device 700 can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.
[0174] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 8 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a coding method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the coding method as described above is implemented.
[0175] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above encoding method can be implemented.
[0176] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0177] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0178] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0179] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0180] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0181] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A coding method, characterized in that: include: Acquire target information to be encoded, and determine a target register state of a component encoder where the target information to be encoded is located; Determine, according to the target register state, a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables; wherein each of the encoding lookup tables is constructed according to the information to be encoded, the register state and a check bit pair corresponding to the information to be encoded; Determine a target check bit pair corresponding to the target information to be encoded from the target encoding lookup table based on the target information to be encoded; An encoding result of the target information to be encoded is determined based on the target check bit pair.
2. The method according to claim 1, characterized in that The process of constructing the encoding lookup table includes the following steps: determining different first register states according to the historical states of each register in the component encoder; Determining different first information to be encoded according to the historical information to be encoded; Inputting each of the first register states and each of the first information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded; For each state of the first register, a first coding lookup table is constructed according to each pair of the first information to be encoded and the corresponding first check bit.
3. The method according to claim 2, characterized in that The step of inputting each of the first register states and each of the first information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded includes: Inputting each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial to obtain a second register state; The second register state is input into a pre-configured first output polynomial and a pre-configured second output polynomial respectively to obtain the first check bit pair corresponding to each of the first information to be encoded.
4. The method according to claim 2, characterized in that: After determining different first information to be encoded according to the historical information to be encoded, the method further includes: Interleaving each of the first information to be encoded to obtain second information to be encoded corresponding to each of the first information to be encoded; Inputting each of the first register states and each of the second information to be encoded into a pre-configured feedback branch polynomial and an output polynomial to obtain a second check bit pair corresponding to each of the first information to be encoded; For each state of the first register, a second encoding lookup table is constructed according to each pair of the first information to be encoded and the corresponding second check bit.
5. The method according to claim 4, characterized in that Determining a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables according to the target register state includes: According to the target register state, a first target encoding lookup table and a second target encoding lookup table corresponding to the target register state are determined from a plurality of pre-configured first encoding lookup tables and second encoding lookup tables respectively.
6. The method according to claim 2, characterized in that The first information to be encoded is a combination of information bit pairs, and the inputting of each of the first register states and each of the first information to be encoded into a preconfigured feedback branch polynomial and an output polynomial to obtain a first check bit pair corresponding to each of the first information to be encoded includes: For each of the information bit pair combinations, obtaining a first group of information bit pairs of the current information bit pair combination, inputting the first group of information bit pairs and the current first register state into a pre-configured feedback branch polynomial to obtain a third register state; Inputting the third register state into a preconfigured output polynomial to obtain a third check bit pair corresponding to the first group of information bit pairs, and updating the current first register state to the third register state; For the remaining groups of information bit pairs in the current information bit pair combination, the steps of obtaining the corresponding third check bit pairs and updating the current first register state are performed, and the third check bit pairs corresponding to each group of information bit pairs in the current information bit pair combination are combined to form a first check bit pair corresponding to the current information bit pair combination.
7. The method according to claim 6, characterized in that The method further comprises: The current first register state updated by the last group of information bit pairs in the current information bit pair combination is used as a fourth register state corresponding to the current information bit pair combination, wherein the fourth register state is used to cooperate with the new information bit pair combination to generate a new first check bit pair.
8. An encoding device, characterized in that: include: An acquisition module, used for acquiring target information to be encoded, and determining a target register state of a component encoder where the target information to be encoded is located; A first determination module is used to determine a target encoding lookup table corresponding to the target register state from a plurality of pre-configured encoding lookup tables according to the target register state; wherein each encoding lookup table is constructed according to information to be encoded, a register state and a check bit pair corresponding to the information to be encoded; A second determination module is used to determine a target check bit pair corresponding to the target information to be encoded from the target encoding lookup table based on the target information to be encoded; The third determination module is used to determine the encoding result of the target information to be encoded based on the target check bit pair.
9. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the encoding method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the encoding method according to any one of claims 1 to 7 are implemented.