Data transmission system based on data stream bit-by-bit return verification

Abstract

The invention relates to data transmission, in particular to a data transmission system based on data stream bit-by-bit return verification, which comprises a data transmission layer used for data interaction between an internal memory of a chip and the data transmission layer, performing read-write in a DMA (direct memory access) mode to realize data transmission of different lengths, and caching data of a current data transmission task at the same time; data retransmission is carried out when the data verification is wrong; the data link layer is used for packing and transmission control of data, and a transmitting end state machine TFSM and a receiving end state machine RFSM are respectively arranged in a transmitting end TX and a receiving end RX so as to carry out working state control; the data conversion layer is used for encoding and verifying data, converting parallel data into serial data, transmitting the serial data to the outside through LVDS (Low Voltage Differential Signaling), and feeding back a data verification result to the data link layer; according to the technical scheme provided by the invention, the defect that the data transmission efficiency is greatly reduced due to the fact that data retransmission needs to be carried out on the whole data packet when the data verification is wrong can be overcome.

Description

Technical Field

[0001] The invention relates to data transmission, and in particular to a data transmission system based on bit-by-bit return verification of data streams. Background Art

[0002] Single event upset (SEU) is a phenomenon in which a high-energy particle hits a semiconductor component, causing a change in logic from "0" to "1", leading to a logic error. In environments with harsh electromagnetic radiation, such as outer space, communication between chips is often affected by SEU. Since high-computing chips need to match communication interfaces with high transmission rates, once a data error occurs in the communication interface, it will cause functional errors in the entire device.

[0003] When developing high-performance radiation-resistant components, the reinforcement technologies usually adopted include register multi-mode redundancy, memory data interleaving and pipeline self-refresh, etc. For data transmission modules, including high-speed transmission equipment, data packets are generally used for data transmission. The reinforcement method is only to reinforce the register or memory, and the data is more often used in the form of data verification. Once the data verification is wrong, the entire data packet needs to be retransmitted, which will greatly reduce the data transmission efficiency. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a data transmission system based on bit-by-bit return verification of data streams, which can effectively overcome the defect of the prior art that when a data verification error occurs, the entire data packet needs to be retransmitted, resulting in a significant reduction in data transmission efficiency.

[0006] (II) Technical solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] A data transmission system based on bit-by-bit data stream return verification, comprising a data transmission layer, a data link layer and a data conversion layer;

[0009] The data transmission layer is used for data exchange between the internal memory of the chip and this layer. It uses DMA to read and write, realizes data transmission of different lengths, and caches the data of the current data transmission task for data retransmission when data verification errors occur.

[0010] The data link layer is used for data packaging and transmission control. The transmitter state machine T_FSM and the receiver state machine R_FSM are built in the transmitter TX and the receiver RX respectively to control the working status;

[0011] The data conversion layer is used for data encoding and verification, converting parallel data into serial data, transmitting it to the outside through LVDS, and feeding back the data verification results to the data link layer to determine whether the current transmission data is transmitted normally or retransmitted. At the same time, it can synchronize and verify the data returned through LVDS.

[0012] Preferably, the data transmission layer includes a DMA controller, a configuration register CSR and a retransmission register;

[0013] DMA controller, used to exchange data with the internal memory of the chip, using DMA to read and write;

[0014] Configuration register CSR is used to configure the controller or obtain the controller status, parse the value of the control register into the corresponding control signal, and output it after cross-clock domain processing. At the same time, it samples the input status signal and updates the internal register;

[0015] The retransmission register caches the data of the current data transmission task for data retransmission when a data verification error occurs.

[0016] Preferably, the data conversion layer comprises a data shifter DATASHIFT, a return synchronizer ECHO SYNC and a return checker ECHO COMPARE;

[0017] A data shifter DATASHIFT converts parallel data into serial data;

[0018] The return synchronizer ECHO SYNC aligns the returned serial data and converts it into parallel data;

[0019] The echo checker ECHO COMPARE compares the echo data with the corresponding sent data.

[0020] Preferably, each time a valid data is stored in the transmitting end TX, the TXS_CTRL signal of the transmitting end TX starts to flip, and after the TXS_DATA signal transmitted by the transmitting end TX maintains 4 high levels, it starts to send data, and after sending a valid data, the TXS_CTRL signal remains high, waiting for the return data from the receiving end RX;

[0021] After receiving the returned data, the transmitter TX compares it with the corresponding sent data:

[0022] If the returned data is detected to be wrong, the TXS_CTRL signal of the transmitter TX starts to flip, and the TXS_DATA signal transmitted by the transmitter TX maintains 4 low levels before starting to retransmit the data;

[0023] If the returned data is detected to be correct, the next valid data will be transmitted.

[0024] Preferably, each time the receiving end RX receives a valid data, the TXR_CTRL signal of the receiving end RX starts to flip, and after the TXR_DATA signal transmitted by the receiving end RX maintains a low level, it starts to transmit data back.

[0025] Preferably, the sending end state machine T_FSM in the data link layer includes six working states:

[0026] Reset state: After the chip is powered on and reset, the TX channel enters the reset state, and the output signals are kept at a high level.

[0027] In the data transmission state, when the data transmission layer starts working, there is a 32-bit valid data in the cache of the TX channel, and the data transmission state is entered, and the valid data starts to be sent. At the same time, the TXS_CTRL signal starts to flip, and the rising edge is aligned with the middle of each bit of data. After the transmission is completed, the output signal continues to remain at a high level;

[0028] Data check state: After sending a valid data, it enters the data check state and starts to collect the returned data through the sent back TXR_CTRL signal state, and compares it with the corresponding sent data;

[0029] In the high-level check state, considering the transmission delay, after N cycles, it enters the high-level check state and starts to detect 4-cycle high levels to ensure that the data is transmitted back. If the data check is correct and 4-cycle high levels are detected, it jumps back to the data sending state and continues to transmit the next valid data. If the data check is wrong / no 4-cycle high levels are detected, it jumps into the retransmission waiting state.

[0030] Retransmission waiting state: At this time, TXS_CTRL remains at a low level, notifying the data transmission layer to retransmit data;

[0031] Low level check state, after n cycles, enter the low level check state, until 4 cycles of low level are detected, jump back to the data sending state, and resend the current valid data;

[0032] Wherein, N is the delay period of the transmitting end TX and the receiving end RX for the same group of data transmission, and n is the delay period of the transmitting end TX and the receiving end RX for the same group of data transmission.

[0033] Preferably, the receiving end state machine R_FSM in the data link layer includes five working states:

[0034] Reset state: After the chip is powered on and reset, the RX channel enters the reset state and waits to receive valid data sent by the other end.

[0035] Receiving state: after detecting 3 consecutive high levels, a rising edge is detected, and the receiving state is entered to start receiving valid data.

[0036] Wait-and-see state: after receiving a valid data, wait for the other end to compare and verify the returned data; if three consecutive high levels are detected, it means that the received data is correct, the data is popped out and the state of submission is ready is jumped into; if a rising edge is detected, it directly jumps into the state of submission is ready; if three consecutive low levels are detected, it means that the received data is wrong, the data is discarded and the state of retransmission is jumped into;

[0037] In the submission preparation state, if three rising edges are detected, it means that the next round of valid data reception has started, the current data is popped out and the state jumps back to the receiving state; if three consecutive low levels are detected, it means that the received data is wrong, the other end starts to retransmit the data, and jumps into the retransmission state;

[0038] In the retransmission state, a rising edge is detected, indicating that the retransmission of data has started, and the signal jumps back to the receiving state.

[0039] (III) Beneficial effects

[0040] Compared with the prior art, the present invention provides a data transmission system based on bit-by-bit feedback verification of data streams. Based on the idea of ​​bit-by-bit feedback verification of data streams, a high-speed data transmission protocol resistant to single-particle flipping in a radiation environment is constructed, and bit-by-bit feedback verification of data streams is realized. Bit-by-bit feedback verification of parallel data can be performed, and when a data verification error occurs, only one parallel data needs to be retransmitted. This improves the accuracy of data transmission and can significantly reduce data retransmission loss, thereby ensuring data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a system schematic diagram of the present invention;

[0043] Figure 2 Schematic diagram of a single event upset error occurring at the transmitting end TX before transmission, during transmission, and during transmission of a high level in the present invention;

[0044] Figure 3 A schematic diagram of a single event upset error occurring at a receiving end RX during data return in the present invention;

[0045] Figure 4 Schematic diagram of a transmitter state machine T_FSM of a transmitter TX in the present invention;

[0046] Figure 5 It is a schematic diagram of a receiving end state machine R_FSM of a receiving end RX in the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] A data transmission system based on bit-by-bit data stream return verification, such as Figure 1 As shown, it includes data transmission layer, data link layer and data conversion layer;

[0049] The data transmission layer is used for data exchange between the internal memory of the chip and this layer. It uses DMA to read and write, realizes data transmission of different lengths, and caches the data of the current data transmission task for data retransmission when data verification errors occur.

[0050] The data link layer is used for data packaging and transmission control. The transmitter state machine T_FSM and the receiver state machine R_FSM are built in the transmitter TX and the receiver RX respectively to control the working status;

[0051] The data conversion layer is used for data encoding and verification, converting parallel data into serial data, transmitting it to the outside through LVDS, and feeding back the data verification results to the data link layer to determine whether the current transmission data is transmitted normally or retransmitted. At the same time, it can synchronize and verify the data returned through LVDS.

[0052] like Figure 1 As shown, the data transmission layer includes a DMA controller, a configuration register CSR and a retransmission register;

[0053] DMA controller, used to exchange data with the internal memory of the chip, using DMA to read and write;

[0054] Configuration register CSR is used to configure the controller or obtain the controller status, parse the value of the control register into the corresponding control signal, and output it after cross-clock domain processing. At the same time, it samples the input status signal and updates the internal register;

[0055] The retransmission register caches the data of the current data transmission task for data retransmission when a data verification error occurs.

[0056] like Figure 1 As shown, the data conversion layer includes a data shifter DATASHIFT, a return synchronizer ECHO SYNC and a return checker ECHO COMPARE;

[0057] A data shifter DATASHIFT converts parallel data into serial data;

[0058] The return synchronizer ECHO SYNC aligns the returned serial data and converts it into parallel data;

[0059] The echo checker ECHO COMPARE compares the echo data with the corresponding sent data.

[0060] like Figure 2 As shown, each time a valid data is stored in the transmitter TX, the TXS_CTRL signal of the transmitter TX starts to flip, and after the TXS_DATA signal transmitted by the transmitter TX maintains 4 high levels, it starts to send data. After sending a valid data, the TXS_CTRL signal remains high, waiting for the return data from the receiver RX;

[0061] After the transmitter TX receives the returned data, it compares it with the corresponding sent data:

[0062] If the returned data is detected to be wrong, the TXS_CTRL signal of the transmitter TX starts to flip, and the TXS_DATA signal transmitted by the transmitter TX maintains 4 low levels before starting to retransmit the data;

[0063] If the returned data is detected to be correct, the next valid data will be transmitted.

[0064] like Figure 3 As shown, each time a valid data is received in the receiving end RX, the TXR_CTRL signal of the receiving end RX starts to flip, and after the TXR_DATA signal transmitted by the receiving end RX maintains a low level, it starts to return data.

[0065] like Figure 4 As shown, the sending state machine T_FSM in the data link layer includes six working states:

[0066] Reset state: After the chip is powered on and reset, the TX channel enters the reset state, and the output signals are kept at a high level.

[0067] In the data transmission state, when the data transmission layer starts working, there is a 32-bit valid data in the cache of the TX channel, and the data transmission state is entered, and the valid data starts to be sent. At the same time, the TXS_CTRL signal starts to flip, and the rising edge is aligned with the middle of each bit of data. After the transmission is completed, the output signal continues to remain at a high level;

[0068] Data check state: After sending a valid data, it enters the data check state and starts to collect the returned data through the sent back TXR_CTRL signal state, and compares it with the corresponding sent data;

[0069] In the high-level check state, considering the transmission delay, after N cycles, it enters the high-level check state and starts to detect 4-cycle high levels to ensure that the data is transmitted back. If the data check is correct and 4-cycle high levels are detected, it jumps back to the data sending state and continues to transmit the next valid data. If the data check is wrong / no 4-cycle high levels are detected, it jumps into the retransmission waiting state.

[0070] Retransmission waiting state: At this time, TXS_CTRL remains at a low level, notifying the data transmission layer to retransmit data;

[0071] Low level check state, after n cycles, enter the low level check state, until 4 cycles of low level are detected, jump back to the data sending state, and resend the current valid data;

[0072] Wherein, N is the delay period of the transmitting end TX and the receiving end RX for the same group of data transmission, and n is the delay period of the transmitting end TX and the receiving end RX for the same group of data transmission.

[0073] like Figure 5 As shown, the receiving end state machine R_FSM in the data link layer includes five working states:

[0074] Reset state: After the chip is powered on and reset, the RX channel enters the reset state and waits to receive valid data sent by the other end.

[0075] Receiving state: after detecting 3 consecutive high levels, a rising edge is detected, and the receiving state is entered to start receiving valid data.

[0076] Wait-and-see state: after receiving a valid data, wait for the other end to compare and verify the returned data; if three consecutive high levels are detected, it means that the received data is correct, the data is popped out and the state of submission is ready is jumped into; if a rising edge is detected, it directly jumps into the state of submission is ready; if three consecutive low levels are detected, it means that the received data is wrong, the data is discarded and the state of retransmission is jumped into;

[0077] In the submission preparation state, if three rising edges are detected, it means that the next round of valid data reception has started, the current data is popped out and the state jumps back to the receiving state; if three consecutive low levels are detected, it means that the received data is wrong, the other end starts to retransmit the data, and jumps into the retransmission state;

[0078] In the retransmission state, a rising edge is detected, indicating that the retransmission of data has started, and the signal jumps back to the receiving state.

[0079] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data transmission system based on bit-by-bit data stream return verification, characterized in that: Includes data transmission layer, data link layer and data conversion layer; The data transmission layer is used for data exchange between the internal memory of the chip and this layer. It uses DMA to read and write, realizes data transmission of different lengths, and caches the data of the current data transmission task for data retransmission when data verification errors occur. The data link layer is used for data packaging and transmission control. The transmitter state machine T_FSM and the receiver state machine R_FSM are built in the transmitter TX and the receiver RX respectively to control the working status; The data conversion layer is used for data encoding and verification, converting parallel data into serial data, transmitting it to the outside through LVDS, and feeding back the data verification results to the data link layer to determine whether the current transmission data is transmitted normally or retransmitted. At the same time, it can synchronize and verify the data returned through LVDS.

2. The data transmission system based on bit-by-bit data stream return verification according to claim 1, characterized in that: The data transmission layer includes a DMA controller, a configuration register CSR and a retransmission register; DMA controller, used to exchange data with the internal memory of the chip, using DMA to read and write; Configuration register CSR is used to configure the controller or obtain the controller status, parse the value of the control register into the corresponding control signal, and output it after cross-clock domain processing. At the same time, it samples the input status signal and updates the internal register; The retransmission register caches the data of the current data transmission task for data retransmission when a data verification error occurs.

3. The data transmission system based on bit-by-bit data stream return verification according to claim 2, characterized in that: The data conversion layer includes a data shifter DATASHIFT, a return synchronizer ECHO SYNC and a return checker ECHOCOMPARE; A data shifter DATASHIFT converts parallel data into serial data; The return synchronizer ECHO SYNC aligns the returned serial data and converts it into parallel data; The echo checker ECHO COMPARE compares the echo data with the corresponding sent data.

4. The data transmission system based on bit-by-bit data stream return verification according to claim 3, characterized in that: Each time a valid data is stored in the transmitting end TX, the TXS_CTRL signal of the transmitting end TX starts to flip, and after the TXS_DATA signal transmitted by the transmitting end TX maintains 4 high levels, it starts to send data. After sending a valid data, the TXS_CTRL signal remains high, waiting for the return data from the receiving end RX; After receiving the returned data, the transmitter TX compares it with the corresponding sent data: If the returned data is detected to be wrong, the TXS_CTRL signal of the transmitter TX starts to flip, and the TXS_DATA signal transmitted by the transmitter TX maintains 4 low levels before starting to retransmit the data; If the returned data is detected to be correct, the next valid data will be transmitted.

5. The data transmission system based on bit-by-bit data stream return verification according to claim 4 is characterized in that: Each time the receiving end RX receives a valid data, the TXR_CTRL signal of the receiving end RX starts to flip, and after the TXR_DATA signal transmitted by the receiving end RX maintains a low level, it starts to return data.

6. The data transmission system based on bit-by-bit data stream return verification according to claim 5, characterized in that: The sending end state machine T_FSM in the data link layer includes six working states: Reset state: After the chip is powered on and reset, the TX channel enters the reset state, and the output signals are kept at a high level. In the data transmission state, when the data transmission layer starts working, there is a 32-bit valid data in the cache of the TX channel, and the data transmission state is entered, and the valid data starts to be sent. At the same time, the TXS_CTRL signal starts to flip, and the rising edge is aligned with the middle of each bit of data. After the transmission is completed, the output signal continues to remain at a high level; Data check state: After sending a valid data, it enters the data check state and starts to collect the returned data through the sent back TXR_CTRL signal state, and compares it with the corresponding sent data; In the high-level check state, considering the transmission delay, after N cycles, it enters the high-level check state and starts to detect 4-cycle high levels to ensure that the data is transmitted back. If the data check is correct and 4-cycle high levels are detected, it jumps back to the data sending state and continues to transmit the next valid data. If the data check is wrong / no 4-cycle high levels are detected, it jumps into the retransmission waiting state. Retransmission waiting state: At this time, TXS_CTRL remains at a low level, notifying the data transmission layer to retransmit data; Low level check state, after n cycles, enter the low level check state, until 4 cycles of low level are detected, jump back to the data sending state, and resend the current valid data; Wherein, N is the delay period of the transmitting end TX and the receiving end RX for the same group of data transmission, and n is the delay period of the transmitting end TX and the receiving end RX for the same group of data transmission.

7. The data transmission system based on bit-by-bit data stream return verification according to claim 6, characterized in that: The receiving end state machine R_FSM in the data link layer includes five working states: Reset state: After the chip is powered on and reset, the RX channel enters the reset state and waits to receive valid data sent by the other end. Receiving state: after detecting 3 consecutive high levels, a rising edge is detected, and the receiving state is entered to start receiving valid data. Wait-and-see state: after receiving a valid data, wait for the other end to compare and verify the returned data; if three consecutive high levels are detected, it means that the received data is correct, the data is popped out and the state of submission is ready is jumped into; if a rising edge is detected, it directly jumps into the state of submission is ready; if three consecutive low levels are detected, it means that the received data is wrong, the data is discarded and the state of retransmission is jumped into; In the submission preparation state, if three rising edges are detected, it means that the next round of valid data reception has started, the current data is popped out and the state jumps back to the receiving state; if three consecutive low levels are detected, it means that the received data is wrong, the other end starts to retransmit the data, and jumps into the retransmission state; In the retransmission state, a rising edge is detected, indicating that the retransmission of data has started, and the signal jumps back to the receiving state.

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