A GPU video processing load balancing system based on CXL technology

Abstract

The application discloses a GPU video processing load balancing system based on a CXL technology, and relates to the technical field of video processing.The system comprises a user cluster terminal, a GPU video processing center, n distributed GPU computing cards and a CXL switch, wherein the terminal is responsible for sending a video processing task demand to the GPU video processing center and receiving a video processing result fed back by the GPU video processing center; the GPU video processing center is responsible for receiving a video processing task, evaluating time loss, directly processing the task or distributing the task to the distributed GPU computing cards through the CXL switch, and feeding back processing results to the terminal in time; and the distributed GPU computing card is responsible for receiving and processing the distributed task and sending processing results back to the GPU video processing center.The application can reduce the calculation load of the GPU video processing center server and improve the video processing efficiency.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of video processing, and in particular to a GPU video processing load balancing system based on CXL technology. BACKGROUND

[0002] A GPU (Graphics Processing Unit) is a hardware accelerator specially designed for processing graphics and image calculations. In recent years, with the rise of artificial intelligence, the number of GPUs used by scholars in scientific research and industrial production has increased day by day. The application of GPUs has far exceeded the traditional field of graphics rendering and has expanded to a wider range of high-quality video processing tasks.

[0003] Load balancing: Load balancing is a method of distributing user requests among multiple node devices to improve the overall performance, availability, and reliability of the system. It achieves these goals by optimizing resource usage, maximizing throughput, minimizing response time, and avoiding overloading any one node.

[0004] At present, GPU video processing centers usually use the "CPU cooperates with GPU to jointly process" mode for large-scale video processing tasks. Limited by the performance barrier of GPUs, this mode cannot guarantee the real-time processing needs of a large number of high-standard videos in a single period, and cannot balance the load in the optimal solution, resulting in low video processing efficiency and high delay. Moreover, the existing method needs to complete part of the tasks that should be executed by the GPU through CPU cooperation, which will inevitably cause the loss of CPU computing power and increase the load, thereby affecting the execution process of other important applications of the video processing center server. SUMMARY

[0005] The application provides a GPU video processing load balancing system based on CXL technology to meet the needs of large-scale and efficient video processing of GPU video processing centers in the era of artificial intelligence.

[0006] The GPU video processing load balancing system based on CXL technology solves the above technical problems by adopting the following technical solutions:

[0007] A GPU video processing load balancing system based on CXL technology includes a user cluster terminal, a GPU video processing center, n distributed GPU computing cards, and a CXL Switch.

[0008] The user cluster terminal is responsible for sending video processing task requirements to the GPU video processing center through the network and receiving the video processing results fed back by the GPU video processing center.

[0009] The GPU video processing center is responsible for receiving a video processing task, evaluating time loss based on complexity of the video processing task, and then directly processing the video processing task or distributing the video processing task to the distributed GPU computing card through the CXL Switch, and feeding back the video processing result to the user cluster terminal in time;

[0010] The distributed GPU computing card is responsible for receiving and processing the video processing task distributed, and sending the video processing result back to the GPU video processing center.

[0011] Optionally, the GPU video processing center involved includes a GPU video processing terminal server and a GPU video processing distributed control device connected through a PCIe interface, wherein:

[0012] The GPU video processing terminal server is deployed with a software API of related functions, for the administrator to control the system from the software level and exchange data with the user cluster terminal. The GPU video processing terminal server is also responsible for receiving a video processing task, evaluating time loss based on complexity of the video processing task, and then directly processing the video processing task or distributing the video processing task to the GPU video processing distributed control device through the PCIe interface.

[0013] The GPU video processing distributed control device is responsible for packaging the video processing task, distributing and sending the packaged video processing task to the CXL address of the target distributed GPU computing card through the CXL Switch, and collecting the video processing result and sending it to the GPU video processing terminal server in time.

[0014] Further optionally, the GPU video processing terminal server involved includes a terminal server CPU, a server GPU and a cache module, wherein:

[0015] The terminal server CPU is responsible for receiving a video processing task, and evaluating time loss based on complexity of the video processing task, and then checking whether the server GPU is in an idle state,

[0016] a) if yes, the video processing task is directly distributed to the server GPU, the server GPU executes the video processing task, and the video processing result is sent back to the terminal server CPU,

[0017] b) if no, the video processing task is assigned to the GPU video processing distributed control device through the PCIe interface, the GPU video processing distributed control device polls the working state of the n distributed GPU computing cards, and judges whether to split the video processing task according to the time loss of the video processing task, then the split or unsplit video processing task is assigned to at least one target distributed GPU computing card in an idle state through the CXL Switch, and the target distributed GPU computing card sends the video processing result back to the GPU video processing distributed control device after completing the video processing task, and the GPU video processing distributed control device sends the video processing result back to the terminal server CPU.

[0018] Further optionally, the terminal server CPU involved evaluates the time loss according to the complexity of the video processing task, and the evaluation process specifically applies the following algorithm:

[0019] time total =t*24*time1 (1),

[0020] time1=index x *index y *Complexity / f (2),

[0021]

[0022] Wherein, time total is the time loss evaluation result of the terminal server CPU on the video processing task; t is the total time of the video to be processed; time1 is the estimated time of processing a single frame of video; f is the frequency of the terminal server CPU executing video processing, which is a constant value; Complexity is the complexity coefficient of the target video processing method, which is a constant value; index x , index y are single-order index parameters of each frame of video in x and y directions respectively; Res x , Res y are pixel values of each frame of video in x and y directions respectively; Res refx , Res refy are reference pixel values of each frame of video in x and y directions respectively, which are constant values set by the user; s x , s y are GPU processing step sizes of each frame of video in x and y directions respectively, which are constant values set by the user; k is the GPU processing element width of the video, which is a constant value; alpha x , alpha y are single-order reference values of each frame of video in x and y directions respectively, which are constant values preset by the user.

[0023] Preferably, the server GPU involved executes the video processing task, and sends the video processing result back to the terminal server CPU, and the terminal server CPU generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network;

[0024] Alternatively, the target distributed GPU computing card sends the video processing result back to the GPU video processing distributed control device after completing the video processing task, the GPU video processing distributed control device verifies the video processing result, and then sends the verified video processing result to the terminal server CPU through the PCIe interface, the terminal server CPU generates a video processing log and saves it to the cache module, and finally sends the video processing result to the user cluster terminal through the network.

[0025] Optionally, the GPU video processing distributed control device involved includes an FPGA chip and a DDR5 memory;

[0026] The FPGA chip is responsible for distributing and scheduling the video processing task issued by the terminal server CPU, sending the task instruction and original video data to the target distributed GPU computing card through CXLSwitch packaging, and collecting the video processing result feedback from the target distributed GPU computing card in time, and sending it to the user cluster terminal through the GPU video processing terminal server;

[0027] The DDR5 memory is responsible for receiving and storing the video processing task issued by the GPU video processing terminal server, and sending the video processing task to each target distributed GPU computing card according to the scheduling requirements of the FPGA chip.

[0028] Further optionally, after the target distributed GPU computing card involved receives the video processing task, it processes the video through six steps of data input and decoding, color space conversion, video analysis and processing, special effect application and synthesis, video data encoding, data output and optimization, and sends the video processing result back to the FPGA chip.

[0029] Further optionally, the FPGA chip involved includes an input data cache module, a GPU execution device polling module, a request decoding module, a video processing demand confirmation module, a data header checking module, an MIG module, a task splitting scheme confirmation module, a splitting scheme data transceiver FSM state machine, a non-splitting scheme data transceiver FSM state machine, a data reception merging cache module, a video processing result data verification log generation module, a BRAM storage module and an output data cache module;

[0030] The FPGA chip receives the video processing task distribution and scheduling issued by the terminal server CPU, specifically including:

[0031] The input data caching module caches the task instructions and raw video data, and sends the task instructions to the request decoding module. At the same time, the input data caching module sends a polling instruction to the GPU execution device polling module to start polling the working idle status of the distributed GPU computing card through CXL.

[0032] The request decoding module decodes the task instruction to obtain the general identification code for the FPGA chip to recognize the video processing method, and sends the general identification code and the original video data to the video processing requirement confirmation module.

[0033] The video processing requirement confirmation module confirms whether the video processing task corresponds to the original video data format. If so, it sends the general identification code of the video processing method and the header of the video to be processed to the MIG module and temporarily stores them in the DDR5 memory. Then, it sends the video processing method identification code and the original video data to the task splitting scheme confirmation module.

[0034] The task splitting scheme confirmation module receives the polling results from the GPU execution device polling module via CXL to confirm available distributed GPU computing cards.

[0035] Based on the time consumption assessment data of the terminal server CPU for this video processing task, it is determined whether the video processing task needs to be split and the specific number of splits required, and the number of splits should not exceed the number of idle distributed GPU computing cards. a) If the current video processing task does not need to be split, the task splitting scheme confirmation module directly sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card, and the original video data to the splitting scheme data transceiver FSM state machine. The splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data to the target distributed GPU via CXL. a) If the current video processing task needs to be split, the task splitting scheme confirmation module will sequentially split the original video data into several parts, allocate the CXL address of the idle distributed GPU computing card to each part of the original video data, and send the general identification code of the video processing method, the CXL address of the target distributed GPU computing card and the corresponding part of the original video data to the non-splitting scheme data transceiver FSM state machine. The non-splitting scheme data transceiver FSM state machine sends the general identification code of the video processing method and the original video data split into several parts to the CXL addresses of multiple target distributed GPU computing cards through CXL.

[0036] After the target distributed GPU computing card completes the calculation, it writes the video processing results back to the corresponding split scheme data transceiver FSM state machine / non-split scheme data transceiver FSM state machine through CXL, and sends the video processing results to the data receiving and merging cache module;

[0037] The data receiving, merging, and caching module can directly send the video processing results to the video processing result data verification log generation module and the header verification module, or the data receiving, merging, and caching module can concatenate the video processing results of multiple video processing subtasks and then send them to the video processing result data verification log generation module and the header verification module.

[0038] The header verification module reads the video processing method general identification code and the header data of the video to be processed stored in the DDR5 memory through the MIG module. After confirming that the video processing result corresponds to the video processing task requirements, it informs the video processing result data verification log generation module.

[0039] The video processing result data verification log generation module verifies the video processing results. After verifying that the video processing results executed by the distributed GPU are accurate, it generates a video processing log and stores it in the BRAM memory. Subsequently, the video processing result data verification log generation module sends the verified video processing results to the output data cache module.

[0040] The output data caching module sends the verified video processing results to the terminal server CPU via the PCIe interface.

[0041] Alternatively, the workflow of the GPU video processing load balancing system involved is as follows:

[0042] S1. User cluster terminals send video processing task requests to the GPU video processing center via the network;

[0043] S2, the terminal server CPU of the GPU video processing center first receives the video processing task, and then evaluates the time loss based on the complexity of the video processing task.

[0044] S3. The terminal server CPU checks whether the server GPU is idle. If it is not idle, proceed to step S4; if it is idle, proceed to step S8.

[0045] S4. The terminal server CPU distributes the video processing task to the GPU video processing distributed control device through the PCIe interface.

[0046] S5. The FPGA chip of the GPU video processing distributed control device polls the working status of n distributed GPU computing cards and evaluates whether the current video processing task needs to be split for processing based on the time consumption of the current video processing task. Then, it allocates the corresponding task to at least one target distributed GPU computing card that is in an idle state through CXLSwitch.

[0047] S6. The target distributed GPU computing card completes the corresponding video processing task and sends the video processing results back to the GPU video processing distributed control device.

[0048] S7. The GPU video processing distributed control device receives the video processing result, verifies the video processing result, generates a video processing log, and then sends the verified video processing result back to the terminal server CPU through the PCIe interface, and jumps to step S9.

[0049] S8. The terminal server CPU directly assigns the task to the server GPU. The server GPU executes the current video processing task and sends the video processing result back to the terminal server CPU.

[0050] S9. The terminal server CPU receives the video processing results, generates video processing logs and saves them to the cache module, and then sends the video processing results to the user cluster terminal via the network.

[0051] The GPU video processing load balancing system based on CXL technology of the present invention has the following advantages compared with the prior art:

[0052] 1. This invention adopts a brand-new core design concept of "unified control of distributed GPU computing cards by GPU video processing center". It uses CXL high-speed interconnect technology as the architecture carrier and the terminal server CPU of the video processing center as the video processing control terminal to realize centralized management and overall coordination of multiple distributed GPU computing cards to complete large-scale video processing tasks in parallel in a single time period.

[0053] 2. This invention constructs a GPU video processing load balancing system consisting of user cluster terminals, a GPU video processing center, multiple distributed GPU computing cards, and a CXL Switch equipped with them. By distributing the large-scale video processing demands that would otherwise require the CPU and GPU of the video processing center server to multiple distributed GPU computing cards, large-scale video parallel processing in a single time period is achieved. This greatly reduces the computing load on the GPU video processing center server, significantly improves the system's video processing efficiency, better realizes unified scheduling and control of large-scale GPU video processing, and significantly improves system performance.

[0054] 3. This invention uses CXL technology to realize communication between the video processing center and multiple distributed GPU computing cards, resulting in higher data transmission and communication efficiency and stronger stability. Attached Figure Description

[0055] Appendix Figure 1 This is a system architecture diagram of the present invention;

[0056] Appendix Figure 2 This is a detailed architectural diagram of Embodiment 1 of the present invention;

[0057] Appendix Figure 3This is a block diagram of the FPGA chip in Embodiment 1 of the present invention;

[0058] Appendix Figure 4 This is a flowchart illustrating the GPU video processing load balancing system described in this invention. Detailed Implementation

[0059] To make the technical solution, the technical problem solved, and the technical effect of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments.

[0060] The English terms used in the following embodiments will now be explained:

[0061] CXL technology, short for Compute Express Link, is a new interconnect technology standard designed to achieve high-speed, efficient interconnection between CPUs and accelerators such as GPUs and FPGAs. Through high-bandwidth, low-latency connections, CXL enables memory sharing and consistency between devices, significantly improving computing performance and memory scalability. Furthermore, CXL is not only based on the PCIe specification but also features significant functional extensions, such as memory pooling and memory sharing, allowing multiple devices to access the same memory address space.

[0062] The CXL Switch is a high-performance switch based on Compute Express Link (CXL) technology, designed to enable high-speed interconnection and memory sharing between CPUs and various acceleration devices such as GPUs and FPGAs. By supporting multiple ports and complex topologies, such as CLOS or Mesh types, the CXL Switch provides a more flexible and scalable way to manage computing resources. This switch not only improves processing power and memory scalability within the data center but also provides a solid foundation for future computing needs.

[0063] A GPU (Graphics Processing Unit) is a hardware device specifically designed for high-performance computing tasks. Its main characteristics are powerful parallel processing capabilities and high-speed graphics rendering. GPUs typically contain multiple cores, each capable of independently executing commands, making them excellent at processing large datasets. Compared to traditional graphics cards, GPUs prioritize computational performance over simply handling image output. This design makes them widely used in scientific computing, artificial intelligence, deep learning, and other fields. Furthermore, major GPU manufacturers such as NVIDIA and AMD offer a variety of GPU models to meet the needs of different application scenarios.

[0064] Example 1:

[0065] Combined with appendix Figure 1 This embodiment proposes a GPU video processing load balancing system based on CXL technology, which includes a user cluster terminal, a GPU video processing center, n distributed GPU computing cards and a CXL switch.

[0066] (i) The user cluster terminal is responsible for sending video processing task requests to the GPU video processing center via the network and receiving the video processing results from the GPU video processing center.

[0067] (ii) The GPU video processing center is responsible for receiving video processing tasks, assessing the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or distributing the video processing tasks to the distributed GPU computing cards through the CXL Switch, and promptly feeding back the video processing results to the user cluster terminal.

[0068] 1. The GPU video processing center in this embodiment includes a GPU video processing terminal server and a GPU video processing distributed control device connected via a PCIe interface, wherein:

[0069] The GPU video processing terminal server is equipped with software APIs for related functions, which allow administrators to control the system from the software level and exchange data with user cluster terminals. The GPU video processing terminal server is also responsible for receiving video processing tasks, evaluating the time loss based on the complexity of the video processing tasks, and then directly processing the video processing tasks, or sending the video processing tasks to the GPU video processing distributed control device through the PCIe interface.

[0070] The GPU video processing distributed control unit is responsible for packaging video processing tasks, allocating and sending the packaged video processing tasks to the CXL address of the target distributed GPU computing card through the CXL Switch, and collecting video processing results in a timely manner and sending them to the GPU video processing terminal server.

[0071] Specifically, the terminal server CPU is responsible for receiving video processing tasks and evaluating the time consumption based on the complexity of the video processing tasks. The evaluation process specifically applies the following algorithm:

[0072] time total = t*24*time1 (1),

[0073] time1 = index x *index y *Complexity / f (2),

[0074]

[0075] Among them, timetotal This represents the time consumption assessment result of the terminal server CPU for the video processing task; t is the total duration of the video to be processed; time1 is the estimated processing time for a single frame of video; f is the main frequency of the terminal server CPU executing video processing, which is a constant; Complexity is the complexity coefficient of the target video processing method, which is a constant; index x index y These are the single-order index parameters in the x and y directions for each video frame; Res x Res y These are the pixel values ​​in the x and y directions for each frame of video; Res refx Res refy These are the reference pixel values ​​in the x and y directions for each frame of video, set by the user; s x s y α represents the GPU processing stride in the x and y directions for each video frame, respectively, and is a fixed value set by the user; k is the GPU processing pixel width of the video, which is a fixed value; α x α y These are single-order reference values ​​in the x and y directions for each frame of video, and are user-preset values.

[0076] Specifically, in conjunction with the appendix Figure 2 The GPU video processing terminal server includes a terminal server CPU, a server GPU, and a cache module.

[0077] After assessing the time consumption based on the complexity of the video processing task, the terminal server CPU checks whether the server GPU is idle.

[0078] a) If so, the video processing task is directly assigned to the server GPU. The server GPU executes the video processing task and sends the video processing result back to the terminal server CPU. The terminal server CPU generates a video processing log and saves it to the cache module. Then, the video processing result is sent to the user cluster terminal via the network.

[0079] b) If not, the video processing task is allocated to the GPU video processing distributed control device via the PCIe interface. The GPU video processing distributed control device polls the working status of n distributed GPU computing cards and determines whether to split the video processing task based on the time consumption of the video processing task. Then, the split or unsplit video processing task is allocated to at least one target distributed GPU computing card in an idle state via the CXL Switch. After the target distributed GPU computing card completes the video processing task, it sends the video processing result back to the GPU video processing distributed control device. The GPU video processing distributed control device verifies the video processing result and then sends the verified video processing result to the terminal server CPU via the PCIe interface. The terminal server CPU generates a video processing log and saves it to the cache module. Finally, the video processing result is sent to the user cluster terminal via the network.

[0080] 2. In conjunction with the appendix Figure 2 The GPU video processing distributed control device in this embodiment includes an FPGA chip and a DDR5 memory.

[0081] The FPGA chip is responsible for allocating and scheduling video processing tasks issued by the terminal server CPU, packaging and sending task instructions and raw video data to the target distributed GPU computing card through CXLSwitch, and collecting the video processing results fed back by the target distributed GPU computing card in a timely manner, and sending them to the user cluster terminal through the GPU video processing terminal server.

[0082] The DDR5 memory is responsible for receiving and storing video processing tasks issued by the GPU video processing terminal server, and sending the video processing tasks to each target distributed GPU computing card according to the FPGA chip scheduling requirements.

[0083] Specifically, in conjunction with the appendix Figure 3 The FPGA chip includes an input data buffer module, a GPU execution device polling module, a request decoding module, a video processing requirement confirmation module, a data header verification module, a MIG module, a task splitting scheme confirmation module, a splitting scheme data transceiver FSM state machine, a non-split scheme data transceiver FSM state machine, a data receiving and merging buffer module, a video processing result data verification log generation module, a BRAM storage module, and an output data buffer module.

[0084] The FPGA chip receives video processing task allocation and scheduling from the terminal server CPU, specifically including:

[0085] The input data caching module caches the task instructions and raw video data, and sends the task instructions to the request decoding module. At the same time, the input data caching module sends a polling instruction to the GPU execution device polling module to start polling the working idle status of the distributed GPU computing card through CXL.

[0086] The request decoding module decodes the task instruction to obtain the general identification code for the FPGA chip to recognize the video processing method, and sends the general identification code and the original video data to the video processing requirement confirmation module.

[0087] The video processing requirement confirmation module confirms whether the video processing task corresponds to the original video data format. If so, it sends the general identification code of the video processing method and the header of the video to be processed to the MIG module and temporarily stores them in the DDR5 memory. Then, it sends the video processing method identification code and the original video data to the task splitting scheme confirmation module.

[0088] The task splitting scheme confirmation module receives the polling results from the GPU execution device polling module via CXL to confirm available distributed GPU computing cards.

[0089] Based on the time consumption assessment data of the terminal server CPU for this video processing task, it is determined whether the video processing task needs to be split and the specific number of splits required, and the number of splits should not exceed the number of idle distributed GPU computing cards. a) If the current video processing task does not need to be split, the task splitting scheme confirmation module directly sends the universal identification code of the video processing method, the CXL address of the target distributed GPU computing card, and the original video data to the splitting scheme data transceiver FSM state machine. The splitting scheme data transceiver FSM state machine sends the universal identification code of the video processing method and the original video data to the target distributed GPU via CXL. a) If the current video processing task needs to be split, the task splitting scheme confirmation module will sequentially split the original video data into several parts, allocate the CXL address of the idle distributed GPU computing card to each part of the original video data, and send the general identification code of the video processing method, the CXL address of the target distributed GPU computing card and the corresponding part of the original video data to the non-splitting scheme data transceiver FSM state machine. The non-splitting scheme data transceiver FSM state machine sends the general identification code of the video processing method and the original video data split into several parts to the CXL addresses of multiple target distributed GPU computing cards through CXL.

[0090] After the target distributed GPU computing card completes the calculation, it writes the video processing results back to the corresponding split scheme data transceiver FSM state machine / non-split scheme data transceiver FSM state machine through CXL, and sends the video processing results to the data receiving and merging cache module;

[0091] The data receiving, merging, and caching module can directly send the video processing results to the video processing result data verification log generation module and the header verification module, or the data receiving, merging, and caching module can concatenate the video processing results of multiple video processing subtasks and then send them to the video processing result data verification log generation module and the header verification module.

[0092] The header verification module reads the video processing method general identification code and the header data of the video to be processed stored in the DDR5 memory through the MIG module. After confirming that the video processing result corresponds to the video processing task requirements, it informs the video processing result data verification log generation module.

[0093] The video processing result data verification log generation module verifies the video processing results. After verifying that the video processing results executed by the distributed GPU are accurate, it generates a video processing log and stores it in the BRAM memory. Subsequently, the video processing result data verification log generation module sends the verified video processing results to the output data cache module.

[0094] The output data caching module sends the verified video processing results to the terminal server CPU via the PCIe interface.

[0095] (III) The distributed GPU computing card is responsible for receiving the video processing tasks sent down, and processing the video through six steps: data input and decoding, color space conversion, video analysis and processing, special effects application and synthesis, video data encoding, data output and optimization. Then the video processing results are sent back to the GPU video processing center.

[0096] Example 2:

[0097] Reference Appendix Figure 4 This embodiment proposes a GPU video processing load balancing system based on CXL technology. Based on the structure described in Embodiment 1, it executes the following workflow to achieve load balancing for GPU video processing:

[0098] S1. User cluster terminals send video processing task requests to the GPU video processing center via the network;

[0099] S2, the terminal server CPU of the GPU video processing center first receives the video processing task, and then evaluates the time loss based on the complexity of the video processing task.

[0100] S3. The terminal server CPU checks whether the server GPU is idle. If it is not idle, proceed to step S4; if it is idle, proceed to step S8.

[0101] S4. The terminal server CPU distributes the video processing task to the GPU video processing distributed control device through the PCIe interface.

[0102] S5. The FPGA chip of the GPU video processing distributed control device polls the working status of n distributed GPU computing cards and evaluates whether the current video processing task needs to be split for processing based on the time consumption of the current video processing task. Then, it allocates the corresponding task to at least one target distributed GPU computing card that is in an idle state through CXLSwitch.

[0103] S6. The target distributed GPU computing card completes the corresponding video processing task and sends the video processing results back to the GPU video processing distributed control device.

[0104] S7. The GPU video processing distributed control device receives the video processing result, verifies the video processing result, generates a video processing log, and then sends the verified video processing result back to the terminal server CPU through the PCIe interface, and jumps to step S9.

[0105] S8. The terminal server CPU directly assigns the task to the server GPU. The server GPU executes the current video processing task and sends the video processing result back to the terminal server CPU.

[0106] S9. The terminal server CPU receives the video processing results, generates video processing logs and saves them to the cache module, and then sends the video processing results to the user cluster terminal via the network.

[0107] In summary, the GPU video processing load balancing system based on CXL technology of the present invention can reduce the computing load of the GPU video processing center server and improve video processing efficiency.

[0108] The above specific examples illustrate the principles and implementation methods of the present invention in detail. These embodiments are merely for the purpose of helping to understand the core technical content of the present invention. Based on the above specific embodiments of the present invention, any improvements and modifications made to the present invention by those skilled in the art without departing from the principles of the present invention should fall within the patent protection scope of the present invention.

Claims

1. A CXL technology based GPU video processing load balancing system, characterized in that, It comprises a user cluster terminal, a GPU video processing center, n distributed GPU computing cards and a CXL switch; The user cluster terminal is responsible for sending video processing task requirements to the GPU video processing center through the network and receiving the video processing results fed back by the GPU video processing center; The GPU video processing center comprises a GPU video processing terminal server and a GPU video processing distributed control device connected through a PCIe interface, wherein: The GPU video processing terminal server is deployed with a software API of related functions for the administrator to comprehensively control the system from the software level and exchange data with the user cluster terminal; the GPU video processing terminal server comprises a terminal server CPU, a server GPU and a cache module, wherein: the terminal server CPU is responsible for receiving a video processing task and evaluating the time loss according to the complexity of the video processing task, then checking whether the server GPU is in an idle state, a) if yes, the video processing task is directly assigned to the server GPU, the server GPU executes the video processing task and sends the video processing result back to the terminal server CPU, b) if not, the video processing task is assigned to the GPU video processing distributed control device through the PCIe interface; The GPU video processing distributed control device polls the working states of the n distributed GPU computing cards and judges whether to split the video processing task according to the time loss of the video processing task, then assigns the split or unsplit video processing task to at least one target distributed GPU computing card in an idle state through the CXL switch, the target distributed GPU computing card sends the video processing result back to the GPU video processing distributed control device after completing the video processing task, and the GPU video processing distributed control device sends the video processing result back to the terminal server CPU; The distributed GPU computing card is responsible for receiving and processing the video processing task issued and sending the video processing result back to the GPU video processing center.

2. The CXL technology-based GPU video processing load balancing system according to claim 1, wherein, The terminal server CPU evaluates the time loss according to the complexity of the video processing task, and the evaluation process specifically applies the following algorithm: time total = t * 24 * time1 (1), time1 = index x *index y *Complexity / f(2), wherein, time total is the time consumption evaluation result made by the terminal server CPU on the video processing task; t is the total time length of the video to be processed; time1 is the estimated time length of processing a single frame of video; f is the frequency of the terminal server CPU executing the video processing, which is a constant value; Complexity is the complexity coefficient of the target video processing mode, which is a constant value; index x , index y are the single-order index parameters of each frame of video in the x and y directions, respectively; Res x , Res y are the pixel values of each frame of video in the x and y directions, respectively; Res refx , Res refy are the reference pixel values of each frame of video in the x and y directions, respectively, which are set by the user as constant values; s x , s y are the GPU processing step lengths of each frame of video in the x and y directions, respectively, which are set by the user as constant values; k is the GPU processing element width of the video, which is a constant value; α x , α y are the single-order reference values of each frame of video in the x and y directions, respectively, which are pre-set by the user as constant values.

3. The CXL technology-based GPU video processing load balancing system according to claim 1, wherein, After the server GPU executes the video processing task and sends the video processing result back to the terminal server CPU, the terminal server CPU generates a video processing log and saves it to the cache module, then sends the video processing result to the user cluster terminal through the network; Or, after the target distributed GPU computing card completes the video processing task, it sends the video processing result back to the GPU video processing distributed control device, the GPU video processing distributed control device verifies the video processing result, then sends the verified video processing result to the terminal server CPU through the PCIe interface, the terminal server CPU generates a video processing log and saves it to the cache module, and finally sends the video processing result to the user cluster terminal through the network.

4. The CXL technology-based GPU video processing load balancing system according to claim 3, wherein, The GPU video processing distributed control device comprises an FPGA chip and a DDR5 memory; The FPGA chip is responsible for distributing and scheduling the video processing tasks issued by the terminal server CPU, sending the task instructions and raw video data to the target distributed GPU computing card through CXLSwitch packaging, collecting the video processing results fed back by the target distributed GPU computing card in time, and sending the video processing results to the user cluster terminal through the GPU video processing terminal server. The DDR5 memory is responsible for receiving and storing the video processing tasks issued by the GPU video processing terminal server, and sending the video processing tasks to each target distributed GPU computing card according to the scheduling requirements of the FPGA chip.

5. The CXL technology-based GPU video processing load balancing system according to claim 4, wherein, After receiving the video processing tasks, the target distributed GPU computing card processes the video through six steps of data input and decoding, color space conversion, video analysis and processing, special effect application and synthesis, video data encoding, data output and optimization, and sends the video processing results back to the FPGA chip.

6. The CXL technology-based GPU video processing load balancing system according to claim 4, wherein, The FPGA chip includes an input data buffer module, a GPU execution device polling module, a request decoding module, a video processing requirement confirmation module, a data header checking module, an MIG module, a task splitting scheme confirmation module, a splitting scheme data transceiver FSM state machine, a non-splitting scheme data transceiver FSM state machine, a data reception merging buffer module, a video processing result data verification log generation module, a BRAM storage module, and an output data buffer module. The FPGA chip receives the video processing task distribution and scheduling issued by the terminal server CPU, specifically including: The input data buffer module buffers the task instructions and raw video data, and sends the task instructions to the request decoding module. At the same time, the input data buffer module sends a polling instruction to the GPU execution device polling module to start polling the working idle state of the distributed GPU computing card through CXL; The request decoding module decodes the task instructions to obtain a general identification code recognized by the FPGA chip for the video processing method, and sends the general identification code and the raw video data to the video processing requirement confirmation module; The video processing requirement confirmation module confirms whether the video processing task corresponds to the format of the raw video data. If yes, the general identification code of the video processing method and the video header to be processed are sent to the MIG module and temporarily stored by the DDR5 memory. Then, the video processing method identification code and the raw video data are sent to the task splitting scheme confirmation module; The task splitting scheme confirmation module receives the polling results of the GPU execution device polling module through CXL, and confirms the idle distributed GPU computing card; based on the time loss evaluation data made by the terminal server CPU on the video processing task, it is confirmed whether the video processing task needs to be split and the specific number of splits, and the number of splits does not exceed the number of idle distributed GPU computing cards, a) if the current video processing task does not need to be split, the task splitting scheme confirmation module directly sends the general identification code of the video processing method, the CXL address of the target distributed GPU computing card and the original video data to the splitting scheme data transceiver FSM state machine, and the splitting scheme data transceiver FSM state machine sends the general identification code of the video processing method and the original video data to the CXL address of the target distributed GPU computing card through CXL, b) if the current video processing task needs to be split, the task splitting scheme confirmation module sequentially splits the original video data into several parts, assigns a CXL address of an idle distributed GPU computing card to each part of the original video data, and sends the general identification code of the video processing method, the CXL address of the target distributed GPU computing card and the corresponding part of the original video data to the non-splitting scheme data transceiver FSM state machine, and the non-splitting scheme data transceiver FSM state machine sends the general identification code of the video processing method and the original video data split into several parts to the CXL addresses of multiple target distributed GPU computing cards through CXL; After the target distributed GPU computing card completes the calculation, the video processing result is written back to the corresponding splitting scheme data transceiver FSM state machine / non-splitting scheme data transceiver FSM state machine through CXL, and the video processing result is sent to the data receiving and merging cache module; The data receiving and merging cache module directly sends the video processing result to the video processing result data verification log generation module and the header checking module, or the data receiving and merging cache module splices the video processing results of multiple video processing sub-tasks and then sends them to the video processing result data verification log generation module and the header checking module; The header checking module reads the general identification code of the video processing method and the video header data stored in the DDR5 memory through the MIG module, and informs the video processing result data verification log generation module after confirming that the video processing result corresponds to the video processing task demand without error; The video processing result data verification log generation module verifies the video processing result, generates a video processing log and stores it in the BRAM memory after verifying that the video processing result executed by the distributed GPU is accurate, and then sends the video processing result that passes the verification to the output data cache module; The output data cache module sends the video processing result that passes the verification to the terminal server CPU through the PCIe interface.

7. The CXL technology-based GPU video processing load balancing system according to claim 4, wherein, The working process of the GPU video processing load balancing system is as follows: S1, the user cluster terminal sends the video processing task demand to the GPU video processing center through the network; S2, the terminal server CPU of the GPU video processing center first receives the video processing task, and then evaluates the time loss according to the complexity of the video processing task; S3, the terminal server CPU checks whether the server GPU is in an idle state, if not idle, jump to step S4, if idle, jump to step S8; S4, the terminal server CPU distributes the video processing task to the GPU video processing distributed control device through the PCIe interface; S5, the FPGA chip of the GPU video processing distributed control device polls the working state of the n distributed GPU computing cards, and according to the time loss evaluation of the current video processing task, confirms whether it needs to be split for processing, and then distributes the corresponding task to at least one target distributed GPU computing card in an idle state through the CXL Switch; S6, the target distributed GPU computing card completes the corresponding video processing task and sends the video processing result back to the GPU video processing distributed control device; S7, the GPU video processing distributed control device receives the video processing result, generates a video processing log after verifying the video processing result, and then sends the video processing result that passes the verification back to the terminal server CPU through the PCIe interface, and jumps to step S9; S8, the terminal server CPU directly distributes the task to the server GPU, and the server GPU executes the current video processing task and sends the video processing result back to the terminal server CPU; S9, the terminal server CPU receives the video processing result, generates a video processing log and saves it to the cache module, and then sends the video processing result to the user cluster terminal through the network.

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