Real-time processing device for reflective memory protocol data

Abstract

The invention discloses a reflective memory protocol data real-time processing device, which comprises a reflective memory interface module used for transmitting a protocol data packet; the protocol processing module is used for extracting a plurality of protocol data in the protocol data packet according to a preset protocol template and then carrying out parallel matching identification; performing element analysis on the identified protocol data to obtain an analysis result; the data conversion module is used for converting the analysis result into object model data and outputting the object model data; according to the invention, the parallel identification of the reflective memory protocol packet is realized, the identification delay is reduced, and the real-time performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more particularly to a reflective memory protocol data real-time processing device. Background Art

[0002] At present, most of the existing protocol data recognition methods are based on the "general software + serial matching" mechanism, such as Figure 1 As shown in the figure, the data is first matched with the frame header of protocol A. If it fails, it is matched with the frame header of protocol B until the recognition is successful. This recognition method is inefficient, and the time consumed increases linearly with the number of protocol formats. When the number of protocols reaches dozens or hundreds, the real-time performance of the protocol data real-time processing device cannot be guaranteed.

[0003] Therefore, how to reduce the protocol identification delay is an urgent problem that those skilled in the art need to solve. Summary of the invention

[0004] In view of this, the present invention provides a real-time processing device for reflective memory protocol data, which uses programmable logic devices to implement parallel recognition of reflective memory protocol packets in hardware form, reduces recognition delay, and improves real-time performance.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] A reflective memory protocol data real-time processing device includes a reflective memory interface module, a protocol processing module and a data conversion module. The reflective memory interface module is used to transmit protocol data packets; the protocol processing module is used to extract multiple protocol data in the protocol data packets according to a preset protocol template and then perform parallel matching and identification; it is used to perform element parsing on the identified protocol data to obtain parsing results; the data conversion module is used to convert the parsing results into object model data and then output them.

[0007] Furthermore, the protocol processing module includes a protocol identification module and a protocol automatic parsing module; the protocol identification module is used to receive the protocol data packet and protocol template identification to generate multiple protocol data with template numbers; the protocol automatic parsing module is used to locate the protocol template according to the template number corresponding to the protocol data, and parse each element in the protocol according to the protocol description template to obtain the parsing result.

[0008] Furthermore, the protocol processing module also includes a protocol automatic packaging module, which is used to receive the physical data sent by the protocol conversion module, package it according to the protocol template, and output the packaged data packet to the reflective memory interface module.

[0009] Furthermore, the protocol identification module includes multiple protocol matching units, each of which includes a byte counter, a frame header storage area and a comparison unit; the frame header storage area stores frame header data and outputs a corresponding number of frame header bytes to the comparison unit according to the byte counter; the comparison unit receives the frame header bytes and the frame header template in the protocol template for matching, and outputs the matching result.

[0010] Furthermore, the protocol identification unit also includes an auxiliary logic unit, which is used to obtain the matching progress status of each of the protocol matching units and generate corresponding signal outputs.

[0011] Furthermore, the auxiliary logic unit includes an AND module, a first OR module, a second OR module, a priority encoder and a trigger; the AND module is used to obtain the matching completion signal of each of the protocol matching units, and record the matching completion status and the starting effective time; the first OR module is used to obtain the matching result signal of each of the protocol matching units, and summarize to generate the final matching result; the second OR module is used to obtain the matching occurrence signal of each of the protocol matching units, and the priority encoder is used to obtain the matching occurrence signal of each of the protocol matching units, and perform priority encoding for each of the matching protocol units according to the matching completion flag.

[0012] Furthermore, the protocol matching unit also includes a matching signal generation logic, a matching completion signal generation logic and a rising edge detection logic; the matching completion signal generation logic is used to obtain the matching result output by the comparison unit, the count value output by the byte counter and the frame header length, and generate a matching completion signal; the matching signal generation logic is used to obtain the matching result output by the comparison unit, the count value output by the byte counter and the frame header length, generate a matching result signal, and generate a matching occurrence signal through the rising edge detection logic.

[0013] Furthermore, the comparison unit has a memory function for recording the matching result of each byte during byte-by-byte comparison.

[0014] Furthermore, the data conversion module includes a protocol data and object model data interactive mapping module, and the protocol data and object model data interactive mapping module converts the physical data in the parsing result into object model data according to a preset object model and protocol mapping relationship.

[0015] It can be known from the above technical solution that compared with the prior art, the present invention discloses a real-time processing device for reflective memory protocol data, which realizes the parallel recognition of reflective memory protocol packets in hardware form with programmable logic devices, reduces recognition delay, and improves real-time performance; the present invention can find the first unit that successfully matches in the parallel matching process by introducing a priority encoder. When multiple protocol matching units try to match the same data packet at the same time, the priority encoder can output the signal that completes the match first. This mechanism helps to improve the response speed and efficiency of the system because it avoids waiting for all matching units to complete the match before deciding on the next action. Once a matching unit successfully matches, the system will immediately take corresponding measures, such as starting data transmission or performing other operations. In addition, the priority encoder can also help solve conflict problems, because when multiple matching units match at the same time, only one unit will be selected and the rest will be ignored. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of a protocol identification method of a serial matching mechanism in the prior art;

[0018] Figure 2 A schematic diagram of a protocol identification method of a parallel matching mechanism in an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of the structure of a device for real-time processing of reflective memory protocol data provided by an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of the structure of a reflective memory interface module in an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of the structure of a protocol matching unit in an embodiment of the present invention;

[0022] Figure 6 It is a schematic diagram of the structure of the protocol identification module in an embodiment of the present invention;

[0023] Figure 7 Schematic diagram of the structure of a comparison unit in an embodiment of the present invention;

[0024] Figure 8 It is a schematic diagram of the structure of the Ethernet network interface in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] In order to reduce the delay caused by protocol identification and improve the real-time performance of the device, the present invention adopts a method of parallel protocol identification, and the identification process is as follows: Figure 2 The data is matched with all protocol frame headers in no particular order, and only the successful matching results are retained. The advantage of this recognition method is that no matter how many protocols there are, the final matching time is equal to the time of the successful matching. This method is difficult to implement on the host computer and occupies more resources. Therefore, it is chosen to use resource-rich programmable logic devices such as FPGA on the board to implement it through hardware methods.

[0027] Therefore, the embodiment of the present invention discloses a real-time processing device for reflective memory protocol data, such as Figure 3 ,include:

[0028] Reflective memory interface module, the reflective memory interface module is used to transmit protocol data packets. Figure 4 , the reflective memory interface consists of a reflective memory protocol and an optical module. The reflective memory interface combines the advantages of high bus reliability and stable communication quality with the characteristics of high bandwidth and real-time performance of the fiber channel. The main function of the optical module is to perform photoelectric conversion. In order to reduce the size and weight of the device, the reflective memory protocol logic is implemented in the PL part inside the main control chip. The optical module uses the device HTA8525, which has the characteristics of high density and low power consumption and supports a data transmission rate of 10Gbps. One HTA8525 optical module can support 4 optical channels.

[0029] The protocol processing module is used to extract multiple protocol data in the protocol data packet according to the preset protocol template and then perform parallel matching and identification; the identified protocol data is element parsed to obtain the parsing result. Among them, the protocol processing module is the PL end of the main control chip. At the PS end of the main control chip, the ARM processor imports the protocol data packet transmitted by the reflective memory interface module into the DDR, and then performs subsequent processing through the protocol processing module at the PL end, and finally completes the output to the external system through the Gigabit Ethernet interface at the PS end.

[0030] In one embodiment, the protocol processing module includes a protocol identification module and a protocol automatic parsing module; the protocol identification module is used to receive a protocol data packet and a protocol template to identify and generate a plurality of protocol data with template numbers; the protocol automatic parsing module is used to locate the protocol template according to the template number corresponding to the protocol data, and parse each element in the protocol according to the protocol description template to obtain the parsing result.

[0031] The protocol template is described as follows: Figure 3 As shown, the protocol template is used to describe the four-layer data structure of protocol model, protocol item, protocol frame header / frame tail / element item, and protocol element bit to describe the protocol related information and the transmission characteristics of the protocol.

[0032] In order to further implement the above technical solution, the protocol processing module also includes a protocol automatic packaging module, which is used to receive the physical data sent by the protocol conversion module and then package it according to the protocol template, and output the packaged data packet to the reflective memory interface module. The specific packaging process is: for the element physical value set parsed from the object model data packet, according to the association mapping relationship between the object model and the protocol, locate the protocol description template used for the packet, assign values ​​to each element in the protocol according to the protocol description template, and obtain a complete protocol data packet.

[0033] In order to further implement the above technical solution, the protocol identification module includes multiple protocol matching units, such as Figure 5 Each protocol matching unit includes a byte counter, a frame header storage area and a comparison unit; the frame header storage area stores frame header data and outputs a corresponding number of frame header bytes to the comparison unit according to the byte counter; the comparison unit receives the frame header bytes and the frame header template in the protocol template for matching, and outputs the matching result.

[0034] In order to further implement the above technical solution, the protocol identification module includes multiple protocol matching units and an auxiliary logic unit, and the auxiliary logic unit is used to obtain the matching progress status of each protocol matching unit and generate corresponding signal output. The auxiliary logic unit includes an AND module, a first OR module, a second OR module, a priority encoder and a trigger; the AND module is used to obtain the matching completion signal of each protocol matching unit, and record the matching completion status and the starting effective time; the first OR module is used to obtain the matching result signal of each protocol matching unit, and summarize and generate the final matching result; the second OR module is used to obtain the matching occurrence signal of each protocol matching unit, and the priority encoder is used to determine the matching unit number with the highest priority according to the matching occurrence signal of each protocol matching unit, and retain the encoding result through a 7-bit trigger.

[0035] Specific as Figure 6As shown in the figure, clk represents the clock signal, which is used to synchronize the entire design; rst_n is the reset signal, which performs the reset operation when it is low; rdy is the ready signal, indicating that the received data is ready; byte[7:0]: represents the input byte data, which consists of 8 bits; done[63:0] represents the state of each protocol matching unit after the matching is completed, and 1 means it is completed; match[63:0] represents the matching result of each protocol matching unit, and 1 means the matching is successful; match_ris[63:0] represents the rising edge detection logic. protoid_c[6:0] is a 64 priority encoder, which is used to determine the number of the matching unit with the highest priority according to the ismatch signal. ismatch|(~hasmatch&alldone_ris) means: if there is a matching unit, or if there is no matching but all units have completed the matching and have rising edge detection logic, then set the corresponding flag.

[0036] In this embodiment, 64 protocol matching units form a protocol matching unit array, and a series of auxiliary function logics are added to obtain a protocol identification module. The auxiliary function logic includes a 64-bit AND module, a 64-bit OR module, a 64-bit priority encoder, and an 8-bit trigger; the frame header data area in the protocol matching unit is a storage area containing 16 bytes of space, which stores the information of a protocol frame header. The first byte stores the length of the frame header, and the subsequent 15 bytes store the content of the frame header in sequence. The byte counter counts the bytes of the data packet until the count value is equal to the length of the frame header. The frame header byte is taken out from the frame header data area according to the counter value, and compared with the data packet byte in the comparison unit. A comparison module with a memory function is used as the comparison unit, and the matching results of each byte can be recorded when comparing byte by byte.

[0037] The data conversion module is used to convert the parsing results into object model data and then output them. The protocol data and object model data interactive mapping module converts the physical data in the parsing results into object model data according to the preset object model and protocol mapping relationship. Figure 7 ,The object model is a description of the behavioral characteristics of a real object. An object model has multiple attributes, and each attribute has a minimum element value. ,Reflective memory protocol data belongs to the hardware application protocol, which is generally a simple linear structure, transmitted in the form of data frames, and associated with the preset object model and protocol to achieve interactive mapping between protocol data and object model data.

[0038] In order to further implement the above technical solution, the object model data obtained by the data conversion module is output to the external system through Gigabit Ethernet. Specifically, Realtek RTL8211E-VL can be selected as the Ethernet PHY chip. This chip supports 10 / 100 / 1000Mbps adaptive network transmission rate, can meet the requirements of Bayer Ethernet rate, and can be used as a Gigabit Ethernet network interface for future expansion applications. In specific implementation, the Ethernet PHY chip can be connected to the GPIO interface of BANK501 on the PS end of the Zynq chip, and communicate data with the MAC layer of the PS system through the RGMII interface. The PS end of the Zynq chip supports up to 4 Ethernet ports. The present invention leads to two Gigabit Ethernet ports through the PS end, one of which is responsible for data interaction with the host computer, and the other is used as an external communication interface of the low-frequency signal device. Four low-frequency signal devices provide four Gigabit Ethernet ports to meet the application requirements of 2 100M Ethernet ports.

[0039] Specific as Figure 8 As shown, in terms of power supply, +3.3V and +1.8V power supplies provide the total power supply to RTL8211E-VL, and 3.3V and 1.05V voltages are generated by the internal switching regulator, and then supplied to the network chip itself after voltage stabilization; if RTL8211E-VL needs to support a baud rate of 1000M, an external clock is required to provide a 25M or 50M clock, and an active crystal oscillator is used here; the MAC of Zynq7000 PS is connected to the transmit and receive pins of the PCS layer of RTL8211E-VL, and the GPIO is connected to the management interface for data transmission and management; the MDI interface of RTL8211E-VL is connected to the RJ45 with a transformer. At the same time, the chip has an LED management function to control the LED of RJ45 to indicate the network status.

[0040] In another embodiment, the Zynq series SOC platform and embedded GPU module can be used to construct a device framework to form a Zynq SOC acceleration engine part and a GPU acceleration module, wherein the Zynq SOC acceleration engine part is composed of a large-capacity data storage, a configuration storage, a main processor ARM, and a computing acceleration engine implemented by programmable logic. The data storage controller is composed of a large-capacity Micro SD card to realize the input protocol data cache required for rapid protocol recognition calculation, the recognition result data storage, and the storage of customized function acceleration engine configuration information. The heterogeneous resource protocol data splitting is performed in the ARM processor, and the main part of the protocol recognition runs in the function accelerator to complete the protocol recognition in real time.

[0041] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0042] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A real-time processing device for reflective memory protocol data, characterized in that: include: A reflective memory interface module for transmitting protocol data packets; The protocol processing module is used to extract multiple protocol data in the protocol data packet according to the preset protocol template and then perform parallel matching and identification; Perform element parsing on the identified protocol data to obtain a parsing result; The data conversion module is used to convert the parsing results into object model data and then output them.

2. A device for real-time processing of reflective memory protocol data according to claim 1, characterized in that: The protocol processing module includes a protocol identification module and a protocol automatic parsing module; The protocol identification module is used to receive the protocol data packet and the protocol template identification to generate a plurality of protocol data with template numbers; The protocol automatic parsing module is used to locate the protocol template according to the template number corresponding to the protocol data, and parse each element in the protocol according to the protocol description template to obtain a parsing result.

3. A real-time processing device for reflective memory protocol data according to claim 2, characterized in that: The protocol processing module also includes a protocol automatic packaging module, which is used to receive the physical data sent by the protocol conversion module, package it according to the protocol template, and output the packaged data packets to the reflective memory interface module.

4. A real-time processing device for reflective memory protocol data according to claim 2 or 3, characterized in that: The protocol identification module includes a plurality of protocol matching units, each of which includes a byte counter, a frame header storage area and a comparison unit; The frame header storage area stores frame header data and outputs a corresponding number of frame header bytes to the comparison unit according to the byte counter; The comparison unit receives the frame header byte and matches the frame header template in the protocol template, and outputs a matching result.

5. The device for real-time processing of reflective memory protocol data according to claim 4, characterized in that: The protocol identification unit also includes an auxiliary logic unit, which is used to obtain the matching progress status of each of the protocol matching units and generate corresponding signal outputs.

6. A device for real-time processing of reflective memory protocol data according to claim 5, characterized in that: The auxiliary logic unit includes an AND module, a first OR module, a second OR module, a priority encoder and a trigger; The AND module is used to obtain the matching completion signal of each of the protocol matching units, and record the matching completion status and the starting effective time; The first or module is used to obtain the matching result signals of each of the protocol matching units and summarize and generate a final matching result; The second or module is used to obtain the matching occurrence signal of each of the protocol matching units to confirm the matching progress status; The priority encoder is used to obtain the matching occurrence signal of each of the protocol matching units, and perform priority encoding on the corresponding protocol matching unit according to the matching progress status.

7. The device for real-time processing of reflective memory protocol data according to claim 6, characterized in that: The protocol matching unit also includes matching signal generation logic, matching completion signal generation logic and rising edge detection logic; The matching completion signal generation logic is used to obtain the matching result output by the comparison unit, the count value output by the byte counter and the frame header length, and generate a matching completion signal; The matching signal generation logic is used to obtain the matching result output by the comparison unit, the count value output by the byte counter and the frame header length, generate a matching result signal, and generate a matching occurrence signal through a rising edge detection logic.

8. The device for real-time processing of reflective memory protocol data according to claim 4, characterized in that: The comparison unit has a memory function for recording the matching results of each byte during byte-by-byte comparison.

9. The device for real-time processing of reflective memory protocol data according to claim 1, characterized in that: The data conversion module includes a protocol data and object model data interactive mapping module, which converts physical data in the parsing result into object model data according to a preset object model and protocol mapping relationship.

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