Image preprocessing method and system based on FPGA
By implementing image preprocessing methods on FPGA, including grayscale transformation, denoising and background superposition, the problems of complex algorithms and low resource utilization efficiency in the prior art are solved, and the practicality and quality of image processing are improved.
Patent Information
- Application Number
- CN202411475210.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2024-12-27
AI Technical Summary
In the prior art, the image preprocessing algorithm is complex and cannot effectively utilize few logical resources, resulting in poor practical effect in subsequent secondary development.
Using FPGA-based image preprocessing methods, including grayscale transformation, image denoising and background superposition, it can replace floating-point operations through monochrome channel extraction, mean filtering, median filtering, Alpha channel control and magnification, and achieve high efficiency. image preprocessing.
It improves image display effect and quality, simplifies algorithms, reduces the use of logical resources, and reserves specific image processing module interfaces for subsequent development.
Smart Images
Figure CN119211449A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of image preprocessing, and in particular relates to an image preprocessing method and system based on FPGA. Background Art
[0002] In the process of image acquisition and transmission, noise is usually generated, which reduces the image quality and affects subsequent processing. Therefore, it is necessary to perform some preprocessing on the image, such as image filtering and image enhancement. Image preprocessing technology has been widely valued in many application fields and has achieved significant pioneering achievements. These fields include aerospace, biomedical engineering, industrial detection, robot vision, public security and justice, military guidance, culture and art, etc., making image processing a new discipline with a striking and promising future. With the in-depth development of image processing technology, since the mid-1970s, with the rapid development of computer technology, artificial intelligence, and thinking science research, digital image processing has developed to a higher and deeper level. People have begun to study how to interpret images with computer systems to achieve a similar understanding of the external world as the human visual system, which is called image understanding or computer vision. Many countries have invested more manpower and material resources in this research and have achieved many important research results. Among them, the representative achievement is the visual computing theory proposed by Marr of MIT in the late 1970s. This theory has become the dominant idea in the field of computer vision for more than ten years. Although image understanding has made considerable progress in theoretical research, it is a relatively difficult research field and faces many difficulties. Since humans themselves know very little about their own visual processes, computer vision is a new field that needs further exploration.
[0003] FPGA is a programmable logic device with high flexibility and programmability. It can realize different functions through programming. In the field of image processing, FPGA can implement various image processing algorithms and technologies, such as image filtering, edge detection, image segmentation, etc.
[0004] Through the above analysis, the problems and defects of the existing technology are as follows: the algorithm in the image preprocessing of the existing technology is complex, and it cannot use a small amount of logical resources for image preprocessing, and the practical effect is poor in the subsequent secondary development to achieve specific image processing. Summary of the invention
[0005] In order to overcome the problems existing in the related art, the disclosed embodiments of the present invention provide an image preprocessing method and system based on FPGA, and specifically relate to an image preprocessing combination algorithm implementation method based on FPGAK7 series.
[0006] The technical solution is as follows: an image preprocessing method based on FPGA, comprising:
[0007] S1, grayscale conversion function module FPGA implementation; collect information of two consecutive lines of video data stored in the dual-port RAM inside the FPGA, and use the method of monochrome channel extraction to realize grayscale conversion and display;
[0008] S2, image denoising function module FPGA implementation; image denoising is processed in FPGA through mean filtering and median filtering;
[0009] S3, background overlay and image scaling function module FPGA implementation; add Alpha channel in FPGA to control the transparency of displayed objects; replace floating point operations with magnification to achieve image background overlay, and after image background overlay, reduce the image resolution and display it on the screen.
[0010] In step S1, the method for monochrome channel extraction includes: extracting pixel point information of one channel in a 2*2 GBRG array, replacing pixel point information of other three channels with a fixed position in the 2*2 array, and the fixed position image only contains grayscale information of one color.
[0011] In step S1, the grayscale conversion function module is implemented by FPGA, including: designing a dual-port RAM inside the FPGA to store information of two consecutive rows of video data, then reading out the even columns of the even rows and the odd columns of the odd rows, and reading each pixel value twice in succession, and using the monochrome channel extraction method to obtain the numerical information of a single channel of a 2*2 matrix to achieve grayscale conversion and display.
[0012] In step S2, the mean filter performs image noise reduction processing in the FPGA, including:
[0013] In FPGA, shift_RAM shift register is used to cache video data from 2 to 3 lines, and the 3*3 pixel matrix window is realized by using the register beat delay method to obtain the result after cmos_data accumulation;
[0014] The accumulated result of cmos_data is processed by averaging; the accumulated result of cmos_data is multiplied by 1024 and then divided, the value of 1024 divided by 9 is calculated in advance, multiplied by the accumulated sum, and then divided by 1024 to obtain the final value;
[0015] The mean calculation formula is: cmos_data*(64+32+16+1) / 1024.
[0016] In step S2, the median filter performs image noise reduction processing in the FPGA, including:
[0017] Data cache: Design a RAM-based shift register inside the FPGA and control the parameters of the RAM-based shift register, which are the bit width of the data and the number of taps of the shift register.
[0018] Matrix generation: Perform register tapping delay processing on each row of pixel data output from the taps export, perform register caching twice, and the data output by the delay register is the value of a 3*3 matrix;
[0019] Sorting method: Sort the 3*3 matrix in real time.
[0020] Furthermore, in the data cache, the shift_RAM shift register includes three taps outlets, the spacing of each taps is set to 640, each taps stores one row of pixel data, and a total of three rows of image pixel data are stored; at each rising edge of the clock, the pixel data is simultaneously moved in the shift_RAM, and data is moved out of the taps outlet at each moment.
[0021] In step S3, an Alpha channel is added in the FPGA to control the transparency of the displayed object, including:
[0022] The three images are a, b, and c. Image c is the mixed image effect produced by viewing image a through image b. Alpha is used as the transparency of image b, and the value range is 0 to 1; 1 means complete transparency, and 0 means complete opacity. The mixing formula is as follows:
[0023] R(c)=Alpha×R(a)+(1-Alpha)×R(b)
[0024] G(c)=Alpha×R(a)+(1-Alpha)×R(b)
[0025] B(c)=Alpha×R(a)+(1-Alpha)×R(b)
[0026] Where R(c), B(c) and G(c) are the RGB pixel components of image c;
[0027] For the monochrome channel, the background image is assigned 0.25 and the original image is assigned 0.75, which means that the transparency of the background is 75% and the transparency of the original image is 25%. The background image and the original image are superimposed to achieve the effect of image background superposition. The specific calculation formula is as follows:
[0028] Result = 0.75 × I + 0.25 × J
[0029] Among them, I is the RGB value of the original image, J is the RGB value of the background image, and Result is the value after background superposition.
[0030] In the implementation of image background overlay, it is also necessary to select the magnification instead of floating-point operations, and the equation transformation through the magnification is as follows:
[0031] 4×Result=3×I+J=I+2×I+J.
[0032] In step S3, after the image background is superimposed, the image is reduced in resolution and displayed on the screen, including:
[0033] For dual-channel videos captured by two CMOS image sensors, the resolution of 640*480 is reduced to 320*240 and displayed in a quarter of the screen area. Valid rows or columns are extracted at equal intervals and written into the memory.
[0034] Another object of the present invention is to provide an FPGA-based image preprocessing system, which is implemented by an FPGA-based image preprocessing method, and the system includes:
[0035] Grayscale conversion function module, used to collect information of two consecutive lines of video data stored in the dual-port RAM inside the FPGA, and realize grayscale conversion and display by using the method of monochrome channel extraction;
[0036] Image denoising function module, used to reduce the noise of the image in FPGA through mean filtering and median filtering;
[0037] The background overlay and image scaling function module is used to add an Alpha channel in the FPGA to control the transparency of the displayed object; the image background overlay is realized by replacing the floating-point operation with the magnification factor; after the image background is overlaid, the image resolution is reduced and displayed on the screen.
[0038] In combination with all the above technical solutions, the beneficial effects of the present invention are as follows: the present invention provides a simple and efficient method for implementing a combined algorithm for image preprocessing, which performs a pipeline combination of grayscale transformation + image denoising + background overlay + image scaling on the image data collected in the early stage, and implements the algorithm in an FPGA digital logic circuit according to the characteristics of the programmable logic device itself, thereby improving the display effect and quality of the video. The present invention focuses on the efficient implementation process of the combined application of basic image preprocessing algorithms such as grayscale transformation, denoising, Alpha background overlay and image scaling in the FPGA, performs image preprocessing with a simpler algorithm and fewer logic resources, and reserves an interface for subsequent secondary development to implement specific image processing algorithm modules. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;
[0040] Figure 1 is a flow chart of an image preprocessing method based on FPGA provided by an embodiment of the present invention;
[0041] Figure 2 is a schematic diagram of a method for extracting a single color channel provided by an embodiment of the present invention;
[0042] Figure 3 It is a schematic diagram of the principle of a dual-port RAM provided by an embodiment of the present invention;
[0043] Figure 4 is a schematic diagram of the mean filtering principle provided by an embodiment of the present invention;
[0044] Figure 5 is a design principle diagram of a shift_RAM provided in an embodiment of the present invention;
[0045] Figure 6 It is a schematic diagram of the median filtering based on sorting statistics provided by an embodiment of the present invention;
[0046] Figure 7 It is a schematic diagram of the interface of the shift_RAM provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.
[0048] Embodiment 1, as Figure 1 As shown, the FPGA-based image preprocessing method provided by the embodiment of the present invention includes:
[0049] S1, grayscale conversion function module FPGA implementation; collect information of two consecutive lines of video data stored in the dual-port RAM inside the FPGA, and use the method of monochrome channel extraction to realize grayscale conversion and display;
[0050] In the field of image processing, it is not convenient to increase the processing speed by directly processing color images, because color images contain a large amount of data. In most applications, people do not care about color information, and the same is true for the security monitoring industry. Therefore, converting color images into grayscale images is an important processing method. After processing the color image, if R=G=B, the output image is a grayscale image. Therefore, by putting the same grayscale value in each RGB channel, the conversion of color images to grayscale images can be completed.
[0051] The most commonly used image grayscale transformations are the following:
[0052] Average value method: The average value method is the simplest method. In grayscale images, R=G=B. Therefore, the average value method directly adds the three pixel components of RGB and divides by three. The calculation formula is as follows to get the grayscale value of the pixel. However, the image obtained by this method is overall darker. This is because in a frame of image, the information weights of the three RGB channels are different. Simply adding and taking the average value will cause the loss of image information.
[0053] GRAY=(R+G+B) / 3
[0054] Among them, GRAY is the grayscale value, and R, G, and B are the red, green, and blue pixel information respectively.
[0055] Weight method: This method considers the weight of the amount of information provided by the three RGB channels in a frame of image. Through a large number of experiments, the empirical formula is summarized as follows. By increasing the proportion of the G component and reducing the proportion of the R and B components, the color image can be converted to grayscale.
[0056] GRAY=R×0.299+G×0.587+B×0.114
[0057] The method used in the FPGA implementation method of the present invention is a method of monochromatic channel extraction, such as Figure 2 As shown, in the 2*2 GBRG array, the pixel information of one channel is extracted, that is, a fixed position in the 2*2 array is used to replace the pixel information of the other three channels, so that the image only contains the grayscale information of one color, and finally the grayscale transformation and display of the image are realized.
[0058] Once you understand the implementation principle of the algorithm, you can implement it on FPGA. Design a dual-port RAM inside the FPGA to store the information of two consecutive rows of video data, then read out the even columns of even rows and the odd columns of odd rows, and read each pixel value twice in succession. Finally, you get a 2*2 matrix, which is the numerical information of a channel, to achieve grayscale conversion and display. Figure 3The figure shows a schematic diagram of a dual-port RAM, where cmos_data is the information of the input pixel point, and q_data is the information of the pixel point at a specific position read by controlling the read address.
[0059] S2, image denoising function module FPGA implementation; image denoising is processed in FPGA through mean filtering and median filtering;
[0060] The COMS image sensor will be affected by temperature during the charge conversion process, and errors will also occur during the A / D conversion of the image signal. It is inevitable that the collected image has noise signals, so the image must be denoised. Image noise can be divided into salt and pepper noise, impulse noise, and Gaussian noise. Salt and pepper noise will cause random black and white dots to appear in the image; white bright spots will appear in the impulse noise image; Gaussian noise is a type of impulse noise, but the grayscale value distribution satisfies the Gaussian distribution. The current image denoising method is mainly to filter the image. This invention will introduce the implementation method of mean filtering and median filtering.
[0061] First, perform mean filtering. Mean filtering noise reduction is a linear filtering method. Compared with other filtering methods, this method is relatively simple. Figure 4 As shown in the figure, a mean filter template is given. This template contains the information of the pixels around the target pixel. The target pixel in the middle of the image is replaced by the average value of all pixels in the template. For a 3*3 pixel matrix, the value of the midpoint pixel p22 is equal to the average value of all pixel values. The calculation formula is as follows:
[0062] Pmean=(p11+p12+p13+p21+p22+p23+p11+p12+p13) / 9
[0063] Among them, Pmean is the average value of the surrounding pixels, and p11-p12 are the surrounding pixels of p22 respectively.
[0064] The implementation of the mean filter algorithm in FPGA requires caching 2 to 3 lines of video data, and then using the register beat delay method to implement a 3*3 pixel matrix window. The data cache can be implemented by designing a dual-port RAM inside the FPGA, or by designing a shift_RAM (shift register). This design uses shift_RAM. The design principle of shift_RAM is as follows Figure 5 After the shift_RAM is designed, it can be instantiated at the top level and the corresponding code can be implemented.
[0065] The final cmos_data is the result of accumulation, and it needs to be averaged. The specific implementation method is: multiply the accumulated result of cmos_data by 1024 and then divide it. You can calculate the value of 1024 divided by 9 in advance, multiply it by the accumulated sum, and then divide it by 1024 to get the final value.
[0066] The mean calculation formula is: cmos_data*(64+32+16+1) / 1024.
[0067] Further median filtering is performed. Median filtering is a nonlinear signal processing technology that can effectively suppress salt and pepper noise. It is often used to protect image edge information in image processing. Its basic principle is to replace the target pixel in the image with the median value of the pixel values of each point in its neighborhood template. This median filtering technology is based on the sorting statistical theory. The values of all grayscale pixel points in the n*n matrix are sorted by size to find the median value to replace the original pixel, such as Figure 6 shown.
[0068] The implementation process of median filtering on FPGA can be divided into three steps:
[0069] Data cache: Designing a RAM-based shift register inside the FPGA can easily cache large amounts of data without occupying other logic resources. The main parameters that need to be controlled during the design process are the data bit width and the number of shift register taps outputs. The data output from the shift register can be used for other operations.
[0070] like Figure 7 The figure shows the interface diagram of shift_RAM. In the design, a 3*3 matrix is used for filtering. Therefore, three taps outlets need to be designed in shift_RAM. The spacing of each tap is set to 640, which means that each tap needs to store 1 row of pixel data, and a total of 3 rows of image pixel data need to be stored. At the rising edge of each clock, the pixel data moves simultaneously in shift_RAM, and data is moved out of the taps outlet at every moment.
[0071] like Figure 7 The figure shows the interface diagram of shift_RAM. In the design, a 3*3 matrix is used for filtering. Therefore, three taps outlets need to be designed in shift_RAM. The spacing of each tap is set to 640, which means that each tap needs to store 1 row of pixel data, and a total of 3 rows of image pixel data need to be stored. At the rising edge of each clock, the pixel data moves simultaneously in shift_RAM, and data is moved out of the taps outlet at every moment.
[0072] Sorting method: The key to implementing median filtering is to sort the 3*3 matrix in real time. The traditional median filtering sorting method uses the bubble method to compare pixel values and find the middle value. The implementation process is relatively complicated and time-consuming.
[0073] S3, background overlay and image scaling function module FPGA implementation; add Alpha channel in FPGA to control the transparency of displayed objects; replace floating point operations with magnification to achieve image background overlay, and after image background overlay, reduce the image resolution and display it on the screen.
[0074] Alpha background overlay represents the transparent blending of an image, which can make an object transparent and achieve a semi-transparent effect of the background color. Assuming that the pixel points already exist in the three channels of R, G, and B, now a set of channels needs to be added to control the transparency of the displayed object. The added channel is the Alpha channel.
[0075] Assume there are three images, a, b, and c. Image c is the mixed image effect produced by viewing image a through image b. Therefore, Alpha can be used as the transparency of image b, with a value range of 0 to 1. 1 means completely transparent, and 0 means completely opaque. The mixing formula is as follows:
[0076] R(c)=Alpha×R(a)+(1-Alpha)×R(b)
[0077] G(c)=Alpha×R(a)+(1-Alpha)×R(b)
[0078] B(c)=Alpha×R(a)+(1-Alpha)×R(b)
[0079] Where R(c), B(c) and G(c) are the RGB pixel components of image c;
[0080] It is not difficult to see that Alpha is the value that controls the transparency of the image, so the semi-transparency effect can be achieved by changing the value of Alpha.
[0081] For example, here we take the monochrome channel as an example, assigning the background image to 0.25 and the original image to 0.75, which means the transparency of the background is 75% and the transparency of the original image is 25%. By overlaying the background image and the original image, the effect of image background overlay can be achieved. The specific calculation formula is as follows:
[0082] Result = 0.75 × I + 0.25 × J
[0083] Among them, I is the RGB value of the original image, J is the RGB value of the background image, and Result is the value after background superposition.
[0084] Since FPGA is not suitable for floating-point operations, shift operations or magnifications are selected to replace floating-point operations when implementing the algorithm. The present invention transforms the equation by magnification as follows:
[0085] 4×Result=3×I+J=I+2×I+J
[0086] The formula can be expressed in Verilog HDL code as:
[0087] wire[9:0]result;
[0088] assign rseult=data+(cmos_data*2+cmos_data);
[0089] always@(posedge sclk)
[0090] cmos_data_o<=result[9:2];
[0091] The resolution of the camera is 640*480. In order to display the dual-channel videos captured by the two CMOS image sensors on the same monitor without distortion, the resolution of 640*480 can be reduced to 320*240 and displayed in a quarter of the screen. It is only necessary to extract valid rows or columns at equal intervals, that is, extract once every two rows or columns and write them into the memory.
[0092] Since it is a dual-channel camera, writing every two columns into the memory can realize the reduced display of 4 images. The upper two are the images of the first camera, and the lower two are the images of the second camera. It is only necessary to write to the memory when the column counter is an even number, and the write addresses of the two cameras can be seamlessly connected.
[0093] Embodiment 2, the embodiment of the present invention provides an image preprocessing system based on FPGA, the system comprising:
[0094] Grayscale conversion function module, used to realize grayscale conversion and display of two consecutive lines of video data stored in the dual-port RAM inside the FPGA by using the method of monochrome channel extraction;
[0095] Image denoising function module, used to perform image denoising in FPGA through mean filtering and median filtering;
[0096] The background overlay and image scaling function module is used to add an Alpha channel in the FPGA to control the transparency of the displayed object, and replace the floating-point operation with the magnification factor to achieve image background overlay. After the image background is overlaid, the image resolution is reduced and displayed on the screen.
[0097] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0098] Since the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present invention, their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.
[0099] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment.
[0100] An embodiment of the present invention further provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program.
[0101] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.
[0102] An embodiment of the present invention further provides an information data processing terminal, which, when executed on an electronic device, provides a user input interface to implement the steps in the above method embodiments. The information data processing terminal is not limited to mobile phones, computers, and switches.
[0103] An embodiment of the present invention further provides a server, which is used to provide a user input interface to implement the steps in the above method embodiments when executed on an electronic device.
[0104] An embodiment of the present invention provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.
[0105] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.
[0106] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.
Claims
1. An image preprocessing method based on FPGA, characterized in that: The method includes: S1, grayscale conversion function module FPGA implementation; collect information of two consecutive lines of video data stored in the dual-port RAM inside the FPGA, and use the method of monochrome channel extraction to realize grayscale conversion and display; S2, image denoising function module FPGA implementation; image denoising is processed in FPGA through mean filtering and median filtering; S3, background overlay and image scaling function module FPGA implementation; add Alpha channel in FPGA to control the transparency of displayed objects; replace floating point operations with magnification to achieve image background overlay, and after image background overlay, reduce the image resolution and display it on the screen.
2. The FPGA-based image preprocessing method according to claim 1, characterized in that: In step S1, the method for monochrome channel extraction includes: extracting pixel point information of one channel in a 2*2 GBRG array, replacing pixel point information of other three channels with a fixed position in the 2*2 array, and the fixed position image only contains grayscale information of one color.
3. The FPGA-based image preprocessing method according to claim 1, characterized in that: In step S1, the grayscale conversion function module is implemented by FPGA, including: designing a dual-port RAM inside the FPGA to store information of two consecutive rows of video data, then reading out the even columns of the even rows and the odd columns of the odd rows, and reading each pixel value twice in succession, and using the monochrome channel extraction method to obtain the numerical information of a single channel of a 2*2 matrix to achieve grayscale conversion and display.
4. The FPGA-based image preprocessing method according to claim 1, characterized in that: In step S2, the mean filter performs image noise reduction processing in the FPGA, including: In FPGA, shift_RAM shift register is used to cache video data from 2 to 3 lines, and the 3*3 pixel matrix window is realized by using the register beat delay method to obtain the result after cmos_data accumulation; The accumulated result of cmos_data is processed by averaging; the accumulated result of cmos_data is multiplied by 1024 and then divided, the value of 1024 divided by 9 is calculated in advance, multiplied by the accumulated sum, and then divided by 1024 to obtain the final value; The mean calculation formula is: cmos_data*(64+32+16+1) / 1024.
5. The FPGA-based image preprocessing method according to claim 1, characterized in that: In step S2, the median filter performs image noise reduction processing in the FPGA, including: Data cache: Design a RAM-based shift register inside the FPGA and control the parameters of the RAM-based shift register, which are the bit width of the data and the number of taps of the shift register. Matrix generation: Perform register tapping delay processing on each row of pixel data output from the taps export, perform register caching twice, and the data output by the delay register is the value of a 3*3 matrix; Sorting method: Sort the 3*3 matrix in real time.
6. The FPGA-based image preprocessing method according to claim 5, characterized in that: In the data cache, the shift_RAM shift register includes three taps exports, the spacing of each tap is set to 640, each tap stores 1 row of pixel data, and a total of 3 rows of image pixel data are stored; at the rising edge of each clock, the pixel data moves simultaneously in the shift_RAM, and data is moved out of the taps export at each moment.
7. The FPGA-based image preprocessing method according to claim 1, characterized in that: In step S3, an Alpha channel is added in the FPGA to control the transparency of the displayed object, including: The three images are a, b, and c. Image c is the mixed image effect produced by viewing image a through image b. Alpha is used as the transparency of image b, and the value range is 0 to 1; 1 means complete transparency, and 0 means complete opacity. The mixing formula is as follows: R(c)=Alpha×R(a)+(1-Alpha)×R(b) G(c)=Alpha×R(a)+(1-Alpha)×R(b) B(c)=Alpha×R(a)+(1-Alpha)×R(b) Where R(c), B(c) and G(c) are the RGB pixel components of image c; For the monochrome channel, the background image is assigned 0.25 and the original image is assigned 0.75, which means that the transparency of the background is 75% and the transparency of the original image is 25%. The background image and the original image are superimposed to achieve the effect of image background superposition. The specific calculation formula is as follows: Result = 0.75 × i + 0.25 × J Among them, I is the RGB value of the original image, J is the RGB value of the background image, and Result is the value after background superposition.
8. The FPGA-based image preprocessing method according to claim 7, characterized in that: In the implementation of image background overlay, it is also necessary to select the magnification instead of floating-point operations, and the equation transformation through the magnification is as follows: 4×Result=3×I+J=I+2×I+J.
9. The FPGA-based image preprocessing method according to claim 1, characterized in that: In step S3, after the image background is superimposed, the image is reduced in resolution and displayed on the screen, including: For dual-channel videos captured by two CMOS image sensors, the resolution of 640*480 is reduced to 320*240 and displayed in a quarter of the screen area. Valid rows or columns are extracted at equal intervals and written into the memory.
10. An image preprocessing system based on FPGA, characterized in that: The system is implemented by the FPGA-based image preprocessing method according to any one of claims 1 to 9, and the system comprises: Grayscale conversion function module, used to collect information of two consecutive lines of video data stored in the dual-port RAM inside the FPGA, and realize grayscale conversion and display by using the method of monochrome channel extraction; Image denoising function module, used to reduce the noise of the image in FPGA through mean filtering and median filtering; The background overlay and image scaling function module is used to add an Alpha channel in the FPGA to control the transparency of the displayed object; the image background overlay is realized by replacing the floating-point operation with the magnification factor; after the image background is overlaid, the image resolution is reduced and displayed on the screen.