Image sensor and readout circuit thereof

Abstract

The invention provides an image sensor and a readout circuit thereof, the readout circuit of the image sensor is formed by connecting a ramp voltage circuit, a comparison circuit, a counter circuit and a negation control circuit, when counting is switched, the negation control circuit is set to control the counter circuit to negate a first digital code value into a second digital code value, and the second digital code value is converted into a second digital code value. In the second quantization time period, the counter circuit counts into a third digital code value on the basis of the second digital code value, correlated double sampling is achieved, fixed mode noise is eliminated, the imaging quality is improved, a buffer and an additional holding circuit do not need to be arranged in the reading circuit, the circuit structure is simplified, power consumption is reduced, and the cost is reduced. The counter circuit can be ensured to work in a high-frequency counting mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of image sensors, and in particular relates to an image sensor and a readout circuit thereof. Background Art

[0002] CMOS image sensors have the advantages of low voltage, low power consumption, low cost and high integration, and have important application value in the fields of machine vision, consumer electronics, high-definition monitoring and medical imaging. The analog-to-digital converter (ADC) is an important part of the readout circuit of the CMOS image sensor, and is responsible for converting the analog signal output by the pixel into a digital signal. Column-level ADCs are generally used in CMOS image sensors, and the common ones are single slope ADC (SS SDC), successive approximation ADC (SAR ADC) and cyclic ADC (Cyclic ADC).

[0003] The counter in a traditional SS ADC is generally a reversible counter, that is, it can switch between up / down counting. Figure 1 As shown in FIG. 1 , the N-bit counter circuit is composed of cascaded counter units. When count_up is 1, the output signal QB of the inverting output terminal of this stage is used as the clock signal of the next stage, which is an upward counting mode; when count_up is 0, the output signal Q of the positive output terminal of this stage is used as the clock signal of the next stage, which is a downward counting mode. After the two counting stops, the final counting result D <n-1:0>Stored in memory.

[0004] Since the operating frequency of count_clk is very high (usually hundreds of MHz or even more than 1GHz), the traditional reversible counter needs to insert a two-choice data selector and a buffer for driving between each level of counter units, which increases power consumption. At the same time, the structure faces the problem of keeping the first quantization result stable during the up / down counting switching, and an additional holding circuit is required, which makes the circuit layout more complicated, increases the parasitic capacitance and resistance of the routing, further increases the power consumption, and limits the maximum operating frequency of the counter. Summary of the invention

[0005] The object of the present invention is to provide a readout circuit of an image sensor, aiming to solve the problems of high power consumption and complex structure of a traditional reversible counter.

[0006] A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, comprising:

[0007] A ramp voltage circuit configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively;

[0008] a comparison circuit, wherein a first input terminal of the comparison circuit is connected to the pixel unit, and a second input terminal of the comparison circuit is connected to the ramp voltage circuit, and is configured to compare a reset signal or a pixel signal output by the pixel unit with the ramp voltage signal, and output a reset pulse signal or a pixel pulse signal;

[0009] a counter circuit connected to the comparison circuit, configured to count the first pulse signal in the first quantization time period and store the first digital code value; in the second quantization time period, the counter circuit counts the second pulse signal based on the second digital code value and stores it as a third digital code value, the first pulse signal and the second pulse signal are the reset pulse signal and the pixel pulse signal to each other;

[0010] An inversion control circuit is connected to the counter circuit. Between the first quantization time period and the second quantization time period, the inversion control circuit is triggered by a mode selection signal to output an inversion control signal, so that the counter circuit is triggered by the inversion control signal to invert the first digital code value into the second digital code value and store it.

[0011] A second aspect of an embodiment of the present invention provides an image sensor, comprising a pixel array, a control circuit, and a plurality of readout circuits of the image sensor as described above, wherein the pixel array comprises a plurality of pixel units arranged in an array;

[0012] The readout circuit of each of the image sensors is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit of each of the image sensors is also respectively connected to the control circuit.

[0013] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the readout circuit of the above-mentioned image sensor is connected by a ramp voltage circuit, a comparison circuit, a counter circuit and an inversion control circuit. When switching counting, the counter circuit is controlled by setting the inversion control circuit to invert the first digital code value into a second digital code value, so that in the second quantization time period, the counter circuit counts the second digital code value as a third digital code value, thereby realizing correlated double sampling, eliminating fixed pattern noise, and improving imaging quality. In addition, in the readout circuit, there is no need to set a buffer and an additional holding circuit, which simplifies the circuit structure, reduces power consumption, and ensures that the counter circuit operates in a high-frequency counting mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0015] Figure 1 is a circuit diagram of a traditional counter circuit;

[0016] Figure 2 A schematic diagram of the structure of an image sensor provided in Embodiment 6 of the present invention;

[0017] Figure 3 for Figure 2 A circuit diagram of a pixel unit in the image sensor shown;

[0018] Figure 4 A schematic diagram of the structure of a readout circuit provided in Embodiment 1 of the present invention;

[0019] Figure 5 A schematic diagram of the structure of a readout circuit provided in Embodiment 2 of the present invention;

[0020] Figure 6 A circuit diagram of a readout circuit provided in Embodiment 3 of the present invention;

[0021] Figure 7 A schematic diagram of the signal timing of the readout circuit provided in Embodiment 3 and Embodiment 4 of the present invention;

[0022] Figure 8 A circuit diagram of a readout circuit provided in Embodiment 4 of the present invention;

[0023] Fig. 9 A schematic diagram of the structure of a D flip-flop provided in Embodiment 3 and Embodiment 4 of the present invention;

[0024] Fig.10 A schematic diagram of the structure of a readout circuit provided in Embodiment 5 of the present invention;

[0025] Fig.11 for Fig.10 The circuit diagram of the storage circuit in the readout circuit is shown. DETAILED DESCRIPTION

[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0028] Embodiment 1

[0029] A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, such as Figure 2 As shown, the image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may also include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array, and a plurality of pixel units arranged in columns are connected in common. The control circuit 3 selects the pixel units in each row through a row selection signal, and sequentially outputs the pixel signals of each row to the readout circuit 1. The plurality of pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3, so that the control circuit 3 determines the image information according to the digital code value.

[0030] Among them, the pixel unit generally includes a photoelectric conversion element, a transmission transistor TX, a reset transistor RST, a source follower transistor SF and a row selection transistor SEL, wherein the photoelectric conversion element includes but is not limited to a photodiode PD, such as a Pin-type photodiode PD, and at the same time, the number of the photoelectric conversion element, the transmission transistor TX, the reset transistor RST, the source follower transistor SF and the row selection transistor SEL can be one or more, that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited, such as Figure 3 As shown, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, wherein the cathode of the photodiode PD is connected to the first end of the transfer transistor TX, the second end of the transfer transistor TX, the first end of the reset transistor RST, and the controlled end of the source follower transistor SF are all coupled to the floating diffusion node, the anode of the photodiode PD is grounded, the second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD, the second end of the source follower transistor SF is connected to the first end of the row selection transistor SEL, and the second end of the row selection transistor SEL constitutes the output end of the pixel unit 2 and is used to output the corresponding pixel signal.

[0031] CMOS image sensors using a readout circuit 1 arranged in columns face the problem of fixed pattern noise FPN. This is because the threshold voltages of transistors in each column of pixels are mismatched to a certain extent due to factors such as process and temperature. Under the same lighting conditions, the mismatch will cause the column consistency of the pixel output signal to deteriorate. Figure 3 The 4T active pixel structure shown can perform a Correlated Double Sampling (CDS) operation to read out the reset signal Vrst and the exposure signal Vsig of the pixel respectively, and then make a difference between the two. Since the two signals contain the same fixed pattern noise (FPN), the FPN can be eliminated by making a difference, thereby improving the imaging quality.

[0032] The common CDS operation is to use two ramp signals in the SS ADC to quantize the reset signal Vrst and the exposure signal Vsig of the pixel twice, and control the counter circuit to count down and up respectively during the two quantization periods, so as to make a difference in the analog voltage value output by the pixel in the digital domain. Therefore, the counter circuit in this structure is a reversible counter, that is, it can realize the switching between counting up and counting down, such as Figure 1 As shown in FIG. 1 , the N-bit counter circuit is composed of cascaded counter units. When count_up is 1, the output signal QB of the inverting output terminal of this stage is used as the clock signal count_clk of the next stage, which is an upward counting mode; when count_up is 0, the output signal Q of the positive output terminal of this stage is used as the clock signal count_clk of the next stage, which is a downward counting mode. After the two counting stops, the final counting result D <n-1:0>Stored in memory.

[0033] Since the operating frequency of count_clk is very high (usually hundreds of MHz or even more than 1GHz), the traditional reversible counter needs to insert a two-choice data selector MUX1 and a buffer for driving between each level of counter units, which increases power consumption. At the same time, the structure faces the problem of keeping the first quantization result stable during the up / down counting switching, and requires an additional holding circuit, which makes the circuit layout more complicated, increases the parasitic capacitance and resistance of the routing, further increases power consumption, and limits the maximum operating frequency of the counter.

[0034] In order to solve the above technical problems, Figure 4 As shown, in this embodiment, the readout circuit 1 of the image sensor includes:

[0035] The ramp voltage circuit 10 is configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively;

[0036] A comparison circuit 20, whose first input terminal is connected to the pixel unit and whose second input terminal is connected to the ramp voltage circuit 10, is configured to compare the reset signal or the pixel signal output by the pixel unit with the ramp voltage signal and output a reset pulse signal or a pixel pulse signal;

[0037] The counter circuit 30 is connected to the comparison circuit 20 and is configured to count the first pulse signal in a first quantization time period and store a first digital code value; in a second quantization time period, the counter circuit 30 counts the second pulse signal based on the second digital code value and stores it as a third digital code value, wherein one of the first pulse signal and the second pulse signal is a reset pulse signal and the other is a pixel pulse signal;

[0038] The inversion control circuit 40 is connected to the counter circuit 30. Between the first quantization time period and the second quantization time period, it is triggered by the mode selection signal mode_sel to output the inversion control signal trig_pulse, so that the counter circuit 30 is triggered by the inversion control signal trig_pulse to invert the first digital code value into a second digital code value and store it.

[0039] In this embodiment, the ramp voltage circuit 10 generates two ramp voltage signals in the first quantization time period and the second quantization time period. The slopes and gains of the two ramp voltage signals may be the same or different.

[0040] The ramp voltage signal of the corresponding time period is output to the comparison circuit 20. The comparison circuit 20 receives the reset signal or pixel signal of the pixel unit in the corresponding time period. The reset signal and the pixel signal are respectively compared with the ramp voltage signal. The reset signal is compared with the ramp voltage signal in the first quantization time period or the second quantization time period to generate a reset pulse signal. The pixel signal is compared with the ramp voltage signal in another quantization time period to generate a pixel pulse signal.

[0041] The counter circuit 30 counts up or down the reset pulse signal or the pixel pulse signal within the first quantization time period. When the first quantization is completed, the counter circuit 30 generates and stores the first digital code value after the current quantization. The counter circuit 30 has a rewritable function, that is, it inverts the digital code value stored in itself according to the inversion control signal trig_pulse, for example, inverts the first digital code value 0100 to generate 1011.

[0042] Between two quantization time periods, the inversion control circuit 40 receives the mode selection signal mode_sel, and the inversion control circuit 40 triggers the output of the inversion control signal trig_pulse accordingly. The counter circuit 30 inverts the first digital code value stored in itself according to the received inversion control signal trig_pulse, and generates a second digital code value as the initial state of the second quantization, that is, as the basic value of the counter circuit 30 in the second counting.

[0043] At the initial moment of the second quantization time period, the mode selection signal mode_sel switches state, the counter circuit 30 returns to the counting mode, and quantizes the second pulse signal in the second quantization time period. The counter circuit 30 counts up or down based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting and the second quantization ends.

[0044] Since the second quantization is counted based on the inverse digital code value of the first quantization result, it is equivalent to performing a difference operation on the two digital code values. For example, the first quantization result is the reset signal Vrst, which is inverted to -Vrst. The second pixel signal quantization result is -Vrst+Vsig. Since the two signals contain the same FPN, FPN can be eliminated by difference, thereby improving imaging quality.

[0045] At the same time, by adopting the inverted counting, the counter circuit 30 does not need to switch between up counting and down counting, nor does it need to set up an additional holding circuit. It only needs to add the corresponding inverted control circuit 40. Compared with the traditional counter circuit 30, the number of transistors can be reduced, thereby reducing the layout area and optimizing the routing, thereby achieving the purpose of reducing power consumption.

[0046] The ramp voltage circuit 10 may use a corresponding signal source, a voltage generating circuit, etc., for example Figure 2 The ramp generator shown in FIG. 1 may be a comparator or the like. Optionally, as shown in FIG. Figure 2 As shown, the comparison circuit 20 includes a first capacitor, a second capacitor and a comparator. The first end of the first capacitor is connected to the signal end of the ramp generating circuit, the first end of the second capacitor is used to input the reset signal or pixel signal output by the pixel unit, the second end of the first capacitor is connected to the non-inverting input end of the comparator, and the second end of the second capacitor is connected to the inverting input end of the comparator. When the ramp voltage signal is less than the corresponding reset signal or pixel signal, the comparator outputs a low level, and the counter circuit 30 starts counting. When the ramp voltage signal is greater than the corresponding reset signal or pixel signal, the comparator outputs a high level, and the counter circuit 30 stops counting. At this time, the counting result is the digital code value after the signal is quantized.

[0047] The quantization order of the reset pulse signal and the pixel pulse signal can be set according to the needs. The reset pulse signal can be quantized first and then the pixel pulse signal, or the pixel pulse signal can be quantized first and then the reset pulse signal. Optionally, the counter circuit 30 is configured to count the reset pulse signal in a first quantization time period and store a first digital code value, and to count the pixel pulse signal based on the second digital code value in a second quantization time period and store it as a third digital code value.

[0048] Alternatively, the counter circuit 30 is configured to count the pixel pulse signal in a first quantization time period and store a first digital code value, and to count the reset pulse signal based on the second digital code value in a second quantization time period and store it as a third digital code value.

[0049] When the reset pulse signal is quantized first and the pixel pulse signal is quantized later, in the first quantization time period, the counter circuit 30 quantizes the reset pulse signal first, and the counter circuit 30 quantizes and generates a first digital code value, such as Vrst. Between the two quantization time periods, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the first digital code value corresponding to the reset pulse signal to a second digital code value, that is, -Vrst. In the second quantization time period, the pixel pulse signal is quantized, and the counter circuit 30 counts based on the second digital code value and generates a third digital code value, that is, -Vrst+Vsig. Since the two signals contain the same FPN, the FPN can be eliminated by taking the difference, thereby improving the imaging quality.

[0050] Alternatively, when the pixel pulse signal is quantized first and the reset pulse signal is quantized later, in the first quantization time period, the counter circuit 30 quantizes the pixel pulse signal first, and the counter circuit 30 quantizes to generate a first digital code value, such as Vsig. Between the two quantization time periods, the counter circuit 30 receives the inversion control signal trig_pulse, and inverts the first digital code value corresponding to the pixel pulse signal to a second digital code value, that is, -Vsig. In the second quantization time period, the pixel pulse signal is quantized, and the counter circuit 30 counts based on the second digital code value and generates a third digital code value, that is, -Vsig+Vrst. Since the two signals contain the same FPN, the FPN can be eliminated by taking the difference, thereby improving the imaging quality.

[0051] The counter circuit 30 may adopt a structure corresponding to a D flip-flop DFF, a latch, etc., and the negation control circuit 40 may adopt a signal source, a selection circuit, etc.

[0052] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the readout circuit 1 of the above-mentioned image sensor is connected by a ramp voltage circuit 10, a comparison circuit 20, a counter circuit 30 and an inversion control circuit 40. When switching counting, the inversion control circuit 40 is set to control the counter circuit 30 to invert the first digital code value into a second digital code value, so that in the second quantization time period, the counter circuit 30 counts the second digital code value as a third digital code value, thereby realizing correlated double sampling, eliminating fixed pattern noise, and improving imaging quality. In addition, in the readout circuit 1, there is no need to set a buffer and an additional holding circuit, which simplifies the circuit structure, reduces power consumption, and ensures that the counter circuit 30 operates in a high-frequency counting mode.

[0053] Embodiment 2

[0054] Based on the first embodiment, the optimization and concretization are performed, such as Figure 5 As shown, optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0055] The negation control circuit 40 includes n selection circuits, the first input end of the i-th selection circuit is used to input the negation control signal trig_pulse, the second input end of the first selection circuit 41 is used to input the clock signal count_clk, the third input end of the first selection circuit 41 is used to input the output signal cmp_out of the comparator, the second input end of the second selection circuit 42 to the n-th selection circuit is connected to the output end of the i-1-th stage counter unit, the output end of the i-th selection circuit is connected to the input end of the i-th stage counter unit, i is 1, 2, ..n;

[0056] The i-th selection circuit is configured to output a negated control signal trig_pulse or a clock signal count_clk in response to a mode selection signal mode_sel;

[0057] The first counter unit 31 to the nth counter unit are configured to count the first pulse signal in the first quantization time period, and store the first count value of the current stage respectively, and the count values ​​of the counter units at each stage are combined to generate the first digital code value; between the first quantization time period and the second quantization time period, the first counter unit 31 to the nth counter unit are inverted by the inversion control signal trig_pulse to invert the first count value and store it as the second count value, and the count values ​​of the counter units at each stage are combined to generate the second digital code value;

[0058] In the second quantization period, the first counter unit 31 to the nth counter unit count the second pulse signal based on the second count value and store it as a third count value, and the count values ​​of the counter units at each level are combined to generate a third digital code value.

[0059] In this embodiment, taking the first quantization reset pulse signal and the second quantization pixel pulse signal as examples, each selection circuit is connected to the front end of a counter unit, and outputs the signal corresponding to the signal input end to its own output end according to the received mode selection signal mode_sel. Before quantization, each counter unit is reset, and in the first quantization time period, the pixel unit outputs a reset signal to the comparison circuit 20. The comparison circuit 20 compares the reset signal with the ramp voltage signal and generates a reset pulse signal. The reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the first level mode selection signal mode_sel and triggers the connection of its own second input end and output end. The first selection circuit 41 outputs the clock signal count_clk to the first counter unit 31. The subsequent selection circuit selects and outputs the count value of the counter unit of the previous stage to the counter unit of the next stage. The counter units of each stage respectively store the first count value of the current stage, and the first count values ​​of the counter units of each stage are combined to generate the first digital code value.

[0060] Between the first quantization time period and the second quantization time period, the mode selection signal mode_sel is switched to the second level, each selection circuit outputs the inversion control signal trig_pulse of the first input end to the counter unit at the back end, each counter unit is switched to the inversion mode, and the first count value stored inside itself is inverted to the second count value, and the second count values ​​stored in each counter unit are combined to generate a second digital code value, and then, the mode selection signal mode_sel is switched to the first level again, the inversion control signal trig_pulse also switches the level state, and each counter unit is switched to the counting mode.

[0061] In the second quantization time period, each selection circuit triggers the output clock signal count_clk to the back-end counter unit according to the received first level mode selection signal mode_sel, and each counter unit counts the second pulse signal based on the second count value and stores it as a third count value. The count values ​​of the counter units at each level are combined to generate a third digital code value, and are read out accordingly. At this point, a complete quantization cycle is completed, and finally the third digital code value after the difference between the pixel reset signal and the pixel signal is obtained, thereby eliminating fixed pattern noise and improving imaging quality.

[0062] Among them, the selection circuit can select a corresponding switch structure, a selector, etc., and the counter unit can select a corresponding trigger, latch, etc. structure.

[0063] Embodiment 3

[0064] Based on the optimization and specificization of the second embodiment, in an optional embodiment, as Figure 6 As shown, the first selection circuit 41 includes an AND gate AND1, a two-to-one data selector MUX1 and a first inverter U1;

[0065] The first input end of the AND gate AND1 is used to input the clock signal count_clk, the second input end of the AND gate AND1 is used to input the output signal cmp_out of the comparator, the first input end of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, the output end of the AND gate AND1 is connected to the second input end of the two-to-one data selector MUX1, the output end of the two-to-one data selector MUX1 is connected to the input end of the first inverter U1, and the output end of the first inverter U1 constitutes the output end of the first selection circuit 41;

[0066] The second selection circuit 42 to the nth selection circuit respectively include a two-to-one data selector MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input end of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, the second input end of the two-to-one data selector MUX1 is used to input the numerical value output by the previous stage counter unit, the output end of the two-to-one data selector MUX1 is connected to the input end of the first inverter U1, and the output end of the first inverter U1 is used to constitute the output end of its selection circuit.

[0067] The counter unit includes a D flip-flop DFF and a second inverter U2;

[0068] The clock signal count_clk terminal of the D flip-flop DFF of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop DFF of the i-th counter unit is connected to the input terminal of the second inverter U2 and the data input terminal of the D flip-flop DFF, and the output terminal of the second inverter U2 is connected to the second input terminal of the i+1-th selection circuit.

[0069] In this embodiment, the inverting output terminal of the D flip-flop DFF is connected to the first inverter U1 , and the output terminal of the first inverter U1 serves as the counting output terminal of the counter unit to implement upward counting.

[0070] refer to Figure 6 and Figure 7 Before quantization, at time t1-t2, count_rst switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0071] At time t3, the first quantization is performed. At this time, the output signal cmp_out of the comparator is switched to a high level. After the clock signal count_clk is ANDed with the high level by gate AND1, the clock signal count_clk is output to the second input terminal of the two-to-one data selector MUX1. At this time, the mode selection signal mode_sel is a high level, the clock signal count_clk is selected and output to the first inverter U1, and then output to the D flip-flop DFF. The D flip-flop DFF counts upwards under the action of the clock signal count_clk.

[0072] At time t4, the output of the comparison circuit 20 is flipped, the counting stops, the first quantization ends, and the count value of the first quantization result is stored in each D flip-flop DFF. The first count values ​​output by each second inverter U2 are combined to generate the first digital code value.

[0073] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to the inversion mode.

[0074] At time t6, the inversion control signal trig_pulse switches to a low level, and is selected and output to the first inverter U1 through the two-to-one data selector MUX1, and a rising edge is generated at the clock input end of the D flip-flop DFF, and the count value of the first quantization result stored in the D flip-flop DFF is inverted as the initial state before the second quantization, and the second count values ​​output by each second inverter U2 are combined to generate a second digital code value.

[0075] At time t7, the mode selection signal mode_sel is switched to a high level, and the counter unit returns to the counting mode. At time t8, the negation control signal trig_pulse is switched to a high level.

[0076] At time t9, the second quantization of the pixel pulse signal starts from the initial state. At time t10, the output of the comparison circuit 20 is flipped, the counting stops, and the second quantization ends. At time t11-t12, the final quantization result is stored in the corresponding storage module and then read out. At this point, a complete quantization cycle is completed, and finally the digital code value of the pixel reset signal Vrst and the exposure signal Vsig is obtained.

[0077] Embodiment 4

[0078] Based on the optimization and specificization of the second embodiment, in another optional embodiment, as Figure 8 As shown, the first selection circuit 41 includes an AND gate AND1, a two-to-one data selector MUX1 and a first inverter U1;

[0079] The first input end of the AND gate AND1 is used to input the clock signal count_clk, the second input end of the AND gate AND1 is used to input the output signal cmp_out of the comparator, the first input end of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, the output end of the AND gate AND1 is connected to the second input end of the two-to-one data selector MUX1, the output end of the two-to-one data selector MUX1 is connected to the input end of the first inverter U1, and the output end of the first inverter U1 constitutes the output end of the first selection circuit 41;

[0080] The second selection circuit 42 to the nth selection circuit respectively include a two-to-one data selector MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input end of the two-to-one data selector MUX1 is used to input the inversion control signal trig_pulse, the second input end of the two-to-one data selector MUX1 is used to input the numerical value output by the previous stage counter unit, the output end of the two-to-one data selector MUX1 is connected to the input end of the first inverter U1, and the output end of the first inverter U1 is used to constitute the output end of its selection circuit.

[0081] Optionally, the counter unit comprises a D flip-flop DFF;

[0082] The clock signal count_clk terminal of the D flip-flop DFF of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop DFF of the i-th counter unit is connected to the data input terminal of the D flip-flop DFF, and the positive output terminal of the D flip-flop DFF is connected to the second input terminal of the i+1-th selection circuit.

[0083] In this embodiment, the positive phase output terminal of the D flip-flop DFF is used as the counting output terminal of the counter unit to implement down counting.

[0084] refer to Figure 7 and Figure 8 Before quantization, at time t1-t2, count_rst switches to a low level, resetting the values ​​in all D flip-flops DFF (all outputs become 0).

[0085] At time t3, the first quantization is performed. At this time, the output signal cmp_out of the comparator is switched to a high level. After the clock signal count_clk is ANDed with the high level by gate AND1, the clock signal count_clk is output to the second input terminal of the two-to-one data selector MUX1. At this time, the mode selection signal mode_sel is a high level, the clock signal count_clk is selected and output to the first inverter U1, and then output to the D flip-flop DFF. The D flip-flop DFF counts down under the action of the clock signal count_clk.

[0086] At time t4, the output of the comparison circuit 20 is flipped, the counting stops, the first quantization ends, and the count value of the first quantization result is stored in each D flip-flop DFF. The first count value output by each D flip-flop DFF is combined to generate a first digital code value.

[0087] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to the inversion mode.

[0088] At time t6, the inversion control signal trig_pulse switches to a low level, and is selected and output to the first inverter U1 through the two-to-one data selector MUX1, and a rising edge is generated at the clock input end of the D flip-flop DFF, and the count value of the first quantization result stored in the D flip-flop DFF is inverted as the initial state before the second quantization. The second count value combination output by each D flip-flop DFF generates a second digital code value.

[0089] At time t7, the mode selection signal mode_sel is switched to a high level, and the counter unit returns to the counting mode. At time t8, the negation control signal trig_pulse is switched to a high level.

[0090] At time t9, the second quantization of the pixel pulse signal starts from the initial state. At time t10, the output of the comparison circuit 20 is flipped, the counting stops, and the second quantization ends. At time t11-t12, the final quantization result is stored in the corresponding storage module and then read out. At this point, a complete quantization cycle is completed, and finally the digital code value of the pixel reset signal Vrst and the exposure signal Vsig is obtained.

[0091] In order to realize the negation function of the D flip-flop DFF in the third and fourth embodiments, as shown in FIG. Fig. 9 As shown, optionally, the D flip-flop DFF includes a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a first transmission gate tran1, a second transmission gate tran2, a third transmission gate tran3 and a fourth transmission gate tran4;

[0092] The input end of the third inverter U3 constitutes the data input end of the D flip-flop DFF, the output end of the third inverter U3, the source of the PMOS tube of the first transmission gate tran1 and the drain of the NMOS tube of the first transmission gate tran1 are connected together, the drain of the PMOS tube of the first transmission gate tran1 and the source of the NMOS tube of the first transmission gate tran1, the drain of the PMOS tube of the second transmission gate tran2, the source of the NMOS tube of the second transmission gate tran2 and the input end of the fourth inverter U4 are connected together, the output end of the fourth inverter U4, the input end of the fifth inverter U5, the source of the PMOS tube of the third inverter U3 and the drain of the NMOS tube of the third inverter U3 are connected together, the output end of the fifth inverter U5, the source of the PMOS tube of the second transmission gate tran2 and the drain of the NMOS tube of the second transmission gate tran2 are connected together, the drain of the PMOS tube of the third transmission gate tran3, the source of the NMOS tube of the third transmission gate tran3, the input end of the sixth inverter U6, the fourth transmission gate tran4 are connected together. The drain of the PMOS tube of the first transmission gate tran1 and the source of the NMOS tube of the fourth transmission gate tran4 are connected in common, the source of the PMOS tube of the fourth transmission gate tran4, the drain of the NMOS tube of the fourth transmission gate tran4 and the output end of the seventh inverter U7 are connected, the output end of the sixth inverter U6, the input end of the seventh inverter U7 and the input end of the eighth inverter U8 are connected in common, the output end of the eighth inverter U8 constitutes the non-phase output end of the D flip-flop DFF, the gate of the PMOS tube of the first transmission gate tran1, the gate of the NMOS tube of the second transmission gate tran2, the gate of the NMOS tube of the third transmission gate tran3 and the gate of the PMOS tube of the fourth transmission gate tran4 are connected in common and input the clock signal count_clk, the gate of the NMOS tube of the first transmission gate tran1, the gate of the PMOS tube of the second transmission gate tran2, the gate of the PMOS tube of the third transmission gate tran3 and the gate of the NMOS tube of the fourth transmission gate tran4 are connected in common and input the inverted signal of the clock signal count_clk.

[0093] In this embodiment, the first transmission gate tran1, the fourth inverter U4, the fifth inverter U5 and the second transmission gate tran2 constitute a master latch, the third transmission gate tran3, the sixth inverter U6, the seventh inverter U7 and the fourth transmission gate tran4 constitute a slave latch, the master latch is used to stably latch and output the input value of the D flip-flop DFF, the slave latch is used to stably latch and output the output value of the master latch, the third inverter U3 is used to invert the input data signal and output it to the master latch, the eighth inverter U8 is used to invert the output value of the slave latch and output it, and when the clock signal count_clk end of the D flip-flop DFF receives a rising edge, the third inverter U3, the master latch, the slave latch and the eighth inverter U8 invert and output the latched value.

[0094] Embodiment 5

[0095] Based on the first embodiment, the optimization and concretization are performed, such as Fig.10 As shown, optionally, the readout circuit 1 of the image sensor further includes:

[0096] The storage circuit 50 is connected to the counter circuit 30 and is used for storing the third digital code value and being triggered to read out by the read control signal.

[0097] In this embodiment, after the second quantization is completed, the counter circuit 30 obtains the difference between the digital code values ​​corresponding to the reset pulse signal and the pixel pulse signal, that is, the third digital code value. Figure 7 As shown, at time t11-t12, the write signal output to the storage circuit 50 is enabled to be high level, and the final quantization result is written and stored in the storage circuit 50, and then read out. At this point, a complete quantization cycle is completed, and finally a digital code value of the pixel after the reset signal Vrst and the exposure signal Vsig are obtained.

[0098] Among them, the storage circuit 50 can select a single memory Mem or multiple memories Mem. When a single memory Mem is used, the memory Mem is provided with multiple storage partitions, each storage partition stores a third count value respectively, and multiple third count values ​​are combined to generate a third digital code value. When multiple memories Mem are used, each memory Mem stores a third count value respectively.

[0099] In an alternative embodiment, if Fig.11 As shown, the storage circuit 50 includes:

[0100] The n memories Mem are respectively connected to a counter unit and store count values ​​of corresponding bits of the third digital code value respectively.

[0101] In this embodiment, the storage circuit 50 is composed of a plurality of memories Mem, and each of them stores one bit of the third count value. To simplify the structure, optionally, the memory of the memory Mem is 1 bit.

[0102] Embodiment 6

[0103] The present invention also provides an image sensor, such as Figure 2 As shown, the image sensor includes a pixel array 100, a control circuit 3 and a plurality of image sensor readout circuits 1. The specific structure of the image sensor readout circuit 1 refers to the above embodiment. Since the image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the pixel array 100 includes a plurality of pixel units arranged in an array;

[0104] The readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit 1 of each image sensor is also respectively connected to the control circuit 3 .

[0105] In this embodiment, the image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may also include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array, and the plurality of pixel units arranged in columns are connected in common. The control circuit 3 selects the pixel units in each row through a row selection signal, and sequentially outputs the pixel signals of each row to the readout circuit 1. The plurality of pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3, so that the control circuit 3 determines the image information according to the digital code value.

[0106] Among them, the pixel unit generally includes a photoelectric conversion element, a transmission transistor TX, a reset transistor RST, a source follower transistor SF and a row selection transistor SEL, wherein the photoelectric conversion element includes but is not limited to a photodiode PD, such as a Pin-type photodiode PD, and at the same time, the number of the photoelectric conversion element, the transmission transistor TX, the reset transistor RST, the source follower transistor SF and the row selection transistor SEL can be one or more, that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited, such as Figure 3 As shown, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, wherein the cathode of the photodiode PD is connected to the first end of the transfer transistor TX, the second end of the transfer transistor TX, the first end of the reset transistor RST, and the controlled end of the source follower transistor SF are all coupled to the floating diffusion node, the anode of the photodiode PD is grounded, the second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD, the second end of the source follower transistor SF is connected to the first end of the row selection transistor SEL, and the second end of the row selection transistor SEL constitutes the output end of the pixel unit 2 and is used to output the corresponding pixel signal.

[0107] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A readout circuit for an image sensor, characterized in that: include: A ramp voltage circuit configured to output a ramp voltage signal in a first quantization time period and a second quantization time period of the pixel unit respectively; a comparison circuit, wherein a first input terminal of the comparison circuit is connected to the pixel unit, and a second input terminal of the comparison circuit is connected to the ramp voltage circuit, and is configured to compare a reset signal or a pixel signal output by the pixel unit with the ramp voltage signal, and output a reset pulse signal or a pixel pulse signal; a counter circuit connected to the comparison circuit, configured to count the first pulse signal in the first quantization time period and store the first digital code value; in the second quantization time period, the counter circuit counts the second pulse signal based on the second digital code value and stores it as a third digital code value, the first pulse signal and the second pulse signal are the reset pulse signal and the pixel pulse signal to each other; An inversion control circuit is connected to the counter circuit. Between the first quantization time period and the second quantization time period, the inversion control circuit is triggered by a mode selection signal to output an inversion control signal, so that the counter circuit is triggered by the inversion control signal to invert the first digital code value into the second digital code value and store it.

2. The readout circuit of the image sensor according to claim 1, wherein: The counter circuit is configured to count the reset pulse signal in the first quantization time period and store the first digital code value, and to count the pixel pulse signal based on the second digital code value in the second quantization time period and store it as the third digital code value; Alternatively, the counter circuit is configured to count the pixel pulse signal in the first quantization time period and store the first digital code value, and to count the reset pulse signal based on the second digital code value in the second quantization time period and store it as the third digital code value.

3. The readout circuit of the image sensor according to claim 1, wherein: The counter circuit includes a first counter unit to an nth counter unit; The negation control circuit comprises n selection circuits, the first input end of the i-th selection circuit is used to input the negation control signal, the second input end of the first selection circuit is used to input the clock signal, the third input end of the first selection circuit is used to input the output signal of the comparator, the second input end of the second selection circuit to the n-th selection circuit is connected to the output end of the i-1-th stage counter unit, the output end of the i-th selection circuit is connected to the input end of the i-th stage counter unit, i is 1, 2, ..n; The i-th selection circuit is configured to output the inverted control signal or the clock signal in response to the mode selection signal; The first counter unit to the nth counter unit are configured to count the first pulse signal in the first quantization time period, and respectively store the first count value of the current stage, and the count values ​​of the counter units at each stage are combined to generate the first digital code value; between the first quantization time period and the second quantization time period, the first counter unit to the nth counter unit are inverted by the inversion control signal to the first count value and stored as the second count value, and the count values ​​of the counter units at each stage are combined to generate the second digital code value; In the second quantization time period, the first counter unit to the nth counter unit count the second pulse signal based on the second count value and store it as a third count value, and the count values ​​of the counter units at each level are combined to generate the third digital code value.

4. The readout circuit of the image sensor according to claim 3, characterized in that: The first selection circuit includes an AND gate, a two-to-one data selector and a first inverter; The first input end of the AND gate is used to input the clock signal, the second input end of the AND gate is used to input the output signal of the comparator, the first input end of the two-to-one data selector is used to input the inversion control signal, the output end of the AND gate is connected to the second input end of the two-to-one data selector, the output end of the two-to-one data selector is connected to the input end of the first inverter, and the output end of the first inverter constitutes the output end of the first selection circuit; The second selection circuit to the nth selection circuit respectively include a two-to-one data selector and a first inverter. In the second selection circuit to the nth selection circuit, the first input end of the two-to-one data selector is used to input the inversion control signal, the second input end of the two-to-one data selector is used to input the numerical value output by the previous stage counter unit, the output end of the two-to-one data selector is connected to the input end of the first inverter, and the output end of the first inverter is used to constitute the output end of its selection circuit.

5. The readout circuit of the image sensor according to claim 3, characterized in that: The counter unit includes a D flip-flop and a second inverter; The clock signal end of the D flip-flop of the i-th counter unit is connected to the signal output end of the i-th selection circuit, the inverting output end of the D flip-flop of the i-th counter unit is connected to the input end of the second inverter and the data input end of the D flip-flop, and the output end of the second inverter is connected to the second input end of the (i+1)-th selection circuit.

6. The readout circuit of the image sensor according to claim 3, characterized in that: The counter unit comprises a D flip-flop; The clock signal terminal of the D flip-flop of the i-th counter unit is connected to the signal output terminal of the i-th selection circuit, the inverting output terminal of the D flip-flop of the i-th counter unit is connected to the data input terminal of the D flip-flop, and the positive output terminal of the D flip-flop is connected to the second input terminal of the i+1-th selection circuit.

7. The readout circuit of the image sensor according to claim 5 or 6, characterized in that: The D flip-flop includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first transmission gate, a second transmission gate, a third transmission gate and a fourth transmission gate; The input end of the third inverter constitutes the data input end of the D flip-flop, the output end of the third inverter, the source of the PMOS tube of the first transmission gate, and the drain of the NMOS tube of the first transmission gate are connected together, the drain of the PMOS tube of the first transmission gate, the source of the NMOS tube of the first transmission gate, the drain of the PMOS tube of the second transmission gate, the source of the NMOS tube of the second transmission gate, and the input end of the fourth inverter are connected together, the output end of the fourth inverter, the input end of the fifth inverter, the source of the PMOS tube of the third inverter, and the drain of the NMOS tube of the third inverter are connected together, the output end of the fifth inverter, the source of the PMOS tube of the second transmission gate, and the drain of the NMOS tube of the second transmission gate are connected together, the drain of the PMOS tube of the third transmission gate, the source of the NMOS tube of the third transmission gate, the input end of the sixth inverter are connected together, and the drain of the PMOS tube of the third transmission gate, the source of the NMOS tube of the third transmission gate, and the input end of the sixth inverter are connected together. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention. The first transmission gate of the embodiment of the present invention comprises a first transmission gate of the embodiment of the present invention and a second transmission gate of the embodiment of the present invention.

8. The readout circuit of the image sensor according to claim 3, characterized in that: The readout circuit of the image sensor further includes: The storage circuit is connected to the counter circuit, and is used to store the third digital code value and is triggered to read out by a read control signal.

9. The readout circuit of the image sensor according to claim 8, characterized in that: The storage circuit comprises: n memories are respectively connected to one of the counter units and store count values ​​of corresponding bits of the third digital code value respectively.

10. An image sensor, characterized in that: A method comprising a pixel array, a control circuit and a plurality of readout circuits of the image sensor according to any one of claims 1 to 9, wherein the pixel array comprises a plurality of pixel units arranged in an array; The readout circuit of each of the image sensors is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit of each of the image sensors is also respectively connected to the control circuit.

Images