Semiconductor memory device and semiconductor memory apparatus

Abstract

The invention provides a semiconductor memory device and a semiconductor memory device, and relates to the technical field of semiconductors. The semiconductor memory device comprises a substrate, a capacitor structure, a semiconductor conductive layer, a cover layer and a plurality of gaps; the capacitor structure is arranged on the substrate; the capacitor structure comprises a plurality of capacitors; the semiconductor conductive layer comprises a first part and a second part, and the first part covers the capacitor structure and is in direct contact with the capacitor structure; the second part is filled between the adjacent capacitors; a cap layer on the upper first portion and in direct contact with the first portion; the surface, facing the semiconductor conducting layer, of the cover layer is provided with a fluctuating surface profile, the surface profile is provided with wave crests and wave troughs, and the first part extends into the wave troughs; at least one gap is located in the first portion of the trough. Layering between the semiconductor conductive layer and the cover layer can be reduced or even avoided, and the performance of the semiconductor memory device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor memory device and a semiconductor memory apparatus. Background Art

[0002] With the continuous development of semiconductor technology, semiconductor memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM), are increasingly used and have been widely used in the fields of computers and communications.

[0003] In the related art, the stacked film layers of semiconductor memory devices are prone to delamination or fracture, which reduces the performance of the semiconductor memory devices. Summary of the invention

[0004] In view of the above problems, the present application provides a semiconductor memory device and a semiconductor memory apparatus, which can reduce or even avoid the delamination between the semiconductor conductive layer and the cap layer, thereby improving the performance of the semiconductor memory device.

[0005] In order to achieve the above objectives, the present application provides the following technical solutions:

[0006] A first aspect of an embodiment of the present application provides a semiconductor memory device, comprising:

[0007] substrate;

[0008] A capacitor structure, wherein the capacitor structure is disposed on the substrate; the capacitor structure comprises a plurality of capacitors;

[0009] A semiconductor conductive layer, the semiconductor conductive layer comprising a first portion and a second portion, the first portion covers the capacitor structure and directly contacts the capacitor structure; the second portion is filled between adjacent capacitors;

[0010] A capping layer, the capping layer being located on the upper first portion and in direct contact with the first portion; wherein a surface of the capping layer facing the semiconductor conductive layer has an undulating surface profile, the surface profile having peaks and valleys, and the first portion extends into the valleys;

[0011] A plurality of voids, at least one void is located within the first portion in the valley.

[0012] In a possible implementation manner, the at least one gap faces the bottom of the substrate and is located between adjacent wave peaks and a surface of the cover layer facing away from the substrate.

[0013] In a possible implementation manner, a minimum distance D1 exists between at least one of the gaps and a top surface of the capacitor structure facing away from the substrate;

[0014] There is a distance D2 between two adjacent capacitors in the capacitor structure; and D1 is greater than D2.

[0015] In a possible implementation manner, a plurality of the gaps are spaced apart and arranged in the first portion.

[0016] In a possible implementation, the plurality of gaps include a first gap, a second gap, and a third gap, and the third gap is located in the first portion of the wave valley;

[0017] In a first direction, the first gap is located on one side of the third gap, and the second gap is located on the other side of the third gap;

[0018] There is a first distance D3 between the first gap and the third gap, and there is a second distance D4 between the second gap and the third gap; the first distance D3 is less than or equal to the second distance D4.

[0019] In a possible implementation manner, along the direction from the cap layer to the semiconductor conductive layer, the width of the gap gradually decreases.

[0020] In a possible implementation manner, a section perpendicular to the base is taken as a longitudinal section, and the longitudinal section of the gap is conical or trapezoidal.

[0021] In a possible implementation, taking a section perpendicular to the base as a longitudinal section, the longitudinal section of the gap is semicircular or arc-shaped.

[0022] In a possible implementation, the material of the semiconductor conductive layer includes silicon germanium.

[0023] In one possible implementation, the cover layer is made of an insulating material; the insulating material is selected from at least one of HDP oxide, TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, silicon nitride, and silicon nitride oxide.

[0024] In a possible implementation, the cover layer is made of a conductive material; the conductive material is selected from at least one of tungsten, titanium nitride, and tungsten nitride.

[0025] In a possible implementation, the capacitor includes a first electrode plate, a second electrode plate, and a dielectric layer located between the first electrode plate and the second electrode plate;

[0026] The semiconductor conductive layer is disposed on the second electrode plate.

[0027] A second aspect of an embodiment of the present application provides a semiconductor memory device, comprising: a package and the semiconductor memory device described in the first aspect; the package encapsulates the semiconductor memory device.

[0028] In the semiconductor memory device and semiconductor memory device provided by the embodiments of the present application, there are multiple gaps between the semiconductor conductive layer and the cover layer. The multiple gaps can block the transmission of stress generated by the contraction or expansion process of the semiconductor conductive layer and / or the cover layer, avoid stress concentration at the interface between the semiconductor conductive layer and the cover layer, and further avoid stratification of the semiconductor conductive layer and the cover layer, thereby improving the performance of the semiconductor memory device.

[0029] The surface of the cap layer facing the semiconductor conductive layer has an undulating surface profile, and the surface profile has peaks and valleys, and the first portion extends into the valley so that the first portion is embedded with the cap layer, which can improve the bonding strength between the cap layer and the semiconductor conductive layer. In addition, the portion of the first portion extending into the valley forms a sharp portion where the stress is the greatest, so at least one gap is located in the first portion in the valley, which can avoid stress concentration at the interface between the semiconductor conductive layer and the cap layer as much as possible.

[0030] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor memory device and semiconductor storage device provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic diagram of the structure of a semiconductor memory device provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram of forming a capacitor contact structure during the preparation process of a semiconductor memory device provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of forming a support structure during the preparation of a semiconductor memory device provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of forming a capacitor hole during the preparation process of a semiconductor memory device provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of forming a first electrode plate during the preparation of a semiconductor memory device provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of forming a photoresist layer during the preparation process of a semiconductor memory device provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of removing part of the supporting structure during the preparation process of the semiconductor memory device provided in an embodiment of the present application;

[0039] Figure 8 A schematic diagram of forming a dielectric layer during the preparation process of a semiconductor memory device provided in an embodiment of the present application;

[0040] Fig. 9 Schematic diagram of forming a second electrode plate during the preparation process of a semiconductor memory device provided in an embodiment of the present application Figure 1 ;

[0041] Fig.10 Schematic diagram of forming a second electrode plate during the preparation process of a semiconductor memory device provided in an embodiment of the present application Figure 2 ;

[0042] Fig.11 Schematic diagram of forming a semiconductor conductive layer during the preparation process of a semiconductor memory device provided in an embodiment of the present application Figure 1 ;

[0043] Fig.12 Schematic diagram of forming a semiconductor conductive layer during the preparation process of a semiconductor memory device provided in an embodiment of the present application Figure 2 ;

[0044] Fig.13 Schematic diagram of forming a cap layer during the preparation process of a semiconductor memory device provided in an embodiment of the present application Figure 1 ;

[0045] Fig.14 Schematic diagram of forming a cap layer during the preparation process of a semiconductor memory device provided in an embodiment of the present application Figure 2 ;

[0046] Fig.15 Schematic diagram of forming a conductive plug in a method for preparing a semiconductor memory device provided in an embodiment of the present application Figure 1 ;

[0047] Fig.16Schematic diagram of forming a conductive plug in a method for preparing a semiconductor memory device provided in an embodiment of the present application Figure 2 .

[0048] Description of reference numerals:

[0049] 100: base;

[0050] 200: capacitor; 210: first electrode plate; 220: second electrode plate; 221: barrier layer; 222: conductive layer; 230: dielectric layer;

[0051] 300: semiconductor conductive layer;

[0052] 400: cap layer; 410: crest; 420: trough;

[0053] 500: gap;

[0054] 600: Capacitive contact structure;

[0055] 710: dielectric layer; 720: insulating layer; 730: conductive plug;

[0056] 800: support structure; 810: first support layer; 820: second support layer; 830: third support layer; 840: first sacrificial layer; 850: second sacrificial layer;

[0057] 900: photoresist layer; 910: mask opening. DETAILED DESCRIPTION

[0058] As described in the background technology, the stacked film layers of semiconductor memory devices in the related art are prone to delamination or fracture. The inventors have found that the reason for this problem is that during the use of the semiconductor memory device, the film layer will expand and contract due to heat, and the thermal expansion coefficients of the stacked film layers are different, resulting in different degrees of deformation of the stacked film layers, which in turn makes the stacked film layers prone to delamination or fracture, reducing the performance of the semiconductor memory device.

[0059] In response to the above technical problems, the embodiments of the present application provide a semiconductor memory device and a semiconductor memory device, wherein a plurality of gaps are provided between the semiconductor conductive layer and the cap layer. The plurality of gaps can be used to block the transmission of stress generated during the contraction or expansion of the semiconductor conductive layer and / or the cap layer, thereby avoiding stress concentration at the interface between the semiconductor conductive layer and the cap layer, thereby avoiding stratification of the semiconductor conductive layer and the cap layer, and improving the performance of the semiconductor memory device.

[0060] The surface of the cap layer facing the semiconductor conductive layer has an undulating surface profile, and the surface profile has peaks and valleys, and the first portion extends into the valley so that the first portion is embedded with the cap layer, which can improve the bonding strength between the cap layer and the semiconductor conductive layer. In addition, the portion of the first portion extending into the valley forms a sharp portion where the stress is the greatest, so at least one gap is located in the first portion in the valley, which can avoid stress concentration at the interface between the semiconductor conductive layer and the cap layer as much as possible.

[0061] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application.

[0062] Please refer to the attached Figure 1 An embodiment of the present application provides a semiconductor memory device, which may be a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0063] The semiconductor memory device includes a substrate 100, which is a main bearing component of the semiconductor structure and is used to bear components disposed thereon. The substrate 100 may be any substrate 100 suitable for manufacturing semiconductor elements, such as a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto.

[0064] The semiconductor memory device further includes a capacitor structure, which is disposed on the substrate 100. The capacitor structure includes a plurality of capacitors 200, which are spaced apart on the substrate 100. The capacitor 200 is used as a storage device of the semiconductor memory device to store charges, thereby realizing data storage and reading functions.

[0065] Each capacitor 200 includes a first electrode plate 210, a second electrode plate 220 and a dielectric layer 230, wherein the dielectric layer 230 is disposed between the first electrode plate 210 and the second electrode plate 220 to achieve an insulation arrangement between the first electrode plate 210 and the second electrode plate 220. Among them, one of the first electrode plate 210 and the second electrode plate 220 serves as a lower electrode of the capacitor, and the other of the first electrode plate 210 and the second electrode plate 220 serves as an upper electrode of the capacitor. The following embodiments are described by taking the first electrode plate 210 as the lower electrode and the second electrode plate 220 as the upper electrode as an example.

[0066] Please continue to refer to the attached Figure 1 The second electrode plates 220 are connected together to form a whole, and are connected to the conductive plug 730 through the semiconductor conductive layer 300 and the cap layer 400 to achieve electrical connection between the capacitor 200 and the peripheral circuit. The first electrode plates 210 of the plurality of capacitors 200 are independent of each other, and each first electrode plate 210 can be electrically connected to the source region or the drain region of the substrate 100 through the capacitor contact structure 600.

[0067] In this embodiment, please refer to the attached Figure 1 The first electrode plate 210 is a columnar body perpendicular to the substrate 100, which can increase the volume of the first electrode plate 210, thereby improving the strength of the first electrode plate 210, thereby preventing the capacitor 200 from collapsing and improving the yield of the semiconductor structure.

[0068] The material of the first electrode plate 210 and the second electrode plate 220 may include conductive materials such as metal tungsten and titanium nitride. The material of the dielectric layer 230 may be a dielectric material with a high dielectric constant, for example, the dielectric material may include ZrO x , HfO x 、ZrTiO x 、RuO x , SbO x 、AlO x At least one of the above materials, that is, the material of the dielectric layer 230 can be selected from any one or more of the above materials. Optionally, the dielectric layer 230 can be a stacked structure. For example, the dielectric layer 230 can include a three-layer structure, and the materials of the three-layer structure are zirconium oxide-aluminum oxide-zirconium oxide.

[0069] The semiconductor memory device further includes a semiconductor conductive layer 300 and a cap layer 400. The semiconductor conductive layer 300 includes a first portion 310 and a second portion 320. The first portion 310 covers the capacitor structure and directly contacts the capacitor structure; the second portion 320 is filled between adjacent capacitors 200. In other words, the semiconductor conductive layer 300 is disposed on the second electrode plate 220 and contacts and is electrically connected to the second electrode plate 220 of the capacitor 200.

[0070] The cap layer 400 is disposed on the first portion 310 and directly contacts the first portion 310. The surface of the cap layer 400 facing the semiconductor conductive layer 300 has an undulating surface profile, the surface profile has a crest 410 and a trough 420, and the first portion 310 extends into the trough 420; in other words, the first portion 310 also has a protruding area, which can be embedded in the trough 420 to improve the fit between the semiconductor conductive layer 300 and the cap layer 400.

[0071] In this embodiment, the material of the semiconductor conductive layer 300 may include silicon germanium or polysilicon, and the material of the cap layer 400 is an insulating material or a conductive material. In one example, the material of the cap layer 400 is an insulating material; the insulating material is selected from at least one of HDP oxide, TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, silicon nitride, and silicon oxynitride. In the figure, TEOS is the abbreviation of tetraethyl orthosilicate; USG is the abbreviation of undoped silicate glass; PSG is the abbreviation of phosphosilicate glass; BSG is the abbreviation of borosilicate glass; BPSG is the abbreviation of borophosphosilicate glass; FSG is the abbreviation of fluorinated silicate glass; SOG is the abbreviation of spin-on glass; TOSZ is the abbreviation of tetraorthosilicate zirconium.

[0072] In another example, the cover layer 400 is made of a conductive material; the conductive material is selected from at least one of tungsten, titanium nitride, and tungsten nitride.

[0073] The capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300, or the capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300 and the cover layer 400, so that the capacitor structure is electrically connected to the peripheral circuit to achieve data storage or reading.

[0074] Please refer to the attached Fig.15 and attached Fig.16 When the cap layer 400 is an insulating material, the capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300; please refer to the attached Figure 1 When the cap layer 400 is a conductive material, the capacitor structure is connected to the conductive plug 730 through the semiconductor conductive layer 300 and the cap layer 400 .

[0075] The difference in thermal expansion coefficients between the semiconductor conductive layer 300 and the cap layer 400 is large, so the semiconductor memory device is prone to delamination or fracture during operation. Therefore, the semiconductor memory device provided in this embodiment also includes a plurality of gaps 500, and at least one gap 500 is located in the first part 310 in the trough 420. In other words, a plurality of gaps 500 are arranged in the first part 310 at intervals, and at least one gap 500 is arranged in the first part 310 in the trough 420. The distance between any adjacent gaps 500 can be equal or unequal, and the specific layout can be carried out according to the actual situation.

[0076] In this way, the plurality of gaps 500 can block the transmission of stress generated during the contraction or expansion of the semiconductor conductive layer 300 and / or the cap layer 400, thereby avoiding stress concentration at the interface between the semiconductor conductive layer 300 and the cap layer 400, thereby avoiding stratification of the semiconductor conductive layer 300 and the cap layer 400, and improving the performance of the semiconductor memory device.

[0077] The surface of the cap layer 400 facing the semiconductor conductive layer 300 has an undulating surface profile, and the surface profile has a crest 410 and a trough 420. The first portion 310 extends into the trough 420, so that the first portion 310 is embedded with the cap layer 400, which can improve the bonding strength between the cap layer 400 and the semiconductor conductive layer 300. In addition, the portion of the first portion 310 extending into the trough 420 forms a sharp portion, where the stress is the greatest, so at least one gap 500 is located in the first portion 310 in the trough 420, which can avoid stress concentration at the interface between the semiconductor conductive layer 300 and the cap layer 400 as much as possible.

[0078] It should be noted that, in this embodiment, the number of the gaps 500 in the first portion 310 located in the trough 420 may be one, two or even more. The specific layout needs to be made according to the size of the first portion 310 located in the trough 420. In addition, except for at least one gap 500 in the first portion 310 located in the trough 420, the remaining gaps 500 may be arranged between the semiconductor conductive layer 300 and the cap layer 400.

[0079] While having the function of blocking stress transmission, the multiple gaps 500 can also serve as thermal insulation components. Taking advantage of the fact that the thermal conductivity of air is much lower than that of solid materials, these gaps 500 can significantly reduce the heat conducted through the cover layer 400 to the semiconductor conductive layer 300, thereby improving the thermal stability of the entire capacitor structure, and further improving the thermal stability of the semiconductor storage device.

[0080] In a possible implementation, at least one gap 500 faces the bottom of the substrate 100 and is located between the adjacent wave crest 410 and the surface of the cap layer 400 facing away from the substrate 100; in other words, the distance between the bottom of the at least one gap 500 facing the substrate 100 and the surface of the cap layer 400 facing away from the substrate 100 is a first distance L1, and the distance between any wave crest 410 adjacent thereto and the surface of the cap layer 400 facing away from the substrate 100 is a second distance L2, and the first distance L1 is less than the second distance L2. In this way, under the premise of ensuring that at least one gap 500 effectively reduces local stress concentration, it is also possible to avoid the size of at least one gap 500 being too large in the direction perpendicular to the cap layer 400, reduce the influence of at least one gap 500 on the conductive properties of the semiconductor conductive layer 300, and thereby ensure the performance of the semiconductor memory device.

[0081] It should be understood that the relationship between the first distance L1 and the second distance L2 is not limited to the above description. The first distance L1 may also be equal to the second distance L2, which may be changed according to the performance requirements of the semiconductor memory device or the control of process parameters.

[0082] Please continue to refer to the attached Figure 1 The second electrode plate 220 forms a filling area in the dielectric layer 230, so that the semiconductor conductive layer 300 can not only cover the second electrode plate 220, but also fill in the filling area, thereby increasing the contact area between the semiconductor conductive layer 300 and the second electrode plate 220, thereby reducing the contact resistance between the semiconductor conductive layer 300 and the second electrode plate 220.

[0083] There is a minimum distance D1 between the at least one gap 500 and the top surface of the capacitor structure facing away from the substrate 100 ; that is, there is a minimum distance D1 between the at least one gap 500 and the top surface of the second electrode plate 220 facing away from the substrate 100 .

[0084] There is a distance D2 between two adjacent capacitors 200 in the capacitor structure; that is, the width of the filling area enclosed by the second electrode plate 220 between the adjacent first electrode plates 210 constitutes D2. It should be noted that the width in this embodiment is Figure 1 The size of the first direction M

[0085] In this embodiment, D1 is greater than D2, which can ensure that the thickness of the semiconductor conductive layer 300 located on the top surface of the capacitor structure away from the substrate 100 is greater than the thickness of the semiconductor conductive layer 300 located in the filling area. Such a setting can increase the thickness of the first part 310, thereby providing a better heat dissipation path, helping to reduce the heat generated during the operation of the capacitor structure, thereby improving the stability and durability of the entire capacitor structure.

[0086] In order to facilitate a detailed description of the relative relationship between at least one gap 500 in the first portion 310 located in the trough 420 and its adjacent gaps 500 , it may be taken as an example that the number of gaps 500 in the first portion 310 located in the trough 420 is one.

[0087] Exemplarily, the plurality of voids 500 include a first void 510, a second void 520 and a third void 530, wherein the third void 530 is located within the first portion 310 in the trough 420; in the first direction M, the first void 510 is located on one side of the third void 530, and the second void 520 is located on the other side of the third void 530; that is, the first void 510 and the second void 520 are respectively located on both sides of the third void 530 and are arranged at intervals.

[0088] There is a first distance D3 between the first gap 510 and the third gap 530, and there is a second distance D4 between the second gap 520 and the third gap 530. The first distance D3 is less than or equal to the second distance D4.

[0089] This embodiment can affect the flow path of current in the semiconductor conductive layer 300 by reasonably arranging the first gap 510, the second gap 520 and the third gap 530. By making the first spacing D3 less than or equal to the second spacing D4, the current in the semiconductor conductive layer 300 is more inclined to flow through the narrower channel between the first gap 510 and the second gap 520, which helps to achieve uniform distribution or directional guidance of the current and improve the conductive efficiency and stability of the semiconductor memory device.

[0090] In addition, the semiconductor memory device generates heat during operation, thereby causing thermal expansion. Since the thermal expansion coefficients of the cap layer 400 and the semiconductor conductive layer 300 are different, thermal stress will be generated between the two. By rationally arranging the gaps 500, especially placing the third gaps 530 in the troughs 420, the stress concentration caused by the difference in thermal expansion can be reduced. At the same time, the layout in which the first spacing D3 is less than or equal to the second spacing D4 helps to disperse these stresses and prevent excessive local stress from causing material failure.

[0091] In a possible implementation, along the direction from the cap layer 400 to the semiconductor conductive layer 300, the width of the gap 500 gradually decreases. Figure 1 The width of the gap 500 may be the dimension of the gap 500 in the first direction M.

[0092] The materials of the cap layer 400 and the semiconductor conductive layer 300 are different, and a difference in thermal expansion will occur when the temperature changes. The resulting thermal stress is mainly concentrated at the interface between the cap layer 400 and the semiconductor conductive layer 300. Therefore, the width of the gap 500 is the largest near the interface between the two, which helps to provide a better stress buffer zone, better alleviate the stress at the interface between the cap layer 400 and the semiconductor conductive layer 300, and thus better avoid stratification of the cap layer 400 and the semiconductor conductive layer 300, thereby improving the performance of the semiconductor memory device.

[0093] In addition, along the second direction N and toward the substrate 100, the width of the gap 500 gradually decreases. This structure can enable the semiconductor memory device to more effectively disperse and absorb stress when facing external factors such as temperature changes and mechanical vibrations without sacrificing overall strength, thereby avoiding damage caused by excessive local stress.

[0094] It should be understood that there are multiple options for the shape of the gap 500. In one example, the section perpendicular to the substrate 100 is the longitudinal section, and the longitudinal section of the gap 500 is conical or trapezoidal. In this way, the wider gap portion can absorb more stress changes, while the narrower portion plays a role in further limiting stress transfer, thereby effectively alleviating the stress concentration at the interface between the cap layer 400 and the semiconductor conductive layer 300. In another example, the section perpendicular to the substrate 100 is the longitudinal section, and the longitudinal section of the gap 500 is semicircular or arc-shaped. Among them, the semicircular or arc-shaped gap shape provides a smooth transition edge on the longitudinal section, which helps to reduce the sudden change of stress at the interface, and can guide the stress to propagate along a smoother path, reducing the possibility of stress concentration.

[0095] Regardless of whether the longitudinal cross-sectional shape of the gap 500 is conical, trapezoidal, semicircular or arc-shaped, the common point is that the stress generated by the difference in thermal expansion between the cap layer 400 and the semiconductor conductive layer 300 can be cleverly guided and dispersed by changing the width or shape of the gap 500, thereby reducing the concentration of stress at the interface. When the stress is effectively dispersed, the risk of delamination of the cap layer 400 and the semiconductor conductive layer 300 will be greatly reduced. Therefore, under the premise of being able to reduce the risk of delamination, the selectivity of the longitudinal cross-sectional shape of the gap 500 can be increased.

[0096] The semiconductor memory device provided in the embodiment of the present application may also include a transistor, a word line structure and a bit line structure. Exemplarily, in the present embodiment, the substrate 100 already includes a semiconductor device, for example, a transistor (not shown in the figure) and a word line structure (not shown in the figure) are arranged in the substrate 100, and the word line structure connects the gate of the transistor to control the opening or closing of the transistor. Wherein, the transistor also includes a source and a drain. One of the source and the drain is connected to the capacitor structure, and the other is used to be connected to the bit line structure. The voltage signal on the word line structure can control the opening or closing of the transistor, and then read the data information stored in the capacitor structure through the bit line structure, or write the data information into the capacitor structure for storage through the bit line structure.

[0097] It should be noted that in this embodiment, the capacitor structure can be connected to one of the source and the drain through the capacitor contact structure 600. In order to facilitate further detailed description of the structure of the semiconductor memory device, the following will be explained by describing the preparation method of the semiconductor memory device.

[0098] Exemplarily, a capacitor contact structure 600 is formed on the substrate 100, and the capacitor contact structure 600 is connected to one of the source and the drain. Figure 2 , a dielectric layer 710 can be formed on the substrate 100 by a deposition process; then the dielectric layer 710 is patterned to form a contact hole in the dielectric layer 710, and the contact hole is used to expose at least a portion of the source electrode or at least a portion of the drain electrode; then, a conductive material is deposited in the contact hole by a deposition process to form a capacitor contact structure 600. The top surface of the capacitor contact structure 600 is flush with the top surface of the dielectric layer 710.

[0099] Please refer to the attached Figure 3 A support structure 800 is formed on the dielectric layer 710, wherein the support structure 800 is a stacked structure. Exemplarily, the support structure 800 includes a first support layer 810, a first sacrificial layer 840, a second support layer 820, a second sacrificial layer 850 and a third support layer 830 stacked in sequence, wherein the first support layer 810 is disposed on the substrate 100.

[0100] The materials of the first supporting layer 810 , the second supporting layer 820 and the third supporting layer 830 may include insulating materials such as silicon nitride; the materials of the first sacrificial layer 840 and the second sacrificial layer 850 may include insulating materials such as silicon oxide.

[0101] Please refer to the attached Figure 4 , the support structure 800 is patterned, and a capacitor hole 860 is formed in the support structure 800 . The capacitor hole 860 penetrates the support structure 800 in a direction perpendicular to the substrate 100 , so that the capacitor hole 860 exposes the capacitor contact structure 600 .

[0102] Please refer to the attached Figure 5 The first electrode plate 210 is formed in the capacitor hole 860 by a deposition process. The first electrode plate 210 fills the capacitor hole 860 , and the top surface of the first electrode plate 210 is flush with the top surface of the support structure 800 .

[0103] It should be noted that the capacitor holes 860 divide the support structure 800 into a plurality of columnar structures. After the first electrode plate 210 is formed, part of the film layer of the support structure 800 needs to be removed.

[0104] Please refer to the attached Figure 6 , a photoresist layer 900 is formed on the support structure 800, and then the photoresist layer 900 is patterned to form a mask opening 910 in the photoresist layer 900, wherein the mask opening 910 exposes a columnar structure. The number of the mask openings 910 can be adjusted according to the structure of the semiconductor memory device.

[0105] Please refer to the attached Figure 7 , a wet etching process is used to remove the columnar structure exposed in the mask opening 910 , and then, an etching process is continued to be used to remove the photoresist layer 900 , the first sacrificial layer 840 , and the second sacrificial layer 850 .

[0106] Please refer to the attached Figure 8 , a dielectric layer 230 is formed, and the dielectric layer 230 covers the exposed surface of the first electrode plate 210 , the surface of the support structure 800 , and the top surface of the capacitor contact structure 600 .

[0107] For an example, see the attached Fig. 9 , a second electrode plate 220 is formed on the dielectric layer 230 through a deposition process, and the second electrode plate 220 is a single film layer.

[0108] For another example, see the attached Fig.10 A barrier layer 221 and a conductive layer 222 are stacked on the dielectric layer 230 by a deposition process, and the barrier layer 221 and the conductive layer 222 constitute the second electrode plate 220. The barrier layer 221 is made of titanium nitride, and the conductive layer 222 is made of polysilicon.

[0109] The second electrode plate 220, the first electrode plate 210 located in one of the capacitor holes, and the dielectric layer 230 form a capacitor 200. In this way, the first electrode plates 210 of the plurality of capacitors 200 are relatively independent, and each first electrode plate 210 is connected to the source or drain of the transistor through the capacitor contact structure 600. The second electrode plate 220 connects the plurality of capacitors 200 together, so that the plurality of capacitors 200 are in electrical contact with the semiconductor conductive layer 300.

[0110] The second electrode plate 220 is formed by a unified deposition process, which greatly simplifies the manufacturing process and reduces the production steps and costs compared to the process of making the second electrode plate 220 for each capacitor separately. At the same time, since the second electrode plate 220 is continuous, the defects and variations that may be introduced by separate production are reduced, thereby improving the yield and reliability of the semiconductor memory device.

[0111] Please refer to the attached Fig.11 and attached Fig.12 , forming a semiconductor conductive layer 300, the semiconductor conductive layer 300 is disposed on the second electrode plate 220 and fills the area enclosed by the second electrode plate 220; wherein the top surface of the semiconductor conductive layer 300 is higher than the top surface of the second electrode plate 220. wherein the area enclosed by the second electrode plate 220 constitutes a first portion 310, and the portion located above the support structure constitutes a second portion 320. The first portion 310 of the semiconductor conductive layer 300 covers the capacitor structure and directly contacts the capacitor structure;

[0112] It should be noted that the semiconductor conductive layer 300 with an uneven top surface is obtained through the deposition process, that is, the semiconductor conductive layer 300 has an uneven surface profile.

[0113] Please refer to the attached Fig.13 and attached Fig.14 , continue to use the deposition process to form a capping layer 400, which is located on the upper first part 310 and in direct contact with the first part 310; wherein the surface of the capping layer 400 facing the semiconductor conductive layer 300 has an undulating surface profile, the surface profile has peaks 410 and troughs 420, and the first part 310 extends into the troughs 420.

[0114] By adjusting the process parameters of the semiconductor conductive layer 300 and the cap layer 400, the semiconductor memory device includes a plurality of gaps 500, and at least one gap 500 is located in the first portion 310 in the trough 420. In this way, the plurality of gaps 500 can block the stress generated by the shrinkage or expansion process of the semiconductor conductive layer 300 and / or the cap layer 400, avoid stress concentration at the interface between the semiconductor conductive layer 300 and the cap layer 400, and further avoid delamination of the semiconductor conductive layer 300 and the cap layer 400, thereby improving the performance of the semiconductor memory device.

[0115] Please refer to the attached Figure 1 , Attachment Fig.15 and attached Fig.16 , an insulating layer 720 is formed by a deposition process, and the insulating layer 720 covers the cap layer 400. It should be understood that a semiconductor memory device generally includes an array region and a peripheral circuit region, wherein the array region is used to form a memory cell, and the memory cell includes a transistor and a capacitor structure. The peripheral circuit region is arranged on one side of the array region and is connected to the array region.

[0116] The insulating layer 720 covers not only the capping layer 400 but also the first supporting layer 810 exposed on the peripheral circuit region.

[0117] A conductive plug 730 is formed, and the conductive plug 730 is disposed in the insulating layer 720. The conductive plug 730 extends in a direction perpendicular to the substrate 100, and the end of the conductive plug 730 located on the array region close to the substrate 100 is freely disposed according to the material of the cap layer 400. For example, please refer to the attached Fig.15 and attached Fig.16 When the cover layer 400 is made of a conductive material, the conductive plug 730 located on the array region is disposed in the cover layer 400 near the end of the substrate 100, or in the semiconductor conductive layer 300. Figure 1 When the cover layer 400 is made of insulating material, the conductive plug 730 located on the array region is disposed in the semiconductor conductive layer 300 near the end of the substrate 100 .

[0118] An embodiment of the present application also provides a semiconductor storage device, including a package and the semiconductor storage device described in any of the above embodiments.

[0119] The package body encapsulates the semiconductor memory device, or in other words, the package body is wrapped around the semiconductor memory device to protect the semiconductor memory device. On the one hand, it prevents external water vapor from invading the semiconductor memory device and affecting the normal use of the semiconductor memory device; on the other hand, it makes the packaged semiconductor memory device easy to transport and install.

[0120] In this embodiment, the top surface of the package body is slightly higher than the top surface of the semiconductor memory device, so that the semiconductor memory device can be prevented from being damaged in the subsequent chemical mechanical polishing process, thereby ensuring the performance of the semiconductor memory device, wherein the material of the package body includes but is not limited to resin.

[0121] Since the semiconductor storage device in this embodiment has the semiconductor storage device in any of the above embodiments, the semiconductor storage device in this embodiment has the beneficial effects of the semiconductor storage device in the above embodiments, and this embodiment will not be described in detail here.

[0122] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0123] It should be noted that the phrases "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. mentioned in the specification indicate that the described embodiments may include certain features, structures or characteristics, but not every embodiment may include the certain features, structures or characteristics. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when describing certain features, structures or characteristics in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such features, structures or characteristics in conjunction with other embodiments, whether explicitly or not explicitly described.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor memory device, characterized in that: include: substrate; A capacitor structure, wherein the capacitor structure is disposed on the substrate; The capacitor structure includes a plurality of capacitors; A semiconductor conductive layer, the semiconductor conductive layer comprising a first portion and a second portion, the first portion covers the capacitor structure and directly contacts the capacitor structure; the second portion is filled between adjacent capacitors; A capping layer, the capping layer being located on the upper first portion and in direct contact with the first portion; wherein a surface of the capping layer facing the semiconductor conductive layer has an undulating surface profile, the surface profile having peaks and valleys, and the first portion extends into the valleys; A plurality of voids, at least one void is located within the first portion in the valley.

2. The semiconductor memory device according to claim 1, wherein: The at least one gap faces the bottom of the substrate and is located between the adjacent wave crests and a surface of the cover layer facing away from the substrate.

3. The semiconductor memory device according to claim 1, wherein: There is a minimum distance D1 between at least one of the gaps and a top surface of the capacitor structure facing away from the substrate; There is a distance D2 between two adjacent capacitors in the capacitor structure; The D1 is greater than the D2.

4. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: A plurality of the gaps are spaced apart and arranged in the first portion.

5. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The plurality of voids include a first void, a second void, and a third void, wherein the third void is located within the first portion of the valley; In a first direction, the first gap is located on one side of the third gap, and the second gap is located on the other side of the third gap; There is a first distance D3 between the first gap and the third gap, and there is a second distance D4 between the second gap and the third gap; the first distance D3 is less than or equal to the second distance D4.

6. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: Along the direction from the cap layer to the semiconductor conductive layer, the width of the gap gradually decreases.

7. The semiconductor memory device according to claim 6, wherein: Taking the section perpendicular to the base as the longitudinal section, the longitudinal section of the gap is conical or trapezoidal.

8. The semiconductor memory device according to claim 6, wherein: Taking the section perpendicular to the base as the longitudinal section, the longitudinal section of the gap is semicircular or arc-shaped.

9. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The material of the semiconductor conductive layer includes silicon germanium.

10. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The cover layer is made of insulating material; The insulating material is selected from at least one of HDP oxide, TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, silicon nitride, and silicon nitride oxide.

11. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The cover layer is made of conductive material; The conductive material is selected from at least one of tungsten, titanium nitride and tungsten nitride.

12. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The capacitor comprises a first electrode plate, a second electrode plate and a dielectric layer located between the first electrode plate and the second electrode plate; The semiconductor conductive layer is disposed on the second electrode plate.

13. A semiconductor storage device, characterized in that: A package comprising a semiconductor memory device according to any one of claims 1 to 10; The package encapsulates the semiconductor memory device.

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