Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same. The method for fabricating the semiconductor structure includes forming a plurality of bit line structures and a first contact plug between adjacent bit line structures, wherein a top surface of the first contact plug is lower than a top surface of the bit line structure; forming an isolation layer having a plurality of openings on the top surface of the plurality of bit line structures, each opening exposing a portion of the bit line structure and exposing the first contact plug; and forming a plurality of second contact plugs on the plurality of first contact plugs along the plurality of openings, respectively, wherein a portion of each second contact plug is between adjacent bit line structures and another portion of each second contact plug is on the top surface of the plurality of bit line structures. The semiconductor structure can reduce the problem of short circuit between the contact plugs.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared to static memory, DRAM has advantages such as simpler structure, lower manufacturing cost, and higher capacity density. With the development of technology, the application of DRAM is becoming increasingly widespread.

[0003] Dynamic Random Access Memory (DRAM) is a type of volatile memory. A DRAM device typically includes a memory array region consisting of memory cells and a peripheral region consisting of logic control circuitry. A typical memory cell includes a switching structure (such as a transistor) and a storage structure (such as a capacitor). The logic control circuitry in the peripheral region addresses each memory cell in the memory array region via multiple word lines and bit lines passing through it, and activates the switching structure to electrically connect to the storage structure, thereby performing data reads, writes, or accesses.

[0004] As the size of dynamic random access memory (DRAM) devices continues to shrink, the technical challenges facing patterning processes are becoming increasingly significant, placing ever higher demands on photolithography alignment. For example, due to the shrinking size of memory cells, it is difficult for the switching transistors in the 6F2 architecture to form good electrical contacts with the structures above (such as bit lines or capacitors), or over-etching may occur, leading to short circuits when filling contact plugs and resulting in yield losses. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: forming a plurality of bit line structures and forming a first contact plug between adjacent bit line structures, wherein the top surface of the first contact plug is lower than the top surface of the bit line structure; forming an isolation layer having a plurality of openings on the top surface of the plurality of bit line structures, each opening exposing a portion of the bit line structure and exposing the first contact plug; forming a plurality of second contact plugs on the plurality of first contact plugs along the plurality of openings, wherein a portion of each second contact plug is located between adjacent bit line structures and another portion is located on the top surface of the plurality of bit line structures.

[0006] In some embodiments, the openings are rhomboid in shape, and the rhomboid openings are arranged in a hexagonal close-packed structure on the top surface of the plurality of bitline structures.

[0007] In some embodiments, prior to forming the second contact plug, the method further includes forming a plurality of sidewall protection layers along the plurality of openings, the sidewall protection layers conformally covering the sidewalls of the isolation layer and the sidewalls of the bit line structure exposed by the openings.

[0008] In some embodiments, the materials between the isolation layer, the sidewall protection layer, and the outermost layer of the bitline structure are the same.

[0009] In some embodiments, an isolation layer with multiple openings is formed by a reverse self-aligned dual imaging process.

[0010] In some embodiments, the step of forming an isolation layer with multiple openings includes: forming a lower filler layer on a plurality of first contact plugs, the lower filler layer being located between bit line structures and the top surface of the lower filler layer being flush with the top surface of the bit line structures; forming an upper filler layer on the top surface of the bit line structures and the top surface of the lower filler layer; forming a plurality of first isolation layers extending along a first direction in the upper filler layer; forming a plurality of second isolation layers extending along a second direction in the remaining layer composed of the upper filler layer and the first isolation layers, the second direction intersecting the first direction, the plurality of second isolation layers intersecting with the plurality of first isolation layers in the upper filler layer; using the intersecting plurality of first isolation layers and the plurality of second isolation layers as etching barrier layers, etching the upper filler layer and the lower filler layer downwards to form an isolation layer with multiple openings.

[0011] In some embodiments, before forming the second contact plug, the method further includes: forming a plurality of third contact plugs along a plurality of openings, the third contact plugs being located between adjacent bit line structures and between the top surface of the first contact plug and the bottom surface of the second contact plug.

[0012] In some embodiments, the preparation method further includes: forming a plurality of capacitors on the surfaces of a plurality of third contact plugs, wherein the capacitors are cylindrical or cylindrical capacitors.

[0013] In some embodiments, prior to forming the plurality of bit line structures, the method further includes: providing a substrate, the substrate including a plurality of active regions; forming a plurality of word line structures within the substrate, the word line structures being electrically connected to the active regions; and forming a plurality of bit line contact plugs on the substrate, the bit line structures being electrically connected to the active regions in the substrate through the bit line contact plugs.

[0014] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a plurality of bit line structures; a plurality of first contact plugs respectively located between adjacent bit line structures, the top surface of the first contact plugs being lower than the top surface of the bit line structures; an isolation layer having a plurality of openings located on the top surface of the plurality of bit line structures, wherein each opening exposes a portion of the bit line structure and exposes the first contact plugs; and a plurality of second contact plugs formed within the plurality of openings, a portion of each second contact plug being located between adjacent bit line structures and in contact with the first contact plugs, and another portion being located on the top surface of the plurality of bit line structures.

[0015] In this embodiment of the present disclosure, by forming an isolation layer with multiple openings on the top surface of multiple bit line structures, and then backfilling the openings to form contact plugs with a portion located between adjacent bit line structures and another portion located on the top surface of the bit line structures, a method for forming contact plugs in reverse is provided. This method improves the phenomenon of contact plugs diffusing in the gap between adjacent bit line structures, thereby avoiding short circuits in the contact plugs. This embodiment of the present disclosure can overcome the obstacle of high alignment requirements in photolithography processes. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0017] Figures 2-28 This is a schematic diagram illustrating the semiconductor structure fabrication process according to an exemplary embodiment.

[0018] Figure 29 This is a schematic diagram of the structure of an electronic device according to an exemplary embodiment. Detailed Implementation

[0019] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0020] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0021] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0022] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0023] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0024] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0025] This disclosure provides a semiconductor structure and a method for its fabrication. Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figures 2 to 28 This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure, wherein, Figure 2 , Figure 5 , Figure 8 , Figure 12 , Figure 14 , Figure 16 , Figure 20 , Figure 26 These are schematic diagrams of each stage in the fabrication of a semiconductor structure. Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 9 , Figure 10 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 18 , Figure 19 , Figure 21 , Figure 27 These are cross-sectional views taken along line A-A' and line B-B', respectively, of each stage in the fabrication of the semiconductor structure. Figures 22 to 25 ,as well as Figure 28These are cross-sectional views taken along line A-A' at each stage of semiconductor structure fabrication. The following will combine... Figures 1 to 28 The semiconductor structure and its fabrication process provided in the embodiments of this disclosure will be described in detail. (Refer to...) Figure 1 As shown, the preparation method includes at least the following steps:

[0026] S10: Form multiple bit line structures and form a first contact plug between adjacent bit line structures, wherein the top surface of the first contact plug is lower than the top surface of the bit line structure;

[0027] S20: An isolation layer with multiple openings is formed on the top surface of multiple bit line structures, each opening exposing a portion of the bit line structure and exposing the first contact plug;

[0028] S30: Multiple second contact plugs are formed on multiple first contact plugs along multiple openings, with a portion of each second contact plug located between adjacent bit line structures and another portion located on the top surface of multiple bit line structures.

[0029] It should be understood that Figure 1 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 1 The steps shown can be adjusted in order according to actual needs.

[0030] Please refer to Figures 1 to 3 A substrate 10 is provided, and the substrate 10 is etched to form a plurality of active regions 12 arranged in an array, which are isolated from each other by shallow trench isolation structures 11 (STI). Source regions, drain regions, and channel regions are formed sequentially within the active regions 12, and the transistors of the memory cells are formed on the active regions 12. In this embodiment, a 6F... 2 The architecture of a dynamic random access memory (DRAM) device, where "F" represents the feature size corresponding to the cell.

[0031] The substrate 10 is made of semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art.

[0032] Please continue to refer to this. Figure 2 and Figure 3 , Figure 2 It is a planar schematic diagram that includes bit line structure and word line structure. Figure 3 It is along Figure 2 The figures show cross-sectional views taken along lines A-A' and B-B'. Multiple word line structures 100, such as buried word line structures, are formed within the substrate 10. The buried word line structures are located within the substrate 10 and extend along an X direction parallel to the surface of the substrate 10. Each word line structure 100 connects to multiple active regions 12 along the X-direction. Each word line structure 100 includes a gate dielectric layer (not shown), a gate conductive layer 110, and a gate insulating layer 120. The gate dielectric layer, located between the substrate 10 and the gate conductive layer 110, can be selected from at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a high-k dielectric film with a dielectric constant greater than that of silicon oxide. The gate conductive layer 110 can be selected from at least one of polysilicon (Poly), a metal (e.g., tungsten (W)), or a metal nitride (e.g., titanium nitride (TiN)). The gate insulating layer 120 covers the surface of the gate conductive layer 110 and may be selected from at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON) to protect the word line structure 100.

[0033] Please continue to refer to this. Figures 1 to 3 On the substrate 10, specifically in the direction Z perpendicular to the surface of the substrate 10, a plurality of bit line contact plugs 13 and a plurality of bit line structures 200 are formed. The bit line structures 200 are electrically connected to the active region 12 in the substrate 10 through the bit line contact plugs 13. The plurality of bit line structures 200 are located above the substrate 10 and extend in the Y direction parallel to the surface of the substrate 10, and are perpendicular to the extension direction X of the word line structure 100. The bit line structure 200 includes a first conductive layer 210, a second conductive layer 220, a bit line insulating layer 230 located on the bit line contact plugs 13, and a sidewall layer 240 covering the bit line conductive layers 210, 220 and the bit line insulating layer 230. The first conductive layer 210 and the second conductive layer 220 are, for example, at least one selected from polysilicon, metal (e.g., tungsten (W)) or metal nitride (e.g., titanium nitride (TiN)). Further, for example, the first conductive layer 210 is a polysilicon layer, and the second conductive layer 220 is a metal layer. Of course, the bit line conductive layer may also include a stacked layer formed by more layers. The bit line insulating layer 230 is located on the bit line conductive layers 210 and 220, and is, for example, a silicon nitride (SiN) material. The sidewall layer 240 covers the sidewalls of the bit line conductive layers 210 and 220 and the bit line insulating layer 230. The sidewall layer 240 can form a non-non structure, that is, a sidewall layer composed of silicon nitride (SiN)-silicon oxide (SiO)-silicon nitride (SiN), protecting the bit line structure 200. The bit line contact plug 13 is connected to the first conductive layer 210 in the bit line conductive layer, and is made of the same material as the first conductive layer 210, for example, polysilicon.

[0034] Please continue to refer to this. Figures 1 to 3 A first contact plug 14 is formed between adjacent bit line structures, and the top surface of the first contact plug 14 is lower than the top surface of the bit line structure 200. The first contact plug 14 contacts the active region 12 and can be formed by epitaxial growth on the surface of the active region 12 or by a deposition process. The first contact plug can be doped silicon (Si), silicon-germanium (SiGe), or polysilicon (Poly). Please refer to the following... Figure 3 A lower filler layer material is formed on multiple first contact plugs 14, covering the top surface of the bit line structure 200 and the top surface of the first contact plugs 14. Subsequently, using the bit line structure 200 as a grinding stop layer, the lower filler layer material is planarized to form a lower filler layer 201 flush with the top surface of the bit line structure 200. The lower filler layer material may include an insulating material, such as silicon oxide (SiO), which has a low dielectric constant and high etching selectivity relative to the bit line structure 200. Of course, in other embodiments, the top surface of the lower filler layer 240 may also be higher than the top surface of the bit line structure 200 and cover the bit line structure 200 and the first contact plugs 14. The portion above the top surface of the bit line structure 200 can serve as an upper filler layer 301, thereby avoiding the formation of the upper filler layer 301 and reducing process steps.

[0035] Please return to the reference. Figure 1 An isolation layer 300 with multiple openings 300a is formed on the top surface of multiple bit line structures 200, each opening 300a exposing a portion of the bit line structure 200 and exposing the first contact plug 14.

[0036] For example, please refer to Figure 4 An upper filling layer 301 is formed on the top surface of the bit line structure 200 and the top surface of the lower filling layer 201, and a first initial mask layer 302' and a second initial mask layer 303' are sequentially deposited on the surface of the upper filling layer 301.

[0037] The upper filler layer 301 can be formed on the surface where the bit line structure 200 and the lower filler layer 201 are jointly formed by a deposition process, such as ALD. The upper filler layer 301 can be made of the same material as the lower filler layer, such as silicon oxide (SiO). By removing part of the lower filler layer material to form the upper filler layer 301 located on the surface of the lower filler layer 201, material uniformity can be improved and etching damage to the surface of the filler layer material can be avoided. Furthermore, the density of the formed upper filler layer 301 can be greater than that of the lower filler layer 201 to provide relatively better support.

[0038] The first initial mask layer 302' can be formed on the surface of the upper filler layer 301 by a deposition process, such as an ALD process. It can be made of a material with high etch selectivity relative to the upper filler layer 301 and high hardness to ensure that the pattern maintains the desired morphology during transfer. For example, it can be at least one selected from amorphous carbon (C) layers, silicon (Si) layers, spin-on carbon (SOC) layers, spin-on hard mask (SOH) layers, silicon nitride (SiN) layers, and silicon oxynitride (SiON) layers. The first initial mask layer 302' can be a single layer or multiple layers.

[0039] The second initial mask layer 303' is formed on the first initial mask layer 302', and may include, for example, a spin-coated hard mask (SOH) layer, which can provide good flowability and filling properties. The second initial mask layer 303' can be a single layer or multiple layers. The multilayer second initial mask layer 303' may include a silicon oxynitride (SiON) layer, a spin-coated hard mask (SOH) layer, and a silicon oxynitride (SiON) layer stacked in sequence. The multilayer second initial mask layer 303' has higher etching selectivity than the first initial mask layer 302' and can provide good anti-reflection properties.

[0040] Next, please refer to Figures 5 to 7 , Figure 5 This is a planar schematic diagram showing the formation of multiple photoresist layers 304 extending along the first direction a on the second initial mask layer 303'. Figure 6 It is along Figure 5 Cross-sectional views taken along line A-A' and line B-B'. Please refer to the following. Figure 5 and Figure 6 Photoresist is spin-coated onto the initial second mask layer 303', and after exposure and development, multiple photoresist layers 304 extending along the first direction a are formed. Please refer to [the relevant documentation / reference]. Figure 7 Using the photoresist layer 304 as a mask, the initial second mask layer 303' is etched downwards to form a second mask layer 303 extending along the first direction a. The first direction a is parallel to the surface of the substrate 10 and intersects with the extension direction X of the word line and the extension direction Y of the bit line.

[0041] Please refer to Figure 8 and Figure 9 , Figure 8 This is a planar schematic diagram showing the formation of a third mask layer 305 and a fourth mask layer 306 between the second mask layer 303. Figure 9 It is along Figure 8 The cross-sectional views are taken along lines A-A' and B-B'. A third mask layer 305 is formed on the sidewall of the second mask layer 303, and a fourth mask layer 306 is backfilled between the third mask layers 305. Please continue to refer to the following. Figure 7A third initial mask layer 305' is formed on the surface of the second mask layer 303, and a fourth initial mask layer 306' is backfilled, wherein the fourth initial mask layer 306' can cover the top surface of the third initial mask layer 305'. Then, please refer to... Figure 8 and Figure 9 The fourth initial mask layer 306' and the third initial mask layer 305' located on the surface of the second mask layer 303 are etched to retain the third initial mask layer 305' located on the sidewall of the second mask layer 303, forming the third mask layer 305. The remaining fourth initial mask layers 306' between the third mask layers 305 form the fourth mask layer 306. The material of the third mask layer 305 may, for example, include silicon oxide. The material of the fourth mask layer 306 is the same as the material of the second mask layer 303 to facilitate etching the third mask layer 305 downwards using the second mask layer 303 and the fourth mask layer 305 as etching masks.

[0042] Please refer to Figure 10 Using the second mask layer 303 and the fourth mask layer 306 as etching barrier layers, the third mask layer 305 is etched downwards, followed by the first initial mask layer 302', forming a first mask layer 302 extending along the first direction a. Since the width of the third mask layer 305 is smaller than the width of the second mask layer 303 located between the third mask layers 305, and also smaller than the width of the fourth mask layer 306, after etching away the third mask layer 305 and the first initial mask layer 302', the spacing between adjacent first mask layers 302 is smaller than the spacing between adjacent second mask layers 303, reducing the spacing and doubling the pattern density.

[0043] Please refer to Figure 11 After removing the upper second mask layer 303, third mask layer 305, and fourth mask layer 306, the upper filler layer 301 is etched downwards using the first mask layer 302 as an etching barrier until the top surface of the bit line structure 200 is exposed, forming a plurality of first isolation trenches 310a extending along the first direction a. Subsequently, the first mask layer 302 is removed. The upper filler layer 301 is located on the top surface of both the bit line structure 200 and the lower filler layer 201; therefore, when etching the upper filler layer 301 and exposing a portion of the top surface of the bit line structure 200, a portion of the top surface of the lower filler layer 201 is also necessarily exposed.

[0044] Please refer to Figure 12 and Figure 13 , Figure 12 This is a planar schematic diagram of the first isolation layer 310 extending along the first direction a formed in the upper filling layer 301. Figure 13 It is along Figure 12Cross-sectional views taken along lines A-A' and B-B'. A first isolation layer material is filled into a plurality of first isolation trenches 310a to form a first isolation layer 310. The first isolation layer 310 is located within the upper filling layer 301 and extends along the first direction a. The first isolation layer 310 is continuously located on the bit line structure 200 and the lower filling layer 201. Adjacent first isolation layers 310 are isolated from each other by the upper filling layer 301, which also extends along the first direction a.

[0045] In the exemplary embodiments of this disclosure, the first reverse-self-aligned double patterning (R-SADP) process is performed through the above process to form multiple first isolation layers 310 extending along the first direction a on the top surface of the bit line structure 200. The multiple first isolation layers 310 are located in the upper fill layer 301, doubling the pattern density. The multiple first isolation layers 310 reserve deposition space for the subsequent formation of the second contact plug 16, reducing the high alignment accuracy requirements of the photolithography process.

[0046] Please refer to Figure 14 and Figure 15 , Figure 14 This is a planar schematic diagram showing the formation of multiple photoresist layers 304 extending along the second direction b on the second initial mask layer 303'. Figure 15 It is along Figure 14 The cross-sectional views are taken along lines A-A' and B-B'. Exemplarily, a first initial mask layer 302' and a second initial mask layer 303' are formed again on the layer composed of the remaining upper fill layer 301 and the first isolation layer 310 to facilitate re-patterning in the second direction b. Please refer to [the document for further details]. Figure 14 and Figure 15 Photoresist is spin-coated onto the surface of the second initial mask layer 303', and then exposed and developed to form a plurality of photoresist layers 304 extending along the second direction b.

[0047] Please refer to Figure 16 and Figure 17 , Figure 16 This is a planar schematic diagram showing the formation of a third mask layer 305 and a fourth mask layer 306 between the second mask layer 303. Figure 17 It is along Figure 16 Cross-sectional views taken along lines A-A' and B-B' are shown. Using the photoresist layer 304 as a mask, a second initial mask layer 303' is etched downwards to form a second mask layer 303 extending along the second direction b. The second direction b is parallel to the surface of the substrate 10 and intersects with the extension directions X and Y of the word lines. The second direction b intersects with the first direction a, for example, perpendicularly or obliquely, which can be adjusted according to actual process requirements.

[0048] Please continue to refer to this. Figure 16 and Figure 17 A third mask layer 305 is formed on the sidewall of the second mask layer 303, and a fourth mask layer 306 is backfilled between the third mask layers 305. Similar to the formation process in the first direction a, a third initial mask layer is formed on the surface of the second mask layer 303, and a fourth initial mask layer is backfilled, which may cover the top surface of the third initial mask layer. Subsequently, the fourth initial mask layer and the third initial mask layer located on the surface of the second mask layer 303 are etched to retain the third initial mask layer located on the sidewall of the second mask layer 303, forming the third mask layer 305, while the remaining fourth initial mask layer between the third mask layers 305 forms the fourth mask layer 306. The top surfaces of the second mask layer 303, the third mask layer 305, and the fourth mask layer 306 are flush.

[0049] Please refer to Figure 18 Using the second mask layer 303 and the fourth mask layer 306 as etching barrier layers, the third mask layer 305 is etched downwards, and then the first initial mask layer 302' is etched downwards to form a first mask layer 302 extending along the second direction a. The spacing between adjacent first mask layers 302 is smaller than the spacing between adjacent second mask layers 303.

[0050] Please refer to Figure 19 After removing the remaining second mask layer 303, third mask layer 305, and fourth mask layer 306 from the first mask layer 302, the layer composed of the first mask layer 301 and the first isolation layer 310 is etched downwards, using the second mask layer 302 as an etching barrier layer, until the top surface of the bit line structure 200 is exposed, forming a second isolation trench 320a. The second isolation trench 320a extends along the second direction b, and it is also the location of the sidewall portion of the third mask layer 305 deposited along the second direction b. It is worth noting that during the downward etching process, the second isolation trench 320a not only cuts through the upper filler layer 301 along the second direction b, but also cuts through the first isolation layer 310. Figure 19 As shown in the screenshot of the A-A' line, the first isolation layer 310 located in the upper filling layer 301 is partially etched to form a second isolation trench 320a. Subsequently, after the second isolation trench 320a is filled to form a second isolation layer 320, the first isolation layer 310 and the second isolation layer 320 intersect each other in the upper filling layer 301 on the top surface of the bit line structure 200 through this intersection position.

[0051] Please refer to Figure 20 and Figure 21 , Figure 20This is a planar schematic diagram showing a second isolation layer 320 extending along the second direction b formed in a layer jointly composed of the upper filling layer 301 and the first isolation layer 310. Figure 21 It is along Figure 20 The cross-sectional views are taken along lines A-A' and B-B'. Isolation material is backfilled into the second isolation trench 320a, forming multiple second isolation layers 320 extending along the second direction b within the layer composed of the remaining upper filling layer 301 and the first isolation layer 310. The multiple second isolation layers 320 intersect with the multiple first isolation layers 310 within the upper filling layer 301. The space enclosed by the second isolation layers 320 and the first isolation layers 310 is filled by the upper filling layer 301. In this embodiment, by performing a second R-SADP process, multiple second isolation layers 320 extending along the second direction b are formed on the top surface of the bitline structure 200. These multiple second isolation layers 320 reserve deposition space for the subsequent formation of the second contact plug 16.

[0052] Please refer to Figure 22 Using multiple intersecting first isolation layers 310 and multiple second isolation layers 320 as etching barrier layers, the upper fill layer 301 and the lower fill layer 201 are etched downwards to form an isolation layer 300 with multiple openings 300a. Each opening 300a exposes a portion of the bit line structure 200 and exposes the first contact plug 14. Please refer to the reference. Figure 20 and Figure 22 A portion of the isolation layer 300 is located on the bit line structure 200, and another portion is located on the lower filler layer 201. When the isolation layer 300 is used as a mask, after etching the upper filler layer 301, as the lower filler layer 201 is etched downwards, the top surface of the bit line structure 200 is partially etched, and the portion of the lower filler layer 201 located between the bit line structures 200 that is blocked by the isolation layer 300 is retained. At this time, a deposition space for the second contact plug 16 is formed between adjacent bit line structures 200 and on the top surface of the bit line structure 200. This deposition space is in the shape of an inverted "L". The multiple openings 300a of the isolation layer 300 refer to the horizontal lines in the inverted "L", that is, the openings located on the top surface of the bit line structure 200.

[0053] Please return to the reference. Figure 1 and Figure 22 In one exemplary embodiment provided in this disclosure, an isolation layer 300 is formed by the first isolation layer 310 and the second isolation layer 320 surrounding each other. An isolation layer 300 with a plurality of openings 300a is formed on the top surface of a plurality of bit line structures 200. Each opening 300a exposes a portion of the bit line structure 200 and exposes the first contact plug 14. It is exemplarily shown that the isolation layer 300 with a plurality of openings 300a can be formed by an R-SADP process.

[0054] Please continue to refer to this. Figure 22 In an exemplary embodiment, the first isolation layer 310 and the second isolation layer 320 enclose each other to form an isolation layer 300. The opening 300a is a parallelogram, but in some exemplary embodiments, it can be a rhombus or a rectangle. These openings 300a are offset in opposite directions between the i-th row and the i+1-th row, for example, along the direction X extending along the word line. For example, these openings 300a can be on the top surface of the bit line structure 200, and can be arranged in a hexagonal close-packed (HCP) structure. That is, the projection of six adjacent openings 300a onto the plane of the substrate 10 is a regular hexagon, with an opening 300a at each vertex of the regular hexagon and an opening 300a at the center of the regular hexagon. Subsequently, after filling the second contact plugs 16, the multiple capacitors 400 respectively connected to the multiple second contact plugs 16 also form a hexagonal close-packed structure, forming the densest packed capacitors and improving integration.

[0055] The materials of the first isolation layer 310 and the second isolation layer 320 can be selected from nitrogen-containing material layers, such as at least one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbide nitride (SiOC). The materials of the first isolation layer 310 and the second isolation layer 320 can be the same as each other or different from each other. To improve the adhesion between the materials and avoid peeling or gaps in subsequent processes, the materials of the two can be the same as each other. Furthermore, the material between them and the outermost layer of the bit line structure (i.e., the sidewall layer 240) can both be silicon nitride.

[0056] Please refer to Figure 23 and Figure 24 In an exemplary embodiment of this disclosure, a plurality of sidewall protective layers 330 may be deposited along a plurality of openings 300a, the sidewall protective layers 330 conformally covering the sidewalls of the isolation layer 300 and the sidewalls of the bit line structure 200 exposed by the openings. Specifically, as Figure 23 As shown, a protective layer material 330' is deposited along the opening in an inverted "L"-shaped deposition space using a deposition process, such as the ALD process. The protective layer material 330' covers the top surface of the isolation layer 300, the sidewalls of the isolation layer 300, the top surface of the bit line structure 200, the sidewalls of the bit line structure 200, the top surface of the first contact plug 13, and the remaining sidewalls of the lower filler layer 201. Then, as... Figure 24As shown, the protective layer material 330' located on the top surface of the isolation layer 300, the top surface of the bit line structure 200, and the top surface of the first contact plug 13 is removed by etching back to form a sidewall protective layer 330. The sidewall protective layer 330 can prevent etching damage to the bit line structure 200 when forming the opening 300a, thereby avoiding the diffusion of the second contact plug 16 caused by the interface gap due to multiple depositions of the sidewall layer of the bit line structure 200, that is, the diffusion of the second contact plug 16 into the bit line structure 200 and the diffusion between the second contact plugs 16, causing a short circuit and reducing product yield. Similarly, in the exemplary embodiments of this disclosure, in order to improve the adhesion between materials and reduce the interface gap, the material of the sidewall protective layer 330 can be the same as the material between the outermost layers of the bit line structure 200 and the material of the isolation layer 300, for example, silicon nitride.

[0057] Please refer to Figure 25 A third contact plug 15 is formed along the opening 300a. The third contact plug 15 is located at the bottom of the deposition space, specifically between adjacent bit line structures 200 and on the top surface of the first contact plug 14. As previously stated, the first contact plug 13 is a contact plug that directly contacts the active region in the substrate 10, and it is a doped semiconductor material, such as doped polysilicon. The subsequently deposited second contact plug 16 is a metallic conductive material. To reduce the contact resistance between the two, a third contact plug 15 is formed between the first contact plug 13 and the subsequently deposited second contact plug 16, such as a metal silicide, such as cobalt silicide (CoSi). For example, a layer of cobalt (Co) can be deposited on the surface of the first contact plug 14, and then annealed to form cobalt silicide. Of course, in other embodiments, the third contact plug 15 may not be formed, and the second contact plug 16 may be formed directly.

[0058] Please return to the reference. Figure 1 And please refer to Figure 26 and Figure 27 , Figure 26 This is a planar schematic diagram of the formation of the second contact plug 16. Figure 27 It is along Figure 26The figures show cross-sectional views taken along lines A-A' and B-B'. Multiple second contact plugs 16 are formed by filling along multiple openings 300a. A portion of each second plug 16 is located between adjacent bit line structures 200, and another portion is located on the top surface of the multiple bit line structures 200. Each second contact plug 16 includes a metal barrier layer and a metal conductive layer. Specifically, a metal barrier layer may be deposited along the surface of the sidewall protective layer 330 and the surface of the first contact plug 14 (or, the third contact plug 15), after which a metal conductive layer is backfilled in the remaining space. The metal barrier layer is located between the bit line structure 200 (and the isolation layer 300) and the metal conductive layer to prevent diffusion of the metal conductive layer. For ease of display, only the second contact plug 16 is shown in the figures of this embodiment.

[0059] The metal barrier layer in the second contact plug 16 may be selected from at least one of titanium (Ti), molybdenum (Mo), tungsten (W), or their nitrides, titanium nitride (TiN), molybdenum nitride (MoN), or nitride (WN). The metal conductive layer is selected from at least one of titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), ruthenium (Ru), and iridium (Ir).

[0060] Next, please refer to Figure 28 A capacitor 400 is formed above the bit line structure 200. The capacitor 400 is connected to the active region of the substrate 10 through a second contact plug 16, a third contact plug 15, and a first contact plug 14 to realize data storage. The capacitor 400 can be a cylindrical or pillared capacitor.

[0061] In this embodiment of the present disclosure, by pre-forming an isolation layer 300 with multiple openings on the top surface of the bit line structure 200, and then depositing contact plugs along the openings after removing the filling layers 201 and 301, a method for reverse forming of contact plugs is provided. This method can avoid the phenomenon of short circuits between multiple contact plugs caused by high alignment or etching defects in the photolithography process during the process of first forming a metal conductive layer and then etching back to form multiple contact plugs 14 and 16. Furthermore, in an exemplary embodiment of this disclosure, the sidewalls of the isolation layer 300 and the bit line structure 200 exposed by the opening 300a of the isolation layer 300 form a sidewall protection layer 330. The sidewall protection layer 330 can protect the surfaces of the bit line structure 200 and the isolation layer 300, reduce the interface gap caused by the etching damage of the multiple cap layers and sidewall layers on the bit line structure 200, and avoid the isolation layer 300 being too narrow, thereby preventing the diffusion of the metal barrier layer in the contact plugs 14 and 16, especially the second contact plug 16, which could lead to a short circuit between multiple contact plugs.

[0062] Please continue to refer to this. Figures 26 to 28The semiconductor structure fabricated by the above-described semiconductor structure fabrication method includes a substrate 10, a plurality of word line structures 100, a plurality of bit line contact plugs 13, a plurality of bit line structures 200, a plurality of first contact plugs 14, a plurality of second contact plugs 16, a plurality of third contact plugs 15, an isolation layer 300 with a plurality of openings, and a plurality of capacitors 400. The word line structures 100 are embedded word lines located within the substrate 10. The bit line structures 200 are located above the substrate and are electrically connected to the substrate 10 via the bit line contact plugs 13. The isolation layer 300 with a plurality of openings is located on the top surface of the plurality of bit line structures 200, each opening exposing a portion of the bit line structure 200 and exposing the first contact plugs 14. The first contact plugs 14 are located between adjacent bit line structures 200, and the top surface of the first contact plugs 14 is lower than the top surface of the bit line structures 200. A portion of the second contact plug 16 is located between adjacent bit line structures 200, isolated from each other by the bit line structures 200, and another portion is located on the top surface of the multiple bit line structures 200, isolated from each other by the isolation layer 300. The third contact plug is located between adjacent bit line structures 200, and between the top surface of the first contact plug 14 and the bottom surface of the second contact plug 16. The capacitor 400 is located above the bit line structures 200 and is electrically connected to the substrate 10 in sequence through the second contact plug 16, the third contact plug 15, and the first contact plug 14.

[0063] Please refer to Figure 29 This disclosure also provides an electronic device 1 with storage function. The electronic device includes a processor 2 and a storage device 3 electrically connected to the processor. The storage device includes the aforementioned... Figures 1 to 28 The semiconductor structure 4 described herein. The electronic device can be a terminal device, such as a personal computer, mobile phone, tablet, consumer electronics (e.g., smart home appliances, autonomous vehicles, smart wearable products such as smartwatches and smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, or a server, data center, etc. The memory device 3 can be, for example, dynamic random access memory (DRAM). The semiconductor structure provided by the embodiments of this disclosure can form a 6F... 2 The architecture of the dynamic random access memory (DRAM) device can also form phase-change memory or ferroelectric memory, etc. The storage function in electronic device 1 can be implemented through these memory devices 3.

[0064] In some embodiments, the processor 2 and memory 3 can be two separate chips forming an independent memory. In other embodiments, the memory 3 and processor 2 can also be integrated into the same chip to form an embedded memory. This electronic device 1 is similar to the one described above. Figures 1 to 28 The described semiconductor structure 4 can solve the same technical problem and achieve the same expected results.

[0065] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: forming a plurality of bit line structures and a first contact plug between adjacent bit line structures, the top surface of the first contact plug being lower than the top surface of the bit line structures; forming an isolation layer with a plurality of openings on the top surface of the plurality of bit line structures, each of the openings exposing a portion of the bit line structure and exposing the first contact plug; forming a plurality of second contact plugs on the plurality of first contact plugs along the plurality of openings respectively, a portion of each of the second contact plugs being between adjacent bit line structures and another portion being on the top surface of the plurality of bit line structures; forming the isolation layer with a plurality of openings comprises: forming a lower filling layer on the plurality of first contact plugs, the lower filling layer being between the bit line structures, and the top surface of the lower filling layer being flush with the top surface of the bit line structures; forming an upper filling layer on the top surface of the bit line structures and the top surface of the lower filling layer; forming a plurality of first isolation layers extending in a first direction in the upper filling layer; forming a plurality of second isolation layers extending in a second direction in the layer composed of the remaining upper filling layer and the first isolation layers, the second direction intersecting the first direction, and the plurality of second isolation layers and the plurality of first isolation layers intersecting each other in the upper filling layer; etching the upper filling layer and the lower filling layer downwardly with the plurality of first isolation layers and the plurality of second isolation layers as etching stop layers to form the isolation layer with the plurality of openings.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The openings are rhombic, and the rhombic openings are arranged in a hexagonal close-packed structure on the top surface of the plurality of bit line structures.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before forming the second contact plug, the method further comprises: forming a plurality of sidewall protection layers along the plurality of openings respectively, the sidewall protection layers covering the sidewalls of the isolation layer and the sidewalls of the bit line structures exposed by the openings.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The materials between the isolation layer, the sidewall protection layer, and the outermost layer of the bit line structure are the same.

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The isolation layer with a plurality of openings is formed by a reverse self-aligned double imaging process.

6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before forming the second contact plug, the method further comprises: forming a plurality of third contact plugs along the plurality of openings respectively, the third contact plugs being between adjacent bit line structures and between the top surface of the first contact plug and the bottom surface of the second contact plug.

7. The method of claim 1, wherein the semiconductor structure is formed by a method comprising: The preparation method further comprises: forming a plurality of capacitors on the surface of the plurality of second contact plugs, the capacitors being cylindrical or columnar capacitors.

8. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before forming the plurality of bit line structures, the method further comprises: providing a substrate, the substrate comprising a plurality of active regions; forming a plurality of word line structures in the substrate, the word line structures being electrically connected to the active regions; forming a plurality of bit line contact plugs on the substrate, the bit line structures being electrically connected to the active regions in the substrate through the bit line contact plugs.

9. A semiconductor structure, characterized by The method comprises: a plurality of bit line structures; a plurality of first contact plugs between adjacent bit line structures, the top surface of the first contact plug being lower than the top surface of the bit line structures; a plurality of isolation layers with a plurality of openings, the plurality of isolation layers being on top surfaces of the plurality of bit line structures, wherein each of the openings exposes a portion of the bit line structure and exposes the first contact plug; the isolation layers include a plurality of first isolation layers extending in a first direction and a plurality of second isolation layers extending in a second direction, the second direction intersecting the first direction, the plurality of second isolation layers intersecting the plurality of first isolation layers to enclose the plurality of openings; a plurality of second contact plugs formed in the plurality of openings, a portion of each of the second contact plugs being between adjacent bit line structures in contact with the first contact plug and another portion being on top surfaces of the plurality of bit line structures.

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