Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises a connection structure, a first common electrode, a second common electrode, a first conductive layer and a second conductive layer; the connection structure comprises a first connection part, a second connection part and a conductive connection part; the first connection part is electrically connected with the first common electrode through a first via hole, and the second connection part is electrically connected with the second common electrode through a second via hole; the conductive connection part comprises a first conductive sub-connection part and a second conductive sub-connection part; the first connection part is electrically connected with the second connection part through the first conductive sub-connection part, and the first connection part is electrically connected with the second connection part through the second conductive sub-connection part; the aspect ratio of the first via hole is X1, the aspect ratio of the second via hole is X2, and X1<1X2. The present disclosure can reduce the resistance of the connection part and increase the uniformity of the common electrode network of the entire display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] In the related art, the refresh rate of a high refresh rate product (such as a e-sports display product) can reach 240Hz or even 500Hz, and the corresponding one-line scanning time is very short. When the refresh rate is 500Hz, the one-line scanning time is only 1.8μs, and if the common electrode voltage cannot be restored after being coupled by the data voltage on the data line, line ghosting will occur. SUMMARY

[0003] In one aspect, the display substrate provided by the embodiments of the present disclosure includes a connection structure, a first common electrode, a second common electrode, a first conductive layer, and a second conductive layer; the connection structure includes a first connection part, a second connection part, and a conductive connection part;

[0004] The first connection part is electrically connected to the first common electrode through a first via, and the second connection part is electrically connected to the second common electrode through a second via;

[0005] The conductive connection part includes a first conductive sub-part and a second conductive sub-part; the first connection part is electrically connected to the second connection part through the first conductive sub-part, and the first connection part is electrically connected to the second connection part through the second conductive sub-part;

[0006] The first conductive sub-part is located in the first conductive layer, and the second conductive sub-part is located in the second conductive layer;

[0007] The aspect ratio of the first via is X1, and the aspect ratio of the second via is X2, X1<1X2;

[0008] The aspect ratio of the first via is the ratio of the maximum length of the first via along a first direction to the maximum width of the first via along a second direction, and the aspect ratio of the second via is the ratio of the maximum length of the second via along the first direction to the maximum width of the second via along the second direction;

[0009] The first direction intersects the second direction.

[0010] Optionally, the electrical conductivity of the first conductive layer is less than the electrical conductivity of the second conductive layer.

[0011] Optionally, the first connection part includes a first connection sub-part and a second connection sub-part; the first connection sub-part is electrically connected to the first common electrode and the second connection sub-part through the first via;

[0012] The second connection part includes a third connection part and a fourth connection part, the third connection part is electrically connected with the second common electrode and the fourth connection part through the second via hole;

[0013] The first connection part is electrically connected with the third connection part through the first conductive sub part, and the second connection part is electrically connected with the fourth connection part through the second conductive sub part.

[0014] Optionally, the display substrate further includes a substrate, and the connection structure is arranged on the substrate; the first via hole includes a first via hole part and a second via hole part arranged along a second direction;

[0015] A projection of the first via hole part on the substrate does not overlap with a projection of the second connection part on the substrate; and the projection of the first via hole part on the substrate is inside a projection of the first common electrode on the substrate.

[0016] A projection of the second via hole part on the substrate is inside the projection of the first common electrode on the substrate, and the projection of the second via hole part on the substrate is inside a projection of the second connection part on the substrate.

[0017] The projection of the second connection part on the substrate at least partially overlaps with the projection of the first common electrode on the substrate.

[0018] Optionally, the display substrate further includes a third conductive layer.

[0019] The first common electrode is located in the third conductive layer, the first connection part is located in the first conductive layer, and the second connection part is located in the second conductive layer.

[0020] Optionally, the display substrate further includes a substrate, and the connection structure is arranged on the substrate; the second via hole includes a third via hole part and a fourth via hole part arranged along a first direction;

[0021] A projection of the third via hole part on the substrate does not overlap with a projection of the fourth connection part on the substrate; and the projection of the third via hole part on the substrate is inside a projection of the third connection part on the substrate.

[0022] A projection of the fourth via portion on the substrate substrate is inside a projection of the fourth connection portion on the substrate substrate; a projection of the fourth via portion on the substrate substrate is inside a projection of the third connection portion on the substrate substrate.

[0023] A projection of the fourth connection portion on the substrate substrate at least partially overlaps with a projection of the second common electrode on the substrate substrate.

[0024] Optionally, the display substrate of at least one embodiment of the present disclosure further comprises a fourth conductive layer; the second common electrode is located in the fourth conductive layer, the third connection portion is located in the first conductive layer, and the fourth connection portion is located in the second conductive layer.

[0025] Optionally, X1 is less than or equal to 0.8, and X2 is greater than or equal to 1.2.

[0026] Optionally, X1 / X2 is greater than or equal to 0.3 and less than or equal to 0.6.

[0027] Optionally, a distance between a first edge of a projection of the second via portion on the substrate substrate and a second edge of a projection of the second connection portion on the substrate substrate is greater than a first distance, the first distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0028] The first edge and the second edge are opposite edges.

[0029] Optionally, a shortest distance between an edge of a projection of the first via portion on the substrate substrate and an edge of a projection of the second connection portion on the substrate substrate in a second direction is greater than a second distance, the second distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0030] Optionally, a length of the second via portion in the second direction is greater than a first length, the first length being greater than or equal to 3.9 μm and less than or equal to 4.3 μm.

[0031] Optionally, a distance between an edge of a projection of the first via on the substrate substrate and an edge of a projection of the first connection portion on the substrate substrate is greater than a third distance, the third distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0032] Optionally, a length of the first via in a first direction is greater than a second length, the second length being greater than or equal to 3.8 μm and less than or equal to 4.2 μm.

[0033] Optionally, a distance between a third edge of a projection of the fourth via portion on the substrate and a fourth edge of a projection of the fourth connection portion on the substrate is greater than a fourth distance, the fourth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0034] The third edge and the fourth edge are opposite edges.

[0035] Optionally, a shortest distance between an edge of a projection of the third via portion on the substrate and an edge of a projection of the fourth connection portion on the substrate in a second direction is greater than a fifth distance, the fifth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0036] Optionally, a length of the fourth via portion in the first direction is greater than a third length, the third length being greater than or equal to 3.9 μm and less than or equal to 4.3 μm.

[0037] Optionally, a shortest distance between an edge of a projection of the second via on the substrate and an edge of a projection of the third connection portion on the substrate in the first direction is greater than a sixth distance, the sixth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

[0038] Optionally, a length of the second via in the second direction is greater than a fourth length, the fourth length being greater than or equal to 3.8 μm and less than or equal to 4.2 μm.

[0039] Optionally, a length of a projection of the first via portion on the substrate in the first direction is greater than a length of a projection of the second via portion on the substrate in the first direction; or,

[0040] The length of the projection of the first via portion on the substrate in the first direction is less than the length of the projection of the second via portion on the substrate in the first direction.

[0041] Optionally, a length of the third via portion in the second direction is greater than a length of the fourth via portion in the second direction; or,

[0042] The length of the third via portion in the second direction is less than the length of the fourth via portion in the second direction.

[0043] Optionally, the display substrate further comprises a substrate and a gate line disposed on the substrate.

[0044] A first overlap region exists between a projection of the gate line on the substrate and a projection of the first contact sub-portion in the connection structure on the substrate.

[0045] A second overlap region exists between a normal projection of the gate line on the substrate and a normal projection of a second sub-portion of the connection structure on the substrate;

[0046] An area of the first overlap region is less than an area of the second overlap region.

[0047] Optionally, the display substrate according to at least one of the embodiments of the present disclosure further includes a substrate, and a pixel electrode, a data line, a gate line and a switching transistor disposed on the substrate.

[0048] The gate line includes a first gate line portion and a second gate line portion in communication with each other; and the first gate line portion is multiplexed as a gate electrode of the switching transistor.

[0049] A first electrode of the switching transistor is electrically connected to the data line.

[0050] A second electrode of the switching transistor includes a switching portion, a first electrode portion and a second electrode portion; the switching portion is electrically connected to the pixel electrode, the first electrode portion is disposed on a first side of the switching portion, the second electrode portion is disposed on a second side of the switching portion, and the first side and the second side are opposite sides.

[0051] A normal projection of the first electrode portion on the substrate at least partially overlaps a normal projection of the first gate line portion on the substrate.

[0052] A normal projection of the second electrode portion on the substrate at least partially overlaps a normal projection of the second gate line portion on the substrate.

[0053] Optionally, the display substrate according to at least one of the embodiments of the present disclosure further includes a substrate; and the display substrate includes, in sequence along a direction away from the substrate, a first transparent conductive layer, a gate electrode layer, a source-drain electrode layer and a second transparent conductive layer.

[0054] The first conductive layer is the second transparent conductive layer, and the second conductive layer is the source-drain electrode layer.

[0055] In a second aspect, the embodiments of the present disclosure provide a display device including the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 is a layout diagram of the connection structure according to at least one of the embodiments of the present disclosure;

[0057] Figure 2 is a layout diagram of the first transparent conductive layer in Figure 1 ​

[0058] Figure 3 is a layout diagram of the gate electrode layer in Figure 1

[0059] Figure 4 is a layout diagram of the source-drain electrode layer in Figure 1

[0060] Figure 5 is a layout diagram of the second transparent conductive layer in Figure 1

[0061] Figure 6 is a cross-sectional view of A-A' in Figure 1

[0062] Figure 7 is a cross-sectional view of B-B' in Figure 1

[0063] Figure 8A is an enlarged schematic view of the first via in Figure 1

[0064] Figure 8B is an enlarged schematic view of the first via in Figure 1

[0065] Figure 9A is an enlarged schematic view of the second via in Figure 1

[0066] Figure 9B is an enlarged schematic view of the second via in Figure 1

[0067] Figure 10 is a structural diagram of at least one embodiment of the first via;

[0068] Figure 11 is a structural diagram of at least one embodiment of the first via;

[0069] Figure 12 is a structural diagram of at least one embodiment of the second via;

[0070] Figure 13 is a structural diagram of at least one embodiment of the third via;

[0071] Figure 14 is a layout diagram of the display substrate according to at least one embodiment of the present disclosure;

[0072] Figure 15 is a layout diagram of the first transparent conductive layer in Figure 14

[0073] Figure 16 is a layout diagram of the gate electrode layer in Figure 14 ​​​​​​​​​​​

[0074] Figure 17 yes Figure 14 Layout diagram of the source and drain electrode layers in the image;

[0075] Figure 18 yes Figure 14 Layout diagram of the second transparent conductive layer in the middle;

[0076] Figure 19 yes Figure 14 Layout diagram of the gate electrode layer in the diagram;

[0077] Figure 20 yes Figure 14 Layout diagram of the source and drain electrode layers in the image;

[0078] Figure 21 yes Figure 14 A stack-up diagram of the gate electrode layer and the second transparent conductive layer in the image;

[0079] Figure 22 yes Figure 14 A stack-up diagram of the gate electrode layer and the source / drain electrode layers in the image;

[0080] Figure 23 This is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0081] Figure 24 This is a structural diagram of the display substrate and the first transparent conductive layer included in at least one embodiment of the present disclosure;

[0082] Figure 25 This is a structural diagram of the display substrate, the first transparent conductive layer, and the gate electrode layer included in at least one embodiment of the present disclosure;

[0083] Figure 26 This is a structural diagram of the display substrate, including the substrate, first transparent conductive layer, gate electrode layer, gate insulating layer, semiconductor layer and source / drain electrode layer, as described in at least one embodiment of the present disclosure.

[0084] Figure 27 This is a structural diagram of the display substrate comprising a substrate, a first transparent conductive layer, a gate electrode layer, a gate insulating layer, a semiconductor layer, a source / drain electrode layer, and a passivation layer, according to at least one embodiment of the present disclosure.

[0085] Figure 28 This is a structural diagram of a display substrate comprising a substrate, a first transparent conductive layer, a gate electrode layer, a gate insulating layer, a semiconductor layer, a source / drain electrode layer, a passivation layer, and a second transparent conductive layer, as described in at least one embodiment of this disclosure. Detailed Implementation

[0086] With reference to the drawings and the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure.

[0087] The transistor used in all the embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0088] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0089] The display substrate in the embodiments of the present disclosure comprises a connection structure, a first common electrode, a second common electrode, a first conductive layer and a second conductive layer; the connection structure comprises a first connection part, a second connection part and a conductive connection part;

[0090] The first connection part is electrically connected with the first common electrode through a first via, and the second connection part is electrically connected with the second common electrode through a second via.

[0091] The conductive connection part comprises a first conductive sub-part and a second conductive sub-part; the first connection part is electrically connected with the second connection part through the first conductive sub-part, and the first connection part is electrically connected with the second connection part through the second conductive sub-part.

[0092] The first conductive sub-part is located in the first conductive layer, and the second conductive sub-part is located in the second conductive layer.

[0093] The aspect ratio of the first via is X1, and the aspect ratio of the second via is X2, X1 < 1 < X2.

[0094] The aspect ratio of the first via is the ratio of the maximum length of the first via along a first direction to the maximum width of the via along a second direction, and the aspect ratio of the second via is the ratio of the maximum length of the second via along the first direction to the maximum width of the second via along the second direction.

[0095] The first direction intersects the second direction.

[0096] In the connection structure, the first connection part is electrically connected with the second connection part through the first and second sub-conducting parts respectively, and the second sub-conducting part can reduce the resistance of the sub-conducting part, increase the uniformity of the common electrode network of the whole display panel, and improve the recovery of the common electrode voltage coupled by the data voltage.

[0097] In at least one embodiment of the present disclosure, the first common electrode can be located in the gate electrode layer, the second common electrode can be located in the first transparent conductive layer, the first sub-conducting part can be located in the second transparent conductive layer, and the second sub-conducting part can be located in the source-drain electrode layer, but the present disclosure is not limited thereto.

[0098] Optionally, the first transparent conductive layer can be a first ITO (indium tin oxide) layer, and the second transparent conductive layer can be a second ITO layer.

[0099] In the related art, in a high refresh rate product, for example, in a e-sports display product, the refresh rate can reach 240Hz or above, or even 500Hz, and the corresponding scanning time of one line is very short. When the refresh rate is 500Hz, the scanning time of one line is only 1.8μs. If the common electrode voltage cannot recover after being coupled by the data voltage on the data line, line afterimage will occur. In the related connection structure, the first connection part is electrically connected with the second connection part through the first sub-conducting part, and the first sub-conducting part can be located in the second transparent conductive layer, for example. The resistivity of the second transparent conductive layer is large, and M24 defects will occur. Based on this, in at least one embodiment of the present disclosure, the first connection part is electrically connected with the second connection part through the first sub-conducting part, and the first connection part is electrically connected with the second connection part through the second sub-conducting part. The second sub-conducting part can reduce the resistance of the sub-conducting part.

[0100] Optionally, the conductivity of the first conductive layer is less than the conductivity of the second conductive layer.

[0101] In at least one embodiment of the present disclosure, the resistivity of the second transparent conductive layer is large, and the resistivity of the source-drain electrode layer is small. By electrically connecting the first common electrode and the second common electrode through the second transparent conductive layer and the source-drain electrode layer, the resistance uniformity of the common electrode of the whole display panel can be improved.

[0102] Optionally, the first direction can be a horizontal direction, and the second direction can be a vertical direction, but the present disclosure is not limited thereto.

[0103] Optionally, the first connection part includes a first connection part and a second connection part; the first connection part is electrically connected with the first common electrode and the second connection part through the first via hole;

[0104] The second connection part includes a third connection part and a fourth connection part, and the third connection part is electrically connected with the second common electrode and the fourth connection part through the second via hole;

[0105] The first connection part is electrically connected with the third connection part through the first lead-in sub part, and the second connection part is electrically connected with the fourth connection part through the second lead-in sub part.

[0106] In at least one embodiment of the present disclosure, the first connection part and the first common electrode can be located in different conductive layers, the first connection part and the second connection part can be located in different conductive layers, the third connection part and the second common electrode can be located in different conductive layers, and the third connection part and the fourth connection part can be located in different conductive layers.

[0107] In at least one embodiment of the present disclosure, the first connection part can be located in a second transparent conductive layer, the second connection part can be located in a source-drain electrode layer, the third connection part can be located in a second transparent conductive layer, and the fourth connection part can be located in a source-drain electrode layer, but the present disclosure is not limited thereto.

[0108] In at least one embodiment of the present disclosure, the display substrate can further include a substrate substrate; the connection structure is arranged on the substrate substrate; the first via hole includes a first via hole part and a second via hole part arranged along a second direction;

[0109] The orthogonal projection of the first via hole part on the substrate substrate does not overlap with the orthogonal projection of the second connection part on the substrate substrate, and the orthogonal projection of the first via hole part on the substrate substrate is inside the orthogonal projection of the first common electrode on the substrate substrate.

[0110] The orthogonal projection of the second via hole part on the substrate substrate is inside the orthogonal projection of the first common electrode on the substrate substrate, and the orthogonal projection of the second via hole part on the substrate substrate is inside the orthogonal projection of the second connection part on the substrate substrate.

[0111] The orthogonal projection of the second connection part on the substrate substrate at least partially overlaps with the orthogonal projection of the first common electrode on the substrate substrate.

[0112] In a specific implementation, the first via can be a half-via design, and the first via can be an upper and lower half-via, the lower half-via of the first via is used to electrically connect the first common electrode and the first connection part, and the upper half-via of the first via is used to electrically connect the first connection part and the second connection part; at least one embodiment of the present disclosure can facilitate PI (polyimide) liquid diffusion and improve M24 defects (M24 defects can be Mura (display unevenness) defects) by adopting a half-via design for the first via.

[0113] In at least one embodiment of the present disclosure, the lower half-via of the first via can be formed on the gate electrode layer, the upper half-via of the first via can be formed on the source-drain electrode layer, and the middle bridging part of the first via can be a source-drain metal pattern in the source-drain electrode layer, but the present disclosure is not limited thereto.

[0114] M24 defects can be Mura defects caused by abnormal PI around a PI-free via when there is no PI liquid at the via, or periodic Mura defects caused by uneven PI liquid diffusion at the via. When the via adopts a half-via design, PI liquid diffusion is facilitated.

[0115] Optionally, the display substrate can further include a third conductive layer; the first common electrode is located in the third conductive layer, the first connection part is located in the first conductive layer, and the second connection part is located in the second conductive layer.

[0116] In at least one embodiment of the present disclosure, the third conductive layer can be a gate electrode layer, the first conductive layer can be a second transparent conductive layer, and the second conductive layer can be a source-drain electrode layer, but the present disclosure is not limited thereto.

[0117] In at least one embodiment of the present disclosure, the display substrate further includes a substrate substrate; the connection structure is arranged on the substrate substrate; the second via includes a third via part and a fourth via part arranged along a first direction;

[0118] The orthographic projection of the third via part on the substrate substrate does not overlap with the orthographic projection of the fourth connection part on the substrate substrate; and the orthographic projection of the third via part on the substrate substrate is inside the orthographic projection of the third connection part on the substrate substrate.

[0119] The orthographic projection of the fourth via part on the substrate substrate is inside the orthographic projection of the fourth connection part on the substrate substrate; and the orthographic projection of the fourth via part on the substrate substrate is inside the orthographic projection of the third connection part on the substrate substrate.

[0120] The orthographic projection of the fourth connection part on the substrate substrate at least partially overlaps with the orthographic projection of the second common electrode on the substrate substrate.

[0121] In a specific implementation, the second via can be a half-via design, the second via can be a left-right via, a left half of the second via can be used to electrically connect the second common electrode and the third connection part, and a right half of the second via can be used to electrically connect the third connection part and the fourth connection part. At least one embodiment of the present disclosure can facilitate PI liquid diffusion and improve M24 defects (M24 defects can be Mura defects) by adopting a half-via design for the second via.

[0122] In at least one embodiment of the present disclosure, a left half of the second via can be punched on the second common electrode, a right half of the second via can be punched on the source-drain electrode layer, and a middle bridging part of the second via can be a source-drain metal pattern, but is not limited thereto.

[0123] Optionally, the display substrate can further include a fourth conductive layer; the second common electrode is located in the fourth conductive layer, the third connection part is located in the first conductive layer, and the fourth connection part is located in the second conductive layer.

[0124] In at least one embodiment of the present disclosure, the fourth conductive layer can be a first transparent conductive layer, but is not limited thereto.

[0125] Optionally, X1 is less than or equal to 0.8, and X2 is greater than or equal to 1.2. Further, X1 is less than or equal to 0.64, and X2 is greater than or equal to 1.55.

[0126] In at least one embodiment of the present disclosure, X1 / X2 is greater than or equal to 0.3 and less than or equal to 0.6, for example, X1 / X2 can be 0.3, 0.35, 0.4, 0.45, 0.5, 0.55 or 0.6.

[0127] Optionally, a distance between a first edge of a normal projection of the second via part on the substrate and a second edge of a normal projection of the second connection part on the substrate is greater than a first distance, the first distance is greater than or equal to 1.9 μm and less than or equal to 2.3 μm, for example, the first distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm, so that the first via can be punched on the second conductive layer.

[0128] The first edge and the second edge are opposite edges.

[0129] Optionally, the shortest distance between the edge of the orthographic projection of the first via portion on the substrate and the edge of the orthographic projection of the second connection portion on the substrate along the second direction is greater than a second distance, the second distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm, for example, the second distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm, to ensure the formation of a half via.

[0130] Optionally, the length of the second via portion along the second direction is greater than a first length, the first length being greater than or equal to 3.9 μm and less than or equal to 4.3 μm, for example, the first length can be 3.9 μm, 4 μm, 4.1 μm, 4.2 μm or 4.3 μm, so that even if the second connection portion moves a certain distance due to process deviation when the display substrate is manufactured, the overlapping distance between the second conductive layer and the first via reaches 2 μm or more, ensuring that the first via can be electrically connected with the second conductive layer.

[0131] In at least one embodiment of the present disclosure, the distance between the edge of the orthographic projection of the first via on the substrate and the edge of the orthographic projection of the first connection portion on the substrate is greater than a third distance, the third distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm, for example, the third distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm, to ensure that the first conductive layer wraps the first via and prevents the first via from being exposed and corroded by water vapor and air.

[0132] Optionally, the length of the first via along the first direction is greater than a second length, the second length being greater than or equal to 3.8 μm and less than or equal to 4.2 μm, for example, the second length can be 3.8 μm, 3.9 μm, 4 μm, 4.1 μm or 4.2 μm.

[0133] In at least one embodiment of the present disclosure, the distance between the third edge of the orthographic projection of the fourth via portion on the substrate and the fourth edge of the orthographic projection of the fourth connection portion on the substrate is greater than a fourth distance, the fourth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm, for example, the fourth distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm, to enable the second via to be punched on the second conductive layer.

[0134] The third edge and the fourth edge are opposite edges.

[0135] In at least one embodiment of the present disclosure, the shortest distance between the edge of the orthographic projection of the third via portion on the substrate and the edge of the orthographic projection of the fourth connection portion on the substrate along the second direction is greater than a fifth distance, the fifth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm, for example, the fifth distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm, to ensure the formation of a semi-via.

[0136] Optionally, the length of the fourth via portion along the first direction is greater than a third length, the third length being greater than or equal to 3.9 μm and less than or equal to 4.3 μm, for example, the first length can be 3.9 μm, 4 μm, 4.1 μm, 4.2 μm or 4.3 μm, so that even if the fourth connection portion is shifted by a certain distance due to process deviation when the display substrate is manufactured, the overlapping distance between the second conductive layer and the second via reaches 2 μm or more, ensuring that the second conductive layer can be electrically connected through the second via.

[0137] In at least one embodiment of the present disclosure, the shortest distance between the edge of the orthographic projection of the second via on the substrate and the edge of the orthographic projection of the third connection portion on the substrate along the first direction is greater than a sixth distance, the sixth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm, for example, the fifth distance can be 1.9 μm, 2 μm, 2.1 μs, 2.2 μm or 2.3 μm, to ensure that the first conductive layer wraps the second via and prevents the second via from being exposed and corroded by water vapor and air.

[0138] Optionally, the length of the second via along the second direction is greater than a fourth length, the fourth length being greater than or equal to 3.8 μm and less than or equal to 4.2 μm, for example, the second length can be 3.8 μm, 3.9 μm, 4 μm, 4.1 μm or 4.2 μm.

[0139] Figure 1 is a layout diagram of the connection structure according to at least one embodiment of the present disclosure, Figure 2 is a layout diagram of the first transparent conductive layer in Figure 1 , Figure 3 is a layout diagram of the gate electrode layer in Figure 1 , Figure 4 is a layout diagram of the source-drain electrode layer in Figure 1 , Figure 5 is a layout diagram of the second transparent conductive layer in Figure 1 .

[0140] In Figure 3 , the label GA is a gate line.

[0141] As Figures 1-5As shown, the first common electrode CM1 is electrically connected with the first connecting part L1 and the second connecting part L2 through the first via hole H1 respectively;

[0142] The second common electrode CM2 is electrically connected with the third connecting part L3 and the fourth connecting part L4 through the second via hole H2 respectively;

[0143] The first common electrode CM1 is located in the gate electrode layer, the first connecting part L1 is located in the second transparent conductive layer, the second connecting part L2 is located in the source-drain electrode layer, the second common electrode CM2 is located in the first transparent conductive layer, the third connecting part L3 is located in the second transparent conductive layer, and the fourth connecting part L4 is located in the source-drain electrode layer;

[0144] The first connecting part L1 is electrically connected with the third connecting part L3 through the first sub-connection part D1, and the second connecting part L2 is electrically connected with the fourth connecting part L4 through the second sub-connection part D2;

[0145] The first sub-connection part D1 is located in the second transparent conductive layer, and the second sub-connection part D2 is located in the source-drain electrode layer, but not limited thereto.

[0146] Figure 6 is a cross-sectional view of A-A' in Figure 1 Figure 7 is a cross-sectional view of B-B' in Figure 1 .

[0147] In Figure 6 and Figure 7 , the number 60 is a substrate, the number 61 is a first transparent conductive layer, the number 62 is a gate electrode layer, the number 63 is a source-drain electrode layer, and the number 64 is a second transparent conductive layer;

[0148] The number 601 is a gate insulating layer, and the number 602 is a passivation layer.

[0149] Figure 8A is an enlarged schematic view of the first via hole in Figure 1 Figure 9A is an enlarged schematic view of the second via hole in Figure 1 .

[0150] As shown in Figure 8A , the first via hole H1 includes a first via hole part H11 and a second via hole part H12 arranged along a vertical direction;

[0151] As shown in Figures 1-8A ​​As shown, the orthogonal projection of the first via portion H11 on the substrate substrate does not overlap with the orthogonal projection of the second connection portion L2 on the substrate substrate; the orthogonal projection of the first via portion H11 on the substrate substrate is inside the orthogonal projection of the first common electrode CM1 on the substrate substrate;

[0152] The orthogonal projection of the second via portion H12 on the substrate substrate is inside the orthogonal projection of the first common electrode CM1 on the substrate substrate, and the orthogonal projection of the second via portion H12 on the substrate substrate is inside the orthogonal projection of the second connection portion L2 on the substrate substrate;

[0153] The orthogonal projection of the second connection portion L2 on the substrate substrate at least partially overlaps with the orthogonal projection of the first common electrode CM1 on the substrate substrate.

[0154] As Figure 8A shown, b' is the distance between the lower edge of the orthogonal projection of the first via portion H11 on the substrate substrate and the lower edge of the orthogonal projection of the second connection portion L2 on the substrate substrate in the vertical direction, b' is greater than 2.1 μm, to ensure that the upper and lower half-vias are formed;

[0155] c' is the length of the second via portion H12 in the vertical direction, c' is greater than 4.1 μm, to ensure that even if the second connection portion L2 moves up by 2.1 μm due to process deviation when the display substrate is manufactured, the overlapping distance between the source-drain electrode layer and the first via H1 reaches 2 μm or more, to ensure that the source-drain electrode layer can be electrically connected with the first via H1;

[0156] a1' is the shortest distance between the left edge of the orthogonal projection of the first via H1 on the substrate substrate and the left edge of the orthogonal projection of the first connection portion L1 on the substrate substrate, and a2' is the shortest distance between the right edge of the orthogonal projection of the first via H1 on the substrate substrate and the right edge of the orthogonal projection of the first connection portion L1 on the substrate substrate, both a1' and a2' are greater than 2.1 μm, to ensure that the second transparent conductive layer can wrap around the via to prevent the via from being exposed and being corroded by water vapor and air;

[0157] e' is the distance between the left edge of the orthogonal projection of the second via portion H12 on the substrate substrate and the left edge of the orthogonal projection of the second connection portion L2 on the substrate substrate in the horizontal direction, e' is greater than 2.1 μm, to ensure that the first via H1 can be punched on the source-drain electrode layer;

[0158] d' is the length of the first via H1 in the horizontal direction, d' is greater than 4 μm;

[0159] But not limited to.

[0160] In actual operation, the length of the first via H1 in the horizontal direction needs to be set to be small so as not to affect the pixel aperture ratio.

[0161] In Figure 8A In at least one embodiment shown, the first edge and the second edge can both be lower edges, but not limited to.

[0162] In Figure 8A In at least one embodiment shown, the first via is a rectangular via, but not limited to. In actual operation, the first via can be of other shapes.

[0163] As Figure 8B shown, the first via H1 can be a rounded rectangular via, but not limited to.

[0164] As Figures 1-9A shown, the second via includes a third via portion H23 and a fourth via portion H24 arranged along the horizontal direction;

[0165] The orthographic projection of the third via portion H23 on the substrate substrate does not overlap with the orthographic projection of the fourth connecting portion L4 on the substrate substrate; the orthographic projection of the third via portion H3 on the substrate substrate is inside the orthographic projection of the third connecting portion L3 on the substrate substrate;

[0166] The orthographic projection of the fourth via portion H24 on the substrate substrate is inside the orthographic projection of the fourth connecting portion L4 on the substrate substrate; the orthographic projection of the fourth via portion H24 on the substrate substrate is inside the orthographic projection of the third connecting portion L3 on the substrate substrate;

[0167] The orthographic projection of the fourth connecting portion L4 on the substrate substrate at least partially overlaps with the orthographic projection of the second common electrode CM2 on the substrate substrate.

[0168] As Figure 9A shown, b is the distance between the left edge of the orthographic projection of the third via portion H23 on the substrate substrate and the left edge of the orthographic projection of the fourth connecting portion L4 on the substrate substrate in the horizontal direction, b is greater than 2.1 μm to ensure that the left and right half vias are formed;

[0169] c is the length of the fourth via portion H24 in the horizontal direction, c is greater than 4.1 μm to ensure that even if the fourth connecting portion L4 moves right by 2.1 μm due to process deviation when the display substrate is manufactured, the overlapping distance between the source-drain electrode layer and the second via H2 reaches 2 μm or more, ensuring that the source-drain electrode layer can be electrically connected through the second via H2.

[0170] The distance labeled a1 is the shortest distance between the lower edge of the orthographic projection of the second via H2 on the substrate and the lower edge of the orthographic projection of the third connecting portion L3 on the substrate. The distance labeled a2 is the shortest distance between the upper edge of the orthographic projection of the second via H2 on the substrate and the upper edge of the orthographic projection of the third connecting portion L3 on the substrate. Both a1 and a2 are greater than 2.1 μm to ensure that the second transparent conductive layer can cover the via and prevent the via from being exposed and corroded by moisture and air.

[0171] The distance marked e is the shortest vertical distance between the lower edge of the orthographic projection of the fourth via portion H24 on the substrate and the lower edge of the orthographic projection of the fourth connection portion L4 on the substrate. e is greater than 2.1 μm, ensuring that the second via H2 can be placed on the source and drain electrode layers.

[0172] The length of the second via H2 in the vertical direction is marked with d, and d is greater than 4μm;

[0173] However, this is not the limit.

[0174] In actual operation, the length of the second via H2 in the vertical direction needs to be set to be small in order to avoid affecting the pixel aperture ratio.

[0175] exist Figure 9A In at least one embodiment shown, the third edge and the fourth edge may both be left edges, but are not limited thereto.

[0176] exist Figures 1-9A In one embodiment, both the first via H1 and the second via H2 are rectangular vias, but this is not a limitation.

[0177] exist Figure 9A In at least one embodiment shown, the second via is a rectangular via, but this is not a limitation. In practice, the second via can be of other shapes.

[0178] like Figure 9B As shown, the second via H2 can be a rounded rectangular via, but is not limited to this.

[0179] In at least one embodiment of this disclosure, the length of the orthographic projection of the first via portion onto the substrate along the first direction is greater than the length of the orthographic projection of the second via portion onto the substrate along the first direction; or,

[0180] The length of the orthographic projection of the first via portion on the substrate along the first direction is less than the length of the orthographic projection of the second via portion on the substrate along the first direction.

[0181] As shown in Figure 10 the length of the horizontal direction of the orthographic projection of the first via portion H11 on the substrate substrate is greater than the length of the horizontal direction of the orthographic projection of the second via portion H12 on the substrate substrate.

[0182] As shown in Figure 11 the length of the horizontal direction of the orthographic projection of the first via portion H11 on the substrate substrate is less than the length of the horizontal direction of the orthographic projection of the second via portion H12 on the substrate substrate.

[0183] In at least one embodiment of the present disclosure, the length of the third via portion along the second direction is greater than the length of the fourth via portion along the second direction; or,

[0184] the length of the third via portion along the second direction is less than the length of the fourth via portion along the second direction.

[0185] As shown in Figure 12 the length of the vertical direction of the orthographic projection of the third via portion H23 on the substrate substrate is greater than the length of the vertical direction of the orthographic projection of the fourth via portion H24 on the substrate substrate.

[0186] As shown in Figure 13 the length of the vertical direction of the orthographic projection of the third via portion H23 on the substrate substrate is less than the length of the vertical direction of the orthographic projection of the fourth via portion H24 on the substrate substrate.

[0187] In specific implementation, the first via and the second via can be a "convex" shaped via. Whether it is a narrow-to-wide flow or a wide-to-narrow flow, the "convex" shaped via is more conducive to the diffusion of PI liquid in the via.

[0188] The display substrate provided by the embodiments of the present disclosure comprises a substrate substrate and a first common electrode, a second common electrode and the above-mentioned connecting structure arranged on the substrate substrate.

[0189] The connecting structure is used to electrically connect the first common electrode and the second common electrode.

[0190] The display substrate provided by at least one embodiment of the present disclosure further comprises a gate line arranged on the substrate substrate.

[0191] The orthographic projection of the gate line on the substrate substrate and the orthographic projection of the first conductive sub-portion in the connecting structure on the substrate substrate have a first overlapping area.

[0192] The orthographic projection of the gate line on the substrate substrate and the orthographic projection of the second conductive sub-portion in the connecting structure on the substrate substrate have a second overlapping area.

[0193] The area of the first overlap region is less than the area of the second overlap region, in particular, the area of the first overlap region and the area of the second overlap region are less than a first area, and the first area is greater than or equal to 14 μm 2 and less than or equal to 18 μm 2 For example, the first area can be 14 μm 2 , 15 μm 2 , 16 μm 2 , 17 μm 2 or 18 μm 2 , so as to reduce the parasitic capacitance between the gate line and the first conductive sub, reduce the parasitic capacitance between the gate line and the second conductive sub, and prevent the load on the gate line from increasing.

[0194] As shown in Figures 14-18 , the display substrate includes a substrate, a first row of gate lines GA1, a second row of gate lines GA2, a first row of common electrode lines CML1 and a second row of common electrode lines CML2, a first column of data lines DL1, a second column of data lines DL2, a third column of data lines DL3, a fourth column of data lines DL4, a first second common electrode CM12, a second second common electrode CM22, a third second common electrode CM32, a first row of first column of switching transistors M11, a first row of second column of switching transistors M12, a first row of third column of switching transistors M13, a second row of first column of switching transistors M21, a second row of second column of switching transistors M22, a second row of third column of switching transistors M23, a first connection structure LJ1, a second connection structure LJ2, a first pixel electrode PJ1, a second pixel electrode PJ2 and a third pixel electrode PJ3.

[0195] The first row of common electrode lines CML1 serves as a first first common electrode CM11, and the second row of common electrode lines CML2 serves as a second first common electrode CM21.

[0196] The CML1, the CML2, the GA1 and the GA2 are all located in a gate electrode layer.

[0197] The DL1, the DL2, the DL3, the DL4, a first electrode of the M11, a second electrode of the M11, a first electrode of the M12, a second electrode of the M12, a first electrode of the M13, a second electrode of the M13, a first electrode of the M21, a second electrode of the M21, a first electrode of the M22, a second electrode of the M22, a first electrode of the M23 and a second electrode of the M23 are all located in a source-drain electrode layer.

[0198] The CM12, the CM22 and the CM32 are all located in a first transparent conductive layer.

[0199] PJ1, PJ2 and PJ3 are all located in the second transparent conductive layer.

[0200] Figure 14 is a layout diagram of the display substrate described in at least one embodiment of the present disclosure, Figure 15 is Figure 14 is a layout diagram of the first transparent conductive layer in Figure 16 is Figure 14 is a layout diagram of the gate electrode layer in Figure 17 is Figure 14 is a layout diagram of the source-drain electrode layer in Figure 18 is Figure 14 is a layout diagram of the second transparent conductive layer in Figure 19 is Figure 14 is a layout diagram of the gate electrode layer in Figure 20 is Figure 14 is a layout diagram of the source-drain electrode layer in Figure 21 is Figure 14 is a layout diagram of the gate electrode layer and the second transparent conductive layer in Figure 22 is Figure 14 is a layout diagram of the gate electrode layer and the source-drain electrode layer in

[0201] The display substrate described in at least one embodiment of the present disclosure further comprises a substrate, and a pixel electrode, a data line, a gate line and a switching transistor disposed on the substrate;

[0202] The gate line comprises a first gate line portion and a second gate line portion in communication with each other; the first gate line portion is multiplexed as a gate electrode of the switching transistor;

[0203] The first electrode of the switching transistor is electrically connected with the data line;

[0204] The second electrode of the switching transistor comprises a switching portion, a first electrode portion and a second electrode portion; the switching portion is electrically connected with the pixel electrode, the first electrode portion is disposed on a first side of the switching portion, the second electrode portion is disposed on a second side of the switching portion, and the first side and the second side are opposite sides;

[0205] The orthographic projection of the first electrode portion on the substrate at least partially overlaps with the orthographic projection of the first gate line portion on the substrate;

[0206] The orthographic projection of the second electrode portion on the substrate at least partially overlaps with the orthographic projection of the second gate line portion on the substrate.

[0207] As shown in Figures 14-18 the first electrode S11 of M11 is electrically connected with the first column of data lines DL1, and the first electrode S21 of M21 is electrically connected with the first column of data lines DL1;

[0208] The first electrode S12 of M12 is electrically connected to the second column data line DL2, and the first electrode S22 of M22 is electrically connected to the second column data line DL2.

[0209] The first electrode S13 of M13 is electrically connected to the third column data line DL3, and the first electrode S23 of M23 is electrically connected to the third column data line DL3.

[0210] like Figure 19 As shown, the first row of grid lines includes a first first grid line portion GB11, a first second grid line portion GB12, a second first grid line portion GB21, a second second grid line portion GB22, a third first grid line portion GB31, and a third second grid line portion GB32 that are interconnected; the second row of grid lines includes a fourth first grid line portion GB41, a fourth second grid line portion GB22, a fifth first grid line portion GB51, a fifth second grid line portion GB52, a sixth first grid line portion GB61, and a sixth second grid line portion GB62.

[0211] GB11 is multiplexed as the gate of M11, GB12 is multiplexed as the gate of M12, GB13 is multiplexed as the gate of M13, GB21 is multiplexed as the gate of M21, GB22 is multiplexed as the gate of M22, and GB23 is multiplexed as the gate of M23.

[0212] like Figure 20 As shown, the second electrode of M23 includes a transition part Z1, a first electrode part B1, and a second electrode part B2.

[0213] The first electrode portion B1 is located on the left side of the transition portion Z1, and the second electrode portion B2 is located on the right side of the transition portion Z1.

[0214] like Figures 14-20 As shown, the orthographic projection of the first electrode portion B1 on the substrate at least partially overlaps with the orthographic projection of GB61 on the substrate, and the orthographic projection of the second electrode portion B2 on the substrate at least partially overlaps with the orthographic projection of GB62 on the substrate, so that even if the second row of gate lines GA2 shifts to the right or left due to process deviations, Cgs can be approximately the same, where Cgs is the gate-source parasitic capacitance.

[0215] like Figures 14-22 As shown, there is a first overlapping region A1 between the orthographic projection of the second row of gate lines GA2 on the substrate and the orthographic projection of the first conductive part D1 included in the second connection structure on the substrate, and there is a second overlapping region A2 between the orthographic projection of the second row of gate lines GA2 on the substrate and the orthographic projection of the second conductive part D2 included in the second connection structure on the substrate.

[0216] The area of ​​the first overlapping region A1 is less than 16 μm.2 The second overlap area A2 has an area less than 16 μm 2 To reduce the parasitic capacitance between the second row gate line GA2 and the first conductive sub D1, reduce the parasitic capacitance between the second row gate line GA2 and the second conductive sub D2, and prevent the load on the second row gate line GA2 from increasing.

[0217] As shown in Figure 23 The display substrate can include a first row gate line GA1, a first row common electrode line CML1, a second row gate line GA2, a second row common electrode line CML2, a third row gate line GA3, a third row common electrode line CML3, a common electrode bus VBL, a first column data line DL1, a second column data line DL2, a third column data line DL3, a fourth column data line DL4, a fifth column data line DL5, a sixth column data line DL6, a first row first column pixel electrode P11, a first row second column pixel electrode P12, a first row third column pixel electrode P13, a first row fourth column pixel electrode P14, a first row fifth column pixel electrode P15, a first row sixth column pixel electrode P16, a second row first column pixel electrode P21, a second row second column pixel electrode P22, a second row third column pixel electrode P23, a second row fourth column pixel electrode P24, a second row fifth column pixel electrode P25, a second row sixth column pixel electrode P26, and a plurality of switch transistors.

[0218] The GA1, GA2, GA3, CML1, CML2, CML3, and VBL are all located in the gate electrode layer.

[0219] The VBL is arranged around the display area.

[0220] The VBL, CML1, CML2, and CML3 are in communication.

[0221] The DL1, DL2, DL3, DL4, DL5, and DL6 are all located in the source-drain electrode layer.

[0222] The P11, P12, P13, P14, P15, P16, P21, P22, P23, P24, P25, and P16 are all located in the second transparent conductive layer.

[0223] The CML1 is electrically connected to a first second common electrode located in the first transparent conductive layer through a third connection structure LJ3, and is electrically connected to a second second common electrode located in the first transparent conductive layer through a fourth connection structure LJ4; the first second common electrode is electrically connected to the VBL through a first conductive sub DB1 located in the second transparent conductive layer, and the second second common electrode is electrically connected to the VBL through a second conductive sub DB2 located in the second transparent conductive layer.

[0224] CML2 is electrically connected to the third second common electrode located in the first transparent conductive layer through the fifth connection structure LJ5, and CML2 is electrically connected to the fourth second common electrode located in the first transparent conductive layer through the sixth connection structure LJ6.

[0225] CML3 is electrically connected to the fifth second common electrode located in the first transparent conductive layer through the seventh connection structure LJ7; CML2 is electrically connected to the sixth second common electrode located in the first transparent conductive layer through the eighth connection structure LJ8; CML3 is electrically connected to VBL through the third conductive portion DB3 located in the second transparent conductive layer; and CML3 is electrically connected to VBL through the fourth conductive portion DB4 located in the second transparent conductive layer.

[0226] In at least one embodiment of this disclosure, the display substrate includes a first transparent conductive layer, a gate electrode layer, a source / drain electrode layer, and a second transparent conductive layer arranged sequentially along a direction away from the substrate.

[0227] The first conductive part of the connection structure is located in the first conductive layer; the second conductive part of the connection structure is located in the second conductive layer.

[0228] The first conductive layer is the second transparent conductive layer, and the second conductive layer is the source / drain electrode layer.

[0229] During the fabrication of the display substrate

[0230] First, such as Figure 24 As shown, a first transparent conductive layer 61 is first fabricated on a substrate 60. The thickness of the first transparent conductive layer 61 can be 700 angstroms. After coating, exposure, development and wet etching, a second common electrode is formed.

[0231] like Figure 25 As shown, the gate electrode layer 62 is then fabricated. The gate electrode layer includes a first Mo (molybdenum) layer, a first Al (aluminum) layer and a second Mo layer sequentially disposed along a direction away from the substrate 60. The thickness of the first Mo layer is 150 angstroms, the thickness of the first Al layer is 3000 angstroms and the thickness of the second Mo layer is 800 angstroms. After coating, exposure, development and wet etching, gate lines and common electrode lines are formed.

[0232] like Figure 26 As shown, after the gate lines and common electrode lines are fabricated, a full layer of gate insulating layer 601 is then laid on. The gate insulating layer 601 has a thickness of 4000 angstroms and is made of SiNx (silicon nitride).

[0233] Then, a semiconductor layer 65 is plated, the thickness of the semiconductor layer 65 is 1700 angstrom, and a source-drain electrode layer 63 is plated, the source-drain electrode layer can include a third Mo (molybdenum) layer, a second Al (aluminum) layer and a fourth Mo layer arranged in sequence along the direction away from the substrate 60, the thickness of the third Mo layer is 150 angstrom, the thickness of the second Al layer is 3000 angstrom, and the thickness of the fourth Mo layer is 800 angstrom, and then, by using an SSM (Single Slit Mask) process (4Mask process), a first electrode of a switching transistor, a second electrode of the switching transistor and a channel are formed by wet etching once and dry etching once, the source-drain metal is etched away in the first wet etching to form the first electrode of the switching transistor and the second electrode of the switching transistor, and the channel is exposed in the second dry etching;

[0234] As shown in Figure 27 Afterwards, a passivation layer 602 is made, an entire layer of the passivation layer is deposited, the thickness of the passivation layer 602 is 4000 angstrom, the passivation layer 602 is made of SiNx, and after exposure, development and etching, the dry etching is performed on the unnecessary insulating layer to expose the via, such as the connecting via of the pixel electrode, the first via and the second via;

[0235] As shown in Figure 28 A second transparent conductive layer 64 is made, the thickness of the second transparent conductive layer 64 is 700 angstrom, and after plating, exposure, development and wet etching, the desired pattern (mainly the pixel electrode) and the connecting structure including the conductive pattern in the second transparent conductive layer are formed.

[0236] The 4Mask process is explained as follows: the semiconductor layer and the source-drain electrode layer are made at the same time, compared with the traditional 5Mask, the 4Mask process is to deposit the semiconductor layer and the source-drain electrode layer together, perform the mask only once after coating the photoresist, and form part of the exposure in the channel area by using the SSM process, and then etch out the source-drain metal pattern, and then expose the channel by ashing.

[0237] The display device described in the embodiments of the present disclosure includes the display substrate described above.

[0238] In at least one embodiment of the present disclosure, the display device can be a liquid crystal display, but is not limited thereto. In actual operation, the display device can also be other types of display devices.

[0239] The above is the preferred embodiment of the present disclosure, and it should be pointed out that for ordinary skilled persons in the technical field, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present disclosure.

Claims

1. A display substrate, comprising a connection structure, a first common electrode, a second common electrode, a first conductive layer and a second conductive layer; the connection structure comprises a first connection part, a second connection part and a conductive connection part; the first connection part is electrically connected with the first common electrode through a first via, and the second connection part is electrically connected with the second common electrode through a second via; the conductive connection part comprises a first conductive connection subpart and a second conductive connection subpart; the first connection part is electrically connected with the second connection part through the first conductive connection subpart, and the first connection part is electrically connected with the second connection part through the second conductive connection subpart; the first conductive connection subpart is located in the first conductive layer, and the second conductive connection subpart is located in the second conductive layer; an aspect ratio of the first via is X1, and an aspect ratio of the second via is X2, X1 < 1 < X2; the aspect ratio of the first via is a ratio of a maximum length of the first via along a first direction to a maximum width of the first via along a second direction, and the aspect ratio of the second via is a ratio of a maximum length of the second via along the first direction to a maximum width of the second via along the second direction; the first direction intersects the second direction. 2.The display substrate of claim 1, wherein, an electrical conductivity of the first conductive layer is less than an electrical conductivity of the second conductive layer. 3.The display substrate of claim 1, wherein, the first connection part comprises a first connection subpart and a second connection subpart; the first connection subpart is electrically connected with the first common electrode and the second connection subpart through the first via; the second connection part comprises a third connection subpart and a fourth connection subpart; the third connection subpart is electrically connected with the second common electrode and the fourth connection subpart through the second via; the first connection subpart is electrically connected with the third connection subpart through the first conductive connection subpart, and the second connection subpart is electrically connected with the fourth connection subpart through the second conductive connection subpart. 4.The display substrate of claim 3, wherein, further comprising a substrate, the connection structure is disposed on the substrate; the first via comprises a first via part and a second via part arranged along a second direction; a normal projection of the first via part on the substrate does not overlap with a normal projection of the second connection subpart on the substrate; the normal projection of the first via part on the substrate is inside a normal projection of the first common electrode on the substrate; a normal projection of the second via part on the substrate is inside the normal projection of the first common electrode on the substrate, and the normal projection of the second via part on the substrate is inside a normal projection of the second connection subpart on the substrate; the normal projection of the second connection subpart on the substrate at least partially overlaps with the normal projection of the first common electrode on the substrate. 5.The display substrate of claim 4, wherein, further comprising a third conductive layer; the first common electrode is located in the third conductive layer, the first connection subpart is located in the first conductive layer, and the second connection subpart is located in the second conductive layer. 6.The display substrate of claim 3, wherein, further comprising a substrate; the connection structure is disposed on the substrate; the second via comprises a third via part and a fourth via part arranged along a first direction; A projection of the third via portion on the substrate substrate does not overlap with a projection of the fourth connection portion on the substrate substrate; A projection of the third via portion on the substrate substrate is inside a projection of the third connection portion on the substrate substrate; A projection of the fourth via portion on the substrate substrate is inside a projection of the fourth connection portion on the substrate substrate; A projection of the fourth via portion on the substrate substrate is inside a projection of the third connection portion on the substrate substrate; A projection of the fourth connection portion on the substrate substrate at least partially overlaps with a projection of the second common electrode on the substrate substrate. 7.The display substrate of claim 6, wherein, Further comprising a fourth conductive layer; the second common electrode is in the fourth conductive layer, the third connection portion is in the first conductive layer, and the fourth connection portion is in the second conductive layer. 8.The display substrate of claim 1, wherein, X1 is less than or equal to 0.8, and X2 is greater than or equal to 1.

2. 9.The display substrate of any one of claims 1 to 8, wherein, X1 / X2 is greater than or equal to 0.3 and less than or equal to 0.

6. 10.The display substrate of claim 4, wherein, A distance between a first edge of a projection of the second via portion on the substrate substrate and a second edge of a projection of the second connection portion on the substrate substrate is greater than a first distance, the first distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm; The first edge and the second edge are opposite edges. 11.The display substrate of claim 4, wherein, A shortest distance between an edge of a projection of the first via portion on the substrate substrate and an edge of a projection of the second connection portion on the substrate substrate in a second direction is greater than a second distance, the second distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm. 12.The display substrate of claim 4, wherein, A length of the second via portion in the second direction is greater than a first length, the first length being greater than or equal to 3.9 μm and less than or equal to 4.3 μm. 13.The display substrate of claim 4, wherein, A distance between an edge of a projection of the first via on the substrate substrate and an edge of a projection of the first connection portion on the substrate substrate is greater than a third distance, the third distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm. 14.The display substrate of claim 4, wherein, A length of the first via in the first direction is greater than a second length, the second length being greater than or equal to 3.8 μm and less than or equal to 4.2 μm. 15.The display substrate of claim 6, wherein, A distance between a third edge of a projection of the fourth via portion on the substrate substrate and a fourth edge of a projection of the fourth connection portion on the substrate substrate is greater than a fourth distance, the fourth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm; The third edge and the fourth edge are opposite edges. 16.The display substrate of claim 6, wherein, A shortest distance between an edge of a projection of the third via portion on the substrate substrate and an edge of a projection of the fourth connection portion on the substrate substrate in a second direction is greater than a fifth distance, the fifth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

17. The display substrate of claim 6, wherein, A length of the fourth via portion in the first direction is greater than a third length, the third length being greater than or equal to 3.9 μm and less than or equal to 4.3 μm. 18.The display substrate of claim 5, wherein, A shortest distance between an edge of a projection of the second via on the substrate and an edge of a projection of the third connection portion on the substrate in a first direction is greater than a sixth distance, the sixth distance being greater than or equal to 1.9 μm and less than or equal to 2.3 μm.

19. The display substrate of claim 5, wherein, A length of the second via in a second direction is greater than a fourth length, the fourth length being greater than or equal to 3.8 μm and less than or equal to 4.2 μm. 20.The display substrate of claim 4, wherein, A length of a projection of the first via portion on the substrate in the first direction is greater than a length of a projection of the second via portion on the substrate in the first direction; or A length of a projection of the first via portion on the substrate in the first direction is less than a length of a projection of the second via portion on the substrate in the first direction. A length of the third via portion in the second direction is greater than a length of the fourth via portion in the second direction; or 21. The display substrate of claim 6, wherein, A length of the third via portion in the second direction is less than a length of the fourth via portion in the second direction. Further comprising a substrate and a gate line disposed on the substrate; 22. The display substrate of claim 1, wherein, A first overlap region exists between a projection of the gate line on the substrate and a projection of a first sub-connection portion in the connection structure on the substrate; A second overlap region exists between a projection of the gate line on the substrate and a projection of a second sub-connection portion in the connection structure on the substrate; An area of the first overlap region is less than an area of the second overlap region. Further comprising a substrate and a pixel electrode, a data line, a gate line and a switching transistor disposed on the substrate; 23. The display substrate of claim 1, wherein, The gate line comprises a first gate line portion and a second gate line portion in communication with each other; the first gate line portion is multiplexed as a gate electrode of the switching transistor; A first electrode of the switching transistor is electrically connected with the data line; A second electrode of the switching transistor comprises a switching portion, a first electrode portion and a second electrode portion; the switching portion is electrically connected with the pixel electrode, the first electrode portion is disposed on a first side of the switching portion, the second electrode portion is disposed on a second side of the switching portion, the first side and the second side are opposite sides; A projection of the first electrode portion on the substrate at least partially overlaps with a projection of the first gate line portion on the substrate; A projection of the second electrode portion on the substrate at least partially overlaps with a projection of the second gate line portion on the substrate. Further comprising a substrate; the display substrate comprises a first transparent conductive layer, a gate electrode layer, a source-drain electrode layer and a second transparent conductive layer arranged in sequence along a direction away from the substrate; 24. The display substrate of any one of claims 1 to 8, wherein, The first conductive layer is the second transparent conductive layer, and the second conductive layer is the source-drain electrode layer.

25. A display device comprising the display substrate according to any one of claims 1 to 24. ​

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