Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises a display area and a non-display area, and comprises a base and a circuit structure layer arranged on the base, the circuit structure layer comprises a plurality of pixel circuits arranged in an array in the display area and a plurality of drive circuits in the non-display area; at least one pixel circuit comprises a plurality of transistors, and the plurality of drive circuits are configured to provide drive signals to the plurality of transistors; the circuit structure layer further comprises a high-level power supply line and a low-level power supply line in the non-display area, at least one drive circuit is electrically connected to the high-level power supply line and the low-level power supply line respectively, and the high-level power supply line and the low-level power supply line extend along a first direction; the high-level power supply line connected to at least two drive circuits is the same power supply line and / or the low-level power supply line connected to at least two drive circuits is the same power supply line.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure also provides a display substrate, including: a display area and a non-display area, the display substrate including: a substrate and a circuit structure layer disposed on the substrate, the circuit structure layer including: a plurality of pixel circuits located in the display area and arranged in an array and a plurality of driving circuits located in the non-display area; at least one pixel circuit includes: a plurality of transistors, the plurality of driving circuits being configured to provide driving signals to the plurality of transistors;

[0005] The circuit structure layer further includes: a high-level power line and a low-level power line located in the non-display area, at least one driving circuit being electrically connected to the high-level power line and the low-level power line respectively, and the high-level power line and the low-level power line extending along a first direction;

[0006] At least two drive circuits are connected to the same high-level power line and / or at least two drive circuits are connected to the same low-level power line.

[0007] In some possible implementations, the display area includes: a first side and a second side disposed opposite to each other, and at least one driving circuit is located on the first side and / or the second side of the display area;

[0008] The plurality of driving circuits extend along a second direction, and the first direction intersects with the second direction.

[0009] In some possible implementations, the circuit structure layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer stacked sequentially on a substrate.

[0010] The high-level power line and the low-level power line are located in the third conductive layer and / or the fourth conductive layer.

[0011] In some possible implementations, the circuit structure layer may further include: a fifth insulating layer and a fifth conductive layer;

[0012] The fifth insulating layer and the fifth conductive layer are located between the second conductive layer and the third insulating layer, and the fifth insulating layer is located on the side of the fifth conductive layer closer to the substrate.

[0013] In some possible implementations, the plurality of transistors includes a write transistor, a compensation transistor, and a light-emitting transistor, and the plurality of driving circuits includes a light-emitting driving circuit and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, and the control driving circuit is configured to provide a driving signal to the write transistor and / or the compensation transistor;

[0014] The high-level power line connected to the light-emitting driving circuit and the high-level power line connected to the control driving circuit are the same power line, and / or the low-level power line connected to the light-emitting driving circuit and the low-level power line connected to the control driving circuit are the same power line.

[0015] In some possible implementations, when the high-level power line connected to the light-emitting driving circuit and the high-level power line connected to the control driving circuit are the same power line, the orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit.

[0016] In some possible implementations, when the low-level power line connected to the light-emitting driving circuit and the low-level power line connected to the control driving circuit are the same power line, the orthographic projection of the low-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit.

[0017] In some possible implementations, the light-emitting driving circuit is located on the side of the control driving circuit that is away from the display area;

[0018] The circuit structure layer further includes: an initial light emission signal line, multiple light emission clock signal lines, a control initial signal line, and multiple control clock signal lines located in the non-display area and extending along the first direction; the light emission driving circuit is electrically connected to the initial light emission signal line and the multiple light emission clock signal lines respectively, and the control driving circuit is electrically connected to the control initial signal line and the multiple control clock signal lines respectively.

[0019] The initial light-emitting signal line and the plurality of light-emitting clock signal lines are located on the side of the initial control signal line and the plurality of control clock signal lines away from the display area, and the initial light-emitting signal line is located on the side of the plurality of light-emitting clock signal lines closer to the display area or away from the display area;

[0020] The initial control signal line is located on the side of the plurality of control clock signal lines that is closer to the display area, or on the side that is farther away from the display area.

[0021] In some possible implementations, the light-emitting driving circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors, and the control driving circuit includes: a plurality of control transistors and a plurality of control capacitors;

[0022] The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple control transistors, first plates of multiple light-emitting capacitors, and first plates of multiple control capacitors;

[0023] The second conductive layer includes: the second plates of multiple light-emitting capacitors and the second plates of multiple control capacitors;

[0024] The third conductive layer includes: source and drain electrodes of multiple light-emitting transistors and source and drain electrodes of multiple control transistors.

[0025] The fourth conductive layer includes: an initial light-emitting signal line, at least one light-emitting clock signal line, an initial control signal line, and at least one control clock signal line.

[0026] In some possible implementations, the plurality of transistors includes: a write transistor, a first reset transistor, a compensation transistor, and a light-emitting transistor, wherein the transistor types of the first reset transistor and the compensation transistor are different from those of the write transistor and the light-emitting transistor; the plurality of driving circuits includes: a light-emitting driving circuit, a scan driving circuit, and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, the control driving circuit is configured to provide a driving signal to the write transistor, and the scan driving circuit is configured to provide a driving signal to the first reset transistor and / or the compensation transistor;

[0027] The high-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit are the same power supply line, and / or the low-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit are the same power supply line.

[0028] In some possible implementations, when the high-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or is located between the two adjacent driving circuits connected.

[0029] Alternatively, when the high-level power supply line connected to the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or it is located between two adjacent driving circuits.

[0030] In some possible implementations, when the low-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the low-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power supply line on the substrate, or is located between the two adjacent driving circuits connected.

[0031] Alternatively, when the low-level power line connected to the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or it is located between two adjacent driving circuits.

[0032] In some possible implementations, the light-emitting driving circuit is located on the side of the scanning driving circuit away from the display area, and the control driving circuit is located on the side of the scanning driving circuit closer to the display area;

[0033] The circuit structure layer further includes: an initial light emission signal line, multiple light emission clock signal lines, a control initial signal line, multiple control clock signal lines, a scan initial signal line, and multiple scan clock signal lines, all located in the non-display area and extending along a first direction; the light emission driving circuit is electrically connected to the initial light emission signal line and the multiple light emission clock signal lines, the control driving circuit is electrically connected to the control initial signal line and the multiple control clock signal lines, and the scan driving circuit is electrically connected to the initial scan signal line and the multiple scan clock signal lines.

[0034] The initial light-emitting signal line and the plurality of light-emitting clock signal lines are located on the side of the initial scan signal line and the plurality of scan clock signal lines away from the display area, and the initial light-emitting signal line is located on the side of the plurality of light-emitting clock signal lines closer to the display area or on the side away from the display area;

[0035] The control initial signal line and the plurality of control clock signal lines are located on the side of the scan initial signal line and the plurality of scan clock signal lines closer to the display area, and the control initial signal line is located on the side of the plurality of control clock signal lines closer to the display area or on the side farther away from the display area;

[0036] The initial scan signal line is located on the side of the plurality of scan clock signal lines that is closer to the display area, or on the side that is farther away from the display area.

[0037] In some possible implementations, the light-emitting driving circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the scanning driving circuit includes: a plurality of scanning transistors and a plurality of scanning capacitors; and the control driving circuit includes: a plurality of control transistors and a plurality of control capacitors.

[0038] The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple scanning transistors, gate electrodes of multiple control transistors, first plates of multiple light-emitting capacitors, first plates of multiple scanning capacitors, and first plates of multiple control capacitors.

[0039] The second conductive layer includes: the second plates of multiple light-emitting capacitors, the second plates of multiple scanning capacitors, and the second plates of multiple control capacitors;

[0040] The third conductive layer includes: source and drain electrodes of multiple light-emitting transistors, source and drain electrodes of multiple scanning transistors, and source and drain electrodes of multiple control transistors.

[0041] The fourth conductive layer includes: an initial light emission signal line, at least one light emission clock signal line, an initial scan signal line, at least one scan clock signal line, an initial control signal line, and at least one control clock signal line.

[0042] In some possible implementations, the write transistor and the light-emitting control transistor are P-type transistors, and the first reset transistor and the compensation transistor are N-type metal-oxide transistors.

[0043] In some possible implementations, the plurality of transistors includes: a write transistor, a compensation transistor, a first reset transistor, a second reset transistor, and a light-emitting transistor; the plurality of driving circuits includes: a light-emitting driving circuit, a first reset driving circuit, a second reset driving circuit, and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, the control driving circuit is configured to provide a driving signal to the write transistor and / or the compensation transistor, the first reset driving circuit is configured to provide a driving signal to the first reset transistor, and the second reset driving circuit is configured to provide a driving signal to the second reset transistor;

[0044] The high-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit are the same power supply line, and / or the low-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit are the same power supply line.

[0045] In some possible implementations, when the high-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or is located between the two adjacent driving circuits connected.

[0046] Alternatively, when the high-level power supply line connected to at least three adjacent driving circuits among the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or it is located between two adjacent driving circuits.

[0047] In some possible implementations, when the low-level power line connected to two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits connected.

[0048] Alternatively, when the low-level power supply line connected to at least three adjacent driving circuits among the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the low-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power supply line on the substrate, or it is located between two adjacent driving circuits.

[0049] In some possible implementations, the light-emitting driving circuit is located on the side of the control driving circuit away from the display area, the first reset driving circuit is located between the light-emitting driving circuit and the control driving circuit, and the second reset driving circuit is located on the side of the control driving circuit closer to the display area.

[0050] The circuit structure layer further includes: a light-emitting initial signal line, multiple light-emitting clock signal lines, a control initial signal line, multiple control clock signal lines, a first reset initial signal line, multiple first reset clock signal lines, a second reset initial signal line, and multiple second reset clock signal lines, all located in the non-display area and extending along a first direction; the light-emitting driving circuit is electrically connected to the light-emitting initial signal line and the multiple light-emitting clock signal lines respectively; the control driving circuit is electrically connected to the control initial signal line and the multiple control clock signal lines respectively; the first reset driving circuit is electrically connected to the first reset initial signal line and the multiple first reset clock signal lines respectively; and the second reset driving circuit is electrically connected to the second reset initial signal line and the multiple second reset clock signal lines respectively.

[0051] The initial light-emitting signal line and the plurality of light-emitting clock signal lines are located on the side of the first reset initial signal line and the plurality of first reset clock signal lines away from the display area, and the initial light-emitting signal line is located on the side of the plurality of light-emitting clock signal lines close to the display area or on the side away from the display area;

[0052] The first reset initial signal line and the plurality of first reset clock signal lines are located on the side of the control initial signal line and the plurality of control clock signal lines closer to the display area, and the first reset initial signal line is located on the side of the plurality of first reset clock signal lines closer to the display area or on the side farther away from the display area;

[0053] The control initial signal line and the control clock signal line are located on the side away from the display area of ​​the second reset initial signal line and the plurality of second reset clock signal lines, and the control initial signal line is located on the side of the plurality of control clock signal lines that is close to the display area or on the side away from the display area;

[0054] The second reset initial signal line is located on the side of the plurality of second reset clock signal lines that is closer to the display area or on the side that is farther away from the display area.

[0055] In some possible implementations, the light-emitting driving circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the scanning driving circuit includes: a plurality of scanning transistors and a plurality of scanning capacitors; the first reset driving circuit includes: a plurality of first reset transistors and a plurality of first reset capacitors; and the second reset driving circuit includes: a plurality of second reset transistors and a plurality of second reset capacitors.

[0056] The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple control transistors, gate electrodes of multiple first reset transistors, gate electrodes of multiple second reset transistors, first plates of multiple light-emitting capacitors, first plates of multiple control capacitors, first plates of multiple first reset capacitors, and first plates of multiple second reset capacitors.

[0057] The second conductive layer includes: the second plates of multiple light-emitting capacitors, the second plates of multiple control capacitors, the second plates of multiple first reset capacitors, and the second plates of multiple second reset capacitors;

[0058] The third conductive layer includes: source and drain electrodes of multiple light-emitting transistors, source and drain electrodes of multiple control transistors, source and drain electrodes of multiple first reset transistors, and source and drain electrodes of multiple second reset transistors.

[0059] The fourth conductive layer includes: an initial light emission signal line, at least one initial light emission clock signal line, a control initial signal line, at least one control clock signal line, a first reset initial signal line, at least one first reset clock signal line, a second reset initial signal line, and at least one second reset clock signal line.

[0060] In some possible implementations, the boundary of the display area includes at least one arc-shaped boundary.

[0061] Secondly, this disclosure also provides a display device including the aforementioned display substrate.

[0062] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0063] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0064] Figure 1This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0065] Figures 2A to 2C A schematic diagram showing the connection of multiple drive circuits and power lines provided for an exemplary embodiment;

[0066] Figure 3 This is a schematic diagram of the equivalent circuit of a pixel circuit.

[0067] Figures 4A to 4C A partial schematic diagram of a display substrate including two driving circuits, provided for an exemplary embodiment;

[0068] Figure 5A An equivalent circuit diagram of a light-emitting shift register provided for an exemplary embodiment;

[0069] Figure 5B for Figure 5A The timing diagram of the provided light-emitting shift register;

[0070] Figure 6A An equivalent circuit diagram of a control shift register provided for an exemplary embodiment;

[0071] Figure 6B for Figure 6A The timing diagram for the control shift register is provided;

[0072] Figures 7A to 7F A partial schematic diagram of a display substrate including three driving circuits, provided for an exemplary embodiment;

[0073] Figure 8A An equivalent circuit diagram of a scan shift register provided for an exemplary embodiment;

[0074] Figure 8B for Figure 8A The timing diagram for the provided scan shift register;

[0075] Figures 9A to 9I A partial schematic diagram of a display substrate including four driving circuits, provided for an exemplary embodiment;

[0076] Figure 10 This is a schematic diagram after the semiconductor layer has been formed;

[0077] Figure 11 This is a schematic diagram of the first conductive layer;

[0078] Figure 12 This is a schematic diagram after the first conductive layer has been formed;

[0079] Figure 13 This is a schematic diagram of the second conductive layer;

[0080] Figure 14A schematic diagram after the formation of the second conductive layer;

[0081] Figure 15 This is a schematic diagram of the fifth conductive layer;

[0082] Figure 16 This is a schematic diagram after the fifth conductive layer has been formed;

[0083] Figure 17 This is a schematic diagram of the third conductive layer;

[0084] Figure 18 This is a schematic diagram after the third conductive layer has been formed;

[0085] Figure 19 This is a schematic diagram of the fourth conductive layer;

[0086] Figure 20 This is a schematic diagram after the fourth conductive layer has been formed;

[0087] Figure 21 This is a schematic diagram of the sixth conductive layer;

[0088] Figure 22 This is a schematic diagram after the formation of the sixth conductive layer. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0090] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0091] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0092] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0093] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0094] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0095] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0096] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0097] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0098] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0099] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0100] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0101] Display substrates possess advantages such as high resolution, high response speed, high brightness, and high aperture ratio, offering broad application prospects. To achieve a better visual experience, narrow bezels are a major development direction for displays. Display substrates incorporate driving circuits to drive pixel circuits to emit light, thereby realizing the display. However, display substrates cannot achieve truly narrow bezels.

[0102] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. Figures 2A to 2C This is a schematic diagram illustrating the connection between multiple drive circuits and power lines, provided for an exemplary embodiment. (See diagram below.) Figure 1 and Figures 2A to 2C As shown, the display substrate provided in this embodiment includes: a display area AA and a non-display area AA'. The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: a plurality of pixel circuits P located in the display area and arranged in an array, and a plurality of driving circuits GOA1 to GOA' located in the non-display area. M At least one pixel circuit includes: a plurality of transistors, and a plurality of driving circuits configured to provide driving signals to the plurality of transistors.

[0103] In one exemplary embodiment, such as Figures 2A to 2CAs shown, the circuit structure layer also includes a high-level power line VGH and a low-level power line VGL located in the non-display area, and at least one driving circuit is electrically connected to the high-level power line VGH and the low-level power line VGL, respectively. The high-level power line VGH continuously provides a high-level signal, and the low-level power line VGL continuously provides a low-level signal.

[0104] In one exemplary embodiment, a high-level power line VGH and a low-level power line VGL extend along a first direction.

[0105] In one exemplary embodiment, such as Figures 2A to 2C As shown, at least two drive circuits are connected to the same high-level power line and / or at least two drive circuits are connected to the same low-level power line. For example... Figure 2A This explanation is based on the example of at least two driver circuits being connected to the same high-level power supply line. Figure 2B This explanation is based on the example of at least two driver circuits being connected to the same low-level power supply line. Figure 2C This explanation is based on the example of at least two drive circuits having the same high-level power supply line and at least two drive circuits having the same low-level power supply line.

[0106] In one exemplary embodiment, the display substrate disclosed herein can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0107] In one exemplary embodiment, the display substrate may be an LTPO display substrate or an LTPS display substrate.

[0108] In one exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be one or more of glass and metal sheets, but is not limited to; the flexible substrate may be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited to.

[0109] In one exemplary embodiment, the positional relationship of the multiple driving circuits can be determined according to the structure and function of the display substrate, and this disclosure does not impose any limitations on this.

[0110] In one exemplary embodiment, the display substrate may further include a light-emitting structure layer disposed on the side of the circuit structure layer away from the substrate and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate.

[0111] In one exemplary embodiment, the light-emitting structure layer includes light-emitting elements arranged in an array located in the display area. Each light-emitting element includes a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). The anode is located on the side of the organic light-emitting layer closer to the substrate, and the cathode is located on the side of the organic light-emitting layer farther from the substrate. The light-emitting elements are electrically connected to pixel circuitry.

[0112] In one exemplary embodiment, the circuit structure layer may further include a second power line located in a non-display area, the second power line being electrically connected to the cathode of the light-emitting element.

[0113] In one exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0114] In one exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In one exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0115] In one exemplary embodiment, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0116] In one exemplary embodiment, the pixel circuit may be a 7T1C or 8T1C structure.

[0117] In one exemplary embodiment, Figure 3 This is a schematic diagram of the equivalent circuit of a pixel circuit. For example... Figure 3As shown, the pixel circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 capacitor C, and 8 signal terminals (data signal terminal Data, control signal terminal G, scan signal terminal S, first reset signal terminal Reset1, second reset signal terminal Reset2, light emission signal terminal EM, initial signal terminal Vinit, first power supply terminal VDD, and second power supply terminal VSS).

[0118] In one exemplary embodiment, the first plate of capacitor C is connected to the first power supply terminal VDD, and the second plate of capacitor C is connected to the first node N1. The control electrode of the first transistor T1 is connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is connected to the initial signal terminal Vinit, and the second electrode of the first transistor is connected to the first node N1. The control electrode of the second transistor T2 is connected to the scan signal terminal S, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second node N2. The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the control signal terminal G, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the third node N3. The control electrode of the fifth transistor T5 is connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3. The control electrode of the sixth transistor T6 is connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The control electrode of the seventh transistor T7 is connected to the control signal terminal G, the first electrode of the seventh transistor T7 is connected to the initial signal terminal Vinit, the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to the second power supply terminal VSS.

[0119] In one exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. When the first reset signal terminal Reset1 receives an effective level signal, the first transistor T1 transmits an initialization voltage to the first node N1 to initialize the charge of the first node N1.

[0120] In one exemplary embodiment, the seventh transistor T7 can be referred to as the second reset transistor. When the second reset signal terminal Reset2 receives an effective level signal, the seventh transistor T7 transmits an initialization voltage to the anode of the light-emitting element to initialize the charge on the anode of the light-emitting element.

[0121] In one exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor. When a valid level signal is input to the scan signal terminal S, the second transistor T2 transmits the signal of the second node to the first node N1 to compensate the control electrode of the driving transistor.

[0122] In one exemplary embodiment, the third transistor T3 may be referred to as the driving transistor, which determines the driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on the potential difference between the control terminal and the first terminal.

[0123] In one exemplary embodiment, the fourth transistor T4 can be referred to as the write transistor. When the control signal terminal S1 receives an effective level signal, the fourth transistor T4 causes the data voltage of the data signal terminal Data to be input to the pixel circuit.

[0124] In one exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an effective level signal is input to the light-emitting signal terminal E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a drive current path between the first power supply terminal VDD and the second power supply terminal VSS.

[0125] In one exemplary embodiment, the signal at the first power supply terminal VDD is a continuously high-level signal, and the signal at the second power supply terminal VSS is a low-level signal.

[0126] In one exemplary embodiment, the first power supply terminal VDD is configured to continuously provide a high-level signal, and the second power supply terminal VSS is configured to continuously provide a low-level signal.

[0127] In one exemplary embodiment, the first reset signal terminal Reset1 and the second reset signal terminal Reset2 can be the same signal terminal, and the control signal terminal G and the scan signal terminal S can be the same signal terminal.

[0128] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. Exemplarily, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0129] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), or oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs have advantages such as high mobility and fast charging, while OPTs have advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0130] In one exemplary embodiment, the display substrate further includes: a data signal line, a first reset signal line, a second reset signal line, a control signal line, a scan signal line, and a light emission signal line. The first reset signal terminal of the pixel circuit is electrically connected to the first reset signal line, the second reset signal terminal is electrically connected to the second reset signal line, the control signal terminal is electrically connected to the control signal line, the scan signal terminal is electrically connected to the scan signal line, the light emission signal terminal is connected to the light emission signal line, and the data signal terminal is electrically connected to the data signal line. When the first reset signal terminal and the second reset signal terminal are the same signal terminal, the first reset signal line and the second reset signal line can be the same signal line; when the control signal terminal and the scan signal terminal are the same signal terminal, the control signal line and the scan signal line can be the same signal line.

[0131] The display substrate provided in this disclosure includes a display area and a non-display area. The display substrate includes a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes multiple pixel circuits arranged in an array in the display area and multiple driving circuits located in the non-display area. At least one pixel circuit includes multiple transistors, and the multiple driving circuits are configured to provide driving signals to the multiple transistors. The circuit structure layer further includes a high-level power line and a low-level power line located in the non-display area. At least one driving circuit is electrically connected to the high-level power line and the low-level power line, respectively. The high-level power line and the low-level power line extend along a first direction. The high-level power line connected to at least two driving circuits is the same power line, and / or the low-level power line connected to at least two driving circuits is the same power line. This disclosure reduces the area occupied by multiple driving circuits and achieves a narrow bezel by using the same power line for the high-level power lines connected to at least two driving circuits and / or the same power line for the low-level power lines connected to at least two driving circuits.

[0132] In one exemplary embodiment, the display area includes: a first side and a second side disposed opposite to each other, and at least one driving circuit is located on the first side and / or the second side of the display area. Figure 1 The explanation is based on the example of at least one driving circuit located on the first and second sides of the display area.

[0133] In one exemplary embodiment, a plurality of driving circuits extend along a second direction, and the first direction intersects the second direction.

[0134] In one exemplary embodiment, the circuit structure layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer, sequentially stacked on a substrate. The high-level power line and the low-level power line may be located in the third conductive layer and / or the fourth conductive layer.

[0135] In one exemplary embodiment, the circuit structure layer may further include a fifth insulating layer and a fifth conductive layer. The fifth insulating layer and the fifth conductive layer are located between the second conductive layer and the third insulating layer, with the fifth insulating layer located on the side of the fifth conductive layer closest to the substrate.

[0136] In one exemplary embodiment, the circuit structure layer may further include a sixth insulating layer and a sixth conductive layer. The sixth insulating layer is located on the side of the fourth conductive layer away from the substrate, and the sixth conductive layer is located on the side of the sixth insulating layer away from the substrate.

[0137] In one exemplary embodiment, Figures 4A to 4C A partial schematic diagram of a display substrate including two driving circuits is provided for an exemplary embodiment. (See diagram below.) Figures 4A to 4C As shown, when the display substrate is an LTPS display substrate, the write transistor, compensation transistor, and light-emitting transistor are of the same type, the first reset signal terminal and the second reset signal terminal are the same signal terminal, and the control signal terminal and the scan signal terminal are the same signal terminal. Multiple driving circuits include: a light-emitting driving circuit EM GOA and a control driving circuit GateP GOA. The light-emitting driving circuit EM GOA is configured to provide driving signals to the light-emitting transistor, and the control driving circuit GateP GOA is configured to provide driving signals to the write transistor and / or the compensation transistor.

[0138] In one exemplary embodiment, the high-level power line EVGH connected to the light-emitting driving circuit EM GOA and the high-level power line GVGH connected to the control driving circuit GateP GOA are the same power line and / or the low-level power line EVGL connected to the light-emitting driving circuit EM GOA and the low-level power line GVGL connected to the control driving circuit GateP GOA are the same power line.

[0139] Figure 4A This explanation is based on the example where the low-level power line EVGL connected to the light-emitting driver circuit EM GOA and the low-level power line GVGL connected to the control driver circuit GatePGOA are the same power line, while the high-level power line EVGH connected to the light-emitting driver circuit EM GOA and the high-level power line GVGH connected to the control driver circuit GatePGOA are different power lines. Figure 4B This explanation is based on the example where the low-level power line EVGL connected to the light-emitting driver circuit EM GOA and the low-level power line GVGL connected to the control driver circuit GateP GOA are different power lines, while the high-level power line EVGH connected to the light-emitting driver circuit EM GOA and the high-level power line GVGH connected to the control driver circuit GateP GOA are the same power line. Figure 4C This explanation is based on the example of the low-level power line EVGL connected to the light-emitting driver circuit EM GOA and the low-level power line GVGL connected to the control driver circuit GateP GOA being the same power line, and the high-level power line EVGH connected to the light-emitting driver circuit EM GOA and the high-level power line GVGH connected to the control driver circuit GateP GOA being the same power line.

[0140] In one exemplary embodiment, when the high-level power line connected to the light-emitting driving circuit and the high-level power line connected to the control driving circuit are the same power line, the orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit. This at least partial overlap or location between the orthographic projection of the high-level power line on the substrate and the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate can reduce the area occupied by multiple driving circuits and achieve a narrow bezel.

[0141] In one exemplary embodiment, when the low-level power line connected to the light-emitting driving circuit and the low-level power line connected to the control driving circuit are the same power line, the orthographic projection of the low-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit. This at least partial overlap or location between the orthographic projection of the low-level power line on the substrate and the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate can reduce the area occupied by multiple driving circuits and achieve a narrow bezel.

[0142] In one exemplary embodiment, the positional relationship between the control driving circuit and the light-emitting control circuit can be determined according to the structure and function of the display substrate, and the light-emitting driving circuit EM GOA can be located on the side of the control driving circuit GateP GOA away from the display area.

[0143] In one exemplary embodiment, such as Figures 4A to 4C As shown, the circuit structure layer also includes: an initial light emission signal line ESTV, multiple light emission clock signal lines, a control initial signal line GSTV, and multiple control clock signal lines located in the non-display area and extending along the first direction; the light emission driving circuit is electrically connected to the initial light emission signal line ESTV and the multiple light emission clock signal lines respectively, and the control driving circuit is electrically connected to the control initial signal line GSTV and the multiple control clock signal lines respectively. Figures 4A to 4C This explanation uses three light-emitting clock signal lines ECLK1 to ECLK3 and two control clock signal lines GCLK1 and GCLK2 as an example.

[0144] In one exemplary embodiment, such as Figures 4A to 4C As shown, the initial emission signal line ESTV and multiple emission clock signal lines ECLK1 to ECLK3 are located on the side of the initial control signal line GSTV and multiple control clock signal lines GCLK1 and GCLK2 furthest from the display area. The initial emission signal line ESTV is located on the side of the multiple emission clock signal lines ECLK1 to ECLK3 closest to or furthest from the display area. The initial control signal line GSTV is located on the side of the multiple control clock signal lines GCLK1 and GCLK2 closest to or furthest from the display area. Figures 4A to 4C This explanation uses an example where the initial emission signal line ESTV is located on the side of the multiple emission clock signal lines ECLK1 to ECLK3 furthest from the display area, and the initial control signal line GSTV is located on the side of the multiple control clock signal lines GCLK1 and GCLK2 closest to the display area. The positional relationships between the initial emission signal line ESTV, the multiple emission clock signal lines, the initial control signal line GSTV, and the multiple control clock signal lines can be determined based on the structure and function of the display substrate; this disclosure does not impose any limitations on this.

[0145] In one exemplary embodiment, the light-emitting driving circuit includes a plurality of light-emitting transistors and a plurality of light-emitting capacitors, and the control driving circuit includes a plurality of control transistors and a plurality of control capacitors. A first conductive layer includes the gate electrodes of the plurality of light-emitting transistors, the gate electrodes of the plurality of control transistors, the first plates of the plurality of light-emitting capacitors, and the first plates of the plurality of control capacitors; a second conductive layer includes the second plates of the plurality of light-emitting capacitors and the second plates of the plurality of control capacitors; a third conductive layer includes the source and drain electrodes of the plurality of light-emitting transistors and the source and drain electrodes of the plurality of control transistors; and a fourth conductive layer includes an initial light-emitting signal line, at least one initial light-emitting clock signal line, an initial control signal line, and at least one control clock signal line.

[0146] In one exemplary embodiment, the light-emitting driving circuit may include: a plurality of cascaded light-emitting shift registers, at least one light-emitting shift register including: a plurality of light-emitting control transistors and a plurality of light-emitting capacitors, and at least one stage of the light-emitting shift register is electrically connected to at least one light-emitting signal line.

[0147] In one exemplary embodiment, the light-emitting shift register may include a plurality of light-emitting control transistors and a plurality of light-emitting capacitors. The circuit structure of the light-emitting shift register may be 14T3C, 13T3C, or 10T3C, and this disclosure does not limit it in any way.

[0148] Figure 5A An equivalent circuit diagram of an emissive shift register is provided for an exemplary embodiment. Figure 5B for Figure 5A The timing diagram of the provided light-emitting shift register is shown. Figure 5A As shown, in one exemplary embodiment, the light-emitting shift register includes: a first light-emitting control transistor ET1 to a thirteenth light-emitting control transistor ET13 and a first light-emitting capacitor EC1 to a third light-emitting capacitor EC3.

[0149] In one exemplary embodiment, the control electrode of the first light-emitting control transistor ET1 is electrically connected to the third clock signal terminal ECK3, the first electrode of the first light-emitting control transistor ET1 is electrically connected to the input terminal EIN, and the second electrode of the first light-emitting control transistor ET1 is electrically connected to the first node E1. The control electrode of the second light-emitting control transistor ET2 is electrically connected to the first node E1, the first electrode of the second light-emitting control transistor ET2 is electrically connected to the third clock signal terminal ECK3, and the second electrode of the second light-emitting control transistor ET2 is electrically connected to the second node E2. The control electrode of the third light-emitting control transistor ET3 is electrically connected to the third clock signal terminal ECK3, the first electrode of the third light-emitting control transistor ET3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third light-emitting control transistor ET3 is electrically connected to the second node E2. The control electrode of the fourth light-emitting control transistor ET4 is electrically connected to the third node E3, the first electrode of the fourth light-emitting control transistor ET4 is electrically connected to the first clock signal terminal ECK1, and the second electrode of the fourth light-emitting control transistor ET4 is electrically connected to the fifth node E5. The control electrode of the fifth LED control transistor ET5 is electrically connected to the fourth node E4, the first electrode of the fifth LED control transistor ET5 is electrically connected to the fifth node E5, and the second electrode of the fifth LED control transistor ET5 is electrically connected to the first power supply terminal VGH. The control electrode of the sixth LED control transistor ET6 is electrically connected to the fourth node E4, the first electrode of the sixth LED control transistor ET6 is electrically connected to the first clock signal terminal ECK1, and the second electrode of the sixth LED control transistor ET6 is electrically connected to the sixth node E6. The control electrode of the seventh LED control transistor ET7 is electrically connected to the first clock signal terminal ECK1, the first electrode of the seventh LED control transistor ET7 is electrically connected to the sixth node E6, and the second electrode of the seventh LED control transistor ET7 is electrically connected to the seventh node E7. The control electrode of the eighth LED control transistor ET8 is electrically connected to the first node E1, the first electrode of the eighth LED control transistor ET8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth LED control transistor ET8 is electrically connected to the seventh node E7. The control electrode of the ninth LED control transistor ET9 is electrically connected to the seventh node E7, the first electrode of the ninth LED control transistor ET9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth LED control transistor ET9 is electrically connected to the output terminal EOUT. The control electrode of the tenth LED control transistor ET10 is electrically connected to the third node E3, the first electrode of the tenth LED control transistor ET10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth LED control transistor ET10 is electrically connected to the output terminal EOUT. The control electrode of the eleventh LED control transistor ET11 is electrically connected to the second power supply terminal VGL, the first electrode of the eleventh LED control transistor ET11 is electrically connected to the second node E2, and the second electrode of the eleventh LED control transistor ET11 is electrically connected to the fourth node E4.The control electrode of the twelfth LED control transistor ET12 is electrically connected to the second power supply terminal VGL. The first electrode of the twelfth LED control transistor ET12 is electrically connected to the first node E1, and the second electrode of the twelfth LED control transistor ET12 is electrically connected to the third node E3. The control electrode of the thirteenth LED control transistor ET13 is electrically connected to the second clock signal terminal ECK2. The first electrode of the thirteenth LED control transistor ET13 is electrically connected to the first node E1, and the second electrode of the thirteenth LED control transistor ET13 is electrically connected to the first power supply terminal VGH. The first plate EC11 of the first LED capacitor EC1 is electrically connected to the fourth node E4, and the second plate EC12 of the first LED capacitor EC1 is electrically connected to the sixth node E6. The first plate EC21 of the second LED capacitor EC2 is electrically connected to the seventh node E7, and the second plate EC22 of the second LED capacitor EC2 is electrically connected to the first power supply terminal VGH. The first plate EC31 of the third LED capacitor EC3 is electrically connected to the third node E3, and the second plate EC32 of the third LED capacitor EC3 is electrically connected to the fifth node E5.

[0150] In one exemplary embodiment, the first light-emitting control transistor ET1 to the thirteenth light-emitting control transistor ET13 can be either P-type transistors or N-type transistors.

[0151] In one exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal. Because the second power supply terminal VGL continuously provides a low-level signal, the eleventh light-emitting control transistor ET11 and the twelfth light-emitting control transistor ET12 are continuously turned on.

[0152] In one exemplary embodiment, the second clock signal terminal ECK2 is a low-level signal during the power-on initialization phase to prevent the ninth and tenth light-emitting control transistors ET9 and ET10 of the last light-emitting shift register from conducting simultaneously due to output signal delay, or it is a low-level signal during the abnormal power-off phase to prevent the ninth and tenth light-emitting control transistors ET9 and ET10 from conducting simultaneously. The second clock signal terminal ECK2 continuously provides a high-level signal during the normal display phase, meaning that the thirteenth light-emitting control transistor ET13 remains continuously off during the normal display phase.

[0153] Taking the first light-emitting control transistor ET1 to the thirteenth light-emitting control transistor ET13 as P-type transistors as an example, Figure 5B As shown, the operation of an exemplary embodiment of the light-emitting shift register includes the following stages:

[0154] In the first stage B1, the signal at the first clock signal terminal ECK1 is a high-level signal, and the signal at the third clock signal terminal ECK3 is a low-level signal. When the signal at the third clock signal terminal ECK3 is low, the first light-emitting control transistor ET1, the third light-emitting control transistor ET3, and the twelfth light-emitting control transistor ET12 are turned on. The turned-on first light-emitting control transistor ET1 transmits the high-level signal at the input terminal EIN to the first node E1, thereby making the level of the first node E1 a high-level signal. The turned-on twelfth light-emitting control transistor ET12 transmits the high-level signal of the first node E1 to the third node E2. The second light-emitting control transistor ET2, the fourth light-emitting control transistor ET4, the eighth light-emitting control transistor ET8, and the tenth light-emitting control transistor ET10 are turned off. Additionally, the conducting third LED control transistor ET3 transmits the low-level signal from the third power supply terminal VGL to the second node E2, causing the level of the second node E2 to go low. The conducting eleventh LED control transistor ET11 transmits the low-level signal from the second node E2 to the fourth node E4, causing the level of the fourth node E4 to go low. The fifth and sixth LED control transistors ET5 and ET6 are turned on. The signal at the first clock signal terminal ECK1 is a high-level signal, and the seventh LED control transistor ET7 is turned off. Furthermore, under the action of the third LED capacitor EC3, the ninth LED control transistor ET9 is turned off. In the first stage P1, since both the ninth and tenth LED control transistors ET9 and ET10 are turned off, the signal at the output terminal EOUT remains at the previous low level.

[0155] In the second stage B2, the first clock signal terminal ECK1 is at a low level, and the third clock signal terminal ECK3 is at a high level. With the first clock signal terminal ECK1 at a low level, the seventh LED control transistor ET7 is turned on. With the third clock signal terminal ECK3 at a high level, the first LED control transistor ET1 and the third LED control transistor ET3 are turned off. Under the influence of the third LED capacitor EC3, the first node E1 and the third node E3 can maintain the high level signal from the previous stage. Under the influence of the first LED capacitor EC1, the fourth node E4 can maintain the low level from the previous stage, so the fifth LED control transistor ET5 and the sixth LED control transistor ET6 are turned on. The second LED control transistor ET2, the fourth LED control transistor ET4, the eighth LED control transistor ET8, and the tenth LED control transistor ET10 are turned off. Additionally, the low-level signal at the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the conducting sixth and seventh LED control transistors ET6 and ET7. The ninth LED control transistor ET9 is then turned on, outputting a high-level signal at the first power supply terminal VGH. Therefore, the signal at the output terminal EOUT is a high-level signal.

[0156] In stage B3, the signal at the third clock signal terminal ECK3 is low, and the signal at the first clock signal terminal ECK1 is high. With the first clock signal terminal ECK1 high, the seventh LED control transistor ET7 is turned off. The second, fourth, eighth, and tenth LED control transistors ET2, ET4, ET8, and ET10 are also turned off. With the third clock signal terminal ECK3 low, the first and third LED control transistors ET1 and ET3 are turned on. Under the influence of the second LED capacitor EC3, the ninth LED control transistor ET9 remains on, outputting a high-level signal from the first power supply terminal VGH. Therefore, the output signal EOUT remains high.

[0157] In stage B4, the first clock signal ECK1 is low, and the third clock signal ECK3 is high. With ECK3 high, the first and third LEDs ET1 and ET3 are turned off. With ECK1 low, the seventh LED ET7 is turned on. Due to the storage function of the third LED capacitor EC3, the levels of nodes E1 and E3 remain high from the previous stage, thus turning off the second, fourth, eighth, and tenth LEDs ET2, ET4, ET8, and ET10. Due to the storage function of the first LED capacitor EC1, node E4 remains low from the previous stage, thus turning on the fifth and sixth LEDs ET5 and ET6. In addition, the low-level signal of the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the sixth light-emitting control transistor ET6 and the seventh light-emitting control transistor ET7, and the ninth light-emitting control transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal EOUT is still a high-level signal.

[0158] In stage B5, the signal at the first clock signal terminal ECK1 is high, and the signal at the third clock signal terminal ECK3 is low. When the signal at the third clock signal terminal ECK3 is low, the first LED control transistor ET1 and the third LED control transistor ET3 are turned on. When the signal at the first clock signal terminal ECK1 is high, the seventh LED control transistor ET7 is turned off. The turned-on first LED control transistor ET1 transmits the low-level signal at its input terminal EIN to the first node E1, thus making the level of the first node E1 low. The turned-on twelfth LED control transistor ET12 transmits the low-level signal from the first node E1 to the third node E3, thus making the level of the third node E3 low. The second LED control transistor ET2, the fourth LED control transistor ET4, the eighth LED control transistor ET8, and the tenth LED control transistor ET10 are turned on. The second LED control transistor ET2, which is turned on, transmits the low-level signal from the third clock signal terminal ECK3 to the second node E2, further pulling down the level of the second node E2. Therefore, the second node E2 and the fourth node E4 remain at the low level of the previous stage, thus turning on the fifth LED control transistor ET5 and the sixth LED control transistor ET6. The signal from the first clock signal terminal ECK1 is a high-level signal, and the seventh LED control transistor ET7 is turned off. Additionally, the eighth LED control transistor ET8, which is turned on, transmits the high-level signal from the first power supply terminal VGH to the seventh node E7, and the ninth LED control transistor ET9 is turned off. The tenth LED control transistor ET10, which is turned on, outputs the low-level signal from the second power supply terminal VGL, so the signal at the output terminal EOUT becomes low.

[0159] The input terminal of the first-stage light-emitting shift register is electrically connected to the initial light-emitting signal line, and the output terminal of the i-th-stage light-emitting shift register is electrically connected to the input terminal of the (i+1)-th stage light-emitting shift register. The first clock signal terminal of the i-th-stage light-emitting shift register is electrically connected to the first light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the third light-emitting clock signal line. The first clock signal terminal of the (i+1)-th stage light-emitting shift register is electrically connected to the third light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the first light-emitting clock signal line. The first power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the high-level power supply line connected to the light-emitting driving circuit, and the second power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the low-level power supply line connected to the light-emitting driving circuit.

[0160] In one exemplary embodiment, the scan signal line and the control signal line are the same signal line. The control drive circuit includes multiple cascaded control shift registers, with at least one control shift register electrically connected to the control signal line. The at least one control shift register includes multiple control transistors and multiple control capacitors.

[0161] In one exemplary embodiment, the control shift register includes a plurality of control transistors and a plurality of control capacitors. The circuit structure of the control shift register can be 8T2C, and this disclosure does not limit it in any way.

[0162] Figure 6A An equivalent circuit diagram of a control shift register is provided for an exemplary embodiment. Figure 6B for Figure 6A The timing diagram for the control shift register is provided. (Example:) Figure 6A As shown, the control shift register includes: first control transistors GT1 to eighth control transistors GT8, first control capacitor GC1, and second control capacitor GC2.

[0163] In one exemplary embodiment, the control electrode of the first control transistor GT1 is electrically connected to the first clock signal terminal CK, the first terminal of the first control transistor GT1 is electrically connected to the input terminal GIN, and the second terminal of the first control transistor GT1 is electrically connected to the first node G1; the control electrode of the second control transistor GT2 is electrically connected to the first node G1, the first terminal of the second control transistor GT2 is electrically connected to the first clock signal terminal CK, and the second terminal of the second control transistor GT2 is electrically connected to the second node G2; the control electrode of the third control transistor GT3 is electrically connected to the first clock signal terminal GGCK11, the first terminal of the third control transistor GT3 is electrically connected to the second power supply terminal VGL, and the second terminal of the third control transistor GT3 is electrically connected to the second node G2; the control electrode of the fourth control transistor GT4 is electrically connected to the second node G2, the first terminal of the fourth control transistor GT4 is electrically connected to the first power supply terminal VGH, and the second terminal of the fourth control transistor GT4 is electrically connected to the output terminal GOUT; the control electrode of the fifth control transistor GT5 is electrically connected to the third node G3, and the first terminal of the fifth control transistor GT5 is electrically connected to the second clock signal terminal CK. Signal terminal GCK2 is electrically connected; the second terminal of the fifth control transistor GT5 is electrically connected to the output terminal GOUT; the control terminal of the sixth control transistor GT6 is electrically connected to the second node G2; the first terminal of the sixth control transistor GT6 is electrically connected to the first power supply terminal VGH; the second terminal of the sixth control transistor GT6 is electrically connected to the first terminal of the seventh control transistor GT7; the control terminal of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCK2; the second terminal of the seventh control transistor GT7 is electrically connected to the first node G1; the control terminal of the eighth control transistor GT8 is electrically connected to the second power supply terminal VGL; the first terminal of the eighth control transistor GT8 is electrically connected to the first node G1; the second terminal of the eighth control transistor GT8 is electrically connected to the third node G3; the first plate GC11 of the first control capacitor GC1 is electrically connected to the first power supply terminal VGH; the second plate GC12 of the first control capacitor GC1 is electrically connected to the second node G2; the first plate GC21 of the second control capacitor GC2 is electrically connected to the output terminal GOUT; the second plate GC22 of the second control capacitor GC2 is electrically connected to the third node G3.

[0164] In one exemplary embodiment, the first control transistor GT1 to the eighth control transistor GT8 can be either a P-type transistor or an N-type transistor.

[0165] In one exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal.

[0166] Taking the first control transistor GT1 to the eighth control transistor GT8 as P-type transistors as an example, Figure 6B As shown, the operation of the control shift register provided by an exemplary embodiment includes the following stages:

[0167] During input phase D1, the signals at the first clock signal terminal GCK1 and the input terminal GIN are low-level signals, while the signal at the second clock signal terminal GCK2 is high-level. Since the signal at the first clock signal terminal GCK1 is low, the first control transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node G1 via the first control transistor GT1. Because the signal at the eighth control transistor GT8 receives the low-level signal at the second power supply terminal VGL, the eighth control transistor GT8 is in the on state. The level of the third node G3 can control the fifth control transistor GT5 to turn on, and the signal at the second clock signal terminal GCK2 is transmitted to the output terminal GOUT via the fifth control transistor GT5. That is, during input phase D1, the output terminal GOUT is the signal at the second clock signal terminal GCK2, which is high. Additionally, since the signal at the first clock signal terminal GCK1 is low, the third control transistor GT3 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the second node G2 via the third control transistor GT3. At this time, both the fourth control transistor GT4 and the sixth control transistor GT6 are turned on. Since the signal at the second clock signal terminal GCK2 is a high-level signal, the seventh control transistor GT7 is turned off.

[0168] In output stage D2, the signal at the first clock signal terminal GCK1 is high, the signal at the second clock signal terminal GCK2 is low, and the signal at the input terminal GIN is high. The fifth control transistor GT5 is turned on, and the signal at the second clock signal terminal GCK2 is used as the signal at the output terminal GOUT via the fifth control transistor GT5. In output stage D2, the level at one end of the second control capacitor GC2 connected to the output terminal OUT becomes the signal at the second power supply terminal VGL. Due to the bootstrap effect of the second control capacitor GC2, the eighth control transistor GT8 is turned off, allowing the fifth control transistor GT5 to be turned on more effectively, resulting in a low signal at the output terminal GOUT. Additionally, the signal at the first clock signal terminal GCK1 is high, thus turning off both the first control transistor GT1 and the third control transistor GT3. The second control transistor GT2 is turned on, and the high-level signal at the first clock signal terminal GCK1 is transmitted to the second node G2 via the second control transistor GT2, thereby turning off both the fourth control transistor GT4 and the sixth control transistor GT6. Since the signal at the second clock signal terminal GCK2 is low, the seventh control transistor GT7 is turned on.

[0169] During buffer phase D3, both the first clock signal terminal GCK1 and the second clock signal terminal GCK2 are high-level signals, and the input terminal GIN is also high-level. The fifth control transistor GT5 is turned on, and the second clock signal terminal GCK2 is used as the output signal GOUT via the fifth control transistor GT5. Due to the bootstrap effect of the second control capacitor C2, the level of the first node G1 becomes VGL-VthN1. Furthermore, the first clock signal terminal GCK1 is high-level, thus the first control transistor GT1 and the third control transistor GT3 are both turned off, the eighth control transistor GT8 is turned on, and the second control transistor GT2 is turned on. The high-level signal of the first clock signal terminal GCK1 is transmitted to the second node G2 via the second control transistor GT2, thereby turning off the fourth control transistor GT4 and the sixth control transistor GT6. Since the second clock signal terminal GCK2 is high-level, the seventh control transistor GT7 is turned off.

[0170] In the first sub-stage D41 of the stable phase D4, the signal at the first clock signal terminal GCK1 is low, while the signals at the second clock signal terminal GCK2 and the input terminal GIN are high. Because the signal at the first clock signal terminal GCK1 is low, the first control transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node G1 via the first control transistor GT1. The second control transistor GT2 is turned off. Because the eighth control transistor GT8 is on, the fifth control transistor GT5 is turned off. Because the signal at the first clock signal terminal GCK1 is low, the third control transistor GT3 is turned on, and both the fourth and sixth control transistors GT4 and GT6 are turned on. The high-level signal at the first power supply terminal VGH is transmitted to the output terminal GOUT via the fourth control transistor GT4, meaning the signal at the output terminal GOUT is high.

[0171] In the second sub-stage t42 of the stable phase t4, the signal at the first clock signal terminal GCK1 is high, the signal at the second clock signal terminal GCK2 is low, and the signal at the input terminal GIN is high. The fifth control transistor GT5 and the second control transistor GT2 are both off. Because the signal at the first clock signal terminal GCK1 is high, the first control transistor GT1 and the third control transistor GT3 are both off. Due to the holding effect of the first control capacitor GC1, the fourth control transistor GT4 and the sixth control transistor GT6 are both on. The high-level signal is transmitted to the output terminal GOUT via the fourth control transistor GT4, meaning the signal at the output terminal GOUT is high.

[0172] In the second sub-stage t42, since the signal at the second clock signal terminal GCK2 is a low-level signal, the seventh control transistor GT7 is turned on, so that the high-level signal is transmitted to the third node G3 and the first node G1 via the sixth control transistor GT6 and the seventh control transistor GT7, so that the signals of the third node G3 and the first node G1 remain high-level signals.

[0173] In the third sub-stage t43, both the first clock signal terminal GCK1 and the second clock signal GCK2 are high-level signals, and the input terminal GIN is also high-level. The fifth control transistor GT5 and the second control transistor GT2 are off. Because the first clock signal terminal GCK1 is high-level, both the first control transistor GT1 and the third control transistor GT3 are off, while the fourth control transistor GT4 and the sixth control transistor GT6 are on. The high-level signal is transmitted to the output terminal GOUT via the fourth control transistor GT4, meaning the output terminal GOUT is high-level.

[0174] The input terminal of the first-stage control shift register is electrically connected to the control initial signal line, and the output terminal of the i-th-stage control shift register is electrically connected to the input terminal of the (i+1)-th-stage control shift register. The first clock signal terminal of the i-th-stage control shift register is electrically connected to the first control clock signal line, and the second clock signal terminal is electrically connected to the second control clock signal line. The first clock signal terminal of the (i+1)-th-stage control shift register is electrically connected to the second control clock signal line, and the second clock signal terminal is electrically connected to the first control clock signal line. The first power supply terminal of the i-th-stage control shift register is electrically connected to the high-level power supply line connected to the control drive circuit, and the second power supply terminal of the i-th-stage control shift register is electrically connected to the low-level power supply line connected to the control drive circuit.

[0175] In one exemplary embodiment, Figures 7A to 7F A partial schematic diagram of a display substrate including three driving circuits, provided for an exemplary embodiment. (See diagram below.) Figures 7A to 7FAs shown, when the display substrate is an LTPO display substrate, the multiple transistors include: a write transistor, a first reset transistor, a compensation transistor, and a light-emitting transistor. The transistor types of the first reset transistor and the compensation transistor are different from those of the write transistor and the light-emitting transistor. The first reset signal terminal and the second reset signal terminal are the same signal terminal, while the control signal terminal and the scan signal terminal are different signal terminals. Multiple driving circuits include: a light-emitting driving circuit EM GOA, a scan driving circuit GateN GOA, and a control driving circuit GateP GOA. The light-emitting driving circuit EM GOA is configured to provide a driving signal to the light-emitting transistor, the control driving circuit GateP GOA is configured to provide a driving signal to the write transistor, and the scan driving circuit GateN GOA is configured to provide a driving signal to the first reset transistor and / or the compensation transistor.

[0176] In one exemplary embodiment, the write transistor and the light-emitting control transistor can be P-type transistors.

[0177] In one exemplary embodiment, the first reset transistor and the compensation transistor may be N-type metal-oxide transistors.

[0178] In one exemplary embodiment, the high-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA are the same power supply line, and / or the low-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA are the same power supply line. When the high-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA are the same power supply line, and the low-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit EM GOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA are the same power supply line, the driving circuit connected to the same low-level power supply line can be the same driving circuit as the driving circuit connected to the same high-level power supply line, or they can be different driving circuits.

[0179] In one exemplary embodiment, the power supply line can be a high-level power supply line and / or a low-level power supply line, and the two driving circuits connected to the power supply line can be a light-emitting driving circuit EM GOA and a scanning driving circuit GateN GOA, or a scanning driving circuit GateN GOA and a control driving circuit GateP GOA.

[0180] Figure 7AThis explanation uses the example of the low-level power supply line SVGL connected to the scan drive circuit GateN GOA and the low-level power supply line GVGL connected to the control drive circuit GateP GOA being the same power supply line. Figure 7B This explanation uses the example of the high-level power supply line SVGH connected to the scan drive circuit GateN GOA and the low-level power supply line GVGH connected to the control drive circuit GateP GOA sharing the same power supply line. Figure 7C This explanation uses the example of the scan drive circuit GateN GOA's low-level power line SVGL and the control drive circuit GateP GOA's low-level power line GVGL being the same power line, and the scan drive circuit GateN GOA's high-level power line SVGH and the control drive circuit GateP GOA's low-level power line GVGH being the same power line. Figure 7D This explanation uses the example of the low-level power line EVGL connected to the light-emitting driver circuit EM GOA, the low-level power line SVGL connected to the scanning driver circuit Gate N GOA, and the low-level power line GVGL connected to the control driver circuit Gate PGA being the same power line. Figure 7E This explanation uses the example of the low-level power line EVGH connected to the light-emitting driver circuit EMGOA, the high-level power line SVGH connected to the scanning driver circuit GateN GOA, and the low-level power line GVGH connected to the control driver circuit GateP GOA all sharing the same power line. Figure 7F This explanation is based on the following example: the low-level power line EVGL connected to the light-emitting driver circuit EM GOA, the low-level power line SVGL connected to the scanning driver circuit GateN GOA, and the low-level power line GVGL connected to the control driver circuit GateP GOA are all the same power line; the low-level power line EVGH connected to the light-emitting driver circuit EM GOA, the high-level power line SVGH connected to the scanning driver circuit GateN GOA, and the low-level power line GVGH connected to the control driver circuit GateP GOA are all the same power line.

[0181] In one exemplary embodiment, when the high-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit EMGOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power supply line, the orthographic projection of the high-level power supply line on the substrate overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or is located between the two adjacent driving circuits connected; or, when the high-level power supply line connected to the light-emitting driving circuit EMGOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power supply line, the orthographic projection of the high-level power supply line on the substrate overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or is located between the two adjacent driving circuits.

[0182] In one exemplary embodiment, when the low-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit EMGOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power supply line, the orthographic projection of the low-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power supply line on the substrate, or is located between the two adjacent driving circuits connected; or, when the low-level power supply line connected to the light-emitting driving circuit EMGOA, the scanning driving circuit GateN GOA, and the control driving circuit GateP GOA is the same power supply line, the orthographic projection of the low-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power supply line on the substrate, or is located between the two adjacent driving circuits.

[0183] In one exemplary embodiment, the positional relationship between the control driving circuit, the scan driving circuit, and the light-emitting control circuit can be determined based on the structure and function of the display substrate. The light-emitting driving circuit EM GOA can be located on the side of the scan driving circuit Gate N GOA away from the display area, and the control driving circuit Gate P GOA can be located on the side of the scan driving circuit Gate N GOA closer to the display area.

[0184] In one exemplary embodiment, the circuit structure layer further includes: an initial light emission signal line ESTV, multiple light emission clock signal lines, a control initial signal line GSTV, multiple control clock signal lines, a scan initial signal line SSTV, and multiple scan clock signal lines, all located in the non-display area and extending along a first direction; an initial light emission driving circuit EM GOA is electrically connected to the initial light emission signal line and the multiple light emission clock signal lines, a control driving circuit GateP GOA is electrically connected to the control initial signal line GSTV and the multiple control clock signal lines, and a scan driving circuit GateN GOA is electrically connected to the scan initial signal line SSTV and the multiple scan clock signal lines. Figures 7A to 7F This explanation uses three light-emitting clock signal lines ECLK1 to ECLK3, three scan clock signal lines SCLK1 to SCLK3, and two control clock signal lines GCLK1 and GCLK2 as examples.

[0185] In one exemplary embodiment, such as Figures 7A to 7F As shown, the initial light emission signal line and multiple light emission clock signal lines are located on the side of the initial scan signal line and multiple scan clock signal lines away from the display area, while the initial light emission signal line is located on the side of the multiple light emission clock signal lines closer to the display area or away from the display area. Figures 7A to 7F The illustration shows the initial light-emitting signal line located on the side of the multiple light-emitting clock signal lines that is far from the display area.

[0186] In one exemplary embodiment, such as Figures 7A to 7F As shown, the initial control signal line and multiple control clock signal lines are located on the side of the initial scan signal line and multiple scan clock signal lines closer to the display area, while the initial control signal line is located on the side of the multiple control clock signal lines closer to the display area or on the side farther away from the display area. Figures 7A to 7F The illustration shows the control initial signal line located on the side of the multiple control clock signal lines that is far from the display area.

[0187] In one exemplary embodiment, such as Figures 7A to 7F As shown, the initial scan signal line is located on the side of the multiple scan clock signal lines that is closer to the display area, or on the side that is farther away from the display area. Figures 7A to 7F The illustration shows the initial scan signal line located on one side of the multiple scan clock signal lines closest to the display area.

[0188] In one exemplary embodiment, the scan drive circuit may include: a plurality of cascaded scan shift registers, with at least one scan shift register electrically connected to at least one reset signal line. In one exemplary embodiment, the scan shift register may include: a plurality of scan transistors and a plurality of scan capacitors. The circuit structure of the scan shift register may be 13T3C or 10T3C, and this disclosure does not limit it in any way.

[0189] Figure 8A An equivalent circuit diagram of a scan shift register is provided for an exemplary embodiment. Figure 8B for Figure 8A The timing diagram for the provided scan shift register is shown. Figure 8A As shown, in one exemplary embodiment, the scan shift register includes: a first scan transistor ST1 to a thirteenth scan transistor ST13 and a first scan capacitor SC1 to a third scan capacitor SC3.

[0190] In one exemplary embodiment, the control electrode of the first scanning transistor ST1 is electrically connected to the third clock signal terminal SCK3, the first electrode of the first scanning transistor ST1 is electrically connected to the input terminal SIN, and the second electrode of the first scanning transistor ST1 is electrically connected to the first node S1. The control electrode of the second scanning transistor ST2 is electrically connected to the first node S1, the first electrode of the second scanning transistor ST2 is electrically connected to the third clock signal terminal SCK3, and the second electrode of the second scanning transistor ST2 is electrically connected to the second node S2. The control electrode of the third scanning transistor ST3 is electrically connected to the third clock signal terminal SCK3, the first electrode of the third scanning transistor ST3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third scanning transistor ST3 is electrically connected to the second node S2. The control electrode of the fourth scanning transistor ST4 is electrically connected to the third node S3, the first electrode of the fourth scanning transistor ST4 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the fourth scanning transistor ST4 is electrically connected to the fifth node S5. The control electrode of the fifth scanning transistor ST5 is electrically connected to the fourth node S4, the first electrode of the fifth scanning transistor ST5 is electrically connected to the fifth node S5, and the second electrode of the fifth scanning transistor ST5 is electrically connected to the first power supply terminal VGH. The control electrode of the sixth scanning transistor ST6 is electrically connected to the fourth node S4, the first electrode of the sixth scanning transistor ST6 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the sixth scanning transistor ST6 is electrically connected to the sixth node S6. The control electrode of the seventh scanning transistor ST7 is electrically connected to the first clock signal terminal SCK1, the first electrode of the seventh scanning transistor ST7 is electrically connected to the sixth node S6, and the second electrode of the seventh scanning transistor ST7 is electrically connected to the seventh node S7. The control electrode of the eighth scanning transistor ST8 is electrically connected to the first node S1, the first electrode of the eighth scanning transistor ST8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth scanning transistor ST8 is electrically connected to the seventh node S7. The control electrode of the ninth scanning transistor ST9 is electrically connected to the seventh node S7, the first electrode of the ninth scanning transistor ST9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth scanning transistor ST9 is electrically connected to the output terminal SOUT. The control electrode of the tenth scanning transistor ST10 is electrically connected to the third node S3, the first electrode of the tenth scanning transistor ST10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth scanning transistor ST10 is electrically connected to the output terminal SOUT. The control terminal of the eleventh scanning transistor ST11 is electrically connected to the second power supply terminal VGL. The first terminal of the eleventh scanning transistor ST11 is electrically connected to the second node S2, and the second terminal of the eleventh scanning transistor ST11 is electrically connected to the fourth node S4. The control terminal of the twelfth scanning transistor ST12 is electrically connected to the second power supply terminal VGL. The first terminal of the twelfth scanning transistor ST12 is electrically connected to the first node S1, and the second terminal of the twelfth scanning transistor ST12 is electrically connected to the third node S3.The control terminal of the thirteenth scanning transistor ST13 is electrically connected to the second clock signal terminal SCK2. The first terminal of the thirteenth scanning transistor ST13 is electrically connected to the first node S1, and the second terminal of the thirteenth scanning transistor ST13 is electrically connected to the first power supply terminal VGH. The first plate SC11 of the first scanning capacitor SC1 is electrically connected to the fourth node S4, and the second plate SC12 of the first scanning capacitor SC1 is electrically connected to the sixth node S6. The first plate SC21 of the second scanning capacitor SC2 is electrically connected to the seventh node S7, and the second plate SC22 of the second scanning capacitor SC2 is electrically connected to the first power supply terminal VGH. The first plate SC31 of the third scanning capacitor SC3 is electrically connected to the third node S3, and the second plate SC32 of the third scanning capacitor SC3 is electrically connected to the fifth node S5.

[0191] In one exemplary embodiment, the first scanning transistor ST1 to the thirteenth scanning transistor ST13 can be either P-type transistors or N-type transistors. The tenth scanning transistor ST10 is an output transistor.

[0192] In one exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal. Because the second power supply terminal VGL continuously provides a low-level signal, the eleventh scan transistor ST11 and the twelfth scan transistor ST12 are continuously turned on.

[0193] In one exemplary embodiment, the second clock signal terminal SCK2 is a low-level signal during the power-on initialization phase to prevent the ninth scan transistor ST9 and the tenth scan transistor ST10 of the last-stage scan shift register from conducting simultaneously due to output signal delay, or it is a low-level signal during the abnormal power-off phase to prevent the ninth scan transistor ST9 and the tenth scan transistor ST10 from conducting simultaneously. The second clock signal terminal SCK2 continuously provides a high-level signal during the normal display phase, meaning that the thirteenth scan transistor ST13 remains continuously off during the normal display phase.

[0194] Taking the first scanning transistor ST1 to the thirteenth scanning transistor ST13 as P-type transistors as an example, such as Figure 8B As shown, the operation of a scan shift register provided in an exemplary embodiment includes the following stages:

[0195] In the first stage C1, the signal at the first clock signal terminal SCK1 is high, and the signal at the third clock signal terminal SCK3 is low. With the third clock signal terminal SCK3 low, the first scanning transistor ST1, the third scanning transistor ST3, and the twelfth scanning transistor ST12 are turned on. The turned-on first scanning transistor ST1 transmits the high-level signal at the input terminal SIN to the first node S1, thus making the level of the first node S1 high. The turned-on twelfth scanning transistor ST12 transmits the high-level signal from the first node S1 to the third node S2. The second scanning transistor ST2, the fourth scanning transistor ST4, the eighth scanning transistor ST8, and the tenth scanning transistor ST10 are turned off. Meanwhile, the turned-on third scanning transistor ST3 transmits the low-level signal at the second power supply terminal VGL to the second node S2, thus making the level of the second node S2 low. The turned-on eleventh scanning transistor ST11 transmits the low-level signal from the second node S2 to the fourth node S4, thus making the level of the fourth node S4 low. The fifth scanning transistor ST5 and the sixth scanning transistor ST6 are turned on. The first clock signal line SCK1 is high, and the seventh scan transistor ST7 is off. Additionally, the ninth scan transistor ST9 is off due to the action of the third scan capacitor SC3. In the first stage P1, since both the ninth and tenth scan transistors ST9 and ST10 are off, the output SOUT signal remains at its previous low level.

[0196] In the second stage C2, the signal at the first clock signal terminal SCK1 is low, and the signal at the third clock signal terminal SCK3 is high. With the first clock signal terminal SCK1 low, the seventh scanning transistor ST7 is turned on. With the third clock signal terminal SCK3 high, the first scanning transistor ST1 and the third scanning transistor ST3 are turned off. Under the influence of the third scanning capacitor SC3, the first node S1 and the third node S3 can maintain the high level signal from the previous stage. Under the influence of the first scanning capacitor SC1, the fourth node S4 can maintain the low level from the previous stage, so the fifth scanning transistor ST5 and the sixth scanning transistor ST6 are turned on. The second scanning transistor ST2, the fourth scanning transistor ST4, the eighth scanning transistor ST8, and the tenth scanning transistor ST10 are turned off. In addition, the low-level signal of the first clock signal terminal SCK1 is transmitted to the seventh node S7 through the sixth scanning transistor ST6 and the seventh scanning transistor ST7, and the ninth scanning transistor ST9 is turned on. The turned-on ninth scanning transistor ST9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal SOUT is a high-level signal.

[0197] In the third stage C3, the signal at the third clock signal terminal SCK3 is low, and the signal at the first clock signal terminal SCK1 is high. With the first clock signal terminal SCK1 high, the seventh scanning transistor ST7 is turned off. The second, fourth, eighth, and tenth scanning transistors ST2 and ST8 are also turned off. With the third clock signal terminal SCK3 low, the first and third scanning transistors ST1 and ST3 are turned on. Under the influence of the third scanning capacitor SC3, the ninth scanning transistor ST9 remains on, outputting a high-level signal from the first power supply terminal VGH. Therefore, the signal at the output terminal SOUT remains high.

[0198] In the fourth stage C4, the signal at the first clock signal terminal SCK1 is low, and the signal at the third clock signal terminal SCK3 is high. With the third clock signal terminal SCK3 high, the first scanning transistor ST1 and the third scanning transistor ST3 are turned off. With the first clock signal terminal SCK1 low, the seventh scanning transistor ST7 is turned on. Due to the storage effect of the third scanning capacitor SC3, the levels at the first node S1 and the third node S3 remain high from the previous stage, thus turning off scanning transistors ST2, ST4, ST8, and ST10. Due to the storage effect of the first scanning capacitor SC1, the fourth node S4 continues to remain low from the previous stage, thus turning on the fifth scanning transistor ST5 and the sixth scanning transistor ST6. Furthermore, the low-level signal at the first clock signal terminal SCK1 is transmitted to the seventh node S7 through the turned-on sixth scanning transistor ST6 and seventh scanning transistor ST7. The turned-on ninth scanning transistor ST9 outputs a high-level signal at the first power supply terminal VGH, so the signal at the output terminal SOUT remains high.

[0199] In stage C5, the signal at the first clock signal terminal SCK1 is high, and the signal at the third clock signal terminal SCK3 is low. When the signal at the third clock signal terminal SCK3 is low, the first scanning transistor ST1 and the third scanning transistor ST3 are turned on. When the signal at the first clock signal terminal SCK1 is high, the seventh scanning transistor ST7 is turned off. The turned-on first scanning transistor ST1 transmits the low-level signal at the input terminal SIN to the first node S1, thus making the level of the first node S1 low. The turned-on twelfth scanning transistor ST12 transmits the low-level signal from the first node S1 to the third node S3, thus making the level of the third node S3 low. The second scanning transistor ST2, the fourth scanning transistor ST4, the eighth scanning transistor ST8, and the tenth scanning transistor ST10 are turned on. The second scanning transistor ST2, when turned on, transmits the low-level signal of the third clock signal terminal SCK3 to the second node S2, further pulling down the level of the second node S2. Therefore, the second node S2 and the fourth node S4 remain at the low level of the previous stage, causing the fifth scanning transistor ST5 and the sixth scanning transistor ST6 to be turned on. The signal of the first clock signal terminal SCK1 is a high-level signal, and the seventh scanning transistor ST7 is turned off. Additionally, the eighth scanning transistor ST8, when turned on, transmits the high-level signal of the first power supply terminal VGH to the seventh node S7, and the ninth scanning transistor ST9 is turned off. The tenth scanning transistor ST10, when turned on, outputs the low-level signal of the second power supply terminal VGL, so the signal at the output terminal SOUT becomes low.

[0200] In one exemplary embodiment, the input terminal of the first-stage scan shift register is electrically connected to the scan initial signal line, the output terminal of the i-th-stage scan shift register is electrically connected to the input terminal of the (i+1)-th-stage scan shift register, the first clock signal terminal of the i-th-stage scan shift register is electrically connected to the first scan clock signal line, the second clock signal terminal is electrically connected to the second scan clock signal line, the third clock signal terminal is electrically connected to the third scan clock signal line, the first clock signal terminal of the (i+1)-th-stage scan shift register is electrically connected to the third scan clock signal line, the second clock signal terminal is electrically connected to the second scan clock signal line, the third clock signal terminal is electrically connected to the first scan clock signal line, the first power supply terminal of the i-th-stage scan shift register is electrically connected to the high-level power supply line connected to the scan driving circuit, and the second power supply terminal of the i-th-stage scan shift register is electrically connected to the low-level power supply line connected to the scan driving circuit.

[0201] In one exemplary embodiment, the first conductive layer may include: gate electrodes of a plurality of light-emitting transistors, gate electrodes of a plurality of scanning transistors, gate electrodes of a plurality of control transistors, first plates of a plurality of light-emitting capacitors, first plates of a plurality of scanning capacitors, and first plates of a plurality of control capacitors.

[0202] In one exemplary embodiment, the second conductive layer may include: the second plates of a plurality of light-emitting capacitors, the second plates of a plurality of scanning capacitors, and the second plates of a plurality of control capacitors;

[0203] In one exemplary embodiment, the third conductive layer may include: source and drain electrodes of a plurality of light-emitting transistors, source and drain electrodes of a plurality of scanning transistors, and source and drain electrodes of a plurality of control transistors.

[0204] In one exemplary embodiment, the fourth conductive layer may include: an initial light emission signal line, at least one light emission clock signal line, an initial scan signal line, at least one scan clock signal line, an initial control signal line, and at least one control clock signal line.

[0205] In one exemplary embodiment, Figures 9A to 9I A partial schematic diagram of a display substrate including four driving circuits, provided for an exemplary embodiment. (See diagram below.) Figures 9A to 9I As shown, when the display substrate is an LTPO display substrate, as Figures 9A to 9I As shown, when the display substrate is an LTPS display substrate, the first reset signal terminal and the second reset signal terminal are different signal terminals, while the control signal terminal and the scan signal terminal are the same signal terminal. Multiple driving circuits include: a light-emitting driving circuit EM GOA, a first reset driving circuit RST1 GOA, a second reset driving circuit RST2 GOA, and a control driving circuit GateP GOA; the light-emitting driving circuit EM GOA is configured to provide a driving signal to the light-emitting transistor, the control driving circuit GateP GOA is configured to provide a driving signal to the write transistor and / or the compensation transistor, the first reset driving circuit RST1 GOA is configured to provide a driving signal to the first reset transistor, and the second reset driving circuit RST2 GOA is configured to provide a driving signal to the second reset transistor.

[0206] In one exemplary embodiment, the high-level power lines connected to at least two adjacent driving circuits in the light-emitting driving circuit EM GOA, the first reset driving circuit RST1 GOA, the second reset driving circuit RST2 GOA, and the control driving circuit GateP GOA are the same power line, and / or the low-level power lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit are the same power line. When the high-level power lines connected to at least two adjacent driving circuits in the light-emitting driving circuit EM GOA, the first reset driving circuit RST1 GOA, the second reset driving circuit RST2 GOA, and the control driving circuit GateP GOA are the same power line, and the low-level power lines connected to at least two adjacent driving circuits in the light-emitting driving circuit EM GOA, the first reset driving circuit RST1 GOA, the second reset driving circuit RST2 GOA, and the control driving circuit GateP GOA are the same power line, the driving circuit connected to the same low-level power line can be the same driving circuit as the driving circuit connected to the same high-level power line, or they can be different driving circuits.

[0207] In one exemplary embodiment, the power supply line can be a high-level power supply line and / or a low-level power supply line. The two driving circuits connected to the power supply line connected to the two driving circuits can be a light-emitting driving circuit EM GOA and a first reset driving circuit RST1 GOA, or a first reset driving circuit RST1 GOA and a control driving circuit GateP GOA, or a control driving circuit GateP GOA and a second reset driving circuit RST2 GOA. The three driving circuits connected to the power supply line connected to the three driving circuits can be a light-emitting driving circuit EM GOA, a first reset driving circuit RST1 GOA and a control driving circuit GateP GOA, or a first reset driving circuit RST1 GOA, a control driving circuit GateP GOA and a second reset driving circuit RST2 GOA.

[0208] Figure 9A This explanation will be based on the example where the low-level power supply line EVGL connected to the light-emitting driver circuit EM GOA and the low-level power supply line RVGL connected to the first reset driver circuit RST1 GOA are the same power supply line. Figure 9B This explanation will be based on the example of the high-level power supply line EVGH connected to the light-emitting driver circuit EM GOA and the high-level power supply line RVGH connected to the first reset driver circuit RST1 GOA being the same power supply line. Figure 9CThis explanation will be based on the example where the low-level power line EVGL connected to the light-emitting driver circuit EM GOA and the low-level power line RVGL connected to the first reset driver circuit RST1 GOA are the same power line, and the high-level power line EVGH connected to the light-emitting driver circuit EM GOA and the high-level power line RVGH connected to the first reset driver circuit RST1 GOA are the same power line. Figure 9D This explanation will be based on the example where the low-level power supply line EVGL connected to the light-emitting driver circuit EM GOA, the low-level power supply line RVGL1 connected to the first reset driver circuit RST1 GOA, and the low-level power supply line GVGL connected to the control driver circuit GatePGOA are all connected to the same power supply line. Figure 9E This explanation uses the example of the high-level power line EVGL connected to the light-emitting driver circuit EMGOA, the high-level power line RVGH1 connected to the first reset driver circuit RST1 GOA, and the high-level power line GVGH connected to the control driver circuit GateP GOA all being the same power line. Figure 9F This explanation uses the following example: the low-level power line EVGL connected to the light-emitting driver circuit EM GOA, the low-level power line RVGL1 connected to the first reset driver circuit RST1 GOA, and the low-level power line GVGL connected to the control driver circuit GateP GOA are all connected to the same power line; and the high-level power line EVGL connected to the light-emitting driver circuit EM GOA, the high-level power line RVGH1 connected to the first reset driver circuit RST1 GOA, and the high-level power line GVGH connected to the control driver circuit GateP GOA are all connected to the same power line. Figure 9G This explanation uses the example of the low-level power line EVGL connected to the light-emitting driver circuit EM GOA, the low-level power line RVGL1 connected to the first reset driver circuit RST1 GOA, the low-level power line GVGL connected to the control driver circuit GateP GOA, and the low-level power line RVGL2 connected to the second reset driver circuit RST2 GOA being the same power line. Figure 9H This explanation uses the example of the high-level power line EVGL connected to the light-emitting driver circuit EM GOA, the high-level power line RVGH1 connected to the first reset driver circuit RST1 GOA, the high-level power line GVGH connected to the control driver circuit GateP GOA, and the high-level power line RVGH2 connected to the second reset driver circuit RST2 GOA being the same power line. Figure 9IThe following example illustrates that the low-level power line EVGL connected to the light-emitting driver circuit EM GOA, the low-level power line RVGL1 connected to the first reset driver circuit RST1 GOA, the low-level power line GVGL connected to the control driver circuit GateP GOA, and the low-level power line RVGL2 connected to the second reset driver circuit RST2 GOA are all the same power line.

[0209] In one exemplary embodiment, when the high-level power line connected to two adjacent driving circuits in the light-emitting driving circuit EM GOA, the first reset driving circuit RST1 GOA, the second reset driving circuit RST2 GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the high-level power line on the substrate overlaps with the orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between the two adjacent driving circuits connected; or, when the high-level power line connected to at least three adjacent driving circuits in the light-emitting driving circuit EM GOA, the first reset driving circuit RST1 GOA, the second reset driving circuit RST2 GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the high-level power line on the substrate overlaps with the orthographic projection of one of the driving circuits connected to the high-level power line on the substrate, or is located between two adjacent driving circuits.

[0210] In one exemplary embodiment, when the low-level power line connected to two adjacent driving circuits in the light-emitting driving circuit EM GOA, the first reset driving circuit RST1 GOA, the second reset driving circuit RST2 GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the low-level power line on the substrate overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits connected; or, when the low-level power line connected to at least three adjacent driving circuits in the light-emitting driving circuit EM GOA, the first reset driving circuit RST1 GOA, the second reset driving circuit RST2 GOA, and the control driving circuit GateP GOA is the same power line, the orthographic projection of the low-level power line on the substrate overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits.

[0211] In one exemplary embodiment, the light-emitting driving circuit EM GOA is located on the side of the control driving circuit GateP GOA away from the display area, the first reset driving circuit RST1 GOA is located between the light-emitting driving circuit and the control driving circuit GatePGOA, and the second reset driving circuit RST2 GOA is located on the side of the control driving circuit GateP GOA closer to the display area.

[0212] In one exemplary embodiment, such as Figures 9A to 9I The circuit structure layer also includes: an initial light-emitting signal line ESTV located in the non-display area and extending along the first direction, multiple light-emitting clock signal lines, a control initial signal line GSTV, multiple control clock signal lines, a first reset initial signal line RSTV1, multiple first reset clock signal lines, a second reset initial signal line RSTV2, and multiple second reset clock signal lines. The light-emitting driver circuit EM GOA is electrically connected to the initial light-emitting signal line ESTV and the multiple light-emitting clock signal lines, respectively. The control driver circuit GateP GOA is electrically connected to the control initial signal line GSTV and the multiple control clock signal lines, respectively. The first reset driver circuit RST1 GOA is electrically connected to the first reset initial signal line RSTV1 and the multiple first reset clock signal lines, respectively. The second reset driver circuit RST2 GOA is electrically connected to the second reset initial signal line RSTV2 and the multiple second reset clock signal lines, respectively. Figures 9A to 9I The following explanation uses three light-emitting clock signal lines ECLK1 to ECLK3, two control clock signal lines GCLK1 and GCLK2, two first reset clock signal lines RCLK1 and RCLK2, and two second reset clock signal lines RCLK3 and RCLK4 as an example.

[0213] In one exemplary embodiment, such as Figures 9A to 9I As shown, the initial light-emitting signal line and multiple light-emitting clock signal lines are located on the side of the first reset initial signal line and multiple first reset clock signal lines away from the display area, while the initial light-emitting signal line is located on the side of the multiple light-emitting clock signal lines close to the display area or away from the display area. Figures 9A to 9I This explanation is based on the example where the initial light-emitting signal line is located on the side of the multiple light-emitting clock signal lines that is far from the display area.

[0214] In one exemplary embodiment, such as Figures 9A to 9I As shown, the first reset initial signal line and multiple first reset clock signal lines are located on the side of the control initial signal line and multiple control clock signal lines closer to the display area, and the first reset initial signal line is located on the side of the multiple first reset clock signal lines closer to the display area or on the side farther away from the display area. Figures 9A to 9I This is explained by the fact that the first reset initial signal line is located on the side of the multiple first reset clock signal lines that is far away from the display area.

[0215] In one exemplary embodiment, such as Figures 9A to 9I As shown, the control initial signal line and the control clock signal line are located on the side away from the display area of ​​the second reset initial signal line and multiple second reset clock signal lines, while the control initial signal line is located on the side of the multiple control clock signal lines that is close to the display area or on the side away from the display area. Figures 9A to 9I This is explained by the fact that the initial control signal line is located on the side of the multiple control clock signal lines that is far away from the display area.

[0216] In one exemplary embodiment, such as Figures 9A to 9I As shown, the second reset initial signal line is located on the side of the multiple second reset clock signal lines that is closer to the display area or farther away from the display area. Figures 9A to 9I This is explained by the fact that the second reset initial signal line is located on the side of the multiple second reset clock signal lines that is far from the display area.

[0217] In one exemplary embodiment, the arrangement of signal lines connected to multiple driving circuits can be determined according to the structure and function of the display substrate, and this disclosure does not impose any limitations on this.

[0218] In one exemplary embodiment, the first reset drive circuit includes: a plurality of cascaded first reset shift registers, at least one of which is electrically connected to a control signal line. The at least one first reset shift register includes: a plurality of first reset transistors and a plurality of first reset capacitors.

[0219] In one exemplary embodiment, the first reset shift register includes a plurality of first reset transistors and a plurality of first reset capacitors. The circuit structure of the first reset shift register can be an 8T2C, and this disclosure does not limit it in any way. The circuit structure of the first reset shift register can be the same as the circuit structure of the control shift register, and this disclosure will not repeat it here.

[0220] The connection method of multiple cascaded first reset shift registers with the first reset initial signal line and two first reset clock signal lines is the same as the connection method of multiple cascaded control shift registers with the control initial signal line and two control clock signal lines, and will not be repeated here.

[0221] In one exemplary embodiment, the second reset shift register includes a plurality of second reset transistors and a plurality of second reset capacitors. The circuit structure of the second reset shift register can be 8T2C, and this disclosure does not limit it in any way. The circuit structure of the second reset shift register can be the same as the circuit structure of the control shift register, and this disclosure will not repeat it here.

[0222] The connection method of multiple cascaded second reset shift registers with the second reset initial signal line and two second reset clock signal lines is the same as the connection method of multiple cascaded control shift registers with the control initial signal line and two control clock signal lines, and will not be repeated here.

[0223] In one exemplary embodiment, the boundary of the display area AA includes at least one arcuate boundary. In another exemplary embodiment, the shape of the boundary of the display area may be a rounded rectangle.

[0224] The display substrate provided in this disclosure can achieve large-angle bending on all four sides, which improves the problem of wrinkles in module bonding and increases product yield.

[0225] In one exemplary embodiment, the display substrate may also include other film layers, such as spacers, etc., which are not limited herein.

[0226] The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0227] The following describes an exemplary display substrate provided, using multiple driving circuits including a light-emitting driving circuit, a scanning driving circuit, and a control driving circuit as an example, through the fabrication process of the display substrate.

[0228] (1) Forming an active layer on a substrate includes: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer. For example... Figure 10 As shown, Figure 10This is a schematic diagram after the semiconductor layer has been formed.

[0229] In one exemplary embodiment, the semiconductor layer includes: the active layer ET11 of the first light-emitting control transistor to the active layer ET131 of the thirteenth light-emitting control transistor, the active layer ST11 of the first scanning transistor to the active layer ST131 of the thirteenth scanning transistor, and the active layer GT11 of the first control transistor to the active layer GT81 of the eighth control transistor.

[0230] In one exemplary embodiment, the active layers ET41 of the fourth light-emitting control transistor and ET51 of the fifth light-emitting control transistor are integrally formed, the active layers ET81 of the eighth light-emitting control transistor and ET131 of the thirteenth light-emitting control transistor are integrally formed, the active layers ET91 of the ninth light-emitting control transistor and ET101 of the tenth light-emitting control transistor are integrally formed, the active layers ST91 of the ninth scan transistor and ST101 of the tenth scan transistor are integrally formed, the active layers GT41 of the fourth control transistor and GT51 of the fifth control transistor are integrally formed, and the active layers GT61 of the sixth control transistor and GT71 of the seventh control transistor are integrally formed.

[0231] (2) Forming a first conductive layer includes: depositing a first insulating film on a substrate on which the above pattern is formed; patterning the first insulating film using a patterning process to form a first insulating layer; depositing a first conductive film on the first insulating layer; and patterning the first conductive film using a patterning process to form a first metal layer, such as... Figure 11 and Figure 12 As shown, Figure 11 This is a schematic diagram of the first conductive layer. Figure 12 This is a schematic diagram after the first conductive layer has been formed.

[0232] In one exemplary embodiment, the first conductive layer may include: the control electrode ET12 of the first light-emitting control transistor to the control electrode ET132 of the thirteenth light-emitting control transistor, the first electrode EC11 of the first light-emitting capacitor to the first electrode EC31 of the third light-emitting capacitor, the control electrode ST12 of the first scanning transistor to the control electrode ST132 of the thirteenth scanning transistor, the first electrode SC11 of the first scanning capacitor to the first electrode SC31 of the third scanning capacitor, the control electrode GT12 of the first control transistor to the control electrode GT82 of the eighth control transistor, the first electrode GC11 of the first control capacitor and the first electrode GC21 of the second control capacitor, and the first connection electrode VL1.

[0233] In one exemplary embodiment, the control electrode ET12 of the first light-emitting control transistor and the control electrode ET32 of the third light-emitting control transistor are integrally formed; the control electrode ET112 of the eleventh light-emitting control transistor and the control electrode ET122 of the twelfth light-emitting control transistor are integrally formed; the control electrode ET62 of the sixth light-emitting control transistor and the first electrode EC11 of the first light-emitting capacitor are integrally formed; the control electrode ET42 of the fourth light-emitting control transistor, the first electrode EC31 of the third light-emitting capacitor and the control electrode ET102 of the tenth light-emitting control transistor are integrally formed; the control electrode ET92 of the ninth light-emitting control transistor and the first electrode EC21 of the second light-emitting capacitor are integrally formed; the scan electrode ST12 of the first scan transistor and the scan electrode ST32 of the third scan transistor are integrally formed; and the scan electrode ST12 of the eleventh scan transistor is integrally formed. The scanning electrodes ST122 of the 112th and 12th scanning transistors are integrally formed; the scanning electrode ST62 of the 6th scanning transistor and the first plate SC11 of the 1st scanning capacitor are integrally formed; the scanning electrode ST42 of the 4th scanning transistor, the first plate SC31 of the 3rd scanning capacitor, and the scanning electrode ST102 of the 10th scanning transistor are integrally formed; the scanning electrode ST92 of the 9th scanning transistor and the first plate SC21 of the 2nd scanning capacitor are integrally formed; the control electrode GT12 of the 1st control transistor and the control electrode GT32 of the 3rd control transistor are integrally formed; the control electrode GT42 of the 4th control transistor, the control electrode GT62 of the 6th control transistor, and the first plate GC11 of the 1st control capacitor are integrally formed; and the control electrode GT52 of the 5th control transistor and the first plate GC21 of the 2nd control capacitor are integrally formed.

[0234] (3) Forming a second conductive layer includes: depositing a second insulating film on a substrate with the above-mentioned pattern, and patterning the second insulating film using a patterning process to form a second insulating layer. Depositing a second conductive film on a substrate with a second insulating layer, and patterning the second conductive film using a patterning process to form a second conductive layer. Figure 13 and Figure 14 As shown, Figure 13 This is a schematic diagram of the second conductive layer. Figure 14 This is a schematic diagram after the second conductive layer has been formed.

[0235] In one exemplary embodiment, the second conductive layer includes: a second connecting electrode VL2 to an eighth connecting electrode VL8, a second electrode EC12 of a first light-emitting capacitor to a second electrode EC32 of a third light-emitting capacitor, a second electrode SC12 of a first scanning capacitor to a second electrode SC32 of a third scanning capacitor, a second electrode GC12 of a first control capacitor, and a second electrode GC22 of a second control capacitor.

[0236] (4) Forming a fifth conductive layer includes: depositing a fifth insulating film on a substrate with the above-mentioned pattern; patterning the fifth insulating film using a patterning process to form a fifth insulating layer; depositing a fifth conductive film on the fifth insulating layer; and patterning the fifth conductive film using a patterning process to form a fifth conductive layer, such as... Figure 15 and Figure 16 As shown, Figure 15 This is a schematic diagram of the fifth conductive layer. Figure 16 This is a schematic diagram after the fifth conductive layer has been formed.

[0237] In one exemplary embodiment, the third conductive layer includes: an eighth connecting electrode VL8 to a tenth connecting electrode VL10.

[0238] (5) Forming a third conductive layer includes: depositing a third insulating film on the substrate on which the above-mentioned material is formed; patterning the third insulating film using a patterning process to form a third insulating layer; depositing a third conductive film on the third insulating layer; and patterning the third conductive film using a patterning process to form a third conductive layer, such as... Figure 17 and Figure 18 As shown, Figure 17 This is a schematic diagram of the third conductive layer. Figure 18 This is a schematic diagram after the third conductive layer has been formed.

[0239] In one exemplary embodiment, the fourth conductive layer includes at least: a low-level power line EVGL, the first pole ET13 and the second pole ET14 of the first light-emitting control transistor to the first pole ET133 and the second pole ET134 of the thirteenth light-emitting control transistor, the first pole ST13 and the second pole ST14 of the first scan transistor to the first pole ST133 and the second pole ST134 of the thirteenth scan transistor, a second scan clock signal line SCLK2, and the first pole GT13 and the second pole GT14 of the first control transistor to the first pole GT83 and the second pole GT84 of the eighth control transistor.

[0240] In one exemplary embodiment, the first connecting electrode is electrically connected to VL1 and the first terminal ET13 of the first light-emitting control transistor and the eighth connecting electrode VL8, respectively; the second connecting electrode VL2 is electrically connected to the second terminal ET54 of the fifth light-emitting control transistor and the first terminal ET83 of the eighth light-emitting control transistor, respectively; the third connecting electrode VL3 is connected to the second terminal ET104 of the tenth light-emitting control transistor, respectively; the fourth connecting electrode is electrically connected to the tenth connecting electrode VL10 and the first terminal ST13 of the first scanning transistor, respectively; the fifth connecting electrode VL5 is electrically connected to the second terminal ST114 of the eleventh scanning transistor and the control terminal of the sixth scanning transistor, respectively; the sixth connecting electrode VL6 is electrically connected to the second terminal ST34 of the third scanning transistor and the second terminal ST24 of the second scanning transistor, respectively; the seventh connecting electrode VL is electrically connected to the second terminal of the second control transistor and the second terminal of the fourth control transistor, respectively; and the tenth connecting electrode VL10 is electrically connected to the second terminal ST104 of the tenth scanning transistor.

[0241] (6) Forming a fourth conductive layer includes: depositing a fourth insulating film on a substrate having the above-mentioned pattern; patterning the fourth insulating film using a patterning process to form a fourth insulating layer; depositing a fourth conductive film on the fourth insulating layer; and patterning the fourth conductive film using a patterning process to form a fourth conductive layer, such as... Figure 19 and Figure 20 As shown, Figure 19 This is a schematic diagram of the fourth conductive layer. Figure 20 This is a schematic diagram after the fourth conductive layer has been formed.

[0242] In one exemplary embodiment, the fifth conductive layer includes at least: an initial light emission signal line ESTV, first light emission clock signal lines ECLK1 to third light emission clock signal lines ECLK3, an initial scan signal line SSTV, first scan clock signal line SCLK1, third scan clock signal line SCLK3, an initial control signal line GSTV, first control clock signal line GCLK1, second control clock signal line GCLK2, a high-level power supply line EVGH connected to the light emission driving circuit, a high-level power supply line SVGH connected to the scan driving circuit, a high-level power supply line GVGH connected to the control driving circuit, a low-level power supply line VGL connected to the scan driving circuit, a low-level power supply line GVGL connected to the control driving circuit, an eleventh connection electrode VL11, and a twelfth connection electrode VL12.

[0243] In one exemplary embodiment, the twelfth connection electrode VL12 is electrically connected to the second electrode of the tenth scanning transistor, and the eleventh connection electrode is electrically connected to the eighth connection electrode.

[0244] In one exemplary embodiment, the low-level power line SVGL connected to the scan drive circuit and the low-level power line GVGL connected to the control drive circuit are the same power line.

[0245] In one exemplary embodiment, the light-emitting driving circuit is connected to two low-level power lines. The control electrode of the tenth light-emitting transistor in the light-emitting driving circuit is electrically connected to the low-level power line EVGL connected to the light-emitting driving circuit, and the control electrodes of the eleventh and twelfth light-emitting transistors are electrically connected to the low-level power line SVGL connected to the scanning driving circuit.

[0246] In one exemplary embodiment, the widths of the high-level power line and the low-level power line are greater than the widths of any initial signal line and any clock signal line.

[0247] (7) Forming the sixth conductive layer includes: coating a planarization film on a substrate with the above-mentioned pattern; forming a planarization layer by masking, exposing, and developing the planarization film; depositing a transparent conductive film on the planarization layer; and patterning the transparent conductive film by a patterning process to form the sixth conductive layer, such as... Figure 21 and Figure 22 As shown, Figure 21 This is a schematic diagram of the sixth conductive layer. Figure 22 This is a schematic diagram after the formation of the sixth conductive layer.

[0248] In one exemplary embodiment, the sixth conductive layer includes a first output signal line OL1. The first output signal line is an output signal line of a scan driving circuit; the orthographic projection of at least one of the first output signal lines onto the substrate at least partially overlaps with the orthographic projections of at least one of the control driving circuit, the scan driving circuit, and the light-emitting driving circuit onto the substrate.

[0249] In one exemplary embodiment, the angle between the extension direction of the first output signal line and the first direction is greater than or equal to 0 degrees and less than 45 degrees. The angle between the extension direction of the first output signal line and the first direction may be equal to 0 degrees, and this disclosure does not limit it in any way.

[0250] (8) Forming a light-emitting structure layer includes: coating a second planar thin film on a substrate with the above-mentioned pattern, patterning the second planar thin film by a patterning process to form a second planar layer, depositing an anode thin film on the second planar layer, patterning the anode thin film by a patterning process to form an anode, depositing a pixel definition thin film on the anode, patterning the pixel definition thin film by a patterning process to form a pixel definition layer, evaporating an organic light-emitting thin film on the pixel definition layer, patterning the organic light-emitting thin film by a patterning process to form an organic light-emitting layer, depositing a cathode thin film on the organic light-emitting layer, and patterning the cathode thin film by a patterning process to form a cathode.

[0251] In one exemplary embodiment, an optical coupling layer pattern can be formed after the cathode is formed. The optical coupling layer is disposed on the cathode. The refractive index of the optical coupling layer can be greater than that of the cathode, which is beneficial for light extraction and increases the light extraction efficiency. The material of the optical coupling layer can be an organic material, an inorganic material, or a combination of organic and inorganic materials. It can be a single layer, a multilayer layer, or a composite layer. This disclosure does not limit the specific materials used.

[0252] In one exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer. The active layer thin film may be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene; that is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0253] In one exemplary embodiment, the first insulating layer, the second insulating layer, and the third to fifth insulating layers may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0254] In one exemplary embodiment, the first to fifth conductive films may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti.

[0255] In one exemplary embodiment, the material of the pixel definition layer may include polyimide, acrylic, or polyethylene terephthalate.

[0256] In one exemplary embodiment, a half-tone mask or gray-toned mask patterning process may be used to form a pattern of spacer pillars (PS) 25 when forming a pixel definition layer. The spacer pillars 25 may be disposed outside the pixel opening and are configured to support a fine metal mask in a subsequent vapor deposition process.

[0257] In one exemplary embodiment, the planarization layer may be made of an organic material.

[0258] In one exemplary embodiment, the anode film may be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0259] In an exemplary embodiment, the cathode film may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0260] The display substrate described in this embodiment can be used in display products of any resolution.

[0261] This disclosure also provides a display device, including a display substrate.

[0262] In one exemplary embodiment, the display device can be a monitor, television, mobile phone, tablet computer, navigator, digital photo frame, wearable display product, or any product or component with display function.

[0263] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0264] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0265] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0266] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The display substrate includes a display area and a non-display area, comprising: a substrate and a circuit structure layer disposed on the substrate, the circuit structure layer including: a plurality of pixel circuits located in the display area and arranged in an array, and a plurality of driving circuits located in the non-display area; at least one pixel circuit includes: a plurality of transistors, the plurality of driving circuits being configured to provide driving signals to the plurality of transistors; The circuit structure layer further includes: a high-level power line and a low-level power line located in the non-display area, at least one driving circuit being electrically connected to the high-level power line and the low-level power line respectively, and the high-level power line and the low-level power line extending along a first direction; At least two drive circuits are connected to the same high-level power line and / or at least two drive circuits are connected to the same low-level power line. The circuit structure layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer stacked sequentially on a substrate, wherein the high-level power line and the low-level power line are located in the third conductive layer and / or the fourth conductive layer; The plurality of transistors includes a write transistor, a compensation transistor, and a light-emitting transistor; the plurality of driving circuits includes a light-emitting driving circuit and a control driving circuit; the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor, and the control driving circuit is configured to provide a driving signal to the write transistor and / or the compensation transistor; The high-level power line connected to the light-emitting driving circuit and the high-level power line connected to the control driving circuit are the same power line, and / or the low-level power line connected to the light-emitting driving circuit and the low-level power line connected to the control driving circuit are the same power line.

2. The display substrate according to claim 1, wherein, The display area includes: a first side and a second side disposed opposite to each other, and at least one driving circuit is located on the first side and / or the second side of the display area; The plurality of driving circuits extend along a second direction, and the first direction intersects with the second direction.

3. The display substrate according to claim 1, wherein, The circuit structure layer may further include: a fifth insulating layer and a fifth conductive layer; The fifth insulating layer and the fifth conductive layer are located between the second conductive layer and the third insulating layer, and the fifth insulating layer is located on the side of the fifth conductive layer closer to the substrate.

4. The display substrate according to claim 1, wherein, When the high-level power line connected to the light-emitting driving circuit and the high-level power line connected to the control driving circuit are the same power line, the orthographic projection of the high-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit.

5. The display substrate according to claim 1, wherein, When the low-level power line connected to the light-emitting driving circuit and the low-level power line connected to the control driving circuit are the same power line, the orthographic projection of the low-level power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit or the control driving circuit on the substrate, or is located between the light-emitting driving circuit and the control driving circuit.

6. The display substrate according to any one of claims 1, 4, and 5, wherein, The light-emitting driving circuit is located on the side of the control driving circuit that is away from the display area; The circuit structure layer further includes: an initial light emission signal line, multiple light emission clock signal lines, a control initial signal line, and multiple control clock signal lines located in the non-display area and extending along the first direction; the light emission driving circuit is electrically connected to the initial light emission signal line and the multiple light emission clock signal lines respectively, and the control driving circuit is electrically connected to the control initial signal line and the multiple control clock signal lines respectively. The initial light-emitting signal line and the plurality of light-emitting clock signal lines are located on the side of the initial control signal line and the plurality of control clock signal lines away from the display area, and the initial light-emitting signal line is located on the side of the plurality of light-emitting clock signal lines closer to the display area or away from the display area; The initial control signal line is located on the side of the plurality of control clock signal lines that is closer to the display area, or on the side that is farther away from the display area.

7. The display substrate according to claim 6, wherein, The light-emitting driving circuit includes: multiple light-emitting transistors and multiple light-emitting capacitors; the control driving circuit includes: multiple control transistors and multiple control capacitors. The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple control transistors, first plates of multiple light-emitting capacitors, and first plates of multiple control capacitors; The second conductive layer includes: the second plates of multiple light-emitting capacitors and the second plates of multiple control capacitors; The third conductive layer includes: source and drain electrodes of multiple light-emitting transistors and source and drain electrodes of multiple control transistors. The fourth conductive layer includes: an initial light-emitting signal line, at least one light-emitting clock signal line, an initial control signal line, and at least one control clock signal line.

8. The display substrate according to claim 1 or 3, wherein, The plurality of transistors further includes: a first reset transistor, wherein the transistor types of the first reset transistor and the compensation transistor are different from the transistor types of the write transistor and the light-emitting transistor; the plurality of driving circuits further includes: a scan driving circuit; the control driving circuit is configured to provide a driving signal to the write transistor, and the scan driving circuit is configured to provide a driving signal to the first reset transistor and / or the compensation transistor; The high-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit are the same power supply line, and / or the low-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit are the same power supply line.

9. The display substrate according to claim 8, wherein, When the high-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or is located between the two adjacent driving circuits connected. Alternatively, when the high-level power supply line connected to the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or it is located between two adjacent driving circuits.

10. The display substrate according to claim 8, wherein, When the low-level power line connected to two adjacent driving circuits in the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or is located between the two adjacent driving circuits connected. Alternatively, when the low-level power line connected to the light-emitting driving circuit, the scanning driving circuit, and the control driving circuit is the same power line, the orthographic projection of the low-level power line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power line on the substrate, or it is located between two adjacent driving circuits.

11. The display substrate according to claim 9 or 10, wherein, The light-emitting driving circuit is located on the side of the scanning driving circuit away from the display area, and the control driving circuit is located on the side of the scanning driving circuit closer to the display area; The circuit structure layer further includes: an initial light emission signal line, multiple light emission clock signal lines, a control initial signal line, multiple control clock signal lines, a scan initial signal line, and multiple scan clock signal lines, all located in the non-display area and extending along a first direction; the light emission driving circuit is electrically connected to the initial light emission signal line and the multiple light emission clock signal lines, the control driving circuit is electrically connected to the control initial signal line and the multiple control clock signal lines, and the scan driving circuit is electrically connected to the initial scan signal line and the multiple scan clock signal lines. The initial light-emitting signal line and the plurality of light-emitting clock signal lines are located on the side of the initial scan signal line and the plurality of scan clock signal lines away from the display area, and the initial light-emitting signal line is located on the side of the plurality of light-emitting clock signal lines closer to the display area or on the side away from the display area; The control initial signal line and the plurality of control clock signal lines are located on the side of the scan initial signal line and the plurality of scan clock signal lines closer to the display area, and the control initial signal line is located on the side of the plurality of control clock signal lines closer to the display area or on the side farther away from the display area; The initial scan signal line is located on the side of the plurality of scan clock signal lines that is closer to the display area, or on the side that is farther away from the display area.

12. The display substrate according to claim 11, wherein, The light-emitting driving circuit includes: multiple light-emitting transistors and multiple light-emitting capacitors; the scanning driving circuit includes: multiple scanning transistors and multiple scanning capacitors; and the control driving circuit includes: multiple control transistors and multiple control capacitors. The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple scanning transistors, gate electrodes of multiple control transistors, first plates of multiple light-emitting capacitors, first plates of multiple scanning capacitors, and first plates of multiple control capacitors. The second conductive layer includes: the second plates of multiple light-emitting capacitors, the second plates of multiple scanning capacitors, and the second plates of multiple control capacitors; The third conductive layer includes: source and drain electrodes of multiple light-emitting transistors, source and drain electrodes of multiple scanning transistors, and source and drain electrodes of multiple control transistors. The fourth conductive layer includes: an initial light emission signal line, at least one light emission clock signal line, an initial scan signal line, at least one scan clock signal line, an initial control signal line, and at least one control clock signal line.

13. The display substrate according to claim 8, wherein, The write transistor and the light-emitting transistor are P-type transistors, and the first reset transistor and the compensation transistor are N-type metal-oxide transistors.

14. The display substrate according to claim 1 or 3, wherein, The plurality of transistors further includes: a first reset transistor and a second reset transistor; the plurality of driving circuits further includes: a first reset driving circuit and a second reset driving circuit; the control driving circuit is configured to provide a driving signal to the write transistor and / or the compensation transistor, the first reset driving circuit is configured to provide a driving signal to the first reset transistor, and the second reset driving circuit is configured to provide a driving signal to the second reset transistor; The high-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit are the same power supply line, and / or the low-level power supply lines connected to at least two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit are the same power supply line.

15. The display substrate according to claim 14, wherein, When the high-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or is located between the two adjacent driving circuits connected. Alternatively, when the high-level power supply line connected to at least three adjacent driving circuits among the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the high-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the high-level power supply line on the substrate, or it is located between two adjacent driving circuits.

16. The display substrate according to claim 14, wherein, When the low-level power supply line connected to two adjacent driving circuits in the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the low-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power supply line on the substrate, or is located between the two adjacent driving circuits connected. Alternatively, when the low-level power supply line connected to at least three adjacent driving circuits among the light-emitting driving circuit, the first reset driving circuit, the second reset driving circuit, and the control driving circuit is the same power supply line, the orthographic projection of the low-level power supply line on the substrate partially overlaps with the orthographic projection of one of the driving circuits connected to the low-level power supply line on the substrate, or it is located between two adjacent driving circuits.

17. The display substrate according to claim 15 or 16, wherein, The light-emitting driving circuit is located on the side of the control driving circuit away from the display area, the first reset driving circuit is located between the light-emitting driving circuit and the control driving circuit, and the second reset driving circuit is located on the side of the control driving circuit closer to the display area. The circuit structure layer further includes: a light-emitting initial signal line, multiple light-emitting clock signal lines, a control initial signal line, multiple control clock signal lines, a first reset initial signal line, multiple first reset clock signal lines, a second reset initial signal line, and multiple second reset clock signal lines, all located in the non-display area and extending along a first direction; the light-emitting driving circuit is electrically connected to the light-emitting initial signal line and the multiple light-emitting clock signal lines respectively; the control driving circuit is electrically connected to the control initial signal line and the multiple control clock signal lines respectively; the first reset driving circuit is electrically connected to the first reset initial signal line and the multiple first reset clock signal lines respectively; and the second reset driving circuit is electrically connected to the second reset initial signal line and the multiple second reset clock signal lines respectively. The initial light-emitting signal line and the plurality of light-emitting clock signal lines are located on the side of the first reset initial signal line and the plurality of first reset clock signal lines away from the display area, and the initial light-emitting signal line is located on the side of the plurality of light-emitting clock signal lines close to the display area or on the side away from the display area; The first reset initial signal line and the plurality of first reset clock signal lines are located on the side of the control initial signal line and the plurality of control clock signal lines closer to the display area, and the first reset initial signal line is located on the side of the plurality of first reset clock signal lines closer to the display area or on the side farther away from the display area; The control initial signal line and the control clock signal line are located on the side away from the display area of ​​the second reset initial signal line and the plurality of second reset clock signal lines, and the control initial signal line is located on the side of the plurality of control clock signal lines that is close to the display area or on the side away from the display area; The second reset initial signal line is located on the side of the plurality of second reset clock signal lines that is closer to the display area or on the side that is farther away from the display area.

18. The display substrate according to claim 17, wherein, The light-emitting driving circuit includes: a plurality of light-emitting transistors and a plurality of light-emitting capacitors; the control driving circuit includes: a plurality of control transistors and a plurality of control capacitors; the first reset driving circuit includes: a plurality of first reset transistors and a plurality of first reset capacitors; and the second reset driving circuit includes: a plurality of second reset transistors and a plurality of second reset capacitors. The first conductive layer includes: gate electrodes of multiple light-emitting transistors, gate electrodes of multiple control transistors, gate electrodes of multiple first reset transistors, gate electrodes of multiple second reset transistors, first plates of multiple light-emitting capacitors, first plates of multiple control capacitors, first plates of multiple first reset capacitors, and first plates of multiple second reset capacitors. The second conductive layer includes: the second plates of multiple light-emitting capacitors, the second plates of multiple control capacitors, the second plates of multiple first reset capacitors, and the second plates of multiple second reset capacitors; The third conductive layer includes: source and drain electrodes of multiple light-emitting transistors, source and drain electrodes of multiple control transistors, source and drain electrodes of multiple first reset transistors, and source and drain electrodes of multiple second reset transistors. The fourth conductive layer includes: an initial light emission signal line, at least one initial light emission clock signal line, a control initial signal line, at least one control clock signal line, a first reset initial signal line, at least one first reset clock signal line, a second reset initial signal line, and at least one second reset clock signal line.

19. The display substrate according to claim 1, wherein, The boundary of the display area includes at least one arc-shaped boundary.

20. A display device comprising a display substrate as described in any one of claims 1 to 19.

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