Autonomous frequency retrieval from plasma power supply

Abstract

Embodiments disclosed herein include a processing tool. In one embodiment, the processing tool includes a transmission line sensor and an analog-to-digital (A / D) converter. In an embodiment, the processing tool may further include a digital down converter (DDC) and a frequency digital phase locked loop (dPLL). In one embodiment, the processing tool may further include a transmission line scaling module.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application No. 17 / 737,665, filed on May 5, 2022, the entire contents of which are incorporated herein by reference.

[0003] field

[0004] Embodiments relate to the field of semiconductor manufacturing and, more particularly, to semiconductor processing tools configured to provide frequency retrieval from a plasma power supply.

[0005] Description of Related Technology

[0006] In a plasma processing tool, the plasma is ignited by a cathode, which is coupled to a process gas within the chamber. In most tools, a power source is coupled to the cathode via an impedance matching network (sometimes simply referred to as a "match"). The match allows the impedance of the system to be adjusted to match the impedance of the load to which the cathode is coupled. The load has a wide range of impedances determined by parameters such as the processing conditions, chamber structure, etc. Impedance matching is important in order to provide efficient power transfer from the source to the load.

[0007] In addition to matching impedances, it is also important to know the exact frequency of the power supplied by the power supply. Therefore, a frequency detection system may be included in the power delivery network. Current existing frequency identification schemes require messaging or other information transfer from different systems or subsystems to determine the frequency. Optimal messaging and / or information transfer requires point-to-point network connections and suffers from large group delays between actuator control and feedback between various elements of the dynamic system. Therefore, the necessary frequency feedback is subject to latency.

[0008] Overview

[0009] Embodiments disclosed herein include processing tools. In one embodiment, the processing tool includes a transmission line sensor and an analog to digital (A / D) converter. In one embodiment, the processing tool may further include a digital down converter (DDC) and a frequency digital phase lock loop (dPLL). In one embodiment, the processing tool may further include a transmission line scaling module.

[0010] Other embodiments disclosed herein may also include a processing tool. In one embodiment, the processing tool includes a transmission line sensor and an analog to digital (A / D) converter. In one embodiment, the processing tool may further include a digital down converter (DDC) and a transmission line scaling module.

[0011] Other embodiments may include a semiconductor processing tool. In one embodiment, the semiconductor processing tool may include a chamber, a plasma source coupled to the chamber, and a signal processing module for determining a frequency of a plasma generated by the plasma source. In one embodiment, the signal processing module includes a transmission line sensor, an analog to digital (A / D) converter, a digital down converter (DDC), a frequency digital phase lock loop (dPLL), and a transmission line scaling module.

[0012] BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of a plasma processing tool including a centralized control architecture according to one embodiment.

[0014] Figure 2 is a plan view of a sensor having a current loop, a voltage loop, and a guard ring according to one embodiment.

[0015] Figure 3 are a pair of graphs illustrating down conversion resulting from a low pass filter extracting a desired signal while attenuating other signals, according to an embodiment.

[0016] Figure 4 A process flow diagram of a process for determining power frequency using a process power control module is depicted according to one embodiment.

[0017] Figure 5 is a schematic diagram of a processing system for identifying signal frequency according to one embodiment.

[0018] Figure 6 FIG. 4 is a schematic diagram of a signal processing module when there is no interference according to an embodiment.

[0019] Figure 7 is a schematic diagram of a signal processing architecture according to an embodiment.

[0020] Figure 8 A block diagram of an exemplary computer system that may be used in conjunction with a processing tool is shown according to one embodiment.

[0021] Specific description

[0022] The systems described herein include a power delivery architecture configured to provide frequency retrieval from a plasma power supply. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. It will be apparent to one skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known aspects have not been described in detail in order to avoid unnecessarily obscuring the embodiments. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0023] As mentioned above, for real-time process control and monitoring, it is important to know the frequency of process power. Therefore, the embodiments disclosed herein include detection and retrieval processes with high accuracy, minimum group delay and optimal control. In addition, the scheme described herein is autonomous and does not require messaging and / or information transfer from other systems or subsystems.

[0024] Reference Figure 1 , according to one embodiment, a more detailed schematic diagram of a plasma processing tool 100 is shown. In one embodiment, the plasma processing tool 100 includes a plasma chamber 120. The plasma chamber 120 includes a cathode 122 to couple received power to one or more gases flowing into the plasma chamber 120. In one embodiment, the plasma chamber 120 can be suitable for any typical plasma process in a semiconductor manufacturing environment. For example, the plasma chamber 120 can be a plasma etching chamber, a plasma deposition chamber, a plasma processing chamber, etc. In a specific embodiment, the plasma chamber 120 can be a plasma enhanced chemical vapor deposition (PECVD) chamber, a physical vapor deposition (PVD) chamber, or a plasma enhanced atomic layer deposition (PEALD) chamber.

[0025] In one embodiment, the plasma chamber 120 may be coupled to a power delivery architecture. For example, the power delivery architecture may include one or more power supplies 132 1 -132 nIn the illustrated embodiment, multiple power sources 132 are shown. However, it should be understood that in some embodiments, a single power source 132 may be used. In one embodiment, the power source 132 may include any type of power source. For example, the power source 132 may be a radio frequency power source, a microwave power source, a direct current (DC) power source, a pulsed DC power source, etc.

[0026] In one embodiment, the power source 132 may be coupled to the cathode 122 via an impedance matching network 130. The impedance matching network 130 changes the impedance of the power delivery architecture to match the load in the chamber 120. The impedance of the load may change due to changes in processing conditions (e.g., gas flow rate, pressure, temperature, etc.). As such, the impedance matching network 130 is used to match the changing impedance to provide efficient power delivery to the chamber (i.e., no or minimal reflected power).

[0027] In one embodiment, sensors 151 and 152 may be disposed at opposite ends of the impedance matching network 130. For example, sensor 151 1 -151 n The sensor 152 may be on the upstream side of the impedance matching network 130, and the sensor 152 may be on the downstream side of the impedance matching network 130. The "upstream" side may refer to the input side of the matching network 130, and the "downstream" side may refer to the output side of the matching network 130. As shown in the figure, a plurality of sensors 151 are provided on the upstream side of the impedance matching network 130. 1 -151 n The number of sensors 151 may be equal to the number of power supplies 132. That is, each power supply 132 may have a dedicated sensor 151. The downstream side of the impedance matching network 130 may have a single sensor 152. However, it should be understood that when the matching network 130 has more than one output, there may be additional sensors 152. For example, where there are two outputs (e.g., for the center of the chamber 120 and the edge of the chamber 120), there may be two sensors 152.

[0028] In the case of multiple sensors 151, multiple sensors 151 1 Up to 151 n Can be manufactured on a single PCB. That is, a single module can include multiple sensors. In general, the embodiments described herein include electrical shielding techniques that limit cross coupling between sensors on a single PCB.

[0029] exist Figure 1, sensors 151 and 152 are generally shown as blocks. However, it should be understood that sensors 151 and 152 can be similar to any sensor architecture described in more detail below. For example, each sensor 151 and / or 152 can be a voltage and current (i.e., V / I) sensor. The voltage can be detected by an embedded voltage loop, and the current can be detected by a current loop. The sensor can have a hole through which a cable (e.g., an RF cable) passes.

[0030] In one embodiment, sensors 151 and 152 may be communicatively coupled to process power control module 134. For example, Figure 1 134. However, it should be understood that the processing module may be a microwave process power control module 134, a DC process power control module 134, etc., depending on what type of power supply 132 is included in the tool 100. In one embodiment, sensors 151 and 152 deliver voltage and / or current to the process power control module. In one embodiment, the process power control module may have external connections, such as ENET and ECAT connections.

[0031] In one embodiment, the process power control module 134 may be coupled to the impedance matching network via a digital / analog link. Via the digital / analog link, the process power control module 134 can send control signals to the impedance matching network 130. For example, the control signal can be used to adjust the capacitance of a variable capacitor within the impedance matching network 130. In addition, the process power control module 134 may be coupled to the power supply 132 via a digital / analog link. In this way, the process power control module 134 can coordinate impedance tuning.

[0032] Reference now Figure 2 , according to one embodiment, shows a plan view of a sensor 250. As shown, the sensor 250 is fabricated on a PCB 253. The sensor 250 may include a current loop 254 and a voltage loop 265 within the current loop 254. The current loop 254 and the voltage loop 265 may surround a hole 260 passing through the PCB 253.

[0033] In one embodiment, the current loop 254 may include an inner through hole 255 B And external through hole 255 A The vias 255 may be coupled to each other via traces 256 on the top surface of the PCB 253 and traces 257 on the bottom surface of the PCB 253. In the illustrated embodiment, the current loop 254 includes a pair of windings around the hole 260.

[0034] In one embodiment, the voltage ring 265 may include an inner conductive ring 266 and an outer conductive ring 268. An insulating ring 267 may be disposed between the inner ring 266 and the outer ring 268. The inner ring 266 may be a voltage pickup surface, and the outer ring 268 may be grounded. In one embodiment, the inner ring 266 may define the periphery of the hole 260.

[0035] In one embodiment, the sensor 250 may further include a guard ring 270 around the periphery of the current loop 254. In one embodiment, the guard ring 270 may be grounded. The guard ring 270 may include a through hole (not shown) that couples the guard ring 270 to a ring of similar size and shape on the bottom side of the PCB 253. In this way, an electrical shielding barrier is provided around the pickup component of the sensor 250. Therefore, the sensor performance can be improved.

[0036] In one embodiment, the voltage ring 265 can be coupled to the pickup circuit system 281 on the PCB 253. Figure 2 The pickup circuit system 281 in FIG. 1 is schematically shown as a dashed box. However, it should be understood that the pickup circuit system 281 may include features such as filters, amplifiers, etc. In one embodiment, a pad 283 is provided. The pad 283 may be adapted to connect to a connector (not shown) to feed voltage information back to a processing module, such as the processing module described in more detail above.

[0037] In one embodiment, the current loop 254 may be coupled to the pickup circuitry 282 on the PCB 253. Figure 2 The pickup circuit system 282 in FIG. 1 is schematically shown as a dashed box. However, it should be understood that the pickup circuit system 282 may include features such as filters, amplifiers, etc. In one embodiment, a pad 284 is provided. The pad 284 may be adapted to connect to a connector (not shown) to feed current information back to a processing module, such as the processing module described in more detail above.

[0038] In one embodiment, the pickup circuit system 281 is electrically isolated from the pickup circuit system 282. Electrically isolating the two sets of pickup circuit systems 281 and 282 can reduce cross coupling between the two circuits. In this way, the performance of the sensor 250 can be improved. In one embodiment, the electrical isolation can be provided by a conductive tape 285 disposed between the two sets of pickup circuit systems 281 and 282. In one embodiment, the conductive tape 285 can be grounded. In some embodiments, the conductive tape 285 is electrically coupled to the guard ring 270. The conductive tape 285 can be disposed on the top surface of the PCB 253. In other embodiments, a through hole can be disposed under the conductive tape 285 to extend the electrical isolation through the thickness of the PCB 253.

[0039] Reference now Figure 7, a more detailed icon of a process power control module 790 is shown, according to one embodiment. As described above, the process power control module 790 may include functional blocks to control an impedance matching network and one or more power supplies. As described above, knowing the actual frequency of the power supply is beneficial to process control. Therefore, embodiments disclosed herein include a process power control module 790 configured to implement a frequency detection process.

[0040] In one embodiment, the process power control module 790 may include a dual analog to digital (A / D) converter 741. The dual A / D converter 741 may receive a first input from a voltage sensor and a second input from a current sensor such as a transmission line sensor 750. For example, an analog voltage signal and an analog current signal may be provided to the dual A / D converter 741. The analog voltage signal and the analog current signal may be picked up by a sensor, such as the sensor described in more detail above. For example, the sensor may include a current loop and a voltage loop. In one embodiment, the dual A / D converter 741 may have a sampling rate of about 250 mega samples per second (MSPS) or higher. However, it should be understood that in other embodiments, lower sampling rates are possible.

[0041] In one embodiment, the converted digital signal may be processed by a digital downconverter (DDC) 742. The DDC may receive an input signal and apply a low pass filter to obtain a desired signal. Figure 3 , the first image on the left shows the input digital signal. It can be seen that the desired signal 314 (frequency f) can be surrounded by other signals of varying strengths. A low pass filter function may produce the image on the right. The image on the right shows that the desired signal 315 (frequency f) has been frequency shifted and passed through the DDC, while other signals are significantly attenuated. This provides a better signal-to-noise ratio in a multi-frequency impairment system.

[0042] In one embodiment, the output of the digital conversion may be provided in Cartesian coordinates. In addition, the output may be divided into two branches. The first branch may be passed directly to the transmission line scaling matrix 764, while the second branch may be passed through the digital phase-locked loop dPLL766. The first branch may remain in Cartesian coordinates and propagate signals at a first rate R. The second branch may start in Cartesian coordinates and propagate signals at a second rate nR. In one embodiment, the second rate nR may be greater than the first rate R. For example, the second rate nR may be four or more times greater than the first rate R.

[0043] In one embodiment, the second branch provides Cartesian coordinates to the polar phase converter block. The frequency can then be fed to the scaling matrix 764 and / or fed back to the DDC 742 to provide feedback to the digital down-conversion process to improve the measurement accuracy of the system.

[0044] exist Figure 7 In the description of , a single iteration of the frequency detector is described for simplicity. However, it should be understood that additional frequency detectors may be used in some embodiments. For example, in the case of two or more power supplies, each power supply may have a dedicated frequency detector. Figure 7 A more comprehensive explanation of additional frequency detectors is provided in the further explanation of .

[0045] Reference now Figure 4 , a process 480 for detecting the frequency of a signal from a power supply is described according to an embodiment. In an embodiment, frequency detection can be used as part of a system control architecture to provide efficient power delivery from a power supply to a load (e.g., a plasma load). In an embodiment, process 480 can be used by a power delivery architecture, such as the architecture described in more detail above, although similar processes 480 can also be used for other power delivery architectures.

[0046] In one embodiment, process 480 may start with operation 481, which includes picking up an analog voltage signal and an analog current signal with a transmission line sensor. In one embodiment, the analog voltage signal and the analog current signal may be detected with a sensor including a voltage loop and a current loop, as described in more detail above. In one embodiment, a single sensor may be located before or after the impedance matching network. In other embodiments, multiple sensors may be used (e.g., before and / or after the impedance matching network).

[0047] In one embodiment, process 480 may continue with operation 482, which includes digitizing the analog voltage signal and the analog current signal into a digital voltage signal and a digital current signal. For example, the digitization process may be implemented by an A / D converter. In some embodiments, a dual A / D converter may be used to digitize the two signals. In a specific embodiment, the AD converter may have a sampling rate of about 250MSPS or higher.

[0048] In one embodiment, process 480 may continue with operation 483, which includes down-converting the digital signal to provide a first signal having a first rate and a second signal having a second rate. In one embodiment, the first rate (i.e., the first signal rate) is less than the second rate (i.e., the second signal rate). In a specific embodiment, the second rate may be about four times the first signal rate. In other embodiments, the second rate may be approximately any integer multiple of the first signal rate. Down-conversion may be implemented using a DDC, such as DDC 342 described in more detail above.

[0049] In one embodiment, process 480 may continue with operation 484, which includes extracting the phase V(θ) from the second signal. V ) and phase I(θ I ). For example, the second signal may be fed to a frequency detector, such as the frequency detector described in more detail above. In such an embodiment, the desired signal may be represented in Cartesian form and converted to polar form to derive the time-varying phasor.

[0050] In one embodiment, process 480 may continue with operation 485, which includes multiplying the derivative of the phase by 2π to convert the rotational phase units to revolutions. The multiplication operation may be implemented by a functional block configured to perform frequency conversion.

[0051] In one embodiment, the detected frequency of the desired signal may be fed forward to the scaling matrix. The first signal may also be fed to the scaling matrix. In other embodiments, the detected frequency may be optionally routed back to the DDC as a feedback input to improve the accuracy of the frequency detection.

[0052] Thus, the embodiments described herein allow real-time process control and monitoring using knowledge of process power frequency. The methods of detection and retrieval described herein allow high accuracy and optimal control with minimal group delay. Furthermore, the schemes described herein are autonomous and do not require messaging or information transfer from other systems or subsystems.

[0053] Reference now Figure 5 , according to one embodiment, a schematic diagram of a processing system for identifying a signal frequency is shown. In one embodiment, FIG. A 1 , A 2 Provides input signal and interference icons. Frequencyω c is the frequency of the desired signal, while the frequencies of other signals cause interference, which impairs the performance of the controller and needs to be adequately filtered.

[0054] In one embodiment, a pair of transmission line sensors (TL sensor port 1 and TL sensor port 2) provide signals to a processing system. The signal from TL sensor port 1 is and the signal from TL sensor port 2 is The signal is routed to the dual A / D converter 561 A and 561 B . Dual A / D converter 561 A and 561 B is part of the digital down-conversion block. Additionally, the signal can be routed to the dual A / D converter 561 C and 561 D , both of which are part of a frequency digital phase lock loop (dPLL) block.

[0055] In one embodiment, the dual A / D converter 561 A and 561 B Each of the digital down converters (DDC) 562 1 Provides the imaginary part of a signal (Q) and the real part of a signal (I). DDC 562 1 May have a sampling rate of R. DDC 562 1 The imaginary Q signal and the real I signal can be combined into a composite signal. For example, the first composite signal can be The second composite signal may take the form of In one embodiment, the scaling factor (e.g., K 21 , K 11 , K 12 and K 22 ) can then be multiplied with the composite signal at multiplier 563. The result of the multiplication can then be fed to a transmission line scaling module 564. The transmission line scaling module 564 is a linear combination that receives two composite signals and outputs a set of four outputs. For example, the four outputs may include voltages V L , forward power P F , reflected power P R and current I L .

[0056] In one embodiment, the frequency dPLL block receives the frequency from the dual A / D converter 561 C and 561 D Start. With dual A / D converter 561 A and 561 B Similar, dual A / D converter 561 C and 561 D The real (I) signal and the imaginary (Q) signal are provided. The I and Q signals can then be processed by the DDC 562 2 Processing. DDC 562 2 Can be used with DDC 5621 For example, in some embodiments, the sampling rate may be 2 -1 R. DDC output signals, the signals are combined into a composite signal. The composite signal can take a 11 e j (ωn2^(-k)RTs) and a 22 e j(ωn2^(-k)RTs) In one embodiment, the composite signal may then be converted to polar coordinates using a Cartesian to polar converter 565. The output polar coordinate signal may take the form of θ 1 (n2 -k RTs) and θ 2 (n2 - k The polar coordinate signal may then be processed by a frequency dPLL module 566. The frequency dPLL module 566 may output a frequency ω.

[0057] In one embodiment, the output of the frequency dPLL module 566 may be fed into a direct digital synthesis (DDS) block 567. In one embodiment, the DDS block 567 outputs the conjugate correction value e j(ωnTs) or e -j(ωnTs) , both of which are fed back to the dual A / D converter 561. In the bottom dPLL block, the correction value can be a conjugate pair. The use of a conjugate pair prevents the dPLL from incorrectly locking to an in-band frequency.

[0058] Reference now Figure 6 According to one embodiment, a schematic diagram of a signal processing module when there is no interference is shown. 1 , A 2 As shown, the only frequency is at ω C The TL sensor port pair can then feed into the dual A / D converter 661 A and 661 B . Dual A / D converter 661 A and 661 B The real I and imaginary Q parts of the signal can be output separately and fed to the DDC 662 1 and 662 2 DDC 662 can combine the real and imaginary components of the signal into a signal of the form and composite signal.

[0059] In one embodiment, the composite signal may be converted to polar coordinate form via Cartesian to polar conversion module 665. The converted signal may have the form θ 1 (nRTs) and θ 2(nRTs). The signal in polar coordinate form can then be used to extract the frequency value ω 1 and 2 The frequency value can then be fed into the DDS 667 to provide an output correction value e j(ωnTs) , the output correction value is provided to the dual A / D converter 661.

[0060] In one embodiment, the composite signal may also be passed through a filter 668. The filter 668 may be a finite impulse response (FIR) filter. In a particular embodiment, the filter 668 may be an equalized FIR filter. The output of the filter 668 may be fed to a transmission line scaling module 664. The transmission line scaling module 664 includes a linear combination that receives two composite signals and outputs a set of four outputs. For example, the four outputs may include a load voltage V L , forward power P F , reflected power P R and load current I L In addition, the scaling matrix can generate the input voltage V from the raw DDC complex number. i , incident current I i , reflected voltage V r And the reflected current I r direct delivery.

[0061] Reference now Figure 7 , according to one embodiment, shows a schematic diagram of a signal processing architecture. In one embodiment, the signal processing architecture may include one or more transmission line sensors 750. For example, Figure 7 Three transmission line sensors are shown. In one embodiment, each transmission line sensor may be coupled to a dual A / D converter 741. The dual A / D converter 741 may be coupled to a system on chip 790. In particular, the dual A / D converter is coupled to a programmable logic 794 on the system on chip 790. In one embodiment, the programmable logic 794 may include a thread for each transmission line sensor 750. In one embodiment, each thread may include a DDC 742, a transmission line scaling module 764, and a frequency dPLL 766. In each thread, the DDC 742, the transmission line scaling module 764, and the frequency dPLL 766 may be communicatively coupled to each other, similar to the embodiments described in more detail above.

[0062] In some implementations, the frequency dPLL 766 may be shared between threads. For example, the frequency dPLL 766 of the second transmission line sensor 750 may be shared by the third transmission line sensor 750. That is, the single frequency dPLL 766 may be coupled to a pair of DDCs 742 and a pair of transmission line scaling modules 764.

[0063] In one embodiment, the transmission line scaling module 764 may be communicatively connected to a real-time processor 791. The real-time processor 791 may be communicatively coupled to a memory (eg, DRAM 793) and a message passing controller 792.

[0064] Reference Figure 8 , a block diagram of an exemplary computer system 800 of a processing tool is illustrated, according to one embodiment. In one embodiment, the computer system 800 is coupled to the processing tool and controls the processing in the processing tool. The computer system 800 can be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The computer system 800 can operate as a server or client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 800 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while only a single machine is illustrated with respect to computer system 800, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

[0065] The computer system 800 may include a computer program product or software 822 having a non-transitory machine-readable medium storing instructions that can be used to program the computer system 800 (or other electronic device) to perform a process according to an embodiment. Machine-readable media include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) media include machine (e.g., computer) readable storage media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), machine (e.g., computer) readable transmission media (electrical, optical, acoustic or other forms of propagated signals (e.g., infrared signals, digital signals, etc.), etc.

[0066] In one embodiment, the computer system 800 includes a system processor 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and an auxiliary memory 818 (e.g., a data storage device), which communicate with each other via a bus 830.

[0067] The system processor 802 represents one or more general processing devices, such as a microsystem processor, a central processing unit, etc. More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor that implements other instruction sets, or a system processor that implements a combination of instruction sets. The system processor 802 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal system processor (DSP), a network system processor, etc. The system processor 802 is configured to execute processing logic 826 for performing the operations described herein.

[0068] The computer system 800 may further include a system network interface device 808 for communicating with other devices or machines. The computer system 800 may further include a video display unit 810 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), and a signal generating device 816 (e.g., a speaker).

[0069] The secondary memory 818 may include a machine-accessible storage medium 832 (or more specifically, a computer-readable storage medium) having stored thereon one or more sets of instructions (e.g., software 822) that implement any one or more of the methodologies or functions described herein. The software 822 may also reside, in whole or in part, within the main memory 804 and / or the system processor 802 during execution by the computer system 800, the main memory 804 and the system processor 802 also constituting machine-readable storage media. The software 822 may further be sent or received over the network 820 via the system network interface device 808. In one embodiment, the network interface device 808 may operate using radio frequency coupling, optical coupling, acoustic coupling, or inductive coupling.

[0070] Although in the exemplary embodiment, the machine-accessible storage medium 832 is shown as a single medium, the term "machine-readable storage medium" shall include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" shall also be understood to include any medium that is capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more methods. Therefore, the term "machine-readable storage medium" shall be understood to include, but is not limited to, solid-state memories and optical and magnetic media.

[0071] In the foregoing description, specific exemplary embodiments have been described. It will be apparent that various modifications may be made thereto without departing from the scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A processing tool comprising: Transmission line sensors; Analog-to-digital (A / D) converter; Digital down converter (DDC); Frequency digital phase-locked loop (dPLL); and Transmission line scaling module.

2. The processing tool of claim 1, wherein the A / D converter is configured to receive an analog signal from the transmission line sensor and transmit a digital signal to the DDC.

3. The processing tool of claim 2, wherein the frequency dPLL, the transmission line scaling module, and the DDC are communicatively coupled to each other.

4. The processing tool of claim 1, wherein the transmission line sensor comprises a voltage sensor and a current sensor.

5. The processing tool of claim 4, wherein the A / D converter is a dual A / D converter.

6. The processing tool of claim 1, further comprising: a second transmission line sensor; a second analog-to-digital converter; Second DDC; a second transmission line scaling module; and The second frequency dPLL.

7. The processing tool of claim 6, further comprising: a third transmission line sensor; a third analog-to-digital converter; 3rd DDC; and The third transmission line scaling module.

8. The processing tool of claim 7, wherein the second frequency dPLL is communicatively coupled to the third DDC and the third transmission line scaling module.

9. The processing tool of claim 1, wherein the DDC is configured to process a real component of the signal from the transmission line sensor and an imaginary component of the signal from the transmission line sensor, and wherein the DDC is configured to combine the real component and the imaginary component into a composite signal.

10. The processing tool of claim 9, wherein the transmission line scaling module comprises a plurality of scaling factors, wherein each of the plurality of scaling factors is configured to be multiplied by the composite signal.

11. The processing tool of claim 1, wherein the dPLL feeds frequency back to the DDC via a direct digital synthesis (DDS) module.

12. The processing tool of claim 1, wherein the transmission line scaling module outputs voltage, forward power, reflected power, and current.

13. The processing tool of claim 1, wherein the dPLL comprises a feedback loop, wherein the feedback loop comprises multiplying a signal by a conjugate pair.

14. A processing tool comprising: Transmission line sensors; Analog-to-digital (A / D) converter; Digital down converter (DDC); and Transmission line scaling module.

15. The processing tool of claim 14, wherein a filter is provided before the transmission line scaling module, wherein the complex signal passes through the filter.

16. The processing tool of claim 15, wherein the filter is a finite impulse response (FIR) filter.

17. The processing tool of claim 14, wherein the transmission line scaling module outputs voltage, forward power, reflected power, and current.

18. A semiconductor processing tool comprising: Chamber; a plasma source coupled to the chamber; and A signal processing module for determining the frequency of the plasma generated by the plasma source, comprising: Transmission line sensors; Analog-to-digital (A / D) converter; Digital down converter (DDC); frequency digital phase-locked loop (dPLL); and Transmission line scaling module.

19. The semiconductor processing tool of claim 18, wherein the A / D converter is configured to receive an analog signal from the transmission line sensor and transmit a digital signal to the DDC.

20. The processing tool of claim 18, wherein the frequency dPLL, the transmission line scaling module, and the DDC are communicatively coupled to each other.

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