Semiconductor device with edge sealing piece and manufacturing method of semiconductor device without generating metal hard mask arc discharge

Abstract

A conductive hard mask layer may be patterned with peripheral discrete openings. An anisotropic etch process may be performed to form peripheral discrete through-hole cavities, which are then expanded to form a continuous trench groove. An edge seal structure may be formed in the continuous trench. Alternatively, a conductive bridge structure may be formed prior to forming the patterned conductive hard mask layer, and a trench may be formed around the periphery of the semiconductor die while the conductive bridge structure provides an electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer may be electrically connected to the semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the trench grooves.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Patent Application No. 17 / 932,887 filed on September 16, 2022 and U.S. Non-Provisional Patent Application No. 17 / 932,907 filed on September 16, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and more particularly to methods of preventing metal hard mask arcing during fabrication of edge seals of semiconductor devices, and to semiconductor devices formed using such methods. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a method for making a semiconductor structure is provided, the method comprising: forming a semiconductor die including a semiconductor device and a dielectric material portion over a semiconductor substrate, wherein the dielectric material portion laterally surrounds the semiconductor device; forming a conductive hard mask layer over the semiconductor device and the dielectric material portion; forming a set of peripheral discrete openings through the conductive hard mask layer along the periphery of the dielectric material portion; forming a set of peripheral discrete through-hole cavities through the dielectric material portion down to a top surface of the semiconductor substrate by performing an anisotropic etching process, the anisotropic etching process etching material of the dielectric material portion below the set of peripheral discrete openings; forming a continuous moat trench laterally surrounding an inner region of the dielectric material portion by isotropically extending the set of peripheral discrete through-hole cavities; and forming a conductive edge seal structure by filling the continuous moat trench with at least one conductive material.

[0006] According to another aspect of the present disclosure, a semiconductor die includes: a semiconductor device located on a semiconductor substrate; an inner dielectric material portion that laterally surrounds the semiconductor device; a conductive edge sealing structure that laterally surrounds the inner dielectric material portion, extends vertically from at least the semiconductor substrate to a horizontal plane including the topmost surface of the inner dielectric material portion, and has a laterally undulating inner sidewall and a laterally undulating outer sidewall; and an outer dielectric material portion that laterally surrounds the conductive edge sealing structure.

[0007] According to another aspect of the present disclosure, a method for making a semiconductor structure includes: forming a semiconductor tube core including a semiconductor device and a dielectric material portion above a semiconductor substrate, wherein the dielectric material portion laterally surrounds the semiconductor device; forming a contact level dielectric layer above the semiconductor device and the dielectric material portion; forming a conductive bridge structure through the contact level dielectric layer or below the contact level dielectric layer in a peripheral area of ​​the semiconductor tube core; forming a conductive hard mask layer above the contact level dielectric layer and the conductive bridge structure; forming an edge sealing opening through the conductive hard mask layer along the periphery of the dielectric material portion, wherein an inner portion of the conductive hard mask layer located in an area surrounded by an inner periphery of the edge sealing opening is electrically connected to the semiconductor substrate through the conductive bridge structure and through a vertical extension of the conductive hard mask layer; forming a continuous moat trench by anisotropically etching a region of the dielectric material portion located below the edge sealing opening; and forming a conductive edge sealing structure by filling the continuous moat trench with at least one conductive material.

[0008] According to another aspect of the present disclosure, a semiconductor die includes: a semiconductor device located on a semiconductor substrate; an internal dielectric material portion, which laterally surrounds the semiconductor device; a contact-level dielectric layer, which overlies the semiconductor device and the internal dielectric material portion; a conductive bridge structure, which has at least one top surface located within a horizontal plane including a top surface of the contact-level dielectric layer; a conductive edge sealing structure, which laterally surrounds the internal dielectric material portion, extends vertically from the semiconductor substrate to a horizontal plane including the top surface of the contact-level dielectric layer, and extends above at least one surface of the conductive bridge structure and contacts the at least one surface; and an external dielectric material portion, which laterally surrounds the conductive edge sealing structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming at least one peripheral device and a semiconductor material layer according to an embodiment of the present disclosure.

[0010] Figure 2is a schematic vertical cross-sectional view of a first exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers according to an embodiment of the present disclosure.

[0011] Figure 3A is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped terrace and a dielectric material portion according to an embodiment of the present disclosure.

[0012] Figure 3B Yes Figure 3A Top view of a wafer with a two-dimensional array of dies at a processing step.

[0013] Figure 3C As Figure 3B A top view of a cell area of ​​a repeating unit in a wafer.

[0014] Figure 4A is a schematic vertical cross-sectional view of a first exemplary structure after forming a storage opening and a support opening according to an embodiment of the present disclosure.

[0015] Figure 4B yes Figure 4A A top view of an exemplary structure of FIG. The vertical plane A-A' is Figure 4A The plane of the section.

[0016] Figure 4C yes Figure 4A and Figure 4B Top view of the cell area at the processing step.

[0017] FIG. 5A to FIG. 5H are sequential schematic vertical cross-sectional views of a memory opening within a first exemplary structure during formation of a memory stack structure, an optional dielectric core, and a drain region therein according to an embodiment of the present disclosure.

[0018] Figure 6 is a schematic vertical cross-sectional view of a first exemplary structure after forming a memory stack structure and a support pillar structure according to an embodiment of the present disclosure.

[0019] Fig. 7A is a schematic vertical cross-sectional view of a first exemplary structure after forming backside trenches according to an embodiment of the present disclosure.

[0020] Figure 7B yes Fig. 7A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig. 7A A schematic vertical cross-sectional view of a plane.

[0021] Figure 7C It is along Figure 7B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0022] Figure 8 is a schematic vertical cross-sectional view of a first exemplary structure after forming a backside recess according to an embodiment of the present disclosure.

[0023] 9A to 9D are sequential vertical cross-sectional views of regions of a first exemplary structure during formation of a conductive layer according to an embodiment of the present disclosure.

[0024] Fig. 10A is a schematic vertical cross-sectional view of the first exemplary structure after removal of deposited conductive material from within the backside trenches according to an embodiment of the present disclosure.

[0025] Fig. 10B yes Fig. 10A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig. 10A A schematic vertical cross-sectional view of a plane.

[0026] Fig. 10C It is along Fig. 10B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0027] Fig. 10D is included in FIG. 10A to FIG. 10C 1. A top view of a cell area of ​​a wafer of a first exemplary structure at a processing step of FIG.

[0028] Fig.11A is a schematic vertical cross-sectional view of the first exemplary structure after forming a backside trench fill structure and a contact level dielectric layer and after removing a portion of material above the substrate from the kerf area according to an embodiment of the present disclosure.

[0029] Fig. 11B yes Fig.11A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig.11A A schematic vertical cross-sectional view of a plane.

[0030] Fig. 11C is included in Fig.11A and Fig. 11B FIG. 1 is a partial perspective top view of a cell area of ​​a wafer of a first exemplary structure at a processing step of FIG.

[0031] Fig. 12A is a vertical cross-sectional view of a cell region of a wafer including a first exemplary structure after forming a patterned conductive hard mask layer and forming various via cavities including perimeter discrete via cavities according to an embodiment of the present disclosure. The various insets provide magnified views within the die.

[0032] Fig. 12B yes Fig. 12A A top view of a cell area of ​​a wafer.

[0033] Fig. 12C yes Fig. 12A and Fig. 12B A vertical cross-sectional view of a region of a first exemplary structure within a die is shown in FIG.

[0034] Fig.13A is a vertical cross-sectional view of a cell region of a wafer including the first exemplary structure after forming continuous moat trenches according to an embodiment of the present disclosure.

[0035] Fig. 13B yes Fig.13A A top view of a cell area of ​​a wafer.

[0036] Fig. 13C It is along Fig.13A A horizontal cross-sectional view of a unit area of ​​a wafer taken along a horizontal plane CC'.

[0037] Fig.13D yes FIG. 13A to FIG. 13C A vertical cross-sectional view of a region of a first exemplary structure within a die is shown in FIG.

[0038] Fig.14A is a vertical cross-sectional view of a cell region of a wafer including a first exemplary structure after forming a contact via structure and a metal edge seal structure according to an embodiment of the present disclosure.

[0039] Fig. 14B yes Fig.14A A top view of a cell area of ​​a wafer.

[0040] Fig. 14C yes Fig.14A and Fig. 14B A vertical cross-sectional view of a region of a first exemplary structure within a die is shown in FIG.

[0041] Fig.14D yes Fig. 14C A top view of a region of a first exemplary structure.

[0042] Fig.14E It is along Fig.14D A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0043] Fig.15A is a vertical cross-sectional view of a cell region of a wafer including a second exemplary structure after forming an edge region recess cavity and a drain contact via cavity according to an embodiment of the present disclosure.

[0044] Fig. 15B yes Fig.15A A top view of a cell area of ​​a wafer.

[0045] Fig. 15C yes Fig.15A and Fig. 15B 00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in .

[0046] Fig.16A is a vertical cross-sectional view of a cell region of a wafer including a second exemplary structure after forming a conductive bridge structure and a drain contact via structure according to an embodiment of the present disclosure.

[0047] Fig. 16B yes Fig.16A A top view of a cell area of ​​a wafer.

[0048] Fig. 16C yes Fig.16A and Fig. 16B 00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in .

[0049] Fig.17A is a vertical cross-sectional view of a cell region of a wafer including a second exemplary structure after forming a patterned conductive hard mask layer and various via cavities and continuous moat trenches according to an embodiment of the present disclosure.

[0050] Fig. 17B yes Fig.16A A top view of a cell area of ​​a wafer.

[0051] Fig. 17C yes Fig.17A and Fig. 17B 00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in .

[0052] Fig.17D It is along Fig. 17B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0053] Fig.17E It is along Fig. 17B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0054] Fig.18A is a vertical cross-sectional view of a cell region of a wafer including a second exemplary structure after forming a conductive edge seal structure according to an embodiment of the present disclosure.

[0055] Fig.18B yes Fig.18A A top view of a cell area of ​​a wafer.

[0056] Fig.18C yes Fig.18A and Fig.18B00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in .

[0057] Fig.18D It is along Fig.18B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0058] Fig.18E It is along Fig.18B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0059] Fig.19A is a vertical cross-sectional view of the third exemplary structure after forming backside trenches, pillar cavities, and a conductive layer according to an embodiment of the present disclosure.

[0060] Fig.19B Yes Fig.19A FIG. 1 is a top view of a unit area of ​​a wafer of a third exemplary structure.

[0061] Fig.19C It is along Fig.19B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0062] Fig.19D It is along Fig.19B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0063] Fig. 20A is a vertical cross-sectional view of the third exemplary structure after forming a backside trench fill structure and a metal pillar structure according to an embodiment of the present disclosure.

[0064] Fig. 20B Yes Fig. 20A FIG. 1 is a top view of a unit area of ​​a wafer of a third exemplary structure.

[0065] Fig. 20C It is along Fig. 20B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0066] Fig.20D It is along Fig. 20B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0067] Fig.21A is a vertical cross-sectional view of a cell region of a wafer including a third exemplary structure after forming a contact level dielectric layer, removing a portion of material above the substrate from the kerf area, forming a patterned conductive hard mask layer, and forming a drain contact via cavity (including a contact level via cavity) according to an embodiment of the present disclosure. The various insets provide enlarged views within the die.

[0068] Fig. 21B yes Fig.21A A top view of a cell area of ​​a wafer.

[0069] Fig. 21C yes Fig.21A and Fig. 21B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG.

[0070] Fig.21D It is along Fig. 21B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0071] Fig.21E is along Fig. 21B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'.

[0072] Fig.22A is a vertical cross-sectional view of a cell region of a wafer including a third exemplary structure after forming a conductive hard mask layer by depositing at least one conductive material in a drain contact via cavity and a contact level via cavity according to an embodiment of the present disclosure. The various insets provide magnified views within the die.

[0073] Fig. 22B yes Fig.22A A top view of a cell area of ​​a wafer.

[0074] Fig. 22C yes Fig.22A and Fig. 22B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG.

[0075] Fig.22D It is along Fig. 22B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0076] Fig.22E is along Fig. 22B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'.

[0077] Fig.23A is a vertical cross-sectional view of a cell region of a wafer including a third exemplary structure after patterning a conductive hard mask layer and forming various via cavities and moat trenches according to an embodiment of the present disclosure. The various insets provide magnified views within the die.

[0078] Fig. 23B yes Fig.23A A top view of a cell area of ​​a wafer.

[0079] Fig.23C yes Fig.23A and Fig. 23B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG.

[0080] Fig.23D It is along Fig. 23B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0081] Fig.23E is along Fig. 23B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'.

[0082] Fig.24A is a vertical cross-sectional view of a cell region of a wafer including a third exemplary structure after forming various metal via structures and conductive edge seal structures according to an embodiment of the present disclosure. The various insets provide magnified views within the die.

[0083] Fig. 24B yes Fig.24A A top view of a cell area of ​​a wafer.

[0084] Fig.24C yes Fig.24A and Fig. 24B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG.

[0085] Fig.24D It is along Fig. 24B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0086] Fig.24E is along Fig. 24B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'. DETAILED DESCRIPTION

[0087] As discussed above, the present disclosure is directed to methods of preventing metal hard mask arcing during fabrication of edge seals of semiconductor devices, and to semiconductor devices formed using such methods, and various aspects of the disclosure are described below.

[0088] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0089] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0090] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0091] Generally speaking, a semiconductor die or a semiconductor package may include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four dies). A die is the smallest unit that can independently execute a command or report a status. Each die contains one or more planes (usually one or two planes). Although there are some limitations, the same concurrent operations can occur on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased by a single erase operation. Each block contains multiple pages, which are the smallest units that can be programmed, that is, the smallest units on which a read operation can be performed.

[0092] refer to Figure 1, shows a first exemplary structure according to an embodiment of the present disclosure, which can be used, for example, to manufacture a device structure including a vertical NAND memory device. The exemplary structure includes a substrate (9, 10) which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer 9 (such as a silicon wafer) and an optional semiconductor material layer 10 (such as a doped well in a silicon wafer or an epitaxial silicon layer grown on a silicon wafer). The substrate can have a main surface 7, which can be, for example, the topmost surface of the substrate semiconductor layer 9. In one embodiment, the main surface 7 can be a single crystal semiconductor surface, such as a single crystal semiconductor surface.

[0093] As used herein, "semiconductor material" refers to a semiconductor material having a -6 S / cm to 1.0×10 5 S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm, and can produce materials with electrical conductivity in the range of 1.0 S / cm to 1.0×10 5 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -6 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -6 S / cm to 1.0×10 5S / cm) in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "conductive material" refers to a conductive material that includes at least one conductive element therein. All conductivity measurements are performed under standard conditions.

[0094] At least one peripheral device 700 for peripheral circuits may be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device may include, for example, a field effect transistor. For example, at least one shallow trench isolation structure 720 may be formed by etching a portion of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer may be formed over the substrate semiconductor layer 9, and may be subsequently patterned to form at least one gate structure (750, 752, 754, 758), each of which may include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrode (752, 754) may include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 may be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric liner. An active region 730 may be formed in the upper portion of the substrate semiconductor layer 9, for example, by introducing electrical dopants using the at least one gate structure (750, 752, 754, 758) as a masking structure. Additional masks may be employed as needed. The active region 730 may include source and drain regions of a field effect transistor.

[0095] A first dielectric liner 761 and a second dielectric liner 762 may be optionally formed. Each of the first dielectric liner and the second dielectric liner (761, 762) may include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide and non-stoichiometric silicon oxide having more or less than two oxygen atoms for each silicon atom. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 761 may be a silicon oxide layer, and the second dielectric liner 762 may be a silicon nitride layer. At least one semiconductor device of the peripheral circuit may include a driver circuit of a subsequently formed memory device, which may include at least one NAND device.

[0096] A dielectric material such as silicon oxide may be deposited over the at least one semiconductor device and may be subsequently planarized to form a planarized dielectric layer 770. In one embodiment, the planarized top surface of the planarized dielectric layer 770 may be coplanar with the topmost surface of the dielectric liner (761, 762). Subsequently, the planarized dielectric layer 770 and the dielectric liner (761, 762) may be removed from a certain area to physically expose the top surface of the substrate semiconductor layer 9. As used herein, a surface is "physically exposed" if the surface is in physical contact with a vacuum or a gaseous material (such as air).

[0097] The optional semiconductor material layer 10 (if present) can be formed on the top surface of the substrate semiconductor layer 9 by depositing a single crystalline semiconductor material (e.g., by selective epitaxy) before, during, or after forming the at least one peripheral device 700. The single crystalline semiconductor material of the semiconductor material layer 10 can be epitaxially aligned with the single crystalline structure of the substrate semiconductor layer 9. The portion of the deposited semiconductor material positioned above the top surface of the planarization dielectric layer 770 can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer 10 can have a top surface that is coplanar with the top surface of the planarization dielectric layer 770.

[0098] The region (i.e., area) of at least one peripheral device 700 is referred to herein as the peripheral device region 200. The region where the memory array is subsequently formed is referred to herein as the memory array region 100. A contact region 300 for subsequently forming a stepped terrace of a conductive layer may be provided between the memory array region 100 and the peripheral device region 200. In an alternative embodiment, the peripheral device region 200 containing at least one semiconductor device 700 for peripheral circuits may be located under the memory array region 100 in an under-array CMOS configuration. In another alternative embodiment, the peripheral device region 200 may be located on a separate substrate that is subsequently bonded to the memory array region 100.

[0099] refer to Figure 2 , a stack of alternating multiple first material layers (which may be insulating layers 32) and second material layers (which may be sacrificial material layers 42) is formed above the top surface of the substrate (9, 10). The alternating multiple first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instances of the first element and the second element may form a unit that is periodically repeated within the alternating multiple elements.

[0100] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer 42. In this case, the stack may include a plurality of insulating layers 32 and sacrificial material layers 42 alternating, and the insulating layers 32 and sacrificial material layers 42 are stacked alternately in the process of forming the insulating layers 32 and the sacrificial material layers 42. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0101] Insulating materials that can be used for insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials, which are generally referred to as high dielectric constant (high-k) dielectric oxides. In one embodiment, the first material of insulating layer 32 may be silicon oxide.

[0102] The second material of the sacrificial material layer 42 is a sacrificial material that can be selectively removed for the first material of the insulating layer 32. As used herein, if the removal process removes the first material at a rate at least twice the removal rate of the second material, the removal of the first material is "selective" for the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. The sacrificial material layer 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer including silicon nitride, and may be substantially composed only of silicon nitride.

[0103] In one embodiment, insulating layer 32 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0104] The thickness of the insulating layer 32 and the sacrificial material layer 42 can be in the range of 20nm to 50nm, but lesser and greater thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the insulating layer 32 and sacrificial material layer 42 pair can be in the range of 2 to 1,024, typically 8 to 256, but more repetitions can also be used. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially constant within each respective sacrificial material layer 42.

[0105] Although an embodiment is described in which the spacer material layer is a sacrificial material layer 42 that is subsequently replaced by a conductive layer, alternative embodiments are expressly contemplated herein in which the sacrificial material layer is formed as a conductive layer. In this case, the step of replacing the spacer material layer with a conductive layer may be omitted.

[0106] Optionally, an insulating capping layer 70 may be formed over the alternating stack (32, 42). The insulating capping layer 70 includes a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating capping layer 70 may include a dielectric material that may be used for the insulating layer 32 as described above. The insulating capping layer 70 may have a greater thickness than each insulating layer 32. The insulating capping layer 70 may be deposited by, for example, chemical vapor deposition. In one embodiment, the insulating capping layer 70 may be a silicon oxide layer.

[0107] refer to FIG. 3A to FIG. 3C A stepped surface is formed at the peripheral region of the alternating stack (32, 42), which is referred to herein as a terrace region. Figure 3A is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped terrace and dielectric material portion 65 according to an embodiment of the present disclosure.

[0108] Figure 3B Yes Figure 3A FIG. 1 is a top view of a wafer 1000 having a two-dimensional array of semiconductor dies 900 at a processing step. Figure 3A The portion shown in the first exemplary structure may be located at Figure 3B 1. A portion of a semiconductor die 900 within a unit area UA within the two-dimensional array of semiconductor die 900 shown in FIG. Figure 3C is Figure 3B FIG. 1 is a top view of a unit area UA repeated in the x-direction and the y-direction on the surface of the wafer 1000. Each unit area UA includes a corresponding semiconductor die 900 and a cutout area 902 laterally surrounding the corresponding semiconductor die 900. In one embodiment, the entire cutout area 902 may be covered by the dielectric material portion 65.

[0109] As used herein, "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface, and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and portions of the alternating stacks (32, 42) are removed from the volume by forming the stepped surfaces. A "stepped cavity" refers to a cavity having stepped surfaces.

[0110] The platform area is formed in a contact area 300 located between the memory array area 100 and the peripheral device area 200, which includes at least one semiconductor device for a peripheral circuit. The stepped cavity may have various stepped surfaces so that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more levels, and the second type of etching process laterally expanding the area to be vertically etched in a subsequent first type of etching process. As used herein, a "level" of a structure including a plurality of alternating levels is defined as the relative position of a pair of first material layers and second material layers within the structure.

[0111] Each sacrificial material layer 42 except the topmost sacrificial material layer 42 in the alternating stack (32, 42) extends laterally further than any overlying sacrificial material layer 42 in the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that extend continuously from a bottommost layer in the alternating stack (32, 42) to a topmost layer in the alternating stack (32, 42).

[0112] Each vertical step of the stepped surface may have a height of one or more pairs of insulating layers 32 and sacrificial material layers. In one embodiment, each vertical step may have a height of a single pair of insulating layers 32 and sacrificial material layers 42. In another embodiment, multiple "columns" of steps may be formed along the first horizontal direction hd1, so that each vertical step has a height of multiple pairs of insulating layers 32 and sacrificial material layers 42, and the number of columns may be at least the number of the multiple pairs. Each column of steps may be vertically offset from each other so that each of the sacrificial material layers 42 has a physically exposed top surface in the corresponding column of the step. In an illustrative example, two columns of steps are formed for each block of the memory stack structure to be subsequently formed, so that one column of steps provides a physically exposed top surface for odd-numbered sacrificial material layers 42 (such as counting from the bottom) and the other column of steps provides a physically exposed top surface for even-numbered sacrificial material layers (such as counting from the bottom). A configuration of three, four, or more columns of steps with a corresponding set of vertical offsets between the physically exposed surfaces of the sacrificial material layers 42 may also be adopted. Each sacrificial material layer 42 has a greater lateral extent than any covering sacrificial material layer 42 in at least one direction, such that each physically exposed surface of any sacrificial material layer 42 has no overhang. In one embodiment, the vertical steps within each column of steps may be arranged along a first horizontal direction hd1, and the columns of steps may be arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to the boundary between the memory array region 100 and the contact region 300.

[0113] A dielectric material portion 65 (i.e., an insulating filling material portion) can be formed in the stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the dielectric material portion 65. The dielectric material portion 65 includes a stepped bottom surface so that the lateral extent of the dielectric material portion 65 increases with the vertical distance from the semiconductor substrate (9, 10). Therefore, the horizontal surface segments and vertical surface segments of the bottom surface of the dielectric material portion have a backward stepped profile. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The dielectric material portion 65 is also referred to as a backward stepped dielectric material portion. If silicon oxide is used for the dielectric material portion 65 , the silicon oxide of the dielectric material portion 65 may or may not be doped with a dopant, such as B, P, and / or F.

[0114] Optionally, a drain selection level isolation structure 72 may be formed by the insulating cap layer 70 and a subset of the sacrificial material layer 42 positioned at the drain selection level. The drain selection level isolation structure 72 may be formed, for example, by forming a drain selection level isolation trench and filling the drain selection level isolation trench with a dielectric material such as silicon oxide. Excess portions of the dielectric material may be removed from above the top surface of the insulating cap layer 70.

[0115] refer to FIG. 4A to FIG. 4C A photolithographic material stack (not shown) including at least a photoresist layer may be formed over insulating capping layer 70 and dielectric material portion 65 and may be photolithographically patterned to form openings in the photolithographic material stack. Figure 4A is a schematic vertical cross-sectional view of a first exemplary structure after forming a storage opening 49 and a support opening 19 according to an embodiment of the present disclosure. Figure 4B yes Figure 4A A top view of an exemplary structure of FIG. The vertical plane A-A' is Figure 4A The plane of the section. Figure 4C yes Figure 4A and Figure 4B A top view of the unit area UA at the processing step.

[0116] The openings include a first set of openings formed above the memory array region 100 and a second set of openings formed above the contact region 300. The pattern in the photolithographic material stack can be transferred through the insulating cap layer 70 or the dielectric material portion 65 and through the alternating stack (32, 42) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. The portion of the alternating stack (32, 42) below the opening in the patterned photolithographic material stack is etched to form a memory opening 49 and a support opening 19. As used herein, "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, "support opening" refers to a structure in which a support structure (such as a support column structure) that mechanically supports other elements is subsequently formed. The memory opening 49 is formed through the insulating cap layer 70 and the entire alternating stack (32, 42) in the memory array region 100. The support opening 19 is formed through the dielectric material portion 65 and the portion of the alternating stack (32, 42) located below the stepped surface in the contact region 300.

[0117] The memory opening 49 extends through the entirety of the alternating stack (32, 42). The support opening 19 extends through a subset of the layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch the material through the alternating stack (32, 42) can be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0118] The memory openings 49 and the support openings 19 may extend from the top surface of the alternating stack (32, 42) to at least a horizontal plane including the topmost surface of the semiconductor material layer 10. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19, overetching of the semiconductor material layer 10 may be optionally performed. Overetching may be performed before, during, or after removing the photolithographic material stack. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the unrecessed top surface of the semiconductor material layer 10 by a recessed depth. The recessed depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger recessed depths may also be used. Overetching is optional and may be omitted. If overetching is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 may be coplanar with the topmost surface of the semiconductor material layer 10.

[0119] Each of the memory opening 49 and the support opening 19 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 may be formed in the memory array area 100. A two-dimensional array of support openings 19 may be formed in the contact area 300. The substrate semiconductor layer 9 and the semiconductor material layer 10 together constitute a substrate (9, 10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the memory opening 49 and the support opening 19 may extend to the top surface of the substrate semiconductor layer 9.

[0120] FIG. 5A to FIG. 5H shows the structural changes in the storage opening 49, which is Figure 4A and Figure 4B The same structural changes occur simultaneously in each of the other storage openings 49 and each support opening 19.

[0121] refer to Figure 5A , showing Figure 4A and Figure 4BMemory opening 49 in an exemplary device structure of . Memory opening 49 extends through insulating cap layer 70, alternating stack (32, 42), and optionally extends into an upper portion of semiconductor material layer 10. At this processing step, each support opening 19 can extend through dielectric material portion 65, a subset of layers in alternating stack (32, 42), and optionally through an upper portion of semiconductor material layer 10. The bottom surface of each memory opening can be recessed to a depth in the range of 0 nm to 30 nm relative to the top surface of semiconductor material layer 10, although greater recess depths can also be used. Optionally, sacrificial material layer 42 can be partially laterally recessed, for example by isotropic etching, to form a lateral recess (not shown).

[0122] refer to Figure 5B , an optional pedestal channel portion (e.g., epitaxial pedestal) 11 may be formed at the bottom portion of each memory opening 49 and each support opening 19, for example, by selective epitaxy. Each pedestal channel portion 11 includes a single crystalline semiconductor material epitaxially aligned with the single crystalline semiconductor material of the semiconductor material layer 10. In one embodiment, the pedestal channel portion 11 may be doped with an electrical dopant of the same conductivity type as the semiconductor material layer 10. In one embodiment, the top surface of each pedestal channel portion 11 may be formed above a horizontal plane including the top surface of the sacrificial material layer 42. In this case, at least one source select gate electrode may be subsequently formed by replacing each sacrificial material layer 42 located below the horizontal plane including the top surface of the pedestal channel portion 11 with a corresponding conductive material layer. The pedestal channel portion 11 may be a portion of a transistor channel extending between a source region that will be subsequently formed in the substrate (9, 10) and a drain region that will be subsequently formed in the upper portion of the memory opening 49. A memory cavity 49' exists in the unfilled portion of the memory opening 49 above the pedestal channel portion 11. In one embodiment, the base channel portion 11 may include single crystal silicon. In one embodiment, the base channel portion 11 may have a doping of a first conductivity type, which is the same conductivity type as the semiconductor material layer 10 that the base channel portion contacts. If the semiconductor material layer 10 is not present, the base channel portion 11 may be formed directly on the substrate semiconductor layer 9, which may have a doping of the first conductivity type.

[0123] refer to Figure 5C A stack of layers including an optional blocking dielectric layer 52 , a memory material layer 54 , a dielectric material liner 56 , and an optional sacrificial capping material layer 601 may be sequentially deposited in the memory opening 49 by respective conformal deposition processes.

[0124] The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is essentially composed of a dielectric metal oxide. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include multiple dielectric metal oxide layers having different material compositions. Alternatively or in addition, the blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. The thickness of the blocking dielectric layer 52 may be in the range of 3nm to 20nm, but smaller and larger thicknesses may also be used. Alternatively, the blocking dielectric layer 52 may be omitted, and the backside blocking dielectric layer may be formed after forming a backside recess on the surface of the memory film to be formed subsequently.

[0125] Subsequently, a memory material layer 54 may be formed. In general, the memory material layer may include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store a data bit in the form of the presence or absence of charge, ferroelectric polarization direction, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which may be silicon nitride, for example. Alternatively, the memory material layer 54 may include a continuous layer or patterned discrete portions of a conductive material, such as doped polysilicon or a conductive material, which is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed into lateral recesses into the sacrificial material layer 42. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer.

[0126] In another embodiment, the sacrificial material layer 42 may be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and an anisotropic etching process may be employed to form the memory material layer 54 into a plurality of vertically spaced memory material portions. Although the present disclosure is described using an embodiment in which the memory material layer 54 is a single continuous layer, embodiments in which the memory material layer 54 is replaced by a plurality of vertically spaced memory material portions (which may be charge trapping material portions or electrically isolated conductive material portions) are expressly contemplated herein. The memory material layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be employed.

[0127] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, their alloys and / or their combinations. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 can be in the range of 2nm to 20nm, but smaller and larger thicknesses can also be used.

[0128] The optional sacrificial covering material layer 601 includes a sacrificial material that can be subsequently selectively removed for the material of the dielectric material liner 56. In one embodiment, the sacrificial covering material layer 601 may include a semiconductor material such as amorphous silicon, or may include a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial covering material layer 601 may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial covering material layer 601 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. The memory cavity 49' is formed in the space of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 601).

[0129] refer to Figure 5D , the optional sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the blocking dielectric layer 52 overlying the insulating capping layer 70 are anisotropically etched in sequence using at least one anisotropic etching process. Portions of the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the blocking dielectric layer 52 located above the top surface of the insulating capping layer 70 may be removed by at least one anisotropic etching process. In addition, horizontal portions of the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the blocking dielectric layer 52 at the bottom of each memory cavity 49' may be removed to form openings in the remaining portions thereof. Each of the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the blocking dielectric layer 52 may be etched by a corresponding anisotropic etching process using a corresponding etching chemistry, which may be the same or different for the various material layers.

[0130] Each remaining portion of the sacrificial capping material layer 601 may have a tubular configuration. The memory material layer 54 may include a charge trapping material, a floating gate material, a ferroelectric material, a resistive memory material that can provide at least two different levels of resistivity (such as a phase change material), or any other memory material that can store information through a change of state. In one embodiment, each memory material layer 54 may include a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the memory material layer 54 may be a memory material layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0131] The surface of the base channel portion 11 (or the surface of the semiconductor material layer 10 in the case where the base channel portion 11 is not adopted) can be physically exposed below the opening through the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54 and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed, so that the recessed semiconductor surface below the memory cavity 49' is vertically offset from the topmost surface of the base channel portion 11 (or the semiconductor material layer 10 in the case where the base channel portion 11 is not adopted) by a recessed distance. The dielectric material liner 56 is located above the memory material layer 54. A set of blocking dielectric layers 52, memory material layers 54 and dielectric material liner 56 in the memory opening 49 constitutes a memory film 50, which includes a plurality of charge storage regions (including a portion of the memory material layer 54), and the plurality of charge storage regions are insulated from surrounding materials by the blocking dielectric layer 52 and the dielectric material liner 56. In one embodiment, the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the blocking dielectric layer 52 may have vertically coincident sidewalls. The sacrificial capping material layer 601 may then be removed selectively to the material of the dielectric material liner 56. In the case where the sacrificial capping material layer 601 comprises a semiconductor material, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) may be performed to remove the sacrificial capping material layer 601. Alternatively, if the sacrificial capping material layer 601 comprises a semiconductor material, it may be retained in the final device.

[0132] refer to Figure 5E, the semiconductor channel layer 60L can be directly deposited on the semiconductor surface of the base channel portion 11 or on the semiconductor material layer 10 (if the base channel portion 11 is omitted), and directly deposited on the dielectric material liner 56. The semiconductor channel layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L may have a first conductivity type of doping, which is the same as the conductivity type of the semiconductor material layer 10 and the base channel portion 11. The semiconductor channel layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The semiconductor channel layer 60L may partially fill the memory cavity 49 ′ in each memory opening, or may completely fill the cavity in each memory opening.

[0133] refer to Fig. 5F In the case where the memory cavity 49' in each memory opening is not completely filled with the semiconductor channel layer 60L, a dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarization deposition process such as spin coating.

[0134] refer to Figure 5G , horizontal portions of dielectric core layer 62L may be removed, for example, by a recess etching process, so that each remaining portion of dielectric core layer 62L is located within a corresponding memory opening 49 and has a corresponding top surface below a horizontal plane including a top surface of insulating cap layer 70. Each remaining portion of dielectric core layer 62L constitutes dielectric core 62.

[0135] refer to Figure 5H, a doped semiconductor material having a doping of a second conductivity type may be deposited in each recessed region above the dielectric core 62. The deposited semiconductor material may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the deposited semiconductor material may be in the range of 5.0×1018 / cm3 to 2.0×1021 / cm3, but lower and higher dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel layer 60L may be removed (e.g., by chemical mechanical planarization (CMP) or a recessed etching process) from above a horizontal plane including the top surface of the insulating cap layer 70.

[0136] Each remaining portion of the doped semiconductor material having the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L having the first conductivity type constitutes a vertical semiconductor channel 60. The vertical semiconductor channel 60 is formed directly on the dielectric material liner 56. The dielectric material liner 56 is surrounded by the memory material layer 54 and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent group of the blocking dielectric layer 52, the memory material layer 54 and the dielectric material liner 56 together constitutes a memory film 50, which can store charge or polarization for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and a backside blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0137] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a dielectric material liner, a plurality of memory elements including a portion of the memory material layer 54, and an optional blocking dielectric layer 52. The entire set of material portions filling the memory opening 49 is referred to herein as a memory opening filling structure 58. The entire set of material portions filling the support opening 19 constitutes a support pillar structure.

[0138] Generally, a memory opening filling structure 58 may be formed within each memory opening 49. The memory opening filling structure 58 includes an optional blocking dielectric layer 52, a memory material layer 54, an optional dielectric material liner 56, and a vertical semiconductor channel 60. The dielectric material liner 56 may laterally surround the vertical semiconductor channel 60. The memory material layer 54 may laterally surround the dielectric material liner 56.

[0139] Where a blocking dielectric layer 52 is present in each memory opening filling structure 58, the blocking dielectric layer 52 may be formed on the sidewalls of the memory opening 49, and a vertical stack of memory elements (which may include portions of the memory material layer 54) may be formed on the blocking dielectric layer 52. In one embodiment, the vertical stack of memory elements includes portions of the charge storage layer (including the memory material layer 54) at the level of the sacrificial material layer 42. Where a dielectric material liner 56 is present in each memory opening filling structure 58, the dielectric material liner 56 may be formed on the vertical stack of memory elements. In one embodiment, the dielectric material liner 56 may include a tunneling dielectric layer. In this case, a vertical semiconductor channel 60 may be formed on the tunneling dielectric layer. The blocking dielectric layer 52 laterally surrounds the charge storage layer, and the tunneling dielectric layer may be located between the charge storage layer and the vertical semiconductor channel 60. When the sacrificial material layer 42 is subsequently replaced with a conductive layer, a vertical NAND string may be formed through each memory opening.

[0140] refer to Figure 6 , shows an exemplary structure after forming a memory opening filling structure 58 and a support pillar structure 20 in the memory opening 49 and the support opening 19, respectively. Figure 4A and Figure 4B An instance of memory opening fill structure 58 is formed within each memory opening 49 of the structure. FIG. 4A to FIG. 4C An instance of a support column structure 20 is formed within each support opening 19 of the structure.

[0141] Each memory stack structure 55 includes a vertical semiconductor channel 60 and a memory film 50. The memory film 50 may include a dielectric material liner 56 laterally surrounding the vertical semiconductor channel 60, a vertical charge storage region stack (including a portion of the memory material layer 54) laterally surrounding the dielectric material liner 56, and an optional blocking dielectric layer 52. Although the present disclosure is described using the configuration shown for the memory stack structure, the method of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0142] refer to 7A to 7C The capping dielectric layer 73 may be formed over the alternating stacks ( 32 , 42 ) of the insulating layers 32 and the sacrificial material layers 42 , and over the memory opening filling structures 58 and the support pillar structures 20 . Fig. 7A is a schematic vertical cross-sectional view of a first exemplary structure after forming backside trenches 79 according to an embodiment of the present disclosure. Figure 7B yes Fig. 7A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig. 7A A schematic vertical cross-sectional view of a plane. Figure 7C It is along Figure 7B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0143] The capping dielectric layer 73 may include silicon oxide, silicon nitride, or silicon oxynitride. The capping dielectric layer 73 may have a thickness in the range of 50 nm to 500 nm, although lesser and greater thicknesses may also be employed.

[0144] A photoresist layer (not shown) may be applied over the capping dielectric layer 73 and photolithographically patterned to form openings in the areas between the clusters of memory opening fill structures 58. The pattern in the photoresist layer may be transferred through the capping dielectric layer 73, the alternating stacks (32, 42), and / or the dielectric material portions 65 using anisotropic etching to form backside trenches 79 extending vertically from at least the top surface of the capping dielectric layer 73 to the top surface of the substrate (9, 10), and extending laterally through the memory array region 100 and the contact region 300.

[0145] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction hd1, and may be laterally spaced apart from each other along a second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1. The memory stack structures 55 may be arranged in rows extending along the first horizontal direction hd1. The drain selection level isolation structure 72 may extend laterally along the first horizontal direction hd1. Each backside trench 79 may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain selection level isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, which does not change with translation along the first horizontal direction hd1. The multi-row memory stack structures 55 may be located between an adjacent pair of backside trenches 79 and drain selection level isolation structures 72, or between an adjacent pair of drain selection level isolation structures 72. In one embodiment, the backside trenches 79 may include a source contact opening, wherein a source contact via structure may be subsequently formed. The photoresist layer may be removed, for example, by ashing.

[0146] By implanting electrical dopants into the physically exposed surface portion of the semiconductor material layer 10, a source region 61 can be formed at the surface portion of the semiconductor material layer 10 below each backside trench 79. The upper portion of the semiconductor material layer 10 extending between the source region 61 and the plurality of pedestal channel portions 11 constitutes a horizontal semiconductor channel 59 for a plurality of field effect transistors. The horizontal semiconductor channels 59 are connected to the plurality of vertical semiconductor channels 60 through the respective pedestal channel portions 11. The horizontal semiconductor channels 59 contact the source region 61 and the plurality of pedestal channel portions 11.

[0147] refer to Figure 8 and Fig.9A For example, an etching process may be used to introduce an etchant into the backside trench 79 , which selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32 . Fig.9A Shows Figure 8 A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the second material of the sacrificial material layer 42 may be selective to the first material of the insulating layer 32, the material of the dielectric material portion 65, the semiconductor material of the semiconductor material layer 10, and the outermost material of the memory film 50. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32 and the dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

[0148] The etching process that selectively removes the second material for the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process that introduces the etchant into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process that immerses the exemplary structure in a wet etching tank including phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the dielectric material portion 65, and the memory opening filling structure 58 provide structural support, while the backside recess 43 exists in the volume previously occupied by the sacrificial material layer 42.

[0149] Each back side recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back side recess 43 may be greater than the height of the back side recess 43. Multiple back side recesses 43 may be formed in the volume of the second material from which the sacrificial material layer 42 is removed. The memory opening in which the memory stack structure 55 is formed is referred to herein as the front side opening or the front side cavity, in contrast to the back side recess 43. In one embodiment, the memory array area 100 includes a three-dimensional NAND string array having a plurality of device levels disposed above the substrate (9, 10). In this case, each back side recess 43 may define a space for receiving a corresponding word line of the three-dimensional NAND string array.

[0150] Each of the plurality of backside recesses 43 may extend substantially parallel to the top surface of the substrate (9, 10). The backside recess 43 may be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each backside recess 43 may have a uniform height throughout.

[0151] The physically exposed surface portions of the optional base channel portion 11 and the semiconductor material layer 10 can be converted into dielectric material portions by thermal conversion and / or plasma conversion of semiconductor material to dielectric material. For example, thermal conversion and / or plasma conversion can be used to convert the surface portion of each base channel portion 11 into a tubular dielectric spacer 116, and each physically exposed surface portion of the semiconductor material layer 10 into a planar dielectric portion 616. In one embodiment, each tubular dielectric spacer 116 can be topologically homeomorphic to a torus, i.e., roughly annular. As used herein, if the shape of the element can be continuously stretched without destroying the hole or forming a new hole into the shape of the torus, the element is topologically homeomorphic to the torus. The tubular dielectric spacer 116 includes a dielectric material that includes the same semiconductor element as the base channel portion 11, and additionally includes at least one non-conductive element such as oxygen and / or nitrogen, so that the material of the tubular dielectric spacer 116 is a dielectric material. In one embodiment, tubular dielectric spacer 116 may include a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of base channel portion 11. Likewise, each planar dielectric portion 616 includes a dielectric material that includes the same semiconductor elements as the semiconductor material layer and additionally includes at least one non-conductive element such as oxygen and / or nitrogen, such that the material of planar dielectric portion 616 is a dielectric material. In one embodiment, planar dielectric portion 616 may include a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of semiconductor material layer 10.

[0152] refer to Fig. 9B Optionally, a backside blocking dielectric layer 44 may be formed. The backside blocking dielectric layer 44, if present, comprises a dielectric material that serves as a control gate dielectric for a control gate subsequently formed in the backside recess 43. In the case where a blocking dielectric layer 52 is present within each memory opening, the backside blocking dielectric layer 44 is optional. In the case where the blocking dielectric layer 52 is omitted, the backside blocking dielectric layer 44 is present.

[0153] The backside blocking dielectric layer 44 may be formed in the backside recess 43 and on the sidewalls of the backside trench 79. The backside blocking dielectric layer 44 may be formed directly on the horizontal surface of the insulating layer 32 in the backside recess 43 and on the sidewalls of the memory stack structure 55. If the backside blocking dielectric layer 44 is formed, it is optional to form the tubular dielectric spacer 116 and the planar dielectric portion 616 before forming the backside blocking dielectric layer 44. In one embodiment, the backside blocking dielectric layer 44 may be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer 44 may be substantially composed of aluminum oxide. The thickness of the backside blocking dielectric layer 44 may be in the range of 1nm to 15nm, such as 2nm to 6nm, but smaller and larger thicknesses may also be used.

[0154] The dielectric material of the backside blocking dielectric layer 44 may be a dielectric metal oxide (such as aluminum oxide), a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element and / or at least one lanthanide element. Alternatively or additionally, the backside blocking dielectric layer 44 may include a silicon oxide layer. The backside blocking dielectric layer 44 may be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer 44 is formed on the sidewalls of the backside trench 79, the horizontal surface and sidewalls of the insulating layer 32, the portion of the sidewall surface of the memory stack structure 55 that is physically exposed to the backside recess 43, and the top surface of the planar dielectric portion 616. A backside cavity 79' exists in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44.

[0155] refer to Fig. 9C , a conductive barrier layer 46A may be deposited in the backside recess 43. The conductive barrier layer 46A includes a conductive material that may serve as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited conductive fill material. The conductive barrier layer 46A may include a conductive nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the conductive barrier layer 46A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the conductive barrier layer 46A may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller and larger thicknesses may also be used. In one embodiment, the conductive barrier layer 46A may be substantially composed of a conductive metal nitride such as TiN.

[0156] refer to Fig.9D, the metal filling material is deposited in a plurality of backside recesses 43, on the sidewalls of at least one backside trench 79, and on the top surface of the capping dielectric layer 73 to form a conductive filling material layer 46B. The conductive filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. In one embodiment, the conductive filling material layer 46B can be substantially composed of at least one elemental metal. At least one elemental metal of the conductive filling material layer 46B can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the conductive filling material layer 46B can be substantially composed of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 can be used to deposit the conductive filling material layer 46B. In one embodiment, the conductive filling material layer 46B can be a tungsten layer including residual fluorine atoms as impurities. The conductive filling material layer 46B is spaced apart from the insulating layer 32 and the memory stack structure 55 by the conductive barrier layer 46A, which is a conductive barrier layer that blocks fluorine atoms from diffusing therethrough.

[0157] A plurality of conductive layers 46 may be formed in the plurality of backside recesses 43, and a continuous conductive material layer 46L may be formed on the sidewalls of each backside trench 79 and over the capping dielectric layer 73. Each conductive layer 46 includes a portion of a conductive barrier layer 46A and a portion of a conductive filling material layer 46B located between a pair of vertically adjacent dielectric material layers such as a pair of insulating layers 32. The continuous conductive material layer 46L includes a continuous portion of the conductive barrier layer 46A and a continuous portion of the conductive filling material layer 46B located in the backside trench 79 or over the capping dielectric layer 73.

[0158] Each sacrificial material layer 42 may be replaced by a conductive layer 46. A backside cavity 79' exists in a portion of each backside trench 79 that is not filled with a backside blocking dielectric layer 44 and a continuous conductive material layer 46L. A tubular dielectric spacer 116 laterally surrounds the base channel portion 11. When the conductive layer 46 is formed, the bottommost conductive layer 46 laterally surrounds each tubular dielectric spacer 116.

[0159] refer to FIG. 10A to FIG. 10D The deposited conductive material of the continuous conductive material layer 46L is etched back from the sidewalls of each backside trench 79 and from over the capping dielectric layer 73, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Fig. 10A is a schematic vertical cross-sectional view of the first exemplary structure after removal of continuous conductive material layer 46L from within backside trench 79 according to an embodiment of the present disclosure. Fig. 10B yes Fig. 10A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig. 10AA schematic vertical cross-sectional view of a plane. Fig. 10C It is along Fig. 10B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. Fig. 10D Yes FIG. 10A to FIG. 10C FIG. 1 is a top view of a unit area UA of a wafer of a first exemplary structure at a processing step of FIG.

[0160] Each remaining portion of the deposited conductive material in the back side recess 43 constitutes a conductive layer 46. Each conductive layer 46 can be a conductive line structure. Therefore, the sacrificial material layer 42 is replaced by the conductive layer 46. Each conductive layer 46 can be used as a combination of a plurality of control gate electrodes located at the same level and a word line electrically interconnected (i.e., electrically short-circuited) with the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for a vertical memory device including a memory stack structure 55. In other words, each conductive layer 46 can be a word line used as a common control gate electrode for a plurality of vertical memory devices.

[0161] In one embodiment, the removal of the continuous conductive material layer 46L may be selective to the material of the backside blocking dielectric layer 44. In this case, a horizontal portion of the backside blocking dielectric layer 44 may be present at the bottom of each backside trench 79. In another embodiment, the removal of the continuous conductive material layer 46L may not be selective to the material of the backside blocking dielectric layer 44, or the backside blocking dielectric layer 44 may not be employed. The planar dielectric portion 616 may be removed during the removal of the continuous conductive material layer 46L. A backside cavity 79' is present within each backside trench 79.

[0162] At least one bottommost conductive layer 46 provided when forming conductive layers 46 within the alternating stack (32, 46) may include a source side select gate electrode of a vertical NAND string. At least one topmost conductive layer 46 provided when forming conductive layers 46 within the alternating stack (32, 46) may include a drain side select gate electrode of a vertical NAND string. The remaining conductive layers may include word lines. Each source region 61 is formed in an upper portion of the semiconductor substrate (9, 10). A semiconductor channel (59, 11, 60) extends between each source region 61 and a corresponding set of drain regions 63. The semiconductor channel (59, 11, 60) includes a vertical semiconductor channel 60 of the memory stack structure 55.

[0163] refer to FIG. 11A to FIG. 11C , a backside trench fill structure (74, 76) may be formed in the backside trench 79, a contact level dielectric layer 80 may be formed over the insulating cap layer 70 and the backside trench fill structure (74, 76), and material portions may be removed from the kerf region 902 over the wafer 1000. Fig.11Ais a schematic vertical cross-sectional view of a first exemplary structure after forming backside trench fill structures ( 74 , 76 ) and a contact-level dielectric layer 80 , and after removing material portions above the substrate from the kerf area, according to an embodiment of the present disclosure. Fig. 11B yes Fig.11A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig.11A A schematic vertical cross-sectional view of a plane. Fig. 11C Yes Fig.11A and Fig. 11B FIG. 1 is a partial perspective top view of a unit area UA of a wafer 1000 of a first exemplary structure at a processing step of FIG.

[0164] Specifically, the insulating material layer can be formed in the backside trench 79 and above the capping dielectric layer 73 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organic silicate glass, or a combination thereof. In one embodiment, the insulating material layer may include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in the range of 1.5 nm to 60 nm, but smaller and larger thicknesses can also be used.

[0165] If backside blocking dielectric layer 44 is present, the insulating material layer may be formed directly on the surface of backside blocking dielectric layer 44 and directly on the sidewalls of conductive layer 46. If backside blocking dielectric layer 44 is not used, the insulating material layer may be formed directly on the sidewalls of insulating layer 32 and directly on the sidewalls of conductive layer 46.

[0166] Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the capping dielectric layer 73 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity 79' exists within the volume surrounded by each insulating spacer 74. The top surface of the semiconductor material layer 10 may be physically exposed at the bottom of each backside trench 79.

[0167] The backside contact via structure 76 may be formed in each backside cavity 79'. Each contact via structure 76 may fill a corresponding cavity 79'. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of the backside trench 79 (i.e., the backside cavity 79'). For example, at least one conductive material may include a conductive liner 76A and a conductive filling material portion 76B. The conductive liner 76A may include a conductive liner such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or their stacks. The thickness of the conductive liner 76A may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The conductive filling material portion 76B may include a metal or a conductive alloy. For example, the conductive filling material portion 76B may include W, Cu, Al, Co, Ru, Ni, their alloys, or their stacks.

[0168] The capping dielectric layer 73 overlying the alternating stack (32, 46) may be used as a stop layer to planarize at least one conductive material. If a chemical mechanical planarization (CMP) process is used, the capping dielectric layer 73 may be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes a backside contact via structure 76. The backside contact via structure 76 extends through the alternating stack (32, 46) and contacts the top surface of the source region 61. If a backside blocking dielectric layer 44 is used, the backside contact via structure 76 may contact the sidewalls of the backside blocking dielectric layer 44. Each continuous combination of the insulating spacer 74 and the backside contact via structure 76 constitutes a backside trench filling structure (74, 76).

[0169] Alternatively, the insulating material layer may be formed in the backside trench 79 to completely fill the entire volume of the backside trench 79 and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region 61 and the backside trench via structure 76 may be omitted, and a horizontal source line (e.g., a direct strap contact) may contact one side of the lower portion of the semiconductor channel 60.

[0170] A contact level dielectric layer 80 may be formed over the semiconductor device on the semiconductor substrate (9, 10) and over the dielectric material portion 65. The contact level dielectric layer 80 includes a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride and may have a thickness in the range of 100 nm to 600 nm, although lesser and greater thicknesses may also be employed.

[0171] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and may be photolithographically patterned to cover areas of the semiconductor die 900 but not the kerf regions 902. An etching process such as an anisotropic etching process may be performed to remove material portions from the kerf regions 902 in the wafer 1000. The semiconductor die 900 may be separated above a horizontal plane including the top surface of the semiconductor substrate (9, 10). The photoresist layer may then be removed, for example, by ashing. Each semiconductor die 900 may include a corresponding dielectric material portion, i.e., as in FIG. 3A to FIG. 3C The patterned remainder of the dielectric material portion 65 formed at the processing step.

[0172] In general, a semiconductor die 900 including a semiconductor device and a dielectric material portion 65 can be formed over a semiconductor substrate (9, 10). The dielectric material portion 65 laterally surrounds the semiconductor device. In one embodiment, the semiconductor device can include an alternating stack of insulating layers 32 and conductive layers 46 and a memory opening filling structure 58 located within a memory opening 49 extending vertically through the alternating stack (32, 46) and including a respective vertical stack of memory elements (which can include, for example, a portion of a memory material layer 54 located at the level of the conductive layer 46) and a vertical semiconductor channel 60. In one embodiment, each of the memory opening filling structures 58 includes a NAND string, the conductive layer 46 includes a word line of the NAND string, and the conductive nodes of the semiconductor device include the word lines of the NAND string. In one embodiment, the sidewalls of each semiconductor die 900 may include sidewalls of the dielectric material portion 65 exposed to a cutout region 902 located between the semiconductor die 900 and an additional semiconductor die 900 located above the semiconductor substrate (9, 10), or between an edge semiconductor die 900 and an edge of a semiconductor substrate (e.g., silicon wafer 9).

[0173] refer to FIG. 12A to FIG. 12C A patterned conductive hard mask layer 97 including openings may be formed over each semiconductor die 900. An anisotropic etching process may be performed to form various via cavities (83, 7P, 85, 87) through the openings in the conductive hard mask layer 97. Fig. 12A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a first exemplary structure after forming a patterned conductive hard mask layer 97 and forming various via cavities, including peripheral discrete via cavities 83, according to an embodiment of the present disclosure. The various insets provide enlarged views within the die 900 and the kerf area 902 in the unit area UA. Fig. 12B yes Fig. 12A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 12C yes Fig. 12A and Fig. 12B 9 is a vertical cross-sectional view of a region of a first exemplary structure within die 900 shown in FIG.

[0174] Specifically, the conductive hard mask layer 97 may be formed over the dielectric material portion 65 over the semiconductor device and over the entire area of ​​the wafer 1000. The conductive hard mask layer 97 may include a conductive metal nitride material (such as TiN, TaN, WN and / or MoN) and / or a metal (such as W, Ti, Ta, W, Co, Ru, etc.) and / or a metal alloy (e.g., an alloy of two or more metals, a metal silicide, etc.). In one embodiment, the conductive hard mask layer 97 may include a tungsten layer. The conductive hard mask layer 97 may be deposited by a conformal or non-conformal deposition process, as long as the top horizontal portion of the conductive hard mask layer 97 overlying the contact level dielectric layer 80 is connected to the bottom horizontal portion of the conductive hard mask layer 97 formed in the kerf region 902. The bottom horizontal portion may contact the top surface of the semiconductor substrate (9, 10). A vertically extending portion of the conductive hard mask layer 97 located on the sidewalls of the semiconductor die 900 (including the sidewalls of the dielectric material portion 65) connects the top horizontal portion and the bottom horizontal portion. For example, the conductive hard mask layer 97 can be formed by chemical vapor deposition, physical vapor deposition, electroplating and / or chemical plating. In one embodiment, the top horizontal portion of the conductive hard mask layer 97 overlying the contact level dielectric layer 80 of the semiconductor die 900 can have a thickness in the range of 20nm to 400nm, such as 40nm to 200nm, but smaller and larger thicknesses can also be used. In one embodiment, the conductive hard mask layer 97 extends continuously above the sidewalls of the dielectric material portion 65 of each semiconductor die 900 and contacts a segment of the top surface of the semiconductor substrate (9, 10) located in the cutout area 902.

[0175] A photoresist layer (not shown) may be applied over the conductive hard mask layer 97 and may be photolithographically patterned to form various openings in the photoresist layer. The various openings in the photoresist layer may include discrete openings overlying the drain region 63, the stepped surface of the conductive layer 46, or the peripheral device 70. According to one aspect of the present disclosure, the various openings in the photoresist layer include discrete openings arranged adjacent to the sidewalls of the semiconductor die 900 along the entire perimeter of the top surface of the corresponding horizontal top portion of the conductive hard mask layer 97. A first anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the conductive hard mask layer 97.

[0176] Openings including contact openings 98A and perimeter discrete openings 98B are formed through conductive hard mask layer 97 below the openings in the photoresist layer. A subset of openings including contact openings 98A in conductive hard mask layer 97 are formed over drain region 63, the stepped surface of conductive layer 46, and perimeter device 70. Perimeter discrete openings 98B are formed through conductive hard mask layer 97 along the perimeter of dielectric material portion 65 in each semiconductor die 900. The set of contact openings 98A through conductive hard mask layer 97 may be formed within an area surrounded by the set of perimeter discrete openings 98B in conductive hard mask layer 97. Optionally, the photoresist layer may be removed, for example, by ashing.

[0177] The pattern of the openings (98A, 98B) in the conductive hard mask layer 97 can be transferred through the underlying material portion by performing at least one second anisotropic etching process. In one embodiment, the pattern of all openings in the conductive hard mask layer 97 can be transferred through the underlying material portion by a single second anisotropic etching process. Alternatively, at least one patterned photoresist layer can be employed to cover a respective subset of the openings in the conductive hard mask layer 97, and multiple second anisotropic etching processes can be performed to form a respective set of via cavities under the respective subset of openings in the conductive hard mask layer 97 that are not masked by the respective patterned photoresist layer.

[0178] In the illustrative example, the various via cavities formed by the at least one second anisotropic etching process may include a drain contact via cavity 87, a layer contact via cavity 85, and an optional perimeter contact via cavity 7P formed under a corresponding contact opening 98A in the die 900, and a group of perimeter discrete via cavities 83 formed under a perimeter discrete opening 98B adjacent to a kerf region 902 located at an edge of the die 900 or at an edge of the wafer 1000. The drain contact via cavity 87 is formed through the contact level dielectric layer 80 and the capping dielectric layer 73 over the physically exposed top surface of the corresponding drain region 63. The layer contact via structure 85 is formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 over the top surface of the corresponding conductive layer 46. The optional perimeter contact via cavities 7P are formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 above the physically exposed top surface of the corresponding node of the perimeter device 700 (if present on the wafer 1000). The set of perimeter discrete via cavities 83 are formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 above the physically exposed top surface of the semiconductor substrate (9, 10) adjacent to the kerf region 902.

[0179] A set of contact via cavities (85, 7P, 87) may be formed through the contact level dielectric layer 80 down to the top surface of the conductive nodes of the semiconductor devices in the semiconductor die 900 by performing at least one second anisotropic etching process. The at least one second anisotropic etching process may selectively etch the material of the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portions 65 for the semiconductor devices. According to one aspect of the present disclosure, a set of peripheral discrete via cavities 83 may be formed through the dielectric material portions 65 within each semiconductor die 900 down to the top surface of the semiconductor substrate (9, 10) by performing an anisotropic etching process that etches the material of the dielectric material portions 65 below the set of peripheral discrete openings 98B in the conductive hard mask layer 97. The lateral offset distance between the set of perimeter discrete via cavities 83 in semiconductor die 900 and the sidewalls of semiconductor die 900 can be in the range of 0.5 micrometers to 30 micrometers, such as 1 micrometer to 15 micrometers, although smaller and larger lateral offset distances can also be used. In one embodiment, the entire area of ​​dielectric material portion 65 between the set of perimeter discrete via cavities 83 and the sidewalls of semiconductor die 900 can be free of any semiconductor devices.

[0180] according to Fig. 12A In one aspect of the present disclosure shown in , each point within the conductive hard mask layer 97 is electrically connected to the surface of a segment of the top surface of the semiconductor substrate (9, 10) through a corresponding conductive discharge path located entirely within the conductive hard mask layer 97. For example, each point within a portion of the conductive hard mask layer 97 located within an area surrounded by a set of peripheral discrete openings 98B is electrically connected to the semiconductor substrate (9, 10) through a portion of the conductive hard mask layer 97 that extends laterally between adjacent pairs of peripheral discrete openings 98 through the conductive hard mask layer 97 overlying the set of peripheral discrete via cavities 83. Thus, any charge (e.g., electrons) accumulated in the conductive hard mask layer 97 during the anisotropic etching process can be discharged to the semiconductor substrate (9, 10) through the corresponding discharge path. Thus, arcing can be reduced or avoided during one or more anisotropic etching processes that form the contact via cavities (85, 7P, 87) and the set of peripheral discrete via cavities 83 in each memory die 900. According to one aspect of the present disclosure, electrical grounding of the conductive hard mask layer 97 is provided over the entire conductive hard mask layer 97, and thus, arc discharge can be completely prevented during at least one second anisotropic etching process. In contrast, if a continuous peripheral trench is formed around the edge of the die 900 rather than a peripheral discrete opening 98B, arc discharge may occur across the continuous peripheral trench during the anisotropic etching due to the difference in high voltage charge and low voltage charge in separate portions of the conductive hard mask layer 97 on opposite sides of the trench.

[0181] In one embodiment, the maximum lateral dimension (such as a diameter or a major axis) of each peripheral discrete via cavity 83 can be in the range of 100 nm to 2 microns, such as 200 nm to 1 micron, although smaller and larger maximum lateral dimensions can also be used. In one embodiment, the maximum nearest neighbor distance within a peripheral discrete via cavity 83 can be less than the maximum lateral dimension (such as a diameter or a major axis) of each peripheral discrete via cavity 83 within the group of peripheral discrete via cavities 83. In one embodiment, all sidewall surfaces of the group of peripheral discrete via cavities 83 can be dielectric surfaces, which can include surfaces of the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65.

[0182] The conductive hard mask layer 97 may then be removed, for example, by performing a selective wet etching process. Although embodiments are described above in which the conductive hard mask layer 97 is removed immediately after forming the contact via cavity (85, 7P, 87) and the set of peripheral discrete via cavities 83 in each semiconductor die 900, alternative embodiments are expressly contemplated herein in which the conductive hard mask layer 97 is removed at any subsequent processing step before, during, or after forming the edge seal structure.

[0183] refer to FIG. 13A to FIG. 13D , a photoresist layer 99 may be applied over the wafer 1000 and may be photolithographically patterned to form a moat-shaped opening over each set of peripheral discrete via cavities 83. Subsequently, an isotropic etching process may be performed to laterally expand the discrete via cavities 83 and provide a continuous moat trench 83M within each semiconductor die 900. Fig.13A 83 is a vertical cross-sectional view of a unit area UA of a wafer 1000 including the first exemplary structure after forming a continuous moat trench 83M according to an embodiment of the present disclosure. Fig. 13B yes Fig.13A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 13C It is along Fig.13A FIG. 1 is a horizontal cross-sectional view of a unit area UA of the wafer 1000 taken along a horizontal plane CC′. Fig.13D yes FIG. 13A to FIG. 13C 9 is a vertical cross-sectional view of a region of a first exemplary structure within die 900 shown in FIG.

[0184] Specifically, the photoresist layer 99 may be formed, for example, by spin coating. A photolithography exposure and development process may be performed to pattern the photoresist layer 99. A groove-shaped opening 99M may be formed through the photoresist layer 99 above each group of peripheral discrete via cavities 83, so that the peripheral discrete via cavities 83 are not covered by the patterned photoresist layer 99. An isotropic etching process may be performed to laterally expand the peripheral discrete via cavities 83 until the peripheral discrete via cavities 83 merge with each other and form a continuous moat trench 83M around the perimeter of each semiconductor die 900. The dielectric material portion 65 of each semiconductor die 900 is divided into an inner dielectric material portion 65I laterally surrounded by the continuous moat trench 83M and an outer dielectric material portion 65O laterally surrounding the continuous moat trench 83M. Inner dielectric material portion 65I includes an inner region of dielectric material portion 65 , and outer dielectric material portion 65O includes an outer region of dielectric material portion 65 .

[0185] In one embodiment, each of the peripheral discrete via cavities 83 may have a corresponding circular or elliptical horizontal cross-sectional shape, and the continuous moat trench 83M includes a laterally undulating outer sidewall 83O having horizontal concave outer surface segments abutting each other and a laterally undulating inner sidewall 83I having horizontal concave inner surface segments abutting each other. As used herein, a surface is laterally undulating if the horizontal cross-sectional profile of the surface is undulating. In one embodiment, the region of the dielectric material portion 65 between the continuous moat trench 83M and the sidewall of the semiconductor die 900 (i.e., the outer dielectric material portion 65O) may be free of any semiconductor device, i.e., not in direct contact with any semiconductor device. The photoresist layer 99 may then be removed, for example, by ashing.

[0186] refer to FIG. 14A to FIG. 14E , various contact via structures ( 86 , 8P, 88 ) may be formed in various contact via cavities ( 85 , 7P, 87 ), and a conductive edge seal structure 92 may be formed in the continuous moat trench 83M. Fig.14A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a first exemplary structure after forming a contact via structure ( 86 , 8P) and a conductive edge seal structure 92 according to an embodiment of the present disclosure. Fig. 14B yes Fig.14A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 14C yes Fig.14A and Fig. 14B 9 is a vertical cross-sectional view of a region of a first exemplary structure within die 900 shown in FIG. Fig.14D yes Fig. 14C A top view of a region of a first exemplary structure. Fig.14E It is along Fig.14DA vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0187] Specifically, at least one conductive material is deposited in various contact via cavities (85, 7P, 87) and continuous moat trench 83M. In one embodiment, at least one conductive material may include a conductive nitride liner material and a metal filling material, which may be a metal or a metal alloy. For example, the conductive nitride liner material may include TiN, TaN, WN and / or MoN. The metal filling material may include W, Ti, Ta, Mo, Ru, Co, Cu or an alloy thereof. At least one conductive material may be deposited, for example, by chemical vapor deposition, physical vapor deposition, electroplating and / or chemical plating. Excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process.

[0188] Each remaining portion of the at least one conductive material filling drain contact via cavity 87 constitutes a drain contact via structure 88. Each remaining portion of the at least one conductive material filling layer contact via cavity 85 constitutes a layer contact via structure 86. Each remaining portion of the at least one conductive material filling optional perimeter contact via cavity 7P constitutes an optional perimeter contact via structure 8P. The remaining portion of the at least one conductive material filling continuous moat trench 83M constitutes a conductive edge seal structure 92.

[0189] In one embodiment, each of the contact via structures (88, 86, 8P) in the contact via structures includes a conductive contact liner (88A, 86A, 8PA) and a conductive filling material portion (88B, 86B, 8PB) embedded within the conductive contact liner (88A, 86A, 8PA). The conductive edge seal structure 92 includes a conductive edge seal liner 92A and a conductive edge seal filling material portion 92B embedded within the conductive edge seal liner 92A. In one embodiment, the conductive contact liner (88A, 86A, 8PA) and the conductive edge seal liner 92A have a first conductive composition (e.g., a material composition of a conductive nitride liner material) and have the same thickness, and the conductive edge seal filling material portion 92B and the conductive filling material portion (88B, 86B, 8PB) have a second conductive composition (e.g., a material composition of a conductive filling material).

[0190] In one embodiment, inner dielectric material portion 65I laterally surrounds the semiconductor device of each semiconductor die 900. Conductive edge seal structure 92 laterally surrounds inner dielectric material portion 65I, extends vertically from at least the semiconductor substrate (9, 10) to a horizontal plane including the topmost surface of inner dielectric material portion 65I, and has laterally undulating inner sidewalls 92I and laterally undulating outer sidewalls 92O extending laterally generally parallel to the outer sidewalls closest to the outer sidewalls of semiconductor die 900. In one embodiment, outer dielectric material portion 65O laterally surrounds conductive edge seal structure 92.

[0191] In one embodiment, the outer sidewall of the outer dielectric material portion 65O is an outer sidewall of the semiconductor die 900. In one embodiment, each of the laterally undulating outer sidewalls 92O of the conductive edge seal structure 92 has a corresponding horizontal concave outer surface segment that abuts each other, and each of the laterally undulating inner sidewalls 92I of the conductive edge seal structure 92 has a corresponding horizontal concave inner surface segment that abuts each other. In one embodiment, the outer dielectric material portion 65O is not in direct contact with any of the semiconductor devices in the semiconductor die 900.

[0192] In one embodiment, semiconductor die 900 includes metal interconnect structures, outer dielectric material portion 65O is not in direct contact with any of the metal interconnect structures, and all of the metal interconnect structures are laterally surrounded by conductive edge seal structure 92. In one embodiment, semiconductor die 900 includes contact level dielectric layer 80 overlying semiconductor devices, inner dielectric material portion 65I, and outer dielectric material portion 65O, wherein conductive edge seal structure 92 extends vertically through contact level dielectric layer 80.

[0193] In one embodiment, semiconductor die 900 includes contact via structures (88, 86, 8P) that extend vertically through contact level dielectric layer 80 and contact top surfaces of conductive nodes of the semiconductor device and have top surfaces that are located in the same horizontal plane as top surfaces of conductive edge seal structures 92. In one embodiment, the semiconductor device includes alternating stacks of insulating layers 32 and conductive layers 46 and memory opening filling structures 58 that are located within memory openings 49 that extend vertically through the alternating stacks and include vertical semiconductor channels and corresponding vertical stacks of memory elements. In one embodiment, each of memory opening filling structures 58 includes a NAND string, conductive layer 46 includes a word line of the NAND string, and the conductive nodes of the semiconductor device include the word lines. In some embodiments, the conductive edge seal structures 92 may be formed before, during, or after the conductive edge seal structures 92 are formed. FIG. 13A to FIG. 13DThe conductive hard mask layer 97 is removed after the processing steps.

[0194] Common Reference Figures 1 to 14E And according to various embodiments of the present disclosure, semiconductor die 900 includes a semiconductor device (e.g., a vertical NAND string) located above a semiconductor substrate (9, 10), an inner dielectric material portion 65I laterally surrounding the semiconductor device, a conductive edge seal structure 92, and an outer dielectric material portion 65O laterally surrounding the conductive edge seal structure 92, the conductive edge seal structure laterally surrounding the inner dielectric material portion 65I, extending vertically from at least the semiconductor substrate (9, 10) to a horizontal plane including the topmost surface of the inner dielectric material portion 65I, and having a laterally undulating inner sidewall 92I and a laterally undulating outer sidewall 92O (e.g., a laterally undulating outer sidewall that extends laterally generally parallel to the nearest outer sidewall of the outer sidewall of the semiconductor die 900). In one embodiment, the outer sidewall of the outer dielectric material portion 65O is the outer sidewall of the semiconductor die 900. In one embodiment, each of the laterally undulating outer sidewalls 92O has respective horizontal concave outer surface sections that abut one another, and each of the laterally undulating inner sidewalls 92I has respective horizontal concave inner surface sections that abut one another.

[0195] refer to FIG. 15A to FIG. 15C , showing a second exemplary structure according to an embodiment of the present disclosure. Fig.15A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a second exemplary structure after forming an edge region recess cavity 187 and a drain contact via cavity 87 according to an embodiment of the present disclosure. Fig. 15B yes Fig.15A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 15C yes Fig.15A and Fig. 15B 00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in .

[0196] The following methods can be used FIG. 11A to FIG. 11CThe second exemplary structure is obtained from the first exemplary structure: by forming a photoresist layer 93 over the two-dimensional array of semiconductor die 900; by photolithographically patterning various discrete openings in the photoresist layer 93; and by transferring the pattern of the various discrete openings through the contact level dielectric layer 80 and the capping dielectric layer 73. The edge region recessed cavity 187 can be formed through the contact level dielectric layer 80 and the capping dielectric layer 73 near the outer sidewalls of the dielectric material portion 65 of each semiconductor die 900. The bottom surface of each edge region recessed cavity 187 can be formed at or below the top surface of the dielectric material portion 65. During the same etching step as the edge region recessed cavity 187, a drain contact via cavity 87 is formed through the contact level dielectric layer 80 and the capping dielectric layer 73 above the top surface of the drain region 63. The drain contact via cavity 87 extends through the contact level dielectric layer 80 downward to the top surface of the drain region 63. The top surface of the drain region 63 may be physically exposed at the bottom of each drain contact via cavity 87. The photoresist layer 93 may then be removed, for example, by ashing.

[0197] refer to FIG. 16A to FIG. 16C , at least one conductive material is deposited in the edge region recess cavity 187 and the drain contact via cavity 87 to form a conductive plate 188 and a drain contact via structure 88 . Fig.16A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a second exemplary structure after forming a conductive bridge structure (including a conductive plate 188 ) and a drain contact via structure 88 according to an embodiment of the present disclosure. Fig. 16B yes Fig.16A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 16C yes Fig.16A and Fig. 16B 00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in .

[0198] Specifically, at least one conductive material may include a conductive nitride liner material and a conductive filling material, and the conductive filling material may be a metal or an intermetallic alloy. For example, the conductive nitride liner material may include TiN, TaN, WN and / or MoN. The conductive filling material may include W, Ti, Ta, Mo, Ru, Co, Cu or an alloy thereof. At least one conductive material may be deposited, for example, by chemical vapor deposition, physical vapor deposition, electroplating and / or chemical plating. Excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process.

[0199] Each remaining portion of the at least one conductive material filling the drain contact via cavity 87 constitutes a drain contact via structure 88. Each remaining portion of the at least one conductive material filling the edge region recessed cavity 187 constitutes a conductive plate 188, which is used as a conductive bridge structure during a subsequent anisotropic etching process. In one embodiment, each of the drain contact via structure 88 and the conductive plate 188 includes a conductive contact pad (88A, 188A) and a conductive filling material portion (88B, 188B) embedded in the conductive contact pad 88A. In one embodiment, the conductive contact pads (88A, 188A) can have the same conductive composition (i.e., the material composition of the conductive nitride liner material) and have the same thickness. The conductive filling material portions (88B, 188B) can have the same conductive composition (i.e., the material composition of the conductive filling material) between them.

[0200] In general, at least one conductive structure (such as at least one conductive plate 188) can be formed in the peripheral region of the semiconductor die 900 through the contact level dielectric layer 80. Each conductive structure can then be used as a conductive bridge structure (including the conductive plate 188) during a subsequent anisotropic etching process. In one embodiment, each of the at least one conductive structure (such as at least one conductive plate 188) has a corresponding bottom surface located above a horizontal plane including the top surface of the semiconductor substrate (9, 10). For example, each conductive plate 188 can have a bottom surface located above a horizontal plane including the topmost surface of the conductive layer 46 within the alternating stack (32, 46). Each of the at least one conductive structure (such as at least one conductive plate 188) is electrically isolated from the semiconductor substrate (9, 10).

[0201] refer to FIG. 17A to FIG. 17E , a conductive hard mask layer 97 can be formed above the wafer 1000 and can be patterned to form openings in the conductive hard mask layer, and the pattern of the openings in the conductive hard mask layer 97 can be transferred through the underlying material portions to form various contact via cavities and moat trenches 91. Fig.17A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a second exemplary structure after forming a patterned conductive hard mask layer 97 and various via cavities and continuous moat trenches 91 according to an embodiment of the present disclosure. Fig. 17B yes Fig.16A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 17C yes Fig.17A and Fig. 17B 00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in . Fig.17D It is along Fig. 17B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'. Fig.17EIt is along Fig. 17B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0202] Specifically, the conductive hard mask layer 97 may be formed over the dielectric material portion 65 over the semiconductor device and over the entire area of ​​the wafer 1000. The conductive hard mask layer 97 may include a conductive metal nitride material (such as TiN, TaN, WN and / or MoN) and / or a metal (such as W, Ti, Ta, W, Co, Ru, etc.) and / or a metal alloy. In one embodiment, the conductive hard mask layer 97 may include a tungsten layer. The conductive hard mask layer 97 may be deposited by a conformal or non-conformal deposition process, as long as the top horizontal portion of the conductive hard mask layer 97 overlying the contact level dielectric layer 80 is connected to the bottom horizontal portion of the conductive hard mask layer 97, which is formed in the kerf region 902 and contacts the top surface of the semiconductor substrate (9, 10) through the vertical extension of the conductive hard mask layer 97 located on the sidewalls of the semiconductor die 900 (which includes the sidewalls of the dielectric material portion 65). For example, the conductive hard mask layer 97 may be formed by chemical vapor deposition, physical vapor deposition, electroplating, and / or electroless plating. In one embodiment, the top horizontal portion of the conductive hard mask layer 97 overlying the contact level dielectric layer 80 of the semiconductor die 900 may have a thickness in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the conductive hard mask layer 97 extends continuously over the sidewalls of the dielectric material portion 65 of each semiconductor die 900 and contacts a section of the top surface of the semiconductor substrate (9, 10) located in a kerf region 902 located at an edge of the semiconductor substrate or between one of the additional semiconductor dies 900 located on the semiconductor substrate (9, 10) and the semiconductor die 900.

[0203] A photoresist layer (not shown) may be applied over the conductive hard mask layer 97 and may be photolithographically patterned to form various openings in the photoresist layer. The various openings in the photoresist layer may include a stepped surface overlying the conductive layer 46 and a discrete opening of an optional peripheral device 700. According to one aspect of the present disclosure, at least one groove-shaped opening may be formed in the photoresist layer along the entire periphery of the top surface of the corresponding horizontal top portion of the conductive hard mask layer 97. A groove-shaped opening refers to an opening that separates the area surrounded by the opening and the area located outside the opening, without any connection area between the two areas. In one embodiment, at least one groove-shaped opening may include multiple (e.g., two) groove-shaped openings nested in each other. A first anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer through the conductive hard mask layer 97.

[0204] An opening may be formed through the conductive hard mask layer 97 below the opening in the photoresist layer. A subset of contact openings 97C in the conductive hard mask layer 97 is formed above the stepped surface of the conductive layer 46 and the peripheral device 700. At least one (e.g., two) trench-shaped openings may be formed through the conductive hard mask layer 97 along the perimeter of the dielectric material portion 65 in each semiconductor die 900. The at least one moat-shaped opening is then used to define the area of ​​at least one edge seal structure, and is therefore referred to herein as at least one edge seal opening 97E. In one embodiment, there may be two edge seal openings 97E, and each edge seal opening 97E surrounds an area above the inner region of the dielectric material portion 65 and overlies a corresponding conductive bridge structure (including the conductive plate 188). Thus, at least one conductive bridge structure including at least one conductive plate 188 connects an inner portion of the conductive hard mask layer 97 located inside the innermost perimeter of the at least one edge seal opening 97E to an outer portion of the conductive hard mask layer 97 located outside the outermost perimeter of the at least one edge seal opening 97E. The set of contact openings 97C passing through the conductive hard mask layer 97 may be formed in a region surrounded by at least one trench-shaped opening 97E in the conductive hard mask layer 97. Optionally, the photoresist layer may be removed, for example, by ashing.

[0205] The pattern of the openings (97C, 97E) in the conductive hard mask layer 97 may be transferred through the underlying material portion by performing at least one second anisotropic etching process. In one embodiment, the pattern of all openings (97C, 97E) in the conductive hard mask layer 97 may be transferred through the underlying material portion by a single second anisotropic etching process. Alternatively, at least one patterned photoresist layer may be employed to cover a respective subset of the openings in the conductive hard mask layer 97, and a plurality of second anisotropic etching processes may be performed to form a respective set of via cavities beneath a respective subset of the openings in the conductive hard mask layer 97 that are not masked by the respective patterned photoresist layer.

[0206] In an illustrative example, the various via cavities formed by the at least one second anisotropic etching process may include a layer contact via cavity 85 and an optional perimeter contact via cavity 7P formed through the contact opening 97C, and at least one moat trench 91 formed through the at least one edge seal opening 97E. The drain contact via cavity 87 is formed through the contact level dielectric layer 80 and the capping dielectric layer 73 over the physically exposed top surface of the corresponding drain region 63. The layer contact via structure 85 is formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 over the top surface of the corresponding conductive layer 46. The perimeter contact via cavity 7P is formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 over the physically exposed top surface of the corresponding node of the perimeter device 700. At least one moat trench 91 is formed through the contact-level dielectric layer 80 , the insulating capping layer 70 , and the dielectric material portion 65 over the physically exposed top surface of the semiconductor substrate ( 9 , 10 ).

[0207] A set of contact via cavities (85, 7P) may be formed through the contact level dielectric layer 80 down to the top surface of the conductive nodes of the semiconductor devices in the semiconductor die 900 by performing at least one second anisotropic etching process. The at least one second anisotropic etching process may selectively etch the material of the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portions 65 for the semiconductor devices. According to one aspect of the present disclosure, at least one moat trench 91 may be formed through the dielectric material portions 65 within each semiconductor die 900 down to the top surface of the semiconductor substrate (9, 10) by performing an anisotropic etching process that etches the material of the dielectric material portions 65 below the trench-shaped openings (i.e., edge seal openings) 97E in the conductive hard mask layer 97. The width of each moat trench 91 may be in the range of 0.5 microns to 30 microns, such as 1 micron to 15 microns, although smaller and larger lateral offset distances may also be employed. In one embodiment, the entire area of ​​the dielectric material portion 65 between the innermost moat trench of the at least one moat trench 91 and the sidewalls of the semiconductor die 900 may be free of any semiconductor devices.

[0208] according to Fig.17AIn one aspect of the present disclosure shown in , each point within the conductive hard mask layer 97 is electrically connected to the surface of a segment of the top surface of the semiconductor substrate (9, 10) through a corresponding conductive discharge path located below the conductive hard mask layer 97 and forming a conductive bridge structure. For example, each point within a portion of the conductive hard mask layer 97 located within an area surrounded by at least one moat-shaped opening 97E in the conductive hard mask layer 97 is electrically connected to the semiconductor substrate (9, 10) through at least one conductive bridge structure, the at least one conductive bridge structure including at least one conductive plate 188 overlying the unetched columnar portion of the dielectric material portion 65. Therefore, any charge (e.g., electrons) accumulated in the conductive hard mask layer 97 during the anisotropic etching process can be discharged to the semiconductor substrate (9, 10) through the corresponding discharge path. Therefore, arc discharge can be reduced or avoided during one or more anisotropic etching processes to form the contact via cavity (85, 7P) and at least one moat trench 91 in each memory die 900. According to one aspect of the present disclosure, electrical grounding of the conductive hard mask layer 97 is provided throughout the conductive hard mask layer 97 , and thus, arc discharge may be completely prevented during at least one second anisotropic etching process.

[0209] The top portion of each conductive plate 188 may be recessed in parallel between adjacent portions of the corresponding moat trench 91. Each moat trench 91 may include at least one deep moat portion 91D extending vertically from the top surface of the contact-level dielectric layer 80 to the top surface of the semiconductor substrate (9, 10) and at least one shallow moat portion 91S overlying the recessed top surface of the corresponding conductive plate 188. Thus, each moat trench 91 may extend continuously around and encircle the area of ​​the semiconductor die 900 without a gap. Thus, each moat trench 91 may be a continuous moat trench including at least one deep moat portion 91D extending vertically downward to the top surface of the semiconductor substrate (9, 10) and at least one shallow moat portion 91S overlying the horizontal surface of the conductive bridge structure (including the conductive plate 188), which is recessed below the horizontal plane including the top surface of the contact-level dielectric layer 80.

[0210] In general, each of the at least one conductive bridge structure (such as at least one conductive plate 188) is electrically isolated from the semiconductor substrate (9, 10) before the conductive hard mask layer 97 is formed, and is electrically connected to the semiconductor substrate (9, 10) through the conductive hard mask layer 97 after the conductive hard mask layer 97 is formed during each of the at least one second anisotropic etching process. During each of the at least one second anisotropic etching process, charges (e.g., electrons) are released from each portion of the conductive hard mask layer 97 into the semiconductor substrate (9, 10). In one embodiment, the conductive hard mask layer 97 is formed over the sidewalls of the dielectric material portion 65 and on the top surface of the semiconductor substrate (9, 10). In one embodiment, the at least one second anisotropic etching process etches the material of the dielectric material portion 65 selectively to the material of the conductive bridge structure (including the conductive plate 188), the conductive hard mask layer 97, and the semiconductor substrate (9, 10). Portions of the conductive plate 188 that are not masked by the conductive hard mask layer 97 may be recessed in parallel during the at least one second anisotropic etching process. The recess depth of the vertically recessed top surface of the conductive plate 188 may be in the range of 1% to 50% (e.g., 5% to 25%) of the thickness of the conductive plate 188. The conductive hard mask layer 97 may be partially removed in parallel during the at least one second anisotropic etching process.

[0211] During and after the anisotropic etching process, each conductive bridge structure (including conductive plate 188) connects an inner portion of conductive hard mask layer 97 located inside the inner perimeter of at least one edge seal opening 97E to an outer portion of conductive hard mask layer 97 located outside the outer perimeter of at least one edge seal opening 97E. The conductive hard mask layer 97 may then be removed, for example, by a selective isotropic recess etching process such as a wet etching process.

[0212] refer to FIG. 18A to FIG. 18E Various contact via structures ( 86 , 8P) and at least one conductive edge seal structure 92 may be formed in the various contact via cavities ( 85 , 7P) and at least one moat trench 91 . Fig.18A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a second exemplary structure after forming a conductive edge seal structure 92 according to an embodiment of the present disclosure. Fig.18B yes Fig.18A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig.18C yes Fig.18A and Fig.18B 00140 . A vertical cross-sectional view of a region of a second exemplary structure within a die is shown in . Fig.18D It is along Fig.18B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'. Fig.18E It is along Fig.18B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0213] Specifically, at least one conductive material is deposited in various contact via cavities (85, 7P) and at least one moat trench 91. In one embodiment, at least one conductive material may include a conductive nitride liner material and a conductive filling material, which may be a metal or an intermetallic alloy. For example, the conductive nitride liner material may include TiN, TaN, WN and / or MoN. The conductive filling material may include W, Ti, Ta, Mo, Ru, Co, Cu or an alloy thereof. At least one conductive material may be deposited, for example, by chemical vapor deposition, physical vapor deposition, electroplating and / or chemical plating. Excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process.

[0214] Each remaining portion of the at least one conductive material filling the layer contact via cavity 85 constitutes a layer contact via structure 86. Each remaining portion of the at least one conductive material filling the perimeter contact via cavity 7P constitutes an optional perimeter contact via structure 8P. Each remaining portion of the at least one conductive material filling the moat trench 91 constitutes a conductive edge seal structure 92.

[0215] In one embodiment, each of the contact via structures (86, 8P) includes a conductive contact liner (86A, 8PA) and a conductive fill material portion (86B, 8PB) embedded within the conductive contact liner (86A, 8PA). Each conductive edge seal structure 92 includes a conductive edge seal liner 92A and a conductive edge seal fill material portion 92B embedded within the conductive edge seal liner 92A. In one embodiment, the conductive contact liner (86A, 8PA) and the conductive edge seal liner 92A have a first conductive composition (i.e., a material composition of the conductive nitride liner material) and have the same thickness, and the conductive edge seal fill material portion 92B and the conductive fill material portion (86B, 8PB) have a second conductive composition (i.e., a material composition of the conductive fill material).

[0216] In one embodiment, inner dielectric material portion 65I laterally surrounds the semiconductor device of each semiconductor die 900. Each conductive edge seal structure 92 laterally surrounds inner dielectric material portion 65I, extends vertically from at least the semiconductor substrate (9, 10) to a horizontal plane including the topmost surface of inner dielectric material portion 65I, and may have straight sidewalls extending laterally parallel to the outer sidewalls closest to the outer sidewalls of semiconductor die 900. In one embodiment, outer dielectric material portion 65O laterally surrounds each conductive edge seal structure 92.

[0217] In one embodiment, the outer sidewalls of outer dielectric material portion 650 are outer sidewalls of semiconductor die 900. In one embodiment, outer dielectric material portion 650 is not in direct contact with any of the semiconductor devices in semiconductor die 900.

[0218] In one embodiment, semiconductor die 900 includes metal interconnect structures, outer dielectric material portion 65O is not in direct contact with any of the metal interconnect structures, and all of the metal interconnect structures are laterally surrounded by at least one conductive edge seal structure 92. In one embodiment, semiconductor die 900 includes a contact level dielectric layer 80 overlying the semiconductor device, inner dielectric material portion 65I, and outer dielectric material portion 65O, wherein at least one conductive edge seal structure 92 extends vertically through contact level dielectric layer 80 and dielectric material portions (65I, 65O).

[0219] In one embodiment, semiconductor die 900 includes contact via structures (86, 8P) that extend vertically through contact level dielectric layer 80 and contact top surfaces of conductive nodes of the semiconductor device and have top surfaces that are located in the same horizontal plane as top surfaces of conductive edge seal structures 92. In one embodiment, the semiconductor device includes alternating stacks of insulating layers 32 and conductive layers 46 and memory opening filling structures 58 that are located within memory openings 49 that extend vertically through the alternating stacks and include vertical semiconductor channels 60 and corresponding vertical stacks of memory elements. In one embodiment, each of memory opening filling structures 58 includes a NAND string, conductive layer 46 includes a word line of the NAND string, and the conductive nodes of the semiconductor device include the word lines. In some embodiments, the conductive edge seal structures 92 may be formed before, during, or after forming at least one conductive edge seal structure 92. FIG. 18A to FIG. 18E The conductive hard mask layer 97 is removed after the processing steps.

[0220] refer to Figures 1 to 11C and FIG. 15A to FIG. 18EAnd according to various embodiments of the present disclosure, the semiconductor die 900 includes: a semiconductor device, which is located above the semiconductor substrate (9, 10); an internal dielectric material portion 65I, which laterally surrounds the semiconductor device; a contact-level dielectric layer 80, which overlies the semiconductor device and the internal dielectric material portion 65I; a conductive bridge structure (including a conductive plate 188), which has at least one top surface located within a horizontal plane including the top surface of the contact-level dielectric layer 80; a conductive edge sealing structure 92, which laterally surrounds the internal dielectric material portion 65I, extends vertically from the semiconductor substrate (9, 10) to a horizontal plane including the top surface of the contact-level dielectric layer 80, and extends above at least one surface of the conductive bridge structure (including the conductive plate 188) and contacts the at least one surface; and an external dielectric material portion 65O, which laterally surrounds the conductive edge sealing structure 92.

[0221] In one embodiment, the conductive edge seal structure 92 includes: at least one wall portion extending vertically from the semiconductor substrate (9, 10) to a horizontal plane including the top surface of the contact-level dielectric layer 80 (which fills the corresponding deep moat segment of the moat trench 91); and a connecting portion overlying the conductive bridge structure (including the conductive plate 188) (which fills the corresponding shallow moat segment of the moat trench 91). In one embodiment, the bottommost surface of the conductive bridge structure (including the conductive plate 188) is located above the semiconductor substrate (9, 10) and is vertically spaced apart therefrom.

[0222] In one embodiment, semiconductor die 900 includes contact via structures ( 88 , 86 , 8P) that extend vertically through contact level dielectric layer 80 and contact conductive nodes of the semiconductor device and have top surfaces that lie in the same horizontal plane as a top surface of conductive edge seal structure 92 . In one embodiment, the conductive edge sealing structure 92 includes a conductive edge sealing pad 92A and a conductive edge sealing filling material portion 92B embedded in the conductive edge sealing pad 92A; each contact through-hole structure (88, 86, 8P) in the contact through-hole structure includes a conductive contact pad (88A, 86A, 8PA) and a conductive filling material portion (88B, 86B, 8PB) embedded in the conductive contact pad (88A, 86A, 8PA); the conductive contact pad (88A, 86A, 8PA) and the conductive edge sealing pad 92A have a first conductive composition and have the same thickness; and the conductive edge sealing filling material portion 92B and the conductive filling material portion (88B, 86B, 8PB) have a second conductive composition.

[0223] In one embodiment, the semiconductor device includes: an alternating stack of insulating layers 32 and conductive layers 46; and a memory opening filling structure 58 located within a memory opening 49 extending vertically through the alternating stack and including a corresponding vertical semiconductor channel 60 and a vertical stack of memory elements (e.g., portions of layer 54). In one embodiment, each of the memory opening filling structures 58 includes a NAND string; the conductive layers 46 include a word line of the NAND string; and the conductive nodes of the semiconductor device include the word lines.

[0224] refer to FIG. 19A to FIG. 19D , showing a third exemplary structure according to an embodiment of the present disclosure. Fig.19A is a vertical cross-sectional view of the third exemplary structure after forming backside trenches 79 , pillar cavities 177 , and conductive layer 46 according to an embodiment of the present disclosure. Fig.19B Yes Fig.19A FIG. 1 is a top view of a unit area UA of a wafer 1000 of a third exemplary structure. Fig.19C It is along Fig.19B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'. Fig.19D It is along Fig.19B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0225] The back side trenches 79 may be formed by modifying the pattern of the photoresist layer used to define the pattern of the back side trenches 79. 7A to 7C The third exemplary structure is obtained by patterning the first exemplary structure shown in FIG. Specifically, the photoresist layer is patterned to have additional openings in the region near the edge of the corresponding semiconductor die 900 within each unit area UA. The additional openings are formed as discrete openings in the region of the peripheral portion of the dielectric material portion 65 in the corresponding semiconductor die 900.

[0226] The pillar cavities 177 are formed at the same time as the backside trenches 79 are formed. Each pillar cavity 177 extends vertically from the top surface of the capping dielectric layer 73 to the top surface of the semiconductor substrate (9, 10) through the dielectric material portion 65. In one embodiment, each sidewall of the pillar cavity 177 may be composed of a dielectric surface. Subsequently, a source region 61 may be formed under each backside trench 79. In one embodiment, a dummy source region (not shown) having the same material composition as the source region 61 may be formed under each pillar cavity 177 within the semiconductor substrate (9, 10).

[0227] Then, you can execute the reference Figure 8 , 9A to 9D and FIG. 10A to FIG. 10D The processing steps are described to replace the sacrificial material layer 42 with the conductive layer 46 .

[0228] refer to FIG. 20A to FIG. 20D , executable reference FIG. 10A to FIG. 10D Processing steps are described to form backside trench fill structures ( 74 , 76 ) within each backside trench 79 . Fig. 20A is a vertical cross-sectional view of the third exemplary structure after forming backside trench fill structures ( 74 , 76 ) and conductive pillar structures 176 according to an embodiment of the present disclosure. Fig. 20B Yes Fig. 20A FIG. 1 is a top view of a unit area UA of a wafer 1000 of a third exemplary structure. Fig. 20C It is along Fig. 20B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'. Fig.20D It is along Fig. 20B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'.

[0229] The column cavity filling structures 78 may be formed in parallel in the column cavity 177 while forming the backside trench filling structures (74, 76). In other words, the set of processing steps for forming the backside trench filling structures (74, 76) forms the column cavity filling structures 78 as a byproduct without using any additional processing steps. Each column cavity filling structure 78 may include an optional dielectric liner 144 having the same material composition as the backside blocking dielectric layer 44, a column insulating spacer 174 having the same lateral thickness and the same material composition as the insulating spacer 74, and a conductive column structure 176. Each conductive column structure 176 may include a column conductive liner 176A having the same material composition and the same thickness as the conductive liner 76A of the backside contact via structure 76, and a column conductive filling material portion 176B having the same material composition as the conductive filling material portion 76B of the backside contact via structure 76. The top surface of the conductive column structure 176 may be formed in a horizontal plane including the top surface of the capping dielectric layer 73.

[0230] refer to FIG. 21A to FIG. 21E , executable reference FIG. 10A to FIG. 10D The additional processing steps described above and may be performed with reference to modifying the pattern of the openings in the photoresist layer 93 FIG. 15A to FIG. 14C Describe the processing steps. Fig.21A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a third exemplary structure after forming a contact level dielectric layer 80, removing material portions above the substrate (9, 10) from the kerf area, forming a patterned conductive hard mask layer 97, and forming drain contact via cavities 87 (including contact level via cavities 287) according to an embodiment of the present disclosure. The various insets provide enlarged views within the semiconductor die 900. Fig. 21B yes Fig.21AFIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 21C yes Fig.21A and Fig. 21B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG. Fig.21D It is along Fig. 21B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'. Fig.21E is along Fig. 21B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'.

[0231] Specifically, a contact-level dielectric layer 80 may be formed over the semiconductor device on the semiconductor substrate (9, 10) and over the dielectric material portion 65. The contact-level dielectric layer 80 includes a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride and may have a thickness in the range of 100 nm to 600 nm, although lesser and greater thicknesses may also be employed.

[0232] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and may be photolithographically patterned to cover areas of the semiconductor die 900 but not the kerf regions 902. An etching process such as an anisotropic etching process may be performed to remove material portions from the kerf regions 902 in the wafer 1000. The semiconductor die 900 may be separated above a horizontal plane including the top surface of the semiconductor substrate (9, 10). The photoresist layer may then be removed, for example, by ashing. Each semiconductor die 900 may include a corresponding dielectric material portion, i.e., as in FIG. 3A to FIG. 3C The patterned remainder of the dielectric material portion 65 formed at the processing step.

[0233] Generally, at least one conductive structure, such as at least one conductive pillar structure 176, can be formed in the peripheral region of the semiconductor die 900 through below the contact level dielectric layer 80. In one embodiment, the at least one conductive structure includes at least one conductive pillar structure 176 that contacts the top surface of the semiconductor substrate (9, 10). In one embodiment, the at least one conductive pillar structure 176 is formed before forming the contact level dielectric layer 80. The contact level dielectric layer 80 is formed on the at least one conductive pillar structure 176.

[0234] Subsequently, a photoresist layer 93 may be formed above the two-dimensional array of semiconductor die 900 and may be photolithographically patterned to form various discrete openings in the photoresist layer. The pattern of the openings in the photoresist layer 93 may be transferred through the contact level dielectric layer 80 and the capping dielectric layer 73 (if present) below the openings in the photoresist layer 93. At least one pair of contact level via cavities 287 may be formed directly on the top surface of each conductive pillar structure 176 through the contact level dielectric layer 80. Each pair of contact level via cavities 287 may be spaced apart by different lateral distances from the nearest sidewalls of the semiconductor die 900 (which may be the sidewalls of the dielectric material portion 65). During the same etching step as the contact level via cavities 287, a drain contact via cavity 87 is formed above the top surface of the drain region 63 through the contact level dielectric layer 80 and the capping dielectric layer 73. Drain contact via cavities 87 extend through contact level dielectric layer 80 down to the top surface of drain region 63. The top surface of drain region 63 may be physically exposed at the bottom of each drain contact via cavity 87. Photoresist layer 93 may then be removed, for example, by ashing.

[0235] refer to FIG. 22A to FIG. 22E , a conductive hard mask layer 97 can be formed above the contact level dielectric layer, on the sidewalls of the dielectric material portion 65, on the physically exposed surface segments of the semiconductor substrate (9, 10) in the cutout region 902, and within each of the drain contact via cavity 87 and the contact level via cavity 287. Fig.22A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a third exemplary structure according to an embodiment of the present disclosure after forming a conductive hard mask layer 97 by depositing at least one conductive material in drain contact via cavity 87 and contact level via cavity 287. The various insets provide enlarged views within the die. Fig. 22B yes Fig.22A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig. 22C yes Fig.22A and Fig. 22B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG. Fig.22D It is along Fig. 22B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'. Fig.22E is along Fig. 22B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'.

[0236] Specifically, a conductive hard mask layer 97 may be formed over the dielectric material portion 65 over the semiconductor device and over the entire area of ​​the wafer 1000. The conductive hard mask layer 97 may include a conductive nitride liner 971L including a conductive nitride material such as TiN, TaN, WN and / or MoN and a metal layer 972L including a metal such as W, Ti, Ta, W, Co, Ru, etc. and / or a metal alloy. The conductive hard mask layer 97 may be deposited by a conformal or non-conformal deposition process, as long as the top horizontal portion of the conductive hard mask layer 97 overlying the contact level dielectric layer 80 is connected to the bottom horizontal portion of the conductive hard mask layer 97 formed in the kerf region 902 and contacts the top surface of the semiconductor substrate (9, 10) through the vertically extending portion of the conductive hard mask layer 97 located on the sidewalls of the semiconductor die 900 (including the sidewalls of the dielectric material portion 65). For example, the conductive hard mask layer 97 may be formed by chemical vapor deposition, physical vapor deposition, electroplating, and / or electroless plating. In one embodiment, the top horizontal portion of the conductive hard mask layer 97 overlying the contact level dielectric layer 80 of the semiconductor die 900 may have a thickness in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the conductive hard mask layer 97 extends continuously over the sidewalls of the dielectric material portion 65 of each semiconductor die 900 and contacts a section of the top surface of the semiconductor substrate (9, 10) located in the kerf region 902, which is located between the semiconductor die 900 and an additional semiconductor die 900 located on the semiconductor substrate (9, 10).

[0237] refer to FIG. 23A to FIG. 23E , the conductive hard mask layer 97 is patterned to have openings, and the pattern of the openings in the conductive hard mask layer 97 can be transferred to the underlying dielectric material portion to form various via cavities ( 85 , 7P) and moat trenches 91 . Fig.23A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a third exemplary structure after patterning a conductive hard mask layer 97 and through forming various via cavities and moat trenches according to an embodiment of the present disclosure. The various insets provide enlarged views within the die. Fig. 23B yes Fig.23A FIG. 1 is a top view of a unit area UA of a wafer 1000 .

[0238] Fig.23C yes Fig.23A and Fig. 23B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG. Fig.23D It is along Fig. 23B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'. Fig.23E is along Fig. 23B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'.

[0239] A photoresist layer (not shown) may be applied over the conductive hard mask layer 97 and may be photolithographically patterned to form various openings in the photoresist layer. The various openings in the photoresist layer may include discrete contact openings 97C that overlie the stepped surface of the conductive layer 46 and optionally also overlie the peripheral device 700. According to one aspect of the present disclosure, at least one trench-shaped opening 97E may be formed in the photoresist layer along the entire perimeter of the top surface of the corresponding horizontal top portion of the conductive hard mask layer 97. In one embodiment, the at least one trench-shaped opening may include a plurality of trench-shaped openings 97E nested in each other. A first anisotropic etching process may be performed to transfer the pattern of the openings (97C, 97E) in the photoresist layer through the conductive hard mask layer 97.

[0240] Openings may be formed through the conductive hard mask layer 97 beneath the openings (97C, 97E) in the photoresist layer. A subset of the contact openings 97C in the conductive hard mask layer 97 is formed above the stepped surface of the conductive layer 46 and the peripheral device 700. At least one trench-shaped opening 97E may be formed through the conductive hard mask layer 97 along the periphery of the dielectric material portion 65 in each semiconductor die 900. The at least one trench-shaped opening 97E is subsequently used to define the area of ​​at least one edge seal structure and is therefore referred to herein as at least one edge seal opening 97E. In one embodiment, each edge seal opening 97E surrounds an interior region of the dielectric material portion 65 and overlies a corresponding conductive bridge structure (including the conductive pillar structure 176). According to one aspect of the present disclosure, each edge seal opening 97E within the conductive hard mask layer 97 extends between at least one pair of contact level through-hole cavities 287 filled with the conductive hard mask layer 97 (e.g., Fig.23E ). The set of contact openings 97C passing through the conductive hard mask layer 97 may be formed in a region surrounded by at least one trench-shaped opening 97E in the conductive hard mask layer 97. Optionally, the photoresist layer may be removed, for example, by ashing.

[0241] The pattern of the openings (97C, 97E) in the conductive hard mask layer 97 can be transferred through the underlying dielectric material portion by performing at least one second anisotropic etching process. In one embodiment, the pattern of all openings in the conductive hard mask layer 97 can be transferred through the underlying material portion by a single second anisotropic etching process. Alternatively, at least one patterned photoresist layer can be employed to cover a corresponding subset of the openings in the conductive hard mask layer 97, and multiple second anisotropic etching processes can be performed to form a corresponding set of via cavities under the corresponding subset of openings in the conductive hard mask layer 97 that are not masked by the corresponding patterned photoresist layer.

[0242] In an illustrative example, the various via cavities formed by the at least one second anisotropic etching process may include a layer contact via cavity 85, a perimeter contact via cavity 7P, and at least one moat trench 91. A drain contact via cavity 87 is formed through the contact level dielectric layer 80 and the capping dielectric layer 73 over the physically exposed top surface of the corresponding drain region 63. A layer contact via structure 85 is formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 over the top surface of the corresponding conductive layer 46. A perimeter contact via cavity 87 is formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 over the physically exposed top surface of the corresponding node of the perimeter device 700. At least one moat trench 91 is formed through the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 over the physically exposed top surface of the semiconductor substrate (9, 10) and over at least one conductive pillar structure 176. A horizontal surface section of each conductive pillar structure 176 may be vertically recessed relative to a horizontal plane including a bottom surface of the contact-level dielectric layer 80 .

[0243] A set of contact via cavities (85, 7P) may be formed through the contact level dielectric layer 80 down to the top surface of the conductive node of the semiconductor device in the semiconductor die 900 by performing at least one second anisotropic etching process. The at least one second anisotropic etching process may selectively etch the material of the contact level dielectric layer 80, the insulating cap layer 70, and the dielectric material portion 65 for the semiconductor device. According to one aspect of the present disclosure, at least one moat trench 91 may be formed through the dielectric material portion 65 within each semiconductor die 900 down to the top surface of the semiconductor substrate (9, 10) by performing an anisotropic etching process that etches the material of the dielectric material portion 65 below the trench-shaped opening 97E in the conductive hard mask layer 97. The width of each moat trench 91 may be in the range of 0.5 microns to 30 microns, such as 1 micron to 15 microns, although smaller and larger lateral offset distances may also be employed. In one embodiment, the entire area of ​​the dielectric material portion 65 between the innermost moat trench of the at least one moat trench 91 and the sidewalls of the semiconductor die 900 may be free of any semiconductor devices.

[0244] According to one aspect of the present disclosure, each point within the conductive hard mask layer 97 is electrically connected to the surface of a segment of the top surface of the semiconductor substrate (9, 10) through a corresponding conductive discharge path located below the conductive hard mask layer 97 and forming a conductive bridge structure. For example, each point within a portion of the conductive hard mask layer 97 located within an area surrounded by at least one moat-shaped opening in the conductive hard mask layer 97 is electrically connected to the semiconductor substrate (9, 10) through at least one conductive bridge structure, the at least one conductive bridge structure including at least one conductive pillar structure 176. Therefore, any charges (e.g., electrons) accumulated in the conductive hard mask layer 97 during the anisotropic etching process can be discharged to the semiconductor substrate (9, 10) through the corresponding discharge path. Therefore, arc discharge can be reduced or avoided during one or more anisotropic etching processes to form the contact via cavity (85, 7P) and at least one moat trench 91 in each memory die 900. According to one aspect of the present disclosure, electrical grounding of the conductive hard mask layer 97 is provided throughout the conductive hard mask layer 97 , and thus, arc discharge may be completely prevented during at least one second anisotropic etching process.

[0245] The top portion of each conductive pillar structure 176 may be recessed in parallel between adjacent portions of the corresponding moat trench 91. As described above with respect to the previous embodiment, each moat trench 91 may include at least one deep trench section extending vertically from the top surface of the contact level dielectric layer 80 to the top surface of the semiconductor substrate (9, 10) and at least one shallow trench section overlying the recessed top surface of the corresponding conductive pillar structure 176. Thus, each moat trench 91 may extend continuously around and around the area of ​​the semiconductor die 900 without gaps. Thus, each moat trench 91 may be a continuous moat trench including at least one deep trench portion extending vertically downward to the top surface of the semiconductor substrate (9, 10) and at least one shallow trench portion overlying the horizontal surface of the conductive bridge structure (including the conductive pillar structure 176), which is recessed below the horizontal plane including the top surface of the contact level dielectric layer 80.

[0246] In general, each of the at least one conductive bridge structure (such as the at least one conductive pillar structure 176) is electrically isolated from the semiconductor substrate (9, 10) before forming the conductive hard mask layer 97, and then electrically connected to the semiconductor substrate (9, 10) through the conductive hard mask layer 97 after forming the conductive hard mask layer 97 during each of the at least one second anisotropic etching process. During each of the at least one second anisotropic etching process, charge is released from each portion of the conductive hard mask layer 97 into the semiconductor substrate (9, 10). In one embodiment, the conductive hard mask layer 97 is formed over the sidewalls of the dielectric material portion 65 and on the top surface of the semiconductor substrate (9, 10). In one embodiment, the at least one second anisotropic etching process etches the material of the dielectric material portion 65 selectively to the material of the conductive bridge structure (including the conductive pillar structure 176), the conductive hard mask layer 97, and the semiconductor substrate (9, 10). Portions of the conductive pillar structures 176 that are not masked by the conductive hard mask layer 97 may be recessed in parallel during at least one second anisotropic etching process. The recess depth of the vertically recessed top surface of the conductive plate 188 may be in the range of 1% to 50%, such as 5% to 25%, of the sum of the thicknesses of the capping dielectric layer 73 and the contact level dielectric layer 80. The conductive hard mask layer 97 may be partially removed in parallel during at least one second anisotropic etching process.

[0247] During and after the anisotropic etching process, each conductive bridge structure (including the conductive pillar structure 176) connects an inner portion of the conductive hard mask layer 97 located inside the inner perimeter of the at least one edge seal opening 97E to an outer portion of the conductive hard mask layer 97 located outside the outer perimeter of the at least one edge seal opening 97E. The conductive hard mask layer 97 may then be removed, for example, by a selective isotropic recess etching process such as a wet etching process.

[0248] refer to FIG. 24A to FIG. 24E Various contact via structures ( 86 , 8P) and at least one conductive edge seal structure 92 may be formed in the various contact via cavities ( 85 , 7P) and at least one moat trench 91 . Fig.24A is a vertical cross-sectional view of a unit area UA of a wafer 1000 including a third exemplary structure after forming various metal via structures (86, 8P) and a conductive edge seal structure 92 according to an embodiment of the present disclosure. The various insets provide magnified views within the semiconductor die. Fig. 24B yes Fig.24A FIG. 1 is a top view of a unit area UA of a wafer 1000 . Fig.24C yes Fig.24A and Fig. 24B A vertical cross-sectional view of a region of a third exemplary structure within a die is shown in FIG. Fig.24D It is along Fig. 24B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane DD'. Fig.24E is along Fig. 24B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane EE'.

[0249] Specifically, at least one conductive material is deposited in various contact via cavities (85, 7P) and at least one moat trench 91. In one embodiment, at least one conductive material may include a conductive nitride liner material and a conductive filling material, which may be a metal or an intermetallic alloy. For example, the conductive nitride liner material may include TiN, TaN, WN and / or MoN. The conductive filling material may include W, Ti, Ta, Mo, Ru, Co, Cu or an alloy thereof. At least one conductive material may be deposited, for example, by chemical vapor deposition, physical vapor deposition, electroplating and / or chemical plating. Excess portions of at least one conductive material and metal layer 97 may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process.

[0250] Each remaining portion of the at least one conductive material filling the layer contact via cavity 85 constitutes a layer contact via structure 86. Each remaining portion of the at least one conductive material filling the perimeter contact via cavity 7P constitutes an optional perimeter contact via structure 8P. Each remaining portion of the at least one conductive material filling the moat trench 91 constitutes a conductive edge seal structure 92. Each remaining portion of the metal layer 97 filling the contact level via cavity 287 constitutes a contact level via structure 288 that contacts a corresponding one of the conductive pillar structures 176. Each remaining portion of the metal layer 97 filling the drain contact via cavity 87 constitutes a drain contact via structure 88.

[0251] In one embodiment, each of the contact via structures (86, 8P) includes a conductive contact liner (86A, 8PA) and a conductive fill material portion (86B, 8PB) embedded within the conductive contact liner (86A, 8PA). Each conductive edge seal structure 92 includes a conductive edge seal liner 92A and a conductive edge seal fill material portion 92B embedded within the conductive edge seal liner 92A. In one embodiment, the conductive contact liner (86A, 8PA) and the conductive edge seal liner 92A have a first conductive composition (i.e., a material composition of the conductive nitride liner material) and have the same thickness, and the conductive edge seal fill material portion 92B and the conductive fill material portion (86B, 8PB) have a second conductive composition (i.e., a material composition of the conductive fill material).

[0252] In one embodiment, inner dielectric material portion 65I laterally surrounds the semiconductor device of each semiconductor die 900. Each conductive edge seal structure 92 laterally surrounds inner dielectric material portion 65I, extends vertically from at least the semiconductor substrate (9, 10) to a horizontal plane including the topmost surface of inner dielectric material portion 65I, and may have straight sidewalls extending laterally parallel to the outer sidewalls closest to the outer sidewalls of semiconductor die 900. In one embodiment, outer dielectric material portion 65O laterally surrounds each conductive edge seal structure 92.

[0253] In one embodiment, the outer sidewalls of outer dielectric material portion 650 are outer sidewalls of semiconductor die 900. In one embodiment, outer dielectric material portion 650 is not in direct contact with any of the semiconductor devices in semiconductor die 900.

[0254] In one embodiment, semiconductor die 900 includes metal interconnect structures, outer dielectric material portion 65O is not in direct contact with any of the metal interconnect structures, and all of the metal interconnect structures are laterally surrounded by at least one conductive edge seal structure 92. In one embodiment, semiconductor die 900 includes a contact level dielectric layer 80 overlying the semiconductor device, inner dielectric material portion 65I, and outer dielectric material portion 65O, wherein at least one conductive edge seal structure 92 extends vertically through contact level dielectric layer 80 and dielectric material portions (65I, 65O).

[0255] In one embodiment, semiconductor die 900 includes contact via structures (88, 86, 8P) that extend vertically through contact level dielectric layer 80 and contact top surfaces of conductive nodes of the semiconductor device and have top surfaces that are located in the same horizontal plane as top surfaces of conductive edge seal structures 92. In one embodiment, the semiconductor device includes alternating stacks of insulating layers 32 and conductive layers 46 and memory opening filling structures 58 that are located within memory openings 49 that extend vertically through the alternating stacks and include vertical semiconductor channels 60 and corresponding vertical stacks of memory elements. In one embodiment, each of memory opening filling structures 58 includes a NAND string, conductive layer 46 includes a word line of the NAND string, and the conductive nodes of the semiconductor device include the word lines. In some embodiments, during the formation of at least one conductive edge seal structure 92, the memory opening filling structures 58 may be formed. FIG. 24A to FIG. 24E The conductive hard mask layer 97 is removed after the processing steps.

[0256] refer to Figures 1 to 11C and FIG. 19A to FIG. 24E And according to various embodiments of the present disclosure, a semiconductor die 900 is provided, which includes: a semiconductor device, which is located above a semiconductor substrate (9, 10); an internal dielectric material portion 65I, which laterally surrounds the semiconductor device; a contact-level dielectric layer 80, which overlies the semiconductor device and the internal dielectric material portion 65I; a conductive bridge structure (including a conductive column structure 176 and a contact-level through-hole structure 288), which has at least one top surface located in a horizontal plane including the top surface of the contact-level dielectric layer 80; a conductive edge sealing structure 92, which laterally surrounds the internal dielectric material portion 65I, extends vertically from the semiconductor substrate (9, 10) to a horizontal plane including the top surface of the contact-level dielectric layer 80, and extends above at least one surface of the conductive bridge structure (176, 288) and contacts the at least one surface; and an external dielectric material portion 65O, which laterally surrounds the conductive edge sealing structure 92.

[0257] In one embodiment, the conductive edge sealing structure 92 includes: at least one wall portion (which fills the corresponding deep moat segment of the moat trench 91) extending vertically from the semiconductor substrate (9, 10) to a horizontal plane including the top surface of the contact-level dielectric layer 80; and a connecting portion (which fills the corresponding shallow moat segment of the moat trench 91) overlying the conductive bridge structure (including the conductive column structure 176).

[0258] In one embodiment, semiconductor die 900 includes contact via structures ( 88 , 86 , 8P) that extend vertically through contact level dielectric layer 80 and contact conductive nodes of the semiconductor device and have top surfaces that lie in the same horizontal plane as a top surface of conductive edge seal structure 92 . In one embodiment, the conductive edge sealing structure 92 includes a conductive edge sealing pad 92A and a conductive edge sealing filling material portion 92B embedded in the conductive edge sealing pad 92A; each contact through-hole structure (88, 86, 8P) in the contact through-hole structure includes a conductive contact pad (88A, 86A, 8PA) and a conductive filling material portion (88B, 86B, 8PB) embedded in the conductive contact pad (88A, 86A, 8PA); the conductive contact pad (88A, 86A, 8PA) and the conductive edge sealing pad 92A have a first conductive composition and have the same thickness; and the conductive edge sealing filling material portion 92B and the conductive filling material portion (88B, 86B, 8PB) have a second conductive composition.

[0259] In one embodiment, the semiconductor device includes: an alternating stack of insulating layers 32 and conductive layers 46; and a memory opening filling structure 58 located within a memory opening 49 extending vertically through the alternating stack and including a corresponding vertical semiconductor channel 60 and a vertical stack of memory elements (e.g., portions of layer 54). In one embodiment, each of the memory opening filling structures 58 includes a NAND string; the conductive layers 46 include a word line of the NAND string; and the conductive nodes of the semiconductor device include the word lines.

[0260] Various embodiments of the present disclosure may be used to reduce or eliminate arcing during at least one anisotropic etching process that employs the conductive hard mask layer 97 as an etch mask to form various via cavities in the semiconductor die 900 by providing a conductive path to the semiconductor substrate (9, 10).

[0261] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments employing specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A method for manufacturing a semiconductor structure, the method comprising: forming a semiconductor die including a semiconductor device and a dielectric material portion over a semiconductor substrate, wherein the dielectric material portion laterally surrounds the semiconductor device; forming a conductive hard mask layer over the semiconductor device and the dielectric material portion; forming a set of peripheral discrete openings through the conductive hard mask layer along a perimeter of the dielectric material portion; forming a set of peripheral discrete via cavities through the dielectric material portion down to a top surface of the semiconductor substrate by performing an anisotropic etching process that etches material of the dielectric material portion underlying the set of peripheral discrete openings; forming a continuous moat trench laterally surrounding an interior region of the dielectric material portion by isotropically expanding the set of peripheral discrete via cavities; as well as A conductive edge seal structure is formed by filling the continuous moat trench with at least one conductive material.

2. The method according to claim 1, wherein: The sidewalls of the semiconductor die include sidewalls of the dielectric material portion exposed to a cutout region between the semiconductor die and at least one of an edge of the semiconductor substrate or an additional semiconductor die located above the semiconductor substrate; and A region of the dielectric material portion between the continuous moat trench and the sidewalls of the semiconductor die is free of any semiconductor devices.

3. The method of claim 1, wherein all sidewall surfaces of the set of perimeter discrete via cavities are dielectric surfaces. 4 . The method of claim 1 , further comprising forming a contact-level dielectric layer over the semiconductor device and the dielectric material portion, wherein the set of perimeter discrete via cavities are formed through the contact-level dielectric layer.

5. The method according to claim 4, further comprising: forming a set of contact openings through the conductive hard mask layer within an area surrounded by the set of peripheral discrete openings; as well as A set of contact via cavities is formed through the set of contact openings and the contact level dielectric layer down to a top surface of a conductive node of the semiconductor device by performing the anisotropic etching process, wherein the anisotropic etching process etches material of the contact level dielectric layer selective to the semiconductor device.

6. The method according to claim 5, wherein the semiconductor device comprises: Alternating stacking of insulating and conducting layers; and A memory opening filling structure is located within the memory openings extending vertically through the alternating stack and includes a respective vertical semiconductor channel and a respective vertical stack of memory elements.

7. The method according to claim 6, wherein: Each of the memory opening filling structures includes a NAND string; The conductive layer includes a word line of the NAND string; and The conductive node of the semiconductor device includes the word line.

8. The method of claim 1, wherein a maximum nearest neighbor distance within the perimeter discrete via cavity is less than a maximum lateral dimension of each perimeter discrete via cavity within the set of perimeter discrete via cavities.

9. The method of claim 1, wherein the continuous moat trench comprises: a laterally undulating outer sidewall having horizontal concave outer surface sections abutting one another; and A laterally undulating inner sidewall having horizontal concave inner surface sections abutting each other.

10. The method of claim 1 , wherein the conductive hard mask layer extends continuously over the sidewalls of the dielectric material portion and contacts a segment of the top surface of the semiconductor substrate located in a cutout region between the semiconductor die and an edge of the semiconductor substrate or at least one of additional semiconductor dies located on the semiconductor substrate. 11 . The method of claim 10 , wherein each point within the conductive hard mask layer is electrically connected to a surface of the segment of the top surface of the semiconductor substrate through a corresponding conductive path located entirely within the conductive hard mask layer. 12 . The method of claim 1 , further comprising removing the conductive hard mask layer before, during, or after forming the conductive edge seal structure.

13. A semiconductor die, the semiconductor die comprising: A semiconductor device, wherein the semiconductor device is located above a semiconductor substrate; an inner dielectric material portion, the inner dielectric material portion laterally surrounding the semiconductor device; a conductive edge seal structure laterally surrounding the inner dielectric material portion, extending vertically from at least the semiconductor substrate to a horizontal plane including a topmost surface of the inner dielectric material portion, and having a laterally undulating inner sidewall and a laterally undulating outer sidewall; and An outer dielectric material portion laterally surrounds the conductive edge seal structure.

14. The semiconductor die of claim 13, wherein: The laterally undulating inner sidewall and the laterally undulating outer sidewall extend laterally generally parallel to a nearest outer sidewall of the outer sidewalls of the semiconductor die; The outer sidewall of the outer dielectric material portion includes an outer sidewall of the semiconductor die; Each of the laterally undulating outer sidewalls has respective horizontal concave outer surface sections abutting one another; and Each of the laterally undulating inner sidewalls has respective horizontal concave inner surface sections abutting one another.

15. The semiconductor die of claim 13, wherein: The outer dielectric material portion is not in direct contact with any of the semiconductor devices of the semiconductor die; The semiconductor die includes a metal interconnect structure; The outer dielectric material portion is not in direct contact with any of the metal interconnect structures; and All of the metal interconnect structures are laterally surrounded by the conductive edge seal structure.

16. The semiconductor die of claim 13, further comprising a contact level dielectric layer overlying the semiconductor device, the inner dielectric material portion, and the outer dielectric material portion, wherein the conductive edge seal structure extends vertically through the contact level dielectric layer.

17. The semiconductor die of claim 16, further comprising a contact via structure extending vertically through the contact level dielectric layer and contacting a top surface of a conductive node of the semiconductor device and having a top surface that is within the same horizontal plane as a top surface of the conductive edge seal structure.

18. The semiconductor die of claim 17, wherein the semiconductor device comprises: Alternating stacking of insulating and conducting layers; and A memory opening filling structure is located within the memory openings extending vertically through the alternating stack and includes a vertical semiconductor channel and a corresponding vertical stack of memory elements.

19. The semiconductor die of claim 18, wherein: Each of the memory opening filling structures includes a NAND string; The conductive layer includes a word line of the NAND string; and The conductive node of the semiconductor device includes the word line.

20. The semiconductor die of claim 17, wherein: The conductive edge seal structure includes a conductive edge seal gasket and a conductive edge seal filling material portion embedded in the conductive edge seal gasket; Each of the contact via structures comprises a conductive contact pad and a conductive filling material portion embedded in the conductive contact pad; The conductive contact pad and the conductive edge seal pad have a first conductive composition and have a same thickness; and The conductive edge seal fill material portion and the conductive fill material portion have a second conductive composition.

21. A method for manufacturing a semiconductor structure, the method comprising: forming a semiconductor die including a semiconductor device and a dielectric material portion over a semiconductor substrate, wherein the dielectric material portion laterally surrounds the semiconductor device; forming a contact level dielectric layer over the semiconductor device and the dielectric material portion; forming a conductive bridge structure through or beneath the contact level dielectric layer in a peripheral region of the semiconductor die; forming a conductive hard mask layer over the contact level dielectric layer and the conductive bridge structure; forming an edge seal opening through the conductive hard mask layer along a perimeter of the dielectric material portion, wherein an inner portion of the conductive hard mask layer within an area surrounded by an inner perimeter of the edge seal opening is electrically connected to the semiconductor substrate through the conductive bridge structure and through vertically extending portions of the conductive hard mask layer; forming a continuous moat trench by anisotropically etching a region of the dielectric material portion located below the edge seal opening; as well as A conductive edge seal structure is formed by filling the continuous moat trench with at least one conductive material.

22. The method of claim 21, wherein during the anisotropic etching step, charges are released from each portion of the conductive hard mask layer into the semiconductor substrate.

23. The method of claim 21, wherein the conductive hard mask layer is formed over sidewalls of the dielectric material portion and on a top surface of the semiconductor substrate.

24. The method of claim 21, wherein the anisotropic etching step removes material of the dielectric material portion selective to material of the conductive bridge structure, the conductive hard mask layer, and the semiconductor substrate.

25. The method of claim 21, wherein the edge seal opening surrounds an interior region of the dielectric material portion and overlies the conductive bridge structure.

26. The method of claim 21, wherein after the anisotropic etching step, the conductive bridge structure connects the inner portion of the conductive hard mask layer to an outer portion of the conductive hard mask layer outside an outer perimeter of the edge seal opening.

27. The method of claim 21, further comprising removing the conductive hard mask layer before, during, or after forming the conductive edge seal structure.

28. A method according to claim 21, wherein the continuous moat trench includes at least one deep trench portion extending vertically downward to the top surface of the semiconductor substrate and at least one shallow trench portion overlying a horizontal surface of the conductive bridge structure, the horizontal surface being recessed below a horizontal plane including the top surface of the contact level dielectric layer.

29. The method of claim 21, wherein: The semiconductor device comprises: an alternating stack of insulating layers and conductive layers, and a memory opening filling structure extending vertically through the alternating stack; and Each of the memory opening filling structures comprises a vertical semiconductor channel, a drain region located above the vertical semiconductor channel and a respective vertical stack of memory elements at the level of the conductive layer.

30. The method according to claim 29, further comprising: forming at least one edge region recessed cavity and a drain contact via cavity through the contact level dielectric layer, wherein the drain contact via cavity extends through the contact level dielectric layer downward to a top surface of the drain region; as well as The conductive bridge structure is formed in the at least one edge region recessed cavity.

31. A method according to claim 30, wherein the conductive bridge structure includes a conductive plate, which extends through the contact level dielectric layer, has a bottom surface located above the top surface of the semiconductor substrate, is electrically isolated from the semiconductor substrate before forming the conductive hard mask layer, and is electrically connected to the semiconductor substrate through the conductive hard mask layer when forming the conductive hard mask layer.

32. The method of claim 21, wherein: The conductive bridge structure includes at least one conductive pillar structure, which is formed before forming the contact-level dielectric layer, is located below the contact-level dielectric layer, and contacts the top surface of the semiconductor substrate; The contact-level dielectric layer is formed on the at least one conductive pillar structure; and The conductive edge seal structure is formed on a top surface of the at least one conductive pillar structure.

33. A semiconductor die, the semiconductor die comprising: A semiconductor device, wherein the semiconductor device is located above a semiconductor substrate; an inner dielectric material portion, the inner dielectric material portion laterally surrounding the semiconductor device; a contact level dielectric layer, the contact level dielectric layer overlying the semiconductor device and the inner dielectric material portion; a conductive bridge structure having at least one top surface located within a horizontal plane including a top surface of the contact level dielectric layer; a conductive edge seal structure laterally surrounding the inner dielectric material portion, extending vertically from the semiconductor substrate to the horizontal plane including the top surface of the contact level dielectric layer, and extending over and contacting at least one surface of the conductive bridge structure; and An outer dielectric material portion laterally surrounds the conductive edge seal structure.

34. The semiconductor die of claim 33, wherein the conductive edge seal structure comprises: at least one wall portion extending vertically from the semiconductor substrate to the horizontal plane including the top surface of the contact-level dielectric layer; and Overlying the connecting portion of the conductive bridge structure.

35. The semiconductor die of claim 33, wherein the conductive bridge structure comprises a conductive plate, and a bottommost surface of the conductive bridge structure is above and vertically spaced apart from the semiconductor substrate.

36. The semiconductor die of claim 33, wherein the conductive bridge structure comprises a conductive pillar structure contacting a top surface of the semiconductor substrate and a pair of contact-level metal via structures contacting a top surface of the conductive pillar structure.

37. The semiconductor die of claim 33, further comprising a contact via structure extending vertically through the contact level dielectric layer and contacting a conductive node of the semiconductor device and having a top surface that is within the same horizontal plane as a top surface of the conductive edge seal structure.

38. The semiconductor die of claim 37, wherein: The conductive edge seal structure includes a conductive edge seal gasket and a conductive edge seal filling material portion embedded in the conductive edge seal gasket; Each of the contact via structures comprises a conductive contact pad and a conductive filling material portion embedded in the conductive contact pad; The conductive contact pad and the conductive edge seal pad have a first conductive composition and have a same thickness; and The conductive edge seal fill material portion and the conductive fill material portion have a second conductive composition.

39. The semiconductor die of claim 37, wherein the semiconductor device comprises: Alternating stacking of insulating and conducting layers; and A memory opening filling structure is located within the memory openings extending vertically through the alternating stack and includes a respective vertical semiconductor channel and a respective vertical stack of memory elements.

40. The semiconductor die of claim 39, wherein: Each of the memory opening filling structures includes a NAND string; The conductive layer includes a word line of the NAND string; and The conductive node of the semiconductor device includes the word line.

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