Substrate processing apparatus

Abstract

A substrate processing apparatus is provided. The substrate processing apparatus includes a chamber, a base, an electrostatic holding disk, a control circuit, and a detection circuit. The electrostatic holding disk is disposed on the base. The electrostatic retention disk includes a dielectric member, at least one heater electrode layer, and at least one resistive layer. The dielectric member has a substrate support surface. The at least one heater electrode layer is formed of a first material. The at least one resistive layer is formed of a second material. The at least one resistive layer has a thickness of 300 [mu] m or less. The resistance temperature coefficient of the second material is greater than the resistance temperature coefficient of the first material.

Description

Technical Field

[0001] An exemplary embodiment of the present disclosure relates to a substrate processing apparatus. Background Art

[0002] A substrate processing apparatus is used for processing a substrate. The substrate processing apparatus includes a chamber, a susceptor disposed in the chamber, and an electrostatic holding disk disposed on the susceptor. In Patent Document 1 listed below, a heater is disposed in the electrostatic holding disk.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-163902 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] The present disclosure provides a technique for determining the temperature of an electrostatic holding disk.

[0008] Solutions for solving problems

[0009] In an exemplary embodiment, a substrate processing device is provided. The substrate processing device includes a chamber, a base, an electrostatic holding disk, a control circuit, and a detection circuit. The chamber provides a processing space inside. The base is arranged in the processing space. The base provides an internal space inside. The electrostatic holding disk is arranged on the base. The electrostatic holding disk includes a dielectric member, at least one heater electrode layer, and at least one resistor layer. The dielectric member has a support surface. The support surface includes a substrate support surface. At least one heater electrode layer is arranged in the dielectric member. At least one heater electrode layer is formed of a first material. At least one resistor layer is arranged in the dielectric member. At least one resistor layer is formed of a second material. At least one resistor layer is at least one resistor layer having a thickness of less than 300 μm. The resistance temperature coefficient of the second material is greater than the resistance temperature coefficient of the first material. The control circuit is arranged in the internal space. The control circuit is configured to control the applied power applied to at least one heater electrode layer. The detection circuit is arranged in the internal space. The detection circuit is configured to detect the voltage applied to at least one resistor layer.

[0010] Effects of the Invention

[0011] According to one exemplary embodiment, a technique for determining the temperature of an electrostatic holding disk is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram for explaining a configuration example of a plasma processing system.

[0013] Figure 2 It is a diagram for explaining a configuration example of a capacitive coupling type plasma processing apparatus.

[0014] Figure 3 FIG. 1 is a partially enlarged cross-sectional view of a substrate support portion according to an exemplary embodiment.

[0015] Figure 4 It is an exploded perspective view showing the structure of an electrostatic holding disk according to an exemplary embodiment.

[0016] Figure 5 : is a diagram showing the structure of a detection circuit according to an exemplary embodiment.

[0017] Figure 6 FIG. 1 is a plan view showing the structure of a plurality of zones of an electrostatic holding disk according to an exemplary embodiment.

[0018] Figure 7 It is a partially enlarged cross-sectional view of an electrostatic holding disk according to another exemplary embodiment.

[0019] Figure 8 It is a partially enlarged cross-sectional view of an electrostatic holding disk according to still another exemplary embodiment.

[0020] Fig. 9 It is a partially enlarged cross-sectional view of an electrostatic holding disk according to still another exemplary embodiment.

[0021] Fig.10 It is a partially enlarged cross-sectional view of an electrostatic holding disk according to still another exemplary embodiment.

[0022] Fig.11 It is a partially enlarged cross-sectional view of an electrostatic holding disk according to still another exemplary embodiment.

[0023] Fig.12 : is a diagram showing the structure of a detection circuit according to another exemplary embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In addition, in each of the drawings, the same reference numerals are given to the same or corresponding parts.

[0025] Reference Figure 1 and Figure 2 A plasma processing apparatus as a substrate processing apparatus according to an exemplary embodiment will be described.

[0026] Figure 1: is a diagram for illustrating a structural example of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing device 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing device 1 is an example of a substrate processing device. The plasma processing device 1 includes a plasma processing chamber 10, a substrate support portion 11, and a plasma generating portion 12. The plasma processing chamber 10 has a plasma processing space. In addition, the plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to the gas supply portion 20 described later, and the gas exhaust port is connected to the exhaust system 40 described later. The substrate support portion 11 is arranged in the plasma processing space and has a substrate supporting surface for supporting a substrate.

[0027] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be a capacitively coupled plasma (CCP: Capacitively Coupled Plasma), an inductively coupled plasma (ICP: Inductively Coupled Plasma), an ECR plasma (Electron-Cyclotron-Resonance Plasma: Electron Cyclotron Resonance Plasma), a helicon wave excited plasma (HWP: Helicon Wave Plasma; helicon wave plasma) or a surface wave plasma (SWP: Surface Wave Plasma), etc. In addition, various types of plasma generating units including an AC (Alternating Current: Alternating Current) plasma generating unit and a DC (Direct Current: Direct Current) plasma generating unit may be used. In one embodiment, the AC signal (AC power) used in the AC plasma generating unit has a frequency in the range of 100kHz to 10GHz. Therefore, the AC signal includes an RF (Radio Frequency: Radio Frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100kHz to 150MHz.

[0028] The control unit 2 processes computer-executable commands that cause the plasma processing device 1 to perform various processes described in the present disclosure. The control unit 2 can be configured to control the various elements of the plasma processing device 1 to perform the various processes described herein. In one embodiment, a part or all of the control unit 2 may also be included in the plasma processing device 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is implemented, for example, by a computer 2a. The processing unit 2a1 can be configured to perform various control actions by reading a program from the storage unit 2a2 and executing the read program. The program can be stored in the storage unit 2a2 in advance, or it can be obtained via a medium when necessary. The obtained program is stored in the storage unit 2a2, and is read and executed from the storage unit 2a2 by the processing unit 2a1. The medium can be various storage media readable by the computer 2a, or it can be a communication line connected to the communication interface 2a3. The processing unit 2a1 can be a CPU (Central Processing Unit). The storage unit 2a2 may include a RAM (Random Access Memory), a ROM (Read Only Memory), a HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0029] Various exemplary embodiments have been described above, but the present invention is not limited to the exemplary embodiments described above, and various additions, omissions, substitutions, and changes may be made. In addition, elements in different embodiments may be combined to form other embodiments.

[0030] Next, a configuration example of a capacitive coupling type plasma processing apparatus will be described as an example of the plasma processing apparatus 1 . Figure 2 It is a diagram for explaining a configuration example of a capacitive coupling type plasma processing apparatus.

[0031] A capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. In addition, the plasma processing apparatus 1 includes a substrate support unit 11 and a gas inlet unit. The gas inlet unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas inlet unit includes a shower head 13. The substrate support unit 11 is disposed in the plasma processing chamber 10. The shower head 13 is disposed above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side wall 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support unit 11 are electrically insulated from the shell of the plasma processing chamber 10.

[0032] The substrate support portion 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central area 111a for supporting a substrate W and an annular area 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular area 111b of the main body 111 surrounds the central area 111a of the main body 111 when viewed from above. The substrate W is arranged on the central area 111a of the main body 111, and the ring assembly 112 is arranged on the annular area 111b of the main body 111 in a manner that surrounds the substrate W on the central area 111a of the main body 111. Therefore, the central area 111a is also referred to as a substrate supporting surface for supporting the substrate W, and the annular area 111b is also referred to as a ring supporting surface for supporting the ring assembly 112.

[0033] In one embodiment, the main body 111 includes a base 5 and an electrostatic holding disk 6. The base 5 includes a conductive component. The conductive component of the base 5 can function as a lower electrode. The electrostatic holding disk 6 is arranged on the base 5. The electrostatic holding disk 6 includes a ceramic component 1111a and an electrostatic electrode 1111b arranged in the ceramic component 1111a. The ceramic component 1111a has a central area 111a. In one embodiment, the ceramic component 1111a also has an annular area 111b. In addition, other components surrounding the electrostatic holding disk 6 such as an annular electrostatic holding disk and annular insulating components may also have an annular area 111b. In this case, the ring assembly 112 may be arranged on the annular electrostatic holding disk or the annular insulating component, or on both the electrostatic holding disk 6 and the annular insulating component. In addition, at least one RF / DC electrode coupled to the RF power supply 31 and / or DC power supply 32 described later may also be arranged in the ceramic component 1111a. In this case, at least one RF / DC electrode functions as a lower electrode. When the RF bias signal and / or DC signal described later is supplied to at least one RF / DC electrode, the RF / DC electrode is also referred to as a bias electrode. In addition, the conductive member of the base 5 and at least one RF / DC electrode may function as a plurality of lower electrodes. In addition, the electrostatic electrode 1111b may also function as a lower electrode. Thus, the substrate support portion 11 includes at least one lower electrode.

[0034] The ring assembly 112 includes one or more ring-shaped members. In one embodiment, the one or more ring-shaped members include one or more edge rings and at least one cover ring. The edge ring is formed of a conductive material or an insulating material, and the cover ring is formed of an insulating material.

[0035] In addition, the substrate support portion 11 may also include a temperature control module, which is configured to adjust at least one of the electrostatic holding disk 6, the ring assembly 112 and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a or a combination thereof. A heat transfer fluid such as brine or gas flows in the flow path 1110a. In one embodiment, the flow path 1110a is formed in the base 5, and one or more heaters are arranged in the ceramic component 1111a of the electrostatic holding disk 6. In addition, the substrate support portion 11 may also include a heat transfer gas supply portion, which is configured to supply a heat transfer gas to the gap between the back side of the substrate W and the central area 111a.

[0036] The shower head 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The shower head 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas introduction ports 13c. The processing gas supplied to the gas supply port 13a is introduced into the plasma processing space 10s from the plurality of gas introduction ports 13c through the gas diffusion chamber 13b. In addition, the shower head 13 includes at least one upper electrode. In addition, the gas introduction unit may also include, in addition to the shower head 13, one or more side gas injection units (SGI: Side Gas Injector) installed in one or more openings formed in the side wall 10a.

[0037] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas from the respective corresponding gas sources 21 to the shower head 13 via the respective corresponding flow controllers 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. In addition, the gas supply unit 20 may also include at least one flow modulation device for modulating or pulsing the flow of at least one processing gas.

[0038] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. Thus, plasma is formed from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generating unit 12. In addition, by supplying an RF bias signal to at least one lower electrode, a bias potential can be generated on the substrate W, and ion components in the formed plasma can be introduced to the substrate W.

[0039] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit, and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may also be configured to generate a plurality of source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0040] The second RF generating unit 31b is coupled to at least one lower electrode via at least one impedance matching circuit, and is configured to generate an RF bias signal (RF bias power). The frequency of the RF bias signal may be the same as the frequency of the source RF signal, or may be different from the frequency of the source RF signal. In one embodiment, the RF bias signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the RF bias signal has a frequency in the range of 100kHz to 60MHz. In one embodiment, the second RF generating unit 31b may also be configured to generate a plurality of RF bias signals having different frequencies. The generated one or more RF bias signals are supplied to at least one lower electrode. In addition, in various embodiments, at least one of the source RF signal and the RF bias signal may also be pulsed.

[0041] In addition, the power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generating unit 32a and a second DC generating unit 32b. In one embodiment, the first DC generating unit 32a is connected to at least one lower electrode and is configured to generate a first DC signal. The generated first DC signal is applied to at least one lower electrode. In one embodiment, the second DC generating unit 32b is connected to at least one upper electrode and is configured to generate a second DC signal. The generated second DC signal is applied to at least one upper electrode.

[0042] In various embodiments, the first DC signal and the second DC signal may also be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulse may have a pulse waveform of a rectangle, a trapezoid, a triangle, or a combination thereof. In one embodiment, a waveform generator for generating a sequence of voltage pulses from a DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. In the case where the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulse may have a positive polarity or a negative polarity. In addition, the sequence of voltage pulses may also include one or more positive polarity voltage pulses and one or more negative polarity voltage pulses in one cycle. In addition, the first DC generator 32a and the second DC generator 32b may be provided in addition to the RF power supply 31, or the first DC generator 32a may be provided instead of the second RF generator 31b.

[0043] The exhaust system 40 can be connected to the gas exhaust port 10e provided at the bottom of the plasma processing chamber 10, for example. The exhaust system 40 can include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is adjusted by the pressure regulating valve. The vacuum pump can include a turbomolecular pump, a dry pump, or a combination thereof.

[0044] Below, refer to Figure 3 to Figure 6 A plasma processing apparatus according to one embodiment will be described. Figure 3 1 is a partially enlarged cross-sectional view of a substrate support portion according to an exemplary embodiment. As described above, the plasma processing apparatus 1 includes a chamber 10, a base 5, and an electrostatic holding disk 6. The chamber 10 provides a processing space 10s therein. The base 5 is disposed in the processing space 10s. The base 5 provides an internal space 5s therein.

[0045] The electrostatic holding disk 6 is arranged on the base 5. In one example, the electrostatic holding disk 6 can also be arranged on the base 5 via a heat insulating member (adhesive layer) 51. The heat insulating member 51 is formed of, for example, silicone. The electrostatic holding disk 6 includes a dielectric member 61, at least one heater electrode layer, and at least one resistor layer. At least one resistor layer has a thickness of 300 μm or less. In one embodiment, at least one resistor layer may also have a thickness of 100 μm or less.

[0046] Hereinafter, the plasma processing device 1 including a plurality of heater electrode layers 62 and a plurality of resistor layers 63 will be described, but the plasma processing device 1 may also include a single heater electrode layer and a single resistor layer. The plurality of resistor layers 63 each have a thickness of 300 μm or less. The plurality of resistor layers 63 may each have a thickness of 100 μm or less.

[0047] The ceramic member 1111a is an example of the dielectric member 61. The ceramic member 1111a can be formed by thermal spraying. The dielectric member 61 can be formed of polyimide. The dielectric member 61 has a support surface 61a. The support surface 61a is the upper surface of each of the dielectric member 61 and the electrostatic holding disk 6. The support surface 61a includes a substrate support surface, that is, a central area 111a. The support surface 61a may also include a ring support surface, that is, an annular area 111b.

[0048] like Figure 3As shown, a plurality of heater electrode layers 62 are arranged in the dielectric member 61. A plurality of resistor layers 63 are arranged in the dielectric member 61. In one embodiment, the positions of the plurality of heater electrode layers 62 in the thickness direction D1 in the electrostatic holding disk 6 are different from the positions of the plurality of resistor layers 63 in the thickness direction D1. In one example, the positions of the plurality of heater electrode layers 62 in the thickness direction D1 in the electrostatic holding disk 6 are 6 / 7 of the thickness of the electrostatic holding disk 6 from the support surface 61a, or are closer to the support surface 61a than 6 / 7 of the thickness of the electrostatic holding disk 6 from the support surface 61a. In one embodiment, the plurality of heater electrode layers 62 may extend between the support surface 61a and the plurality of resistor layers 63. In one example, the electrostatic electrode 1111b may extend between the support surface 61a and the plurality of heater electrode layers 62.

[0049] Figure 4 1 is an exploded perspective view showing the structure of an electrostatic holding disk involved in an exemplary embodiment. In one example, the dielectric member 61 is composed of a plurality of stacked dielectric layers 61b. The thickness direction D1 can be the same as the stacking direction of the plurality of dielectric layers 61b. The thickness of the dielectric layer 61b is, for example, 0.35 mm. In one example, the plurality of heater electrode layers 62 and the plurality of resistor layers 63 are respectively arranged on two dielectric layers among the plurality of dielectric layers 61b. The two dielectric layers can be adjacent in the stacking direction. In this case, the distance in the thickness direction D1 between the plurality of heater electrode layers 62 and the plurality of resistor layers 63 is greater than 0.35 mm.

[0050] like Figure 4 As shown in FIG. 1 , each of the plurality of heater electrode layers 62 may include a first end 62a and a second end 62b. In one example, the plurality of heater electrode layers 62 extend on corresponding dielectric layers in the plurality of dielectric layers 61b in a manner of snaking from the first end 62a to the second end 62b. Each of the plurality of resistor layers 63 may include a first end 63a and a second end 63b. In one example, the plurality of resistor layers 63 extend on corresponding dielectric layers in the plurality of dielectric layers 61b in a manner of snaking from the first end 63a to the second end 63b.

[0051] The plurality of heater electrode layers 62 are formed of a first material. In one example, the first material includes at least one material selected from a first group of materials consisting of tungsten, copper, silver, and aluminum. The plurality of resistor layers 63 are formed of a second material. In one example, the second material includes at least one material selected from a second group of materials consisting of tungsten, nickel, molybdenum, and platinum.

[0052] The temperature coefficient of resistance of the second material is greater than the temperature coefficient of resistance of the first material. Specifically, the first material and the second material are respectively selected from the first group of materials and the second group of materials in such a way that the temperature coefficient of resistance of the second material is greater than the temperature coefficient of resistance of the first material. In one embodiment, the second material may be tungsten. The first material and the second material may be tungsten. The first material may be copper and the second material may be tungsten. The first material may be tungsten and the second material may be nickel. The first material may be silver and the second material may be molybdenum. The first material may be aluminum and the second material may be molybdenum. In one embodiment, the temperature coefficient of resistance of the second material may be greater than the temperature coefficient of resistance of the first material.

[0053] like Figure 3 As shown, the plasma processing device 1 further includes a control circuit 7 and a detection circuit 8. In one example, the control circuit 7 and the detection circuit 8 are connected in a manner that allows them to communicate with each other. The control circuit 7 and the detection circuit 8 may also be connected to the control unit 2 in a manner that allows them to communicate. The control circuit 7 and the detection circuit 8 may also be a part of the control unit 2. The control circuit 7 is arranged in the internal space 5s. The control circuit 7 is configured to control the applied power applied to each of the plurality of heater electrode layers 62. The control circuit 7 may be electrically connected to the first end 62a and the second end 62b, respectively.

[0054] The detection circuit 8 is disposed in the internal space 5s. The detection circuit 8 is configured to detect a voltage applied to each of the plurality of resistance layers 63. The detection circuit 8 may be electrically connected to the first end 63a and the second end 63b, respectively.

[0055] Figure 5 8 is a diagram showing a structure of a detection circuit according to an exemplary embodiment. In one embodiment, the detection circuit 8 may include a plurality of resistor voltage divider circuits 81 and a plurality of A / D converters 82. Figure 5 As shown, each of the plurality of resistor voltage divider circuits 81 includes a reference resistor R and a corresponding resistor layer 630 in the plurality of resistor layers 63. The reference resistor R is connected in series with the resistor layer 630. One end of the reference resistor R is connected to a power source, and the other end of the reference resistor R is connected to one end (e.g., the first end 63a) of the resistor layer 630. The other end (e.g., the second end 63b) of the resistor layer 630 is connected to the ground G. The plurality of A / D converters 82 convert the voltage applied to the corresponding resistor layer 630 into a digital value, respectively.

[0056] In one embodiment, a plurality of A / D converters 82 are respectively connected to the first end 63a of the resistor layer 630. The first end 63a is connected to the reference resistor R. The second end 63b can be connected to the ground G. A power supply voltage is applied to the reference resistor R and the resistor layer 630. A voltage of R2 / (R1+R2)×Vin is applied to the resistor layer 630. Here, R1 is the resistance value of the reference resistor R, R2 is the resistance value of the resistor layer 630, and Vin is the power supply voltage. The A / D converter 82 converts the voltage applied to the resistor layer 630 into a digital value. In one example, the detection circuit 8 also includes an FPGA 83 (Field Programmable Gate Array). The FPGA 83 obtains the digital value from the A / D converter 82 and outputs the digital value in a communicable form.

[0057] In the plasma processing apparatus 1, the heat generation of the plurality of heater electrode layers 62 is controlled according to the applied power controlled by the control circuit 7. The temperature of the electrostatic holding disk 6 changes in accordance with the heat generation of the plurality of heater electrode layers 62. When the temperature of the electrostatic holding disk 6 changes, the temperature of the corresponding resistor layer 630 among the plurality of resistor layers 63 arranged in the dielectric member 61 changes. When the temperature of the resistor layer 630 changes, the resistance value of the resistor layer 630 changes in proportion to the resistance temperature coefficient of the second material forming the resistor layer 630.

[0058] In the plurality of resistor voltage divider circuits 81, when the resistance value of the resistor layer 630 changes in accordance with the temperature of the electrostatic holding disk 6, the voltage applied to the resistor layer 630 changes. Thus, the temperature of the resistor layer 630 is determined by the voltage applied to the resistor layer 630. Therefore, in the plasma processing apparatus 1, the temperature of the electrostatic holding disk is determined.

[0059] In one example, the detection circuit 8 is configured to determine the temperature of the resistance layer 630 based on the voltage applied to the resistance layer 630. Each relationship between the temperature of the plurality of resistance layers 63 and the voltage applied to the plurality of resistance layers 63 may be given in advance. In one example, the detection circuit 8 stores the resistance value and the reference voltage of the reference resistor R. In another example, the control circuit 7 may be configured to determine the temperature of the resistance layer 630 based on the voltage applied to the resistance layer 630. The control circuit 7 may obtain the voltage applied to the resistance layer 630 from the detection circuit 8. In yet another example, the control unit 2 may be configured to determine the temperature of the resistance layer 630 based on the voltage applied to the resistance layer 630.

[0060] Figure 6 FIG. 1 is a plan view showing the structure of a plurality of zones of an electrostatic holding disk according to an exemplary embodiment. Figure 6 The support surface 61a is shown as viewed from the thickness direction D1. Figure 6In the example, the support surface 61a has a circular shape centered on the central axis AX when viewed from the thickness direction D1. In one embodiment, the support surface 61a includes a plurality of regions 61c. In one example, the region concentric with the central axis AX includes one or more corresponding regions among the plurality of regions 61c. The plurality of regions 61c may include a plurality of sector-shaped regions including the central axis AX, and a plurality of sector-shaped regions centered on the central axis AX. The electrostatic holding disk 6 includes a plurality of regions 6a, and the plurality of regions 6a respectively include a plurality of regions 61c. Figure 6 As shown, the plurality of regions 6a may respectively include a plurality of areas 61c overlapping the plurality of regions 6a when viewed from the thickness direction D1. Figure 6 In the example shown, the electrostatic holding disk 6 includes 32 zones, but the present invention is not limited thereto. The electrostatic holding disk 6 may include more than 32 zones, or may include less than 32 zones.

[0061] Below, refer to Figure 3 and Figure 6 In one embodiment, the plurality of heater electrode layers 62 are respectively arranged in the plurality of zones 6a. The plurality of resistor layers 63 are respectively arranged in the plurality of zones 6a. The control circuit 7 is configured to control the plurality of applied powers respectively applied to the plurality of heater electrode layers 62. The detection circuit 8 is configured to detect the plurality of voltage values ​​respectively applied to the plurality of resistor layers 63.

[0062] In the plasma processing apparatus 1, the heat generation of the plurality of heater electrode layers 62 is controlled respectively according to the plurality of applied powers controlled by the control circuit 7. The temperatures of the plurality of zones 6a change respectively in accordance with the heat generation of the plurality of heater electrode layers 62. When the temperatures of the plurality of zones 6a change respectively, the temperature of the resistor layer 630 of the corresponding zone among the plurality of zones 6a arranged in the dielectric member 61 changes. When the temperature of the resistor layer 630 changes, the resistance value of the resistor layer 630 changes in proportion to the resistance temperature coefficient of the second material forming the resistor layer 630.

[0063] When the resistance value of the resistance layer 630 changes, the voltage applied to the resistance layer 630 changes. Thus, the temperature of the resistance layer 630 is determined by the voltage applied to the resistance layer 630. Therefore, in the plasma processing apparatus 1, the temperatures of the plurality of zones 6a are determined respectively.

[0064] Below, refer to Figure 7 Next, a structure of an electrostatic holding disk of a plasma processing apparatus according to another embodiment will be described. Figure 7 FIG. 1 is a partially enlarged cross-sectional view of an electrostatic holding disk according to another exemplary embodiment. Figure 7The electrostatic holding disk 6A of the plasma processing apparatus 1A shown will be described.

[0065] In the plasma processing apparatus 1A, the plurality of resistor layers 63 extend between the support surface 61a and the plurality of heater electrode layers 62. According to the plasma processing apparatus 1A, the plurality of resistor layers 63 are provided near the support surface 61a compared to the plurality of heater electrode layers 62, so that the difference between the temperature of the support surface 61a and the temperature of the plurality of resistor layers 63 is small. In addition, the electrostatic electrode 1111b can extend between the support surface 61a and the plurality of resistor layers 63.

[0066] Below, refer to Figure 8 Next, the structure of an electrostatic holding disk of a plasma processing apparatus according to still another embodiment will be described. Figure 8 FIG. 1 is a partially enlarged cross-sectional view of an electrostatic holding disk according to another exemplary embodiment. Figure 8 The electrostatic holding disk 6B of the plasma processing apparatus 1B shown will be described.

[0067] The electrostatic holding disk 6B includes at least one high-frequency electrode layer. Figure 8 In the example shown, the electrostatic holding disk 6B includes a plurality of high-frequency electrode layers 64. The plurality of high-frequency electrode layers 64 can be respectively arranged in a plurality of zones 6a. The plurality of high-frequency electrode layers 64 are respectively electrically connected to the base 5. The plurality of high-frequency electrode layers 64 can be formed of the same material as the material forming the base 5. In one example, the plurality of high-frequency electrode layers 64 are formed of aluminum. In one embodiment, the plasma processing apparatus 1B further includes a high-frequency power supply. The high-frequency power supply is electrically connected to the base 5. The RF power supply 31 is an example of the high-frequency power supply.

[0068] The plurality of high-frequency electrode layers 64 surround the plurality of heater electrode layers 62 and the plurality of resistor layers 63 in the electrostatic holding disk 6B. Alternatively, when viewed from the thickness direction D1, the plurality of heater electrode layers 62 and the plurality of resistor layers 63 are respectively covered by the plurality of high-frequency electrode layers 64. In one embodiment, the electrostatic electrode 1111b may also extend between the support surface 61a and the plurality of high-frequency electrode layers 64.

[0069] In the plasma processing apparatus 1B, the plurality of high-frequency electrode layers 64 have the same potential as the base 5, so the plurality of high-frequency electrode layers 64 can function as lower electrodes. The plurality of heater electrode layers 62 and the plurality of resistor layers 63 are surrounded by the plurality of high-frequency electrode layers 64 having the same potential as the base 5. Therefore, RF noise caused by the RF signal (RF power) is suppressed from being added to the plurality of resistor layers 63.

[0070] The electrostatic holding disk 6B may also include a single high-frequency electrode layer. The single high-frequency electrode layer is continuously arranged in a plurality of regions 6a. The single high-frequency electrode layer surrounds a plurality of heater electrode layers 62 and a plurality of resistor layers 63 in the electrostatic holding disk 6B. Alternatively, when viewed from the thickness direction D1, the plurality of heater electrode layers 62 and the plurality of resistor layers 63 may be covered by the single high-frequency electrode layer.

[0071] Below, refer to Fig. 9 Next, the structure of an electrostatic holding disk of a plasma processing apparatus according to still another embodiment will be described. Fig. 9 FIG. 1 is a partially enlarged cross-sectional view of an electrostatic holding disk according to another exemplary embodiment. Fig. 9 The electrostatic holding disk 6C of the plasma processing apparatus 1C shown will be described.

[0072] The electrostatic holding disk 6C includes a plurality of resistor layers 63C. Each resistor layer 63C in the plurality of resistor layers 63C includes a first resistor layer 631 and a second resistor layer 632. The second resistor layer 632 extends between the first resistor layer 631 and the support surface 61a. The electrostatic electrode 1111b may also extend between the second resistor layer 632 and the support surface 61a. The control unit 2 is configured to detect the first voltage applied to the first resistor layer 631 and the second voltage applied to the second resistor layer 632, respectively. Alternatively, the detection circuit 8 is configured to detect the first voltage applied to the first resistor layer 631 and the second voltage applied to the second resistor layer 632, respectively.

[0073] In one example, in the plasma processing apparatus 1C, the detection circuit 8 includes a plurality of resistance voltage divider circuits 81 and a plurality of A / D converters 82 corresponding to the first resistance layer 631 and the second resistance layer 632 , respectively.

[0074] A first resistor voltage divider circuit corresponding to the first resistor layer 631 among the plurality of resistor voltage divider circuits 81 includes the first resistor layer 631 and a first reference resistor instead of the resistor layer 630 and the reference resistor R. A second resistor voltage divider circuit corresponding to the second resistor layer 632 among the plurality of resistor voltage divider circuits 81 includes the second resistor layer 632 and a second reference resistor instead of the resistor layer 630 and the reference resistor R. A first A / D converter corresponding to the first resistor layer 631 among the plurality of A / D converters 82 converts a voltage applied to the first resistor layer 631 into a digital value. A second A / D converter corresponding to the second resistor layer 632 among the plurality of A / D converters 82 converts a voltage applied to the second resistor layer 632 into a digital value.

[0075] A first voltage is applied to the first resistor layer 631. A second voltage is applied to the second resistor layer 632. The control unit 2 is configured to determine the first temperature of the first resistor layer 631 and the second temperature of the second resistor layer 632 according to the first voltage and the second voltage. In another example, the detection circuit 8 or the control circuit 7 may be configured to determine the first temperature of the first resistor layer 631 and the second temperature of the second resistor layer 632 according to the first voltage and the second voltage.

[0076] The control unit 2 is configured to determine the heat flux q (W / m · K) emitted from the support surface 61a based on the first temperature T1 (K), the second temperature T2 (K), the thermal conductivity S (W / (m·K)) of the dielectric member 61, and the distance L (m) between the first resistor layer 631 and the second resistor layer 632 in the thickness direction D1. 2 ).

[0077] In one example, the control unit 2 determines the heat flux q based on the following relationship.

[0078] q=(T2-T1) / (L / S)

[0079] The thermal conductivity S (W / (m·K)) and the distance L (m) may be given in advance. In one example, the control unit 2 stores the thermal conductivity S (W / (m·K)) and the distance L (m).

[0080] Below, refer to Fig.10 Next, the structure of an electrostatic holding disk of a plasma processing apparatus according to still another embodiment will be described. Fig.10 FIG. 1 is a partially enlarged cross-sectional view of an electrostatic holding disk according to another exemplary embodiment. Fig.10 The electrostatic holding disk 6D of the plasma processing apparatus 1D shown will be described.

[0081] The positions of the plurality of heater electrode layers 62 in the thickness direction D1 in the electrostatic holding disk 6D are the same as the positions of the plurality of resistor layers 63 in the thickness direction D1. In one example, the distance between the support surface 61a and the plurality of heater electrode layers 62 in the thickness direction D1 is equal to the distance between the support surface 61a and the plurality of resistor layers 63 in the thickness direction D1. In the plasma processing apparatus 1D, the plurality of heater electrode layers 62 and the plurality of resistor layers 63 are arranged at the same positions in the thickness direction D1 in the electrostatic holding disk 6D.

[0082] Below, refer to Fig.11 Next, the structure of an electrostatic holding disk of a plasma processing apparatus according to still another embodiment will be described. Fig.11FIG. 1 is a partially enlarged cross-sectional view of an electrostatic holding disk according to another exemplary embodiment. Fig.11 The electrostatic holding disk 6E of the plasma processing apparatus 1E shown will be described.

[0083] The electrostatic holding disk 6E includes a plurality of resistance layers 63E. The plurality of resistance layers 63E respectively include a plurality of layers 63c. In one example, the resistance layer 630 may include a plurality of layers 63c. Each layer 63c of the plurality of layers 63c is a resistance layer. The plurality of layers 63c are stacked between the support surface 61a and the base 5 in the electrostatic holding disk 6E. In one example, the plurality of layers 63c are stacked between the base 5 and the plurality of heater electrode layers 62. The plurality of layers 63c may also be stacked between the support surface 61a and the plurality of heater electrode layers 62. The plurality of layers 63c are connected in series. Adjacent layers of the plurality of layers 63c may be connected in series through vias.

[0084] Various exemplary embodiments have been described above, but the present invention is not limited to the exemplary embodiments described above, and various additions, omissions, substitutions, and changes may be made. In addition, elements in different embodiments may be combined to form other embodiments.

[0085] In another embodiment, the control circuit 7 and the detection circuit 8 may also be arranged outside the internal space 5s.

[0086] Fig.12 2 is a diagram showing a structure of a detection circuit according to another exemplary embodiment. Fig.12 As shown, the detection circuit 8 may also include a constant current source I to replace the reference resistor R. The constant current source I is connected to the resistor layer 630. The A / D converter 82 converts the voltage applied to the resistor layer 630 into a digital value. In one example, the constant current source I is connected to one end (e.g., the first end 63a) of the resistor layer 630. In one embodiment, the A / D converter 82 is connected to one end (the first end 63a) connected to the constant current source I. In this case, the voltage value applied to the resistor layer 630 changes in accordance with the change in the resistance value of the resistor layer 630 in a manner that makes the current applied to the resistor layer 630 constant.

[0087] exist Figure 6 In the embodiment, two or more resistor layers of the plurality of resistor layers 63 may be arranged in at least one of the plurality of zones 6a. In at least one zone, the temperature of two or more portions respectively arranged with the two or more resistor layers is determined. The two or more resistor layers may also include a plurality of layers 63c, respectively.

[0088] exist Figure 6In the embodiment of the present invention, at least one of the plurality of resistance layers 63 may be continuously arranged in two or more regions of the plurality of regions 6a. The two or more regions may also be adjacent to each other. The temperature of the two or more regions of the plurality of regions 6a is determined by at least one of the plurality of resistance layers 63.

[0089] right Figure 8 A plurality of high-frequency electrode layers 64 may also be applied to Figure 3 The electrostatic holding disk 6 shown in FIG. 6A has a plurality of heater electrode layers 62 extending between the support surface 61a and the plurality of resistor layers 63. The plurality of high-frequency electrode layers 64 may also be applied to Fig. 9 The electrostatic holding disk 6C shown in FIG. 6 includes a first resistance layer 631 and a second resistance layer 632. A plurality of high-frequency electrode layers 64 may also be applied to Fig.10 The electrostatic holding disk 6D shown has the same positions of the plurality of heater electrode layers 62 in the thickness direction D1 as the plurality of resistance layers 63 in the thickness direction D1 within the electrostatic holding disk 6D.

[0090] exist Fig. 9 In a modification of the embodiment, the plurality of heater electrode layers 62 may extend between the support surface 61a and the plurality of resistor layers 63C.

[0091] Here, various exemplary embodiments included in the present disclosure are described in the following [E1] to [E19].

[0092] [E1]

[0093] A substrate processing device, comprising:

[0094] a chamber, providing a processing space inside the chamber;

[0095] a base, which is arranged in the processing space and provides an internal space inside the base;

[0096] an electrostatic holding disk, which is arranged on the base, the electrostatic holding disk comprising a dielectric member, at least one heater electrode layer and at least one resistor layer, the dielectric member having a support surface including a substrate support surface, the at least one heater electrode layer being arranged in the dielectric member and being formed of a first material, the at least one resistor layer being arranged in the dielectric member and being formed of a second material and having a thickness of 300 μm or less, the second material having a temperature coefficient of resistance being greater than or equal to the temperature coefficient of resistance of the first material;

[0097] a control circuit disposed in the internal space and configured to control the applied power to the at least one heater electrode layer; and

[0098] The detection circuit is disposed in the internal space and is configured to detect a voltage applied to the at least one resistance layer.

[0099] [E2]

[0100] The substrate processing apparatus according to [E1], wherein:

[0101] The second material has a temperature coefficient of resistance greater than a temperature coefficient of resistance of the first material.

[0102] [E3]

[0103] The substrate processing apparatus according to [E1] or [E2], wherein:

[0104] The second material is tungsten.

[0105] [E4]

[0106] The substrate processing apparatus according to any one of [E1] to [E3], wherein:

[0107] The thickness of the at least one resistance layer is 100 μm or less.

[0108] [E5]

[0109] The substrate processing apparatus according to any one of [E1] to [E4], wherein:

[0110] The position of the at least one heater electrode layer in the thickness direction within the electrostatic holding disk is different from the position of the at least one resistance layer in the thickness direction.

[0111] [E6]

[0112] The substrate processing apparatus according to [E5], wherein:

[0113] The at least one heater electrode layer extends between the at least one resistive layer and the support surface.

[0114] [E7]

[0115] According to the substrate processing apparatus described in [E5],

[0116] The at least one resistive layer extends between the at least one heater electrode layer and the support surface.

[0117] [E8]

[0118] The substrate processing apparatus according to any one of [E1] to [E7], wherein:

[0119] The at least one resistive layer includes a first resistive layer and a second resistive layer,

[0120] the second resistive layer extending between the first resistive layer and the support surface,

[0121] The detection circuit is configured to detect a first voltage applied to the first resistance layer and a second voltage applied to the second resistance layer, respectively.

[0122] The substrate processing device also includes a control unit, which is configured to determine a first temperature of the first resistance layer and a second temperature of the second resistance layer according to the first voltage and the second voltage, respectively, and the control unit is configured to determine a heat flux emitted from the supporting surface based on the first temperature, the second temperature, the thermal conductivity of the dielectric component, and the distance between the first resistance layer and the second resistance layer in the thickness direction.

[0123] [E9]

[0124] The substrate processing apparatus according to any one of [E1] to [E4] and [E8], wherein:

[0125] The position of the at least one heater electrode layer in the thickness direction within the electrostatic holding disk is the same as the position of the at least one resistance layer in the thickness direction.

[0126] [E10]

[0127] The substrate processing apparatus according to any one of [E1] to [E9], wherein:

[0128] The support surface comprises a plurality of regions,

[0129] The electrostatic holding disk includes a plurality of zones including the plurality of regions respectively,

[0130] the at least one heater electrode layer comprises a plurality of heater electrode layers,

[0131] The plurality of heater electrode layers are respectively arranged in the plurality of zones,

[0132] The at least one resistive layer comprises a plurality of resistive layers,

[0133] The plurality of resistance layers include at least one resistance layer for each region respectively arranged in the plurality of regions,

[0134] The control circuit is configured to control the plurality of applied powers applied to the plurality of heater electrode layers, respectively.

[0135] The detection circuit is configured to detect each of a plurality of voltage values ​​applied to the plurality of resistance layers.

[0136] [E11]

[0137] The substrate processing apparatus according to any one of [E1] to [E9], wherein:

[0138] The support surface comprises a plurality of regions,

[0139] The electrostatic holding disk includes a plurality of zones including the plurality of regions respectively,

[0140] the at least one heater electrode layer comprises a plurality of heater electrode layers,

[0141] The plurality of heater electrode layers are respectively arranged in the plurality of zones,

[0142] The at least one resistive layer comprises a plurality of resistive layers,

[0143] The plurality of resistance layers include resistance layers continuously arranged in two or more corresponding regions among the plurality of regions,

[0144] The control circuit is configured to control the plurality of applied powers applied to the plurality of heater electrode layers, respectively.

[0145] The detection circuit is configured to detect each of a plurality of voltage values ​​applied to the plurality of resistance layers.

[0146] [E12]

[0147] The substrate processing apparatus according to any one of [E1] to [E11], wherein:

[0148] The at least one resistive layer comprises a plurality of layers,

[0149] The plurality of layers are stacked between the support surface and the base in the electrostatic holding disk, and the plurality of layers are connected in series.

[0150] [E13]

[0151] The substrate processing apparatus according to any one of [E1] to [E12], wherein:

[0152] The electrostatic holding disk further comprises at least one high-frequency electrode layer,

[0153] The at least one high-frequency electrode layer is electrically connected to the base, and surrounds the at least one heater electrode layer and the at least one resistor layer in the electrostatic holding disk.

[0154] [E14]

[0155] A substrate processing apparatus according to [E13], wherein:

[0156] The substrate processing apparatus further includes a high-frequency power source electrically connected to the base.

[0157] [E15]

[0158] A substrate processing apparatus according to [E13], wherein:

[0159] The electrostatic holding disk further comprises an electrostatic electrode,

[0160] The electrostatic electrode extends between the support surface and the at least one high-frequency electrode layer.

[0161] [E16]

[0162] The substrate processing apparatus according to any one of [E1] to [E15], wherein:

[0163] The detection circuit comprises:

[0164] a resistor voltage divider circuit, comprising the at least one resistor layer and a reference resistor connected in series with the at least one resistor layer; and

[0165] An analog-to-digital converter converts a voltage applied to the at least one resistive layer into a digital value.

[0166] [E17]

[0167] A substrate processing apparatus according to [E16], wherein:

[0168] The analog-to-digital converter is connected to one end of the at least one resistance layer,

[0169] The one end of the at least one resistance layer is connected to the reference resistor.

[0170] [E18]

[0171] The substrate processing apparatus according to any one of [E1] to [E15], wherein:

[0172] The detection circuit comprises:

[0173] a constant current source connected to the at least one resistance layer; and

[0174] An analog-to-digital converter converts a voltage applied to the at least one resistive layer into a digital value.

[0175] [E19]

[0176] A substrate processing apparatus according to [E18], wherein:

[0177] The analog-to-digital converter is connected to one end of the at least one resistance layer connected to the constant current source.

[0178] It can be understood from the above description that the various embodiments of the present disclosure are described in this specification for the purpose of explanation, and various changes can be made to the various embodiments of the present disclosure without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed in this specification are not intended to be limiting, and the true scope and spirit are shown by the attached claims.

[0179] Description of Reference Numerals

[0180] 1: plasma processing device; 2: control unit; 5: base; 5s: internal space; 6, 6A, 6B, 6C, 6D, 6E: electrostatic holding disk; 6a: multiple zones; 7: control circuit; 8: detection circuit; 10: chamber; 10s: processing space; 61: dielectric member; 61a: support surface; 61c: area; 62: multiple heater electrode layers; 63, 63C, 63E: multiple resistance layers; 631: first resistance layer; 632: second resistance layer; 63c: multiple layers; 64: high-frequency electrode layer; 81: resistance voltage divider circuit; 82: A / D converter; 1111b: electrostatic electrode; D1: thickness direction; R: reference resistance; I: constant current source.

Claims

1. A substrate processing device, comprising: a chamber, providing a processing space inside the chamber; a base, which is arranged in the processing space and provides an internal space inside the base; an electrostatic holding disk, which is arranged on the base, the electrostatic holding disk comprising a dielectric member, at least one heater electrode layer and at least one resistor layer, the dielectric member having a support surface including a substrate support surface, the at least one heater electrode layer being arranged in the dielectric member and being formed of a first material, the at least one resistor layer being arranged in the dielectric member and being formed of a second material and having a thickness of 300 μm or less, the second material having a temperature coefficient of resistance being greater than or equal to the temperature coefficient of resistance of the first material; a control circuit disposed in the internal space and configured to control the applied power to the at least one heater electrode layer; and The detection circuit is disposed in the internal space and is configured to detect a voltage applied to the at least one resistance layer.

2. The substrate processing apparatus according to claim 1, wherein: The second material has a temperature coefficient of resistance greater than that of the first material.

3. The substrate processing apparatus according to claim 1, wherein: The second material is tungsten.

4. The substrate processing apparatus according to claim 1, wherein: The thickness of the at least one resistance layer is 100 μm or less.

5. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The position of the at least one heater electrode layer in the thickness direction within the electrostatic holding disk is different from the position of the at least one resistance layer in the thickness direction.

6. The substrate processing apparatus according to claim 5, wherein: The at least one heater electrode layer extends between the at least one resistive layer and the support surface.

7. The substrate processing apparatus according to claim 5, wherein: The at least one resistive layer extends between the at least one heater electrode layer and the support surface.

8. The substrate processing apparatus according to claim 7, wherein: The at least one resistive layer includes a first resistive layer and a second resistive layer, the second resistive layer extending between the first resistive layer and the support surface, The detection circuit is configured to detect a first voltage applied to the first resistance layer and a second voltage applied to the second resistance layer, respectively. The substrate processing device also includes a control unit, which is configured to determine a first temperature of the first resistance layer and a second temperature of the second resistance layer according to the first voltage and the second voltage, respectively, and the control unit is configured to determine a heat flux emitted from the supporting surface based on the first temperature, the second temperature, the thermal conductivity of the dielectric component, and the distance between the first resistance layer and the second resistance layer in the thickness direction.

9. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The position of the at least one heater electrode layer in the thickness direction within the electrostatic holding disk is the same as the position of the at least one resistance layer in the thickness direction.

10. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The support surface comprises a plurality of regions, The electrostatic holding disk includes a plurality of zones including the plurality of regions respectively, the at least one heater electrode layer comprises a plurality of heater electrode layers, The plurality of heater electrode layers are respectively arranged in the plurality of zones, The at least one resistive layer comprises a plurality of resistive layers, The plurality of resistance layers include at least one resistance layer for each region respectively arranged in the plurality of regions, The control circuit is configured to control the plurality of applied powers applied to the plurality of heater electrode layers, respectively. The detection circuit is configured to detect each of a plurality of voltage values ​​applied to the plurality of resistance layers.

11. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The support surface comprises a plurality of regions, The electrostatic holding disk includes a plurality of zones including the plurality of regions respectively, the at least one heater electrode layer comprises a plurality of heater electrode layers, The plurality of heater electrode layers are respectively arranged in the plurality of zones, The at least one resistive layer comprises a plurality of resistive layers, The plurality of resistance layers include resistance layers continuously arranged in two or more corresponding regions among the plurality of regions, The control circuit is configured to control the plurality of applied powers applied to the plurality of heater electrode layers, respectively. The detection circuit is configured to detect each of a plurality of voltage values ​​applied to the plurality of resistance layers.

12. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The at least one resistive layer comprises a plurality of layers, The plurality of layers are stacked between the support surface and the base in the electrostatic holding disk, and the plurality of layers are connected in series.

13. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The electrostatic holding disk further comprises at least one high-frequency electrode layer, The at least one high-frequency electrode layer is electrically connected to the base, and surrounds the at least one heater electrode layer and the at least one resistor layer in the electrostatic holding disk.

14. The substrate processing apparatus according to claim 13, wherein: The substrate processing apparatus further includes a high-frequency power source electrically connected to the base.

15. The substrate processing apparatus according to claim 13, wherein: The electrostatic holding disk further comprises an electrostatic electrode, The electrostatic electrode extends between the support surface and the at least one high-frequency electrode layer.

16. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The detection circuit comprises: a resistor voltage divider circuit, comprising the at least one resistor layer and a reference resistor connected in series with the at least one resistor layer; and An analog-to-digital converter converts a voltage applied to the at least one resistive layer into a digital value.

17. The substrate processing apparatus according to claim 16, wherein: The analog-to-digital converter is connected to one end of the at least one resistance layer, The one end of the at least one resistance layer is connected to the reference resistor.

18. The substrate processing apparatus according to any one of claims 1 to 4, wherein: The detection circuit comprises: a constant current source connected to the at least one resistance layer; and An analog-to-digital converter converts a voltage applied to the at least one resistive layer into a digital value.

19. The substrate processing apparatus according to claim 18, wherein: The analog-to-digital converter is connected to one end of the at least one resistance layer connected to the constant current source.

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