Semiconductor device

Abstract

A first impurity region of the first conductivity type and a second impurity region of the second conductivity type, which are respectively in contact with a third impurity region of the second conductivity type and a fourth impurity region of the first conductivity type of the substrate, are formed on the substrate at an interval in the first direction. Wiring extending in a second direction different from the first direction is formed on the substrate on the fourth impurity region side of the third impurity region and on the third impurity region side of the fourth impurity region. Accordingly, when the plurality of diodes are arranged adjacent to each other, an increase in the chip size of the semiconductor device can be suppressed.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] An ESD protection circuit is known that is provided in a semiconductor device to protect the internal circuit of the semiconductor device from electrostatic discharge (ESD). For example, there is a case where a conductor (conductor) buried (embedded) in a groove is used as a wiring (wiring) of a diode formed in an ESD protection circuit or a wiring of a bidirectional diode arranged between different power domains. The buried wiring for a power line or a ground line is called a BPR (Buried Power Rail).

[0003] [Reference document]

[0004] [Patent document]

[0005] [Patent Document 1] International Publication No. 2020 / 235082

[0006] [Patent Document 2] International Publication No. 2020 / 235084

[0007] [Patent Document 3] International Publication No. 2017 / 212644 Summary of the invention

[0008] [Technical issues to be solved]

[0009] When multiple diodes are arranged adjacent to each other in an ESD protection circuit, a bidirectional diode, etc., the diodes are arranged at predetermined intervals in order to prevent the parasitic bipolar transistor formed between the adjacent diodes from being turned on. As a result, the area of ​​the layout region of the diodes becomes larger, resulting in an increase in the chip size of the semiconductor device.

[0010] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to suppress an increase in the chip size of a semiconductor device when a plurality of diodes are arranged adjacent to each other.

[0011] [Technical solution]

[0012] In one embodiment of the present invention, a semiconductor device includes:

[0013] substrate;

[0014] A first impurity region having a first conductivity type and a second impurity region having a second conductivity type are formed on the substrate at intervals along a first direction in a plan view;

[0015] a third impurity region having the second conductivity type, formed on the substrate in contact with the first impurity region;

[0016] a fourth impurity region having the first conductivity type, formed on the substrate in contact with the second impurity region;

[0017] a first wiring formed on the substrate along a second direction different from the first direction on the fourth impurity region side of the third impurity region in a plan view; and

[0018] The second wiring is formed on the substrate along the second direction on the third impurity region side of the fourth impurity region in a plan view.

[0019] [Beneficial Effects]

[0020] According to the disclosed technology, when a plurality of diodes are arranged adjacent to each other, it is possible to suppress an increase in the chip size of a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] [ Figure 1 ]A circuit diagram showing an example of the main parts of the semiconductor device of the first embodiment.

[0022] [ Figure 2 ] indicates that it is used to form Figure 1 A plan view of an example of a layout of a diode region.

[0023] [ Figure 3 ]along Figure 2 Cross-sectional view along line X1-X2.

[0024] [ Figure 4 ]along Figure 2 The cross-sectional view of the Y1-Y2 line.

[0025] [ Figure 5 ] indicates that it is formed by FinFET transistors Figure 2 A cross-sectional view of an example of a transistor.

[0026] [ Figure 6 ]express Figure 2 A plan view of an example of another structure of the diode region.

[0027] [ Figure 7 ]along Figure 6 Cross-sectional view along line X1-X2.

[0028] [ Figure 8 ]express Figure 2 A plan view of an example of another structure of the diode region.

[0029] [ Fig. 9 ]along Figure 8 Cross-sectional view along line X1-X2.

[0030] [ Fig.10 ]A circuit diagram showing an example of the main parts of a semiconductor device according to the second embodiment.

[0031] [ Fig.11 ]express Fig.10 A plan view of an example of a layout of a bidirectional diode region.

[0032] [ Fig.12 ]A circuit diagram showing an example of the main parts of a semiconductor device according to a third embodiment.

[0033] [ Fig.13 ]express Fig.12 A plan view of an example of the layout of transistors and diodes. DETAILED DESCRIPTION

[0034] The embodiments are described below with reference to the accompanying drawings. Hereinafter, reference numerals representing signals are also used as reference numerals representing signal lines or signal terminals. Reference numerals representing voltages are also used as reference numerals representing voltage lines or voltage terminals for supplying voltages.

[0035] (First embodiment)

[0036] Figure 1 An example of the main part of the semiconductor device of the first embodiment is shown. For example, Figure 1 The semiconductor device SEM1 shown may be a SoC (System on Chip), or may be a single CPU (Central Processing Unit), GPU (Graphics Processing Unit), DSP (Digital Signal Processor), FPGA (Field-Programmable Gate Array), memory, or the like. Figure 1 An example of an input buffer circuit IBUF for receiving a signal SIG in the semiconductor device SEM1 is shown.

[0037] Input buffer circuit IBUF includes ESD protection circuit PC including diodes D10 and D20, p-type field effect transistor PFET10, and n-type field effect transistor NFET10. P-type is an example of the first conductivity type or the second conductivity type, and n-type is an example of the second conductivity type or the first conductivity type.

[0038] The anode of the diode D10 is connected to the ground line VSS, and the cathode is connected to the signal line SIG. The anode of the diode D20 is connected to the signal line SIG, and the cathode is connected to the power line VDD. The ground line VSS is connected to the ground pad (Pad) VSSP, and the power line VDD is connected to the power pad VDDP. The signal line SIG is connected to the signal pad SIGP.

[0039] The field effect transistors PFET10 and NFET10 constitute an inverter that inverts the logic of the signal SIG and outputs it. Hereinafter, the p-type field effect transistor PFET is also referred to as a transistor PFET, and the n-type field effect transistor NFET is also referred to as a transistor NFET. Although there is no particular limitation, the transistors PFET10 and NFET10 are, for example, nanosheet transistors.

[0040] The gates of the transistors PFET10 and NFET10 are connected to the signal line SIG for receiving the signal SIG supplied to the signal pad SIGP. The drains of the transistors PFET10 and NFET10 are connected to the output node (Node) OUT of the input buffer circuit IBUF. The source and back gate of the transistor PFET10 are connected to the power line VDD. The source and back gate of the transistor NFET10 are connected to the ground line VSS. The power line VDD is an example of the first power line or the second power line, and the ground line VSS is an example of the second power line or the first power line.

[0041] Figure 2 The plan view shows the Figure 1 An example of the layout of the diode D20 and D10 region. The diode D20 and D10 are along Figure 2 The transistors PFET (PFET21, PFET22 and PFET23) are arranged adjacent to each other in the X direction in the formation region of the diode D20. Figure 2 The transistors NFET (NFET11, NFET12 and NFET13) are arranged in the formation area of ​​the diode D10 along the Figure 2 The X direction is an example of the first direction. The Y direction is an example of the second direction intersecting the X direction.

[0042] For example, each transistor PFET and NFET is a nanosheet transistor. Each transistor PFET and NFET has a gate electrode GT extending in the X direction, a diffusion region (p+ (p-type) or n+ (n-type)) arranged on both sides of the gate electrode GT in the Y direction, and a local wiring LI connected to the diffusion region. Hereinafter, the formation region of the diode D20 is also referred to as the diode region D20, and the formation region of the diode D10 is also referred to as the diode region D10.

[0043] The diffusion regions p+ of transistors PFET22, NFET11 and NFET13 correspond to the source and drain regions of transistors PFET22, NFET11 and NFET13. The diffusion regions n+ of transistors PFET21, PFET23 and NFET12 correspond to the source and drain regions of transistors PFET21, PFET23 and NFET12.

[0044] The diffusion region p+ of the transistor PFET22 is connected to the buried wiring BPR (SIG) via the local wiring LI and the via (conducting hole (Via) V1 in the diode region D20. The buried wiring BPR (SIG) is connected to the signal line SIG. It should be noted that Figure 2 In FIG. 1 , the through hole V1 is indicated by a dotted rectangle with an X. The transistor PFET22 is an example of a first transistor.

[0045] The diffusion regions n+ of the transistors PFET21 and PFET23 are connected to the buried wiring BPR (VDD) via the local wiring LI and the through hole V1. The buried wiring BPR (VDD) is connected to the power supply line VDD. The diffusion regions n+ of the transistors PFET21 and PFET23 are connected (contacted) to the n-type well region NW (VDD) on the surface of the p-type semiconductor substrate PSUB (VSS).

[0046] Thus, the power supply voltage VDD of the buried wiring BPR (VDD) can be supplied to the well region NW (VDD) via the diffusion region n+ of the transistors PFET21 and PFET23. In addition, a pn junction (pn junction) can be formed between the diffusion region p+ of the transistor PFET22 and the well region NW (VDD). Figure 1 The diode D20.

[0047] The buried wiring BPR (SIG) of the diode region D20 is formed on the opposite side of the diode region D10 side in the well region NW (VDD). The buried wiring BPR (VDD) is formed on the diode region D10 side in the well region NW (VDD). That is, the buried wiring BPR (SIG) and BPR (VDD) are formed on both sides of the transistors PFET21-PFET23 in the X direction in the diode region D20. In the diode region D20, the buried wiring BPR (SIG) is an example of the third wiring, and the buried wiring BPR (VDD) is an example of the first wiring.

[0048] It should be noted that the buried wiring BPR (SIG) may also be formed on the diode region D10 side, and the buried wiring BPR (VDD) may also be formed on the opposite side of the diode region D10 side. In this case, the through hole V1 of the transistor PFET22 is formed on the diode region D10 side, and the through holes V1 of the transistors PFET21 and PFET23 are formed on the opposite side of the diode region D10 side. In addition, only one of the buried wiring BPR (VDD) and the buried wiring BPR (SIG) may be formed on the diode region D10 side. In this case, instead of the other of the buried wiring BPR (VDD) and the buried wiring BPR (SIG), the other of the power supply line VDD and the signal line SIG is formed in the wiring layer above the transistor PFET and connected to the wiring LI.

[0049] The diffusion region n+ of the transistor NFET12 is connected to the buried wiring BPR (SIG) via the local wiring LI and the via V1 in the diode region D10. The buried wiring BPR (SIG) is connected to the signal line SIG. The transistor NFET12 is an example of a second transistor.

[0050] The diffusion regions p+ of the transistors NFET11 and NFET13 are connected to the buried wiring BPR (VSS) via the local wiring LI and the via V1. The buried wiring BPR (VSS) is connected to the ground line VSS. The diffusion regions p+ of the transistors NFET11 and NFET13 are in contact with the p-type well region PW (VSS) on the surface of the semiconductor substrate PSUB (VSS).

[0051] Thus, the ground voltage VSS of the buried wiring BPR (VSS) can be supplied to the well region PW (VSS) via the diffusion region p+ of the transistors NFET11 and NFET13. In addition, a pn junction can be formed between the well region PW (VSS) and the diffusion region n+ of the transistor NFET12. Figure 1 The diode D10.

[0052] The buried wiring BPR (SIG) of the diode region D10 is formed on the diode region D20 side in the well region PW (VSS). The buried wiring BPR (VSS) is formed on the opposite side of the diode region D20 side in the well region PW (VSS). That is, the buried wiring BPR (SIG) and BPR (VSS) are formed on both sides of the transistors NFET11-NFET13 in the X direction in the diode region D10. In the diode region D10, the buried wiring BPR (SIG) is an example of the second wiring, and the buried wiring BPR (VSS) is an example of the fourth wiring.

[0053] It should be noted that, in the diode region D10, the buried wiring BPR (SIG) may also be formed on the side opposite to the diode region D20 side, and the buried wiring BPR (VSS) may also be formed on the side of the diode region D20. In this case, the through hole V1 of the transistor NFET12 is formed on the side opposite to the diode region D20 side, and the through holes V1 of the transistors NFET11 and NFET13 are formed on the side of the diode region D20. In addition, only one of the buried wiring BPR (VSS) and the buried wiring BPR (SIG) may be formed on the side of the diode region D20. In this case, instead of the other of the buried wiring BPR (VSS) and the buried wiring BPR (SIG), the other of the ground line VSS and the signal line SIG is formed in the wiring layer above the transistor NFET, and connected to the wiring LI.

[0054] The semiconductor substrate PSUB (VSS) is provided between the diode regions D20 and D10, and no semiconductor layers such as diffusion regions and well regions are formed. In addition, the well region NW (VDD) of the diode region D20 and the well region PW (VSS) of the diode region D10 are separated by respective buried wirings BPR (VDD) and BPR (SIG).

[0055] Therefore, the leakage current component between the well regions NW (VDD) and PW (VSS) can be reduced, and the conduction of the parasitic bipolar transistor can be suppressed. Alternatively, the formation of the parasitic bipolar transistor between the diode regions D20 and D10 can be suppressed. Accordingly, compared with the case where the buried wirings BPR (VDD) and BPR (SIG) are not formed, the interval between the diode regions D20 and D10 can be narrowed, and the chip size of the semiconductor device SEM1 can be reduced.

[0056] It should be noted that the diode regions D20 and D10 may be alternately and repeatedly arranged along the X direction. The buried wiring BPR is formed on both sides of the diode region D20 in the X direction and on both sides of the diode region D10 in the X direction. For this reason, even when the diode regions D20 and D10 are alternately and repeatedly arranged along the X direction, the conduction of the parasitic bipolar transistor between the adjacent diode regions D20 and D10 or the formation of the parasitic bipolar transistor itself can be suppressed. Accordingly, the interval between the plurality of diodes D20 and D10 can be narrowed, and the chip size of the semiconductor device SEM1 can be further reduced.

[0057] It should be noted that more than four transistors PFET can be arranged side by side in the diode region D20 along the Y direction. Similarly, more than four transistors NFET can be arranged side by side in the diode region D10 along the Y direction. In this case, in each of the diode regions D20 and D10, the diffusion regions p+ and the diffusion regions n+ are formed alternately.

[0058] Figure 3 Shown along Figure 2 The cross section of the line X1-X2 of FIG. The nanosheet type transistors PFET22 and NFET12 are formed on the semiconductor substrate PSUB (VSS). In addition, a STI (Shallow Trench Isolation) film as an insulating film is also formed on the surface of the semiconductor substrate PSUB (VSS). The thick solid lines around the buried wiring BPR (SIG), BPR (VDD) and BPR (VSS) represent the insulating film. Although there are no special restrictions, the local wiring LI, the buried wiring BPR and the through hole V1 are formed of a metal material such as ruthenium, tungsten, molybdenum, copper, etc.

[0059] like Figure 2 As shown, the diffusion region p+ of the transistor PFET22 is connected to the buried wiring BPR (SIG) via the local wiring LI and the through hole V1 in the diode region D20. In addition to the formation region of the through hole V1, an insulating film INS1 of silicon nitride, silicon carbide, etc. is formed between the local wiring LI and the buried wiring BPR (SIG). In addition, the diode D20 is formed by the pn junction between the diffusion region p+ of the transistor PFET22 and the well region NW (VDD).

[0060] In the diode region D10, the diffusion region n+ of the transistor NFET12 is connected to the buried wiring BPR (SIG) formed in the semiconductor substrate PSUB (VSS) via the local wiring LI and the through hole V1. An insulating film INS1 is formed between the local wiring LI and the buried wiring BPR (SIG). In addition, the diode D10 is formed by the pn junction between the p-type well region PW (VSS) of the transistor NFET12 and the diffusion region n+.

[0061] Figure 4 Shown along Figure 2 The cross section of the Y1-Y2 line of the transistor PFET22. In the transistor PFET22, the diffusion regions p+ arranged on both sides of the gate GT in the Y direction are connected to each other via a plurality of nanosheets NS. The local wiring LI of the transistor PFET22 is connected to the well region NW (VDD) via the diffusion region p+.

[0062] In each transistor PFET21 and PFET23, diffusion regions n+ disposed on both sides of the gate GT in the Y direction are connected to each other via a plurality of nanosheets NS. Local wiring LI of each transistor PFET21 and PFET23 is connected to the well region NW (VDD) via the diffusion region n+.

[0063] In each transistor PFET21-PFET23, a plurality of nanosheets NS are formed in a spaced manner along the thickness direction of the semiconductor substrate PSUB, i.e., the Z direction. In addition, an insulating film INS2 is formed between the gate electrode GT and the diffusion region n+ and between the gate electrode GT and the diffusion region p+. Accordingly, in the transistor PFET22, the gate electrode GT and the diffusion region p+ are insulated by the insulating film INS2, and in the transistors PFET21 and PFET23, the gate electrode GT and the diffusion region n+ are insulated by the insulating film INS2. In addition, a gate insulating film (not shown) is also formed between the gate electrode GT and the nanosheet NS.

[0064] Figure 5 The FinFET transistor is shown Figure 2 An example of the case of transistors PFET21-PFET23. In transistors PFET21 and PFET23, a p-type diffusion region p- is formed between a pair of diffusion regions n+ (fins) forming a source region and a drain region to replace Figure 4 In the transistor PFET22, an n-type diffusion region n- is formed between a pair of diffusion regions p+ (fins) forming a source region and a drain region to replace Figure 4 In addition, a gate insulating film (not shown) is formed between the gate electrode GT and the fin.

[0065] The reference symbol p- indicates that the impurity concentration is lower than that of the reference symbol p+. The reference symbol n- indicates that the impurity concentration is lower than that of the reference symbol n+. It should be noted that even in the case of a FinFET transistor, Figure 2 In the case of transistors NFET11-NFET23, they also have Figure 5 In this case, Figure 5 The diffusion area n+ and the diffusion area p+ are exchanged with each other, Figure 5 The diffusion regions n- and p- are exchanged with each other.

[0066] Figure 6 The plan view shows Figure 2 An example of another structure of the diode regions D20 and D10. In addition to the following differences, Figure 6 and Figure 2 The planar structure is similar to that of Figure 6 In the embodiment, the signal line SIG, the power line VDD, and the ground line VSS of the diode regions D20 and D10 are connected to the wiring formed in the wiring layer above the transistors PFET and NFET. Figure 6 Not formed Figure 2 For this purpose, each buried wiring BPR is set to be in a floating state.

[0067] In the diode region D20, the local wiring LI connected to the diffusion region p+ of the transistor PFET22 is connected to the signal SIG wiring W1(SIG) via the through hole V2. In addition, the local wiring LI connected to the diffusion region n+ of the transistors PFET21 and PFET23 is connected to the power supply voltage VDD wiring W1(VDD) via the through hole V2. For example, the wiring W1(SIG) and the wiring W1(VDD) are formed in a manner extending in the Y direction.

[0068] In the diode region D10, the local wiring LI connected to the diffusion region n+ of the transistor NFET12 is connected to the signal SIG wiring W1(SIG) via the through hole V2. In addition, the local wiring LI connected to the diffusion region p+ of the transistors NFET11 and NFET13 is connected to the ground voltage VSS wiring W1(VSS) via the through hole V2. For example, the wiring W1(SIG) and the wiring W1(VSS) are formed in a manner extending along the Y direction.

[0069] The wiring W1(SIG) of the diode region D20 and the wiring W1(SIG) of the diode region D10 are connected to each other via the wiring W2(SIG), and the wiring W2(SIG) is formed above the wiring W1(SIG) via the via V3. For example, the wiring W2(SIG) is formed to extend in the X direction. Figure 6 , through holes V2 and V3 are represented by dashed rectangles with X marks.

[0070] For example, the wirings W1(SIG), W1(VDD), W1(VSS), and W2(SIG) are formed of the same or similar metal material as the local wiring LI. It should be noted that the wiring W2(SIG) that connects the wirings W1(SIG) of the diode regions D20 and D10 may be omitted.

[0071] Figure 7 Shown along Figure 6 The cross section of the X1-X2 line. Figure 7 and Figure 3 The structure shown is similar, the difference between the two is that Figure 7 In the example, the local wiring LI of the transistors PFET22 and NFET12 is connected to the wirings W1 (SIG) and W2 (SIG) of the upper layer, and the buried wiring BPR is set in a floating state.

[0072] Even in Figure 6 and Figure 7 In the structure shown, Figures 2 to 4Similarly to the structure shown, the well regions NW (VDD) and PW (VSS) are separated by the buried wiring BPR. Therefore, the conduction of the parasitic bipolar transistor between the well regions NW (VDD) and PW (VSS) can be suppressed, or the formation of the parasitic bipolar transistor between the diode regions D20 and D10 can be suppressed. Accordingly, the interval between the diode regions D20 and D10 can be narrowed, and the chip size of the semiconductor device SEM1 can be reduced.

[0073] Figure 8 The plan view shows Figure 2 An example of another structure of the diode regions D20 and D10. Figure 6 Detailed description of the same or similar elements is omitted. Figure 8 In the diode region D20, Figure 2 Similarly, the power supply voltage VDD is supplied to the diffusion regions n+ of the transistors PFET21 and PFET23 from the buried wiring BPR (VDD) via the via V1 and the local wiring LI.

[0074] In addition, within the diode region D10, Figure 2 Similarly, the ground voltage VSS is supplied to the diffusion regions p+ of the transistors NFET11 and NFET13 from the buried wiring BPR (VSS) via the via V1 and the local wiring LI. Figure 8 Not formed Figure 6 The other structures of the diode regions D20 and D10 are similar to those of the wirings W1(VDD) and W1(VSS). Figure 2 similar.

[0075] Fig. 9 Shown along Figure 8 The cross section of the X1-X2 line. Figure 7 Detailed description of the same or similar elements is omitted. Fig. 9 and Figure 7 The structures shown are the same or similar except for the following differences, namely, Fig. 9 In Figure 3 The buried wiring BPR (VDD) and BPR (VSS) are not formed. Figure 7 It should be noted that the buried wiring BPR (VDD) may be formed on the side opposite to the diode region D10 side, and the buried wiring BPR (VSS) may be formed on the diode region D20 side.

[0076] Even in Figure 8 and Fig. 9 In the structure shown, Figures 2 to 4 and Figure 6 to Figure 7Similarly to the structure shown, conduction of the parasitic bipolar transistor between the well regions NW (VDD) and PW (VSS) can be suppressed. Alternatively, formation of the parasitic bipolar transistor between the diode regions D20 and D10 can be suppressed. Accordingly, the interval between the diode regions D20 and D10 can be narrowed, and the chip size of the semiconductor device SEM1 can be reduced.

[0077] As described above, in this embodiment, no semiconductor layer such as a diffusion region or a well region is formed between the diode regions D20 and D10 formed adjacent to each other in the ESD protection circuit PC. In addition, the well region NW (VDD) of the diode region D20 and the well region PW (VSS) of the diode region D10 are separated by the buried wiring BPR.

[0078] For this reason, the leakage current component between the well regions NW (VDD) and PW (VSS) can be reduced, and the conduction of the parasitic bipolar transistor can be suppressed. Alternatively, the formation of the parasitic bipolar transistor between the diode regions D20 and D10 can be suppressed. Therefore, the formation of the guard ring in the diode regions D20 and D10 can be omitted.

[0079] Thus, the interval between the diode regions D20 and D10 can be narrowed, and the chip size of the semiconductor device SEM1 can be reduced. In other words, when a plurality of diodes D20 and D10 are arranged adjacent to each other, the layout region of the diodes D20 and D10 can be prevented from increasing, thereby preventing the chip size of the semiconductor device SEM1 from increasing.

[0080] Figure 2 In the embodiment, by connecting the diffusion regions n+ of the transistors PFET21 and PFET23 formed along the Y direction of the transistor PFET22 to the buried wiring BPR (VDD), the power supply voltage VDD can be supplied to the well region NW (VDD) of the diode region D20. By connecting the diffusion regions p+ of the transistors NFET11 and NFET13 formed along the Y direction of the transistor NFET12 to the buried wiring BPR (VSS), the ground voltage VSS can be supplied to the well region PW (VSS) of the diode region D10.

[0081] Even when the diode regions D20 and D10 are alternately and repeatedly arranged in the X direction, the conduction of the parasitic bipolar transistor between the adjacent diode regions D20 and D10 or the formation of the parasitic bipolar transistor itself can be suppressed. Accordingly, the interval between the plurality of diodes D20 and D10 can be narrowed, and the chip size of the semiconductor device SEM1 can be reduced.

[0082] (Second embodiment)

[0083] Fig.10An example of the main part of the semiconductor device according to the second embodiment is shown. Figure 1 The same reference numerals are given to the same or similar elements, and detailed description thereof is omitted. Fig.10 The semiconductor device SEM2 shown may be a SoC, a single CPU, a GPU, a DSP, a FPGA, a memory, and the like.

[0084] Fig.10 The semiconductor device SEM2 shows an input buffer circuit IBUF and a buffer circuit BUF having different power domains and a bidirectional diode BID including diodes D30 and D40 connecting ground lines VSS1 and VSS2 to each other. Hereinafter, a region for forming the bidirectional diode BID is also referred to as a bidirectional diode region BID.

[0085] The input buffer circuit IBUF is formed in the power domain PD1, and the buffer circuit BUF is formed in the power domain PD2. The input buffer circuit IBUF is connected to the power line VDD1 and the ground line VSS1 instead of the power line VDD and the ground line VSS. Figure 1 The power supply line VDD1 is connected to the power supply pad VDD1P, and the ground line VSS1 is connected to the ground pad VSS1P. The power supply domain PD1 is an example of the first power supply domain, and the power supply domain PD2 is an example of the second power supply domain.

[0086] The buffer circuit BUF has an inverter including field effect transistors PFET11 and NFET11 connected in series between the power supply line VDD2 and the ground line VSS2. The gates of the transistors PFET11 and NFET11 are connected to the input node IN. The drains of the transistors PFET11 and NFET11 are connected to the output node OUT2 of the buffer circuit BUF.

[0087] The source and back gate of the transistor PFET11 are connected to the power line VDD2. The source and back gate of the transistor NFET11 are connected to the ground line VSS2. The power line VDD2 is connected to the power pad VDD2P, and the ground line VSS2 is connected to the ground pad VSS2.

[0088] The anode of diode D30 of bidirectional diode BID is connected to ground line VSS2, and the cathode is connected to ground line VSS1. The anode of diode D40 of bidirectional diode BID is connected to ground line VSS1, and the cathode is connected to ground line VSS2.

[0089] Fig.11 The plan view shows Fig.10 An example of the layout of the bidirectional diode region BID. Figure 2The same or similar elements are given the same reference numerals, and detailed description thereof is omitted. Hereinafter, the region for forming the diode D30 is also referred to as the diode region D30. The region for forming the diode D40 is also referred to as the diode region D40.

[0090] In the diode region D40, the buried wirings BPR arranged on both sides in the X direction are not connected to each other. Figure 2 The signal line SIG and the power line VDD are connected to the ground line VSS1 and the ground line VSS2 respectively. The other components and structures of the diode D40 are respectively similar to those of the Figure 2 The composition and structure of the diode region D20 are similar.

[0091] In the diode region D30, the buried wirings BPR arranged on both sides in the X direction are not connected to each other. Figure 2 The signal line SIG is not connected to the ground line VSS, but is connected to the ground line VSS1 and the ground line VSS2 respectively. The other components and structures of the diode D30 are respectively similar to those of the Figure 2 The composition and structure of the diode region D10 are similar.

[0092] For example, transistors PFET21-PFET23 and NFET11-NFET13 are nanosheet transistors, but may also be Figure 5 The FinFET transistor shown is formed. The diode regions D40 and D30 may be alternately and repeatedly arranged along the X direction. In addition, Figure 6 The structure shown is replaced by Fig.11 The structure shown.

[0093] As described above, even in this embodiment, an effect similar to that of the first embodiment can be obtained. For example, in the bidirectional diode BID, the well region NW (VDD) of the diode region D40 and the well region PW (VSS) of the diode region D30 formed adjacent to each other are separated by buried wirings BPR (VSS1) and BPR (VSS2). Accordingly, the conduction of the parasitic bipolar transistor can be suppressed, or the formation of the parasitic bipolar transistor between the diode regions D40 and D30 can be suppressed. Therefore, for example, the interval between the diode regions D40 and D30 formed at the boundary of the plurality of power domains PD1 and PD2 can be narrowed, and the chip size of the semiconductor device SEM2 can be reduced.

[0094] (Third embodiment)

[0095] Fig.12 An example of the main part of the semiconductor device according to the third embodiment is shown. Figure 1 The same reference numerals are given to the same or similar elements, and detailed description thereof is omitted. Fig.12The semiconductor device SEM3 shown may be a SoC, a single CPU, a GPU, a DSP, a FPGA, a memory, and the like. Fig.12 The diagram shows a fail-safe IO buffer (fail-safe IO buffer) FSBUF and an ESD clamp circuit CLMP in the semiconductor device SEM3.

[0096] The fault protection IO buffer FSBUF has an output control circuit OUTCNT, an input control circuit INCNT, a p-type field effect transistor PFET62, an n-type field effect transistor NFET52, and diodes D50, D60, D10, and D20. The diodes D50 and D60 are parasitic diodes formed when the transistors PFET62 and NFET52 are formed. Figure 1 Similarly, diodes D10 and D20 are formed as an ESD protection circuit PC.

[0097] When the power supply voltage VDD is not supplied from the power supply pad VDDP, the fail-safe IO buffer FSBUF is an IO buffer that allows input of a signal from the signal pad SIGP. When the power supply voltage VDD is not supplied from the power supply pad VDDP, the power supply line VDD is the ground voltage VSS. In this state, when a voltage is applied to the signal pad SIGP, in order to prevent a through current from flowing from the signal pad SIGP to the power supply line VDD of the ground voltage VSS, a known method can be used to control so that the current does not flow to the diodes D20 and D60 indicated by the dotted lines.

[0098] When the output enable signal OEN is at an active level, the output control circuit OUTCNT changes to an output mode and outputs a level opposite to the logic level of the internal output signal IOUT to the gates of the transistors PFET62 and NFET52. When the output enable signal OEN is at an inactive level, the output control circuit OUTCNT changes to an output disable mode and outputs a high level to the gate of the transistor PFET62 and a low level to the gate of the transistor NFET52. Accordingly, the output control circuit OUTCNT operates as a tri-state buffer.

[0099] When the output enable signal OEN is at a high level, the input control circuit INCNT changes to an input mode. In the input mode, when the input selection signal INSEL is at an effective level, the input control circuit INCNT outputs the signal SIG received by the signal pad SIGP as the internal input signal IIN. In the input mode, when the input selection signal INSEL is at an inactive level, the input control circuit INCNT fixes the internal input signal IIN to a low level regardless of the logic level of the signal SIG received by the signal pad SIGP.

[0100] When a positive ESD voltage is applied from the signal pad SIGP with the power supply voltage VDD as a reference, a current flows from the signal pad SIGP to the power supply line VDD via the ground line VSS and the clamp circuit CLMP due to the parasitic bipolar action (effect) of the transistor NFET52. In addition, when a negative ESD voltage is applied from the signal pad SIGP with the power supply voltage VDD as a reference, the clamp circuit CLMP causes a current to flow from the power supply line VDD to the ground line VSS. The current flowing into the ground line VSS flows to the signal pad SIGP via the diodes D50 and D10.

[0101] Accordingly, the fault protection IO buffer FSBUF can be protected from ESD discharge. It should be noted that the operation when a positive ESD voltage is applied from the signal pad SIGP with the ground voltage VSS as a reference is similar to the operation when a positive ESD voltage is applied with the power supply voltage VDD as a reference. The operation when a negative ESD voltage is applied from the signal pad SIGP with the ground voltage VSS as a reference is similar to the operation when a negative ESD voltage is applied with the power supply voltage VDD as a reference.

[0102] Fig.13 The plan view shows Fig.12 An example of the layout of transistors PFET62 and NFET52 and diodes D60 and D50. Figure 2 The same or similar elements are given the same reference numerals, and detailed description thereof is omitted. Fig.13 The cross-sectional structure along the line X1-X2 of FIG. 1 is similar to that of FIG. 1 except that the formation position of the through hole V is different. Figure 3 Similar. Along Fig.13 The cross-sectional structure of the Y1-Y2 line is Figure 4 Hereinafter, the region where the diode D60 is formed is also referred to as the diode region D60 , and the region where the diode D50 is formed is also referred to as the diode region D50 .

[0103] The diode region D60 includes transistors PFET61, PFET62, and PFET63. The diffusion regions n+ and n+ of the transistors PFET61 and PFET63 are connected to each other. Figure 2 The diffusion regions n+ of the transistors PFET21 and PFET23 are similarly connected to the power supply line VDD via the local wiring LI, the via V1, and the buried wiring BPR.

[0104] In the transistor PFET62, the diffusion region p+ arranged on one side of the Y direction with the gate electrode GT sandwiched therebetween is connected to the signal line SIG via the local wiring LI, the through hole V1, and the buried wiring BPR (SIG). In addition, in the transistor PFET62, the diffusion region p+ arranged on the other side of the Y direction with the gate electrode GT sandwiched therebetween is connected to the power supply line VDD via the local wiring LI, the through hole V1, and the buried wiring BPR (VDD). Thus, the transistor PFET62 operating as a circuit can be formed. The transistor PFET62 is an example of a first transistor, and the gate electrode of the transistor PFET62 is an example of a first gate electrode.

[0105] The diode region D50 includes transistors NFET51, NFET52, and NFET53. The diffusion regions p+ and p-type of the transistors NFET51 and NFET53 are connected to each other. Figure 2 The diffusion regions p+ of the transistors NFET11 and NFET13 are similarly connected to the ground line VSS via the local wiring LI, the via V1, and the buried wiring BPR (VSS).

[0106] In the transistor NFET52, the diffusion region n+ arranged on one side of the Y direction with the gate electrode GT sandwiched therebetween is connected to the signal line SIG via the local wiring LI, the through hole V1, and the buried wiring BPR (SIG). In addition, in the transistor NFET52, the diffusion region n+ arranged on the other side of the Y direction with the gate electrode GT sandwiched therebetween is connected to the ground line VSS via the local wiring LI, the through hole V1, and the buried wiring BPR (VSS). Thus, a transistor NFET52 that operates as a circuit can be formed. In addition, the transistor NFET52 is connected to the well region PW (VSS) via the diffusion region n+, so that a parasitic bipolar effect via the well region PW can be generated. The transistor NFET52 is an example of a second transistor, and the gate electrode of the transistor NFET52 is an example of a second gate electrode.

[0107] The diode D60 is formed by a pn junction between the p-type diffusion region p+ and the n-type well region NW (VDD) of the transistor PFET62. The diode D50 is formed by a pn junction between the p-type well region PW (VSS) and the n-type diffusion region n+ of the transistor NFET52.

[0108] Based on this, it can be formed Fig.12 The circuit shown is based on transistors PFET62, NFET52, and diodes D60 and D50. In other words, diode D60 is formed as a parasitic diode of transistor PFET62, and diode D50 is formed as a parasitic diode of transistor NFET53.

[0109] For example, transistors PFET61-PFET63 and NFET51-NFET53 are nanosheet transistors, but may also be Figure 5 The FinFET transistor shown is formed. The diode regions D60 and D50 may be alternately and repeatedly arranged along the X direction. In addition, Figure 6 or Figure 8 The structure shown is replaced by Fig.13 The structure shown.

[0110] In addition, when the transistor PFET62 is a nanosheet transistor, the diffusion region p+ and the well region NW (VDD) of the transistor PFET62 may be insulated by an STI film or the like. Fig.12 The diode D20 and Figure 2 Similarly, in the case of transistors formed from nanosheets, Figure 3 The diffusion region p+ and the well region NW (VDD) shown in the figure can be insulated by an STI film or the like. Fig.12 The diodes D60 and D20 indicated by the dotted lines in the figure no longer exist, so there is no need to perform control to suppress the above-mentioned through current.

[0111] As described above, this embodiment also has effects similar to those of the first embodiment. For example, formation of a parasitic bipolar transistor between the well regions NW (VDD) and PW (VSS) of the diode regions D60 and D50 formed adjacent to each other in the fail-safe IO buffer FSBUF can be suppressed.

[0112] Thus, the interval between the diode regions D60 and D50 can be narrowed, and the chip size of the semiconductor device SEM3 can be reduced. In other words, even when the diodes D60 and D50 are formed as parasitic diodes of the transistors PFET62 and NFET52, the interval between the diode regions D60 and D50 can be narrowed, and the chip size of the semiconductor device SEM3 can be reduced.

[0113] Although the present invention has been described above based on the various embodiments, the present invention is not limited to the requirements described in the above embodiments. These can be changed within the scope of the gist of the present invention and can be appropriately determined according to the application form.

[0114] [Explanation of Reference Numerals]

[0115] BID bidirectional diode

[0116] BPR buried wiring

[0117] BUF buffer circuit

[0118] CLMP clamp circuit

[0119] D10, D20, D30, D40, D50, D60 diodes

[0120] FSBUF Fault-Protected IO Buffer

[0121] GT gate electrode

[0122] IBUF input buffer circuit

[0123] IIN internal input signal

[0124] IN Input Node

[0125] INCNT input control circuit

[0126] INS1, INS2 insulation film

[0127] INSEL input selection signal

[0128] IOUT internal output signal

[0129] LI local wiring

[0130] NFET Field Effect Transistor

[0131] NS Nanosheets

[0132] NW (VDD) well region

[0133] n+, n- diffusion regions

[0134] OEN output enable signal

[0135] OUT, OUT2 output nodes

[0136] OUTCNT output control circuit

[0137] PC protection circuit

[0138] PD1, PD2 power domain

[0139] PFET Field Effect Transistor

[0140] PSUB semiconductor substrate

[0141] PW (VSS) well area

[0142] p+, p- diffusion regions

[0143] SEM1, SEM2, SEM3 semiconductor devices

[0144] SIG signal line

[0145] SIGP signal pad

[0146] VDD, VDD1, VDD2 power lines

[0147] VDD1P, VDD2P, VDDP power pads

[0148] V1, V2, V3 through holes

[0149] VSS, VSS1, VSS2 ground wires

[0150] VSS1P, VSS2P, VSSP ground pads

[0151] W1, W2 wiring.

Claims

1. A semiconductor device comprising: substrate; A first impurity region having a first conductivity type and a second impurity region having a second conductivity type are formed on the substrate at intervals along a first direction in a plan view; a third impurity region having the second conductivity type, formed on the substrate in contact with the first impurity region; a fourth impurity region having the first conductivity type, formed on the substrate in contact with the second impurity region; a first wiring formed on the substrate along a second direction different from the first direction on the fourth impurity region side of the third impurity region in a plan view; and The second wiring is formed on the substrate along the second direction on the third impurity region side of the fourth impurity region in a plan view.

2. The semiconductor device according to claim 1, comprising: a fifth impurity region having the second conductivity type, formed on the third impurity region at a distance from the first impurity region in the second direction; and A sixth impurity region having the first conductivity type is formed on the fourth impurity region at a distance from the second impurity region in the second direction.

3. The semiconductor device according to claim 1 or claim 2, comprising: a third wiring formed on the substrate along the second direction on the opposite side of the third impurity region to the first wiring side in a plan view; and A fourth wiring is formed on the substrate along the second direction on the side opposite to the second wiring side of the fourth impurity region in a plan view.

4. The semiconductor device according to claim 3, comprising: a fifth impurity region having the second conductivity type, formed on the third impurity region at a distance from the first impurity region in the second direction; and a sixth impurity region having the first conductivity type, formed on the fourth impurity region at a distance from the second impurity region in the second direction, in, The first impurity region and the second impurity region are connected to a signal line, The third impurity region and the fifth impurity region are connected to one of a first power line and a second power line, and a voltage of the second power line is different from a voltage of the first power line. The fourth impurity region and the sixth impurity region are connected to the other of the first power line and the second power line, The first wiring is connected to one of the first power line and the signal line. The third wiring is connected to the other of the first power line and the signal line. The second wiring is connected to one of the second power line and the signal line. The fourth wiring is connected to the other of the second power line and the signal line.

5. The semiconductor device according to claim 3, comprising: a fifth impurity region having the second conductivity type, formed on the third impurity region at a distance from the first impurity region in the second direction; and a sixth impurity region having the first conductivity type, formed on the fourth impurity region at a distance from the second impurity region in the second direction, in, The first impurity region and the second impurity region are connected to one of a power line of a first power domain and a power line of a second power domain. The fifth impurity region and the sixth impurity region are connected to the other of the power line of the first power domain and the power line of the second power domain. The first wiring is connected to one of a power line of the first power domain and a power line of the second power domain. The third wiring is connected to the other of the power line of the first power domain and the power line of the second power domain. The second wiring is connected to one of the power line of the first power domain and the power line of the second power domain. The fourth wiring is connected to the other of the power line of the first power domain and the power line of the second power domain.

6. The semiconductor device according to claim 1 or claim 2, comprising: a first gate electrode disposed on the third impurity region; a second gate electrode disposed on the fourth impurity region; a first transistor comprising the first gate electrode and the first impurity regions arranged on both sides of the first gate electrode in a plan view; and The second transistor includes the second gate electrode and the second impurity regions arranged on both sides of the second gate electrode in a plan view.

7. The semiconductor device according to claim 6, comprising: a third wiring formed on the substrate along the second direction on the opposite side of the third impurity region to the first wiring side in a plan view; and a fourth wiring formed on the substrate along the second direction on the opposite side of the fourth impurity region from the second wiring in a plan view, in, One of the first impurity regions disposed on both sides of the first gate electrode is connected to one of a first power supply line and a signal line, The other of the first impurity regions disposed on both sides of the first gate electrode is connected to the other of the first power supply line and the signal line, One of the second impurity regions disposed on both sides of the second gate electrode is connected to one of a second power supply line and the signal line, The other of the second impurity regions disposed on both sides of the second gate electrode is connected to the other of the second power supply line and the signal line.

8. The semiconductor device according to claim 7, wherein: The first wiring is connected to one of the first power line and the signal line. The third wiring is connected to the other of the first power line and the signal line. The second wiring is connected to one of the second power line and the signal line, and the fourth wiring is connected to the other of the second power line and the signal line.

9. The semiconductor device according to claim 6, wherein: The first transistor and the second transistor are nanosheet transistors.

10. The semiconductor device according to claim 6, wherein: The first transistor and the second transistor are FinFET transistors.

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