Amplification circuit and amplification method

Abstract

An amplifier circuit (10) configured so as to amplify a high-frequency signal using a plurality of discrete voltages supplied from a tracker circuit (5) within one frame of the high-frequency signal, the amplifier circuit (10) being provided with: a power amplifier (11); and an RC series circuit (17) including a resistor (R1) and a capacitor (C1) connected in series between a voltage supply path (P1) between the tracker circuit (5) and the power amplifier (11) and ground.

Description

Technical Field

[0001] The invention relates to an amplifier circuit and an amplifier method. Background Art

[0002] In recent years, the power added efficiency (PAE) has been improved by applying an envelope tracking (ET) mode to a power amplifier circuit. Patent document 1 discloses a technique for supplying a plurality of discrete voltages to a power amplifier circuit in the ET mode.

[0003] Patent Document 1: U.S. Patent No. 9755672

[0004] However, when a plurality of discrete voltages are supplied to an amplifier circuit as in Patent Document 1, the amplification characteristics of the amplifier circuit may deteriorate. Summary of the invention

[0005] Therefore, the present invention provides an amplifier circuit and an amplification method capable of improving the amplification characteristics of a high-frequency signal.

[0006] An amplifier circuit of one embodiment of the present invention is configured to amplify a high-frequency signal using multiple discrete voltages supplied from a tracker circuit within one frame of the high-frequency signal, and the amplifier circuit comprises: a power amplifier; and an RC series circuit, including a resistor and a first capacitor connected in series between a voltage supply path between the tracker circuit and the power amplifier and ground.

[0007] An amplifier circuit according to one embodiment of the present invention comprises: a power amplifier; an RC series circuit including a resistor and a first capacitor connected in series between a voltage supply path for the power amplifier and ground; and a first bypass capacitor circuit including a second capacitor connected between the voltage supply path and ground.

[0008] An amplification method according to one aspect of the present invention is a method for amplifying a high-frequency signal, wherein in the amplification method, a plurality of discrete voltages are supplied within one frame of the high-frequency signal, an RC series circuit is used to attenuate the ringing of the plurality of discrete voltages, and the plurality of discrete voltages after the ringing is attenuated are used to amplify the high-frequency signal.

[0009] According to the present invention, it is possible to improve the amplification characteristics of high-frequency signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A This is a graph showing an example of transition of the power supply voltage in the average power tracking mode.

[0011] Figure 1BThis is a graph showing an example of transition of the power supply voltage in the digital envelope tracking mode.

[0012] Figure 1C This is a graph showing an example of the transition of the power supply voltage in the analog envelope tracking mode.

[0013] Figure 2 It is a circuit configuration diagram of a communication device according to an embodiment.

[0014] Figure 3 is a flow chart showing an amplification method according to an embodiment.

[0015] Figure 4 4 is a top view of the power amplifier module of the embodiment.

[0016] Figure 5 4 is a top view of the power amplifier module of the embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, the embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below all represent general or specific examples. The numerical values, shapes, materials, components, configurations of components, and connection methods shown in the following embodiments are examples and are not intended to limit the present invention.

[0018] In addition, each figure is a schematic diagram after appropriately emphasizing, omitting or adjusting the ratio in order to express the present invention, and is not necessarily strictly illustrated, and sometimes differs from the actual shape, positional relationship and ratio. In each figure, the same reference numerals are marked for substantially the same structure, and repeated descriptions are sometimes omitted or simplified.

[0019] In the following figures, the x-axis and the y-axis are axes that are orthogonal to each other on a plane parallel to the main surface of the module substrate. Specifically, when the module substrate has a rectangular shape in a plan view, the x-axis is parallel to the first side of the module substrate, and the y-axis is parallel to the second side of the module substrate that is orthogonal to the first side. In addition, the z-axis is an axis perpendicular to the main surface of the module substrate, and its positive direction indicates the upward direction, and its negative direction indicates the downward direction.

[0020] In the circuit structure of the present invention, "connection" includes not only direct connection using connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Connection between A and B" means connection between A and B and both A and B, and connection in series on a path between A and B. "Path between A and B" means a path formed by a conductor that electrically connects A and B.

[0021] In the component configuration of the present invention, "components are configured on a substrate" includes components configured on the main surface of a substrate and components configured inside a substrate. "Components are configured on the main surface of a substrate" includes not only components configured in contact with the main surface of a substrate, but also components configured above the main surface without contacting the main surface (for example, components are stacked on other components configured in contact with the main surface). In addition, "components are configured on the main surface of a substrate" may also include components configured in recesses formed on the main surface. "Components are configured inside a substrate" includes not only components encapsulated in a module substrate, but also components entirely configured between the two main surfaces of a substrate but a portion of the component is not covered by the substrate, and only a portion of the component is configured inside a substrate.

[0022] In addition, in the component arrangement of the present invention, "a top view of the module substrate" means observing the object by orthogonally projecting it onto the xy plane from the positive side of the z-axis. "A and B overlap when viewed from above" means that at least a portion of the area of ​​A orthogonally projected onto the xy plane overlaps at least a portion of the area of ​​B orthogonally projected onto the xy plane. In addition, "A is arranged between B and C" means that at least one of the multiple line segments connecting an arbitrary point in B and an arbitrary point in C passes through A.

[0023] In the present invention, a "terminal" refers to a point where a conductor in an element ends. In addition, when the impedance of a path between elements is sufficiently low, a terminal is interpreted not only as a single point but also as an arbitrary point on the path between elements or the entire path.

[0024] In addition, terms such as “parallel” and “perpendicular” indicating the relationship between elements, terms such as “rectangular” indicating the shape of an element, and numerical ranges do not have strict meanings but also include substantially equivalent ranges, such as errors of several %.

[0025] (Implementation Method)

[0026] Hereinafter, embodiments will be described with reference to the drawings.

[0027] [1.1 Description of tracking mode]

[0028] First, in this embodiment, a tracking mode applied to a voltage supplied to an amplifier circuit is described. The tracking mode is a mode for dynamically adjusting a power supply voltage applied to a power amplifier circuit. There are several types of tracking modes, but in this embodiment, the tracking mode is described in detail. Figure 1A to Figure 1C The average power tracking (APT) mode, digital envelope tracking (ET) mode, and analog ET mode are explained. Figure 1A to Figure 1CIn FIG. 1 , the horizontal axis represents time and the vertical axis represents voltage. In addition, the thick solid line represents the power supply voltage and the thin solid line (waveform) represents the modulation signal.

[0029] Figure 1A 1 is a graph showing an example of the transition of the power supply voltage in the APT mode. In the APT mode, the power supply voltage is varied to a plurality of discrete voltage levels in units of one frame based on the average power. That is, in the APT mode, a plurality of discrete voltages are supplied in units of one frame.

[0030] A frame refers to a unit that constitutes a high-frequency signal (modulated signal), and is pre-defined by standardization groups such as 3GPP (registered trademark) (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame includes 10 subframes, each subframe includes multiple time slots, and each time slot consists of multiple symbols. Each symbol may also include a cyclic prefix (CP). For example, the symbol length is 71μs, the time slot length is 0.5ms, the subframe length is 1ms, and the frame length is 10ms.

[0031] In addition, in this embodiment, a mode in which the voltage level is varied in units of 1 frame or in units larger than 1 frame based on average power is referred to as an APT mode, and is distinguished from a mode in which the voltage level is varied in units smaller than 1 frame (e.g., a subframe, a time slot, or a symbol). For example, a mode in which the voltage level is varied in units of a symbol is referred to as a symbol power tracking (SPT: Symbol Power Tracking) mode, and is distinguished from the APT mode.

[0032] Figure 1B This is a graph showing an example of the transition of the power supply voltage in the digital ET mode. In the digital ET mode, the power supply voltage is varied to a plurality of discrete voltage levels within one frame based on the envelope signal. That is, in the digital ET mode, a plurality of discrete voltages are supplied within one frame.

[0033] The envelope signal is a signal representing the envelope of the modulation signal. The envelope value is, for example, (I 2 +Q 2). Here, (I, Q) represents a constellation point. A constellation point is a point on a constellation diagram that represents a signal modulated by digital modulation. (I, Q) is determined by BBIC4 based on transmission information, for example.

[0034] Furthermore, generally speaking, in the digital ET mode, a plurality of discrete voltages are switched at high speed, so more high-frequency noise, particularly ringing, is generated than in the APT mode, which may deteriorate the quality of PAE and transmission signals.

[0035] Figure 1C 1 is a graph showing an example of the transition of the power supply voltage in the analog ET mode. In the analog ET mode, the power supply voltage is continuously varied based on the envelope signal. That is, in the analog ET mode, a continuous voltage is supplied.

[0036] Furthermore, in general, a DC-DC converter capable of variable output is used in the analog ET mode, so when the envelope of the modulation signal changes at a high speed, it is difficult to make the power supply voltage follow the envelope.

[0037] [1.2 Circuit structure]

[0038] Next, refer to Figure 2 The circuit configurations of the communication device 9 , the high-frequency circuit 1 , and the amplifier circuit 10 according to the present embodiment will be described. Figure 2 It is a circuit configuration diagram of the communication device 9 according to the present embodiment.

[0039] [1.2.1 Circuit Structure of Communication Device 9]

[0040] First, the circuit structure of the communication device 9 is described. Figure 2 As shown, the communication device 9 of the present embodiment includes a high frequency circuit 1 , an antenna 2 , a RFIC (Radio Frequency Integrated Circuit) 3 , a BBIC (Baseband Integrated Circuit) 4 , and a tracker circuit 5 .

[0041] The high frequency circuit 1 transmits a high frequency signal between the antenna 2 and the RFIC 3. The internal structure of the high frequency circuit 1 will be described later.

[0042] The antenna 2 is connected to the antenna connection terminal 100 of the high frequency circuit 1 and transmits the high frequency signal output from the high frequency circuit 1. Alternatively, the antenna 2 may receive a high frequency signal from the outside and output it to the high frequency circuit 1.

[0043] RFIC3 is an example of a signal processing circuit that processes a high-frequency signal. Specifically, RFIC3 performs signal processing on a transmission signal input from BBIC4 by up-conversion or the like, and outputs the high-frequency transmission signal generated by the signal processing to the transmission path of the high-frequency circuit 1. Furthermore, RFIC3 may also perform signal processing on a high-frequency reception signal input via the reception path of the high-frequency circuit 1 by down-conversion or the like, and output the reception signal generated by the signal processing to BBIC4. In addition, RFIC3 has a control unit that controls the high-frequency circuit 1 and the tracker circuit 5. Furthermore, part or all of the functions of the control unit of RFIC3 may also be installed outside RFIC3, for example, may also be installed on BBIC4 or the high-frequency circuit 1.

[0044] BBIC 4 is a baseband signal processing circuit that performs signal processing using an intermediate frequency band lower than the high frequency signal transmitted by high frequency circuit 1. As the signal processed by BBIC 4, for example, an image signal for image display and / or an audio signal for communication via a speaker are used.

[0045] The tracker circuit 5 supplies the power supply voltage to the high frequency circuit 1. Here, the tracker circuit 5 can supply voltage in analog ET mode, digital ET mode and APT mode, and has a digital envelope tracker (digital ET) / average power tracker (APT) 6, an analog envelope tracker (analog ET) 7 and a mode switching switch 8.

[0046] The digital ET / APT6 can supply the power supply voltage to the amplifier circuit 10 in the digital ET mode or the APT mode. For example, the digital ET / APT6 prepares a plurality of discrete voltages in advance, and uses a switch (not shown) to select and output at least one voltage from the plurality of discrete voltages prepared in advance. Thus, the digital ET / APT6 can switch the plurality of discrete voltages supplied to the amplifier circuit 10 through the switch.

[0047] For example, in the digital ET mode, the digital ET / APT6 selects and outputs a plurality of discrete voltages in one frame based on the envelope signal. Also, for example, in the APT mode, the digital ET / APT6 selects and outputs a plurality of discrete voltages in units of one frame or in units larger than one frame based on the average power.

[0048] Furthermore, the digital ET / APT6 may not prepare a plurality of discrete voltages in advance, and may not select and output a voltage from a plurality of discrete voltages by a switch. For example, the digital ET / APT6 may generate and output a plurality of discrete voltages at any time.

[0049] The analog ET 7 can supply the power supply voltage to the amplifier circuit 10 in the analog ET mode. Specifically, the analog ET 7 outputs a continuous voltage based on the envelope signal.

[0050] The mode switching switch 8 is connected between the digital ET / APT6 and the analog ET7 and the amplifier circuit 10. The mode switching switch 8 can selectively connect the digital ET / APT6 and the analog ET7 to the amplifier circuit 10 based on the control signal from the RFIC3. By connecting the digital ET / APT6 to the amplifier circuit 10, the power supply voltage is supplied to the amplifier circuit 10 in the digital ET mode or the APT mode. In addition, by connecting the analog ET7 to the amplifier circuit 10, the power supply voltage is supplied to the amplifier circuit 10 in the analog ET mode.

[0051] also, Figure 2 The circuit configuration of the communication device 9 shown is an example and is not limited thereto. For example, the communication device 9 may not include the antenna 2 and / or the BBIC 4. In addition, for example, the communication device 9 may include a plurality of antennas.

[0052] [1.2.2 Circuit structure of high frequency circuit 1]

[0053] Next, the circuit structure of the high-frequency circuit 1 will be described. Figure 2 As shown, the high frequency circuit 1 includes an amplifier circuit 10, a filter 20, a switch 30, an antenna connection terminal 100, a high frequency input terminal 111, a power supply voltage terminal 112, and a control terminal 113. The components of the high frequency circuit 1 are described below in order.

[0054] The antenna connection terminal 100 is connected to the switch 30 in the high frequency circuit 1, and is connected to the antenna 2 outside the high frequency circuit 1. The high frequency signal amplified by the amplifier circuit 10 is output to the antenna 2 via the antenna connection terminal 100. In addition, the high frequency signal received by the antenna 2 can also be input to the high frequency circuit 1 via the antenna connection terminal 100.

[0055] The high frequency input terminal 111 is a terminal for receiving a high frequency signal from the outside of the high frequency circuit 1. The high frequency input terminal 111 is connected to the RFIC 3 outside the high frequency circuit 1, and is connected to the power amplifier 11 via the matching circuit 13 inside the amplifier circuit 10. Thus, the high frequency signal received from the RFIC 3 via the high frequency input terminal 111 is supplied to the power amplifier 11.

[0056] The power supply voltage terminal 112 is a terminal for receiving a power supply voltage from the tracker circuit 5. The power supply voltage terminal 112 is connected to the tracker circuit 5 outside the amplifier circuit 10, and is connected to the power amplifiers 11 and 12 via the inductors L1 and L2 inside the amplifier circuit 10. Thus, the power supply voltage received from the tracker circuit 5 via the power supply voltage terminal 112 is supplied to the power amplifiers 11 and 12.

[0057] The control terminal 113 is a terminal for transmitting a control signal. In other words, the control terminal 113 is a terminal for receiving a control signal from outside the amplifier circuit 10 and / or a terminal for supplying a control signal to outside the amplifier circuit 10 .

[0058] The amplifier circuit 10 can amplify the high-frequency signal using the voltage supplied from the tracker circuit 5. The internal structure of the amplifier circuit 10 will be described later.

[0059] The filter 20 is connected between the amplifier circuit 10 and the antenna connection terminal 100. Specifically, one end of the filter 20 is connected to the amplifier circuit 10. On the other hand, the other end of the filter 20 is connected to the antenna connection terminal 100 via the switch 30. The filter 20 is, for example, a bandpass filter having a passband including a predetermined frequency band for transmission.

[0060] The prescribed frequency band is a frequency band used for a communication system built using a radio access technology (RAT). The prescribed frequency band is predefined by a standardization group (e.g., 3GPP and IEEE). Examples of communication systems include 5GNR systems, LTE systems, and WLAN (Wireless Local Area Network) systems.

[0061] The switch 30 is connected between the antenna connection terminal 100 and the filter 20. The switch 30 includes a terminal connected to the antenna connection terminal 100 and a terminal connected to the filter 20. In addition, the switch 30 may also include a terminal connected to a filter (not shown) having a passband different from that of the filter 20. In addition, the switch 30 may also include a terminal connected to a filter (not shown) for reception.

[0062] also, Figure 2 The high frequency circuit 1 shown is an example and is not limited thereto. For example, the high frequency circuit 1 may not include the switch 30. Furthermore, the high frequency circuit 1 may not include a receiving path. In this case, a receiving filter, a low noise amplifier, etc. may also be connected to the receiving path. In addition, for example, the high frequency circuit 1 may also include a plurality of antenna connection terminals.

[0063] [1.2.3 Circuit structure of amplifier circuit 10]

[0064] Next, the circuit structure of the amplifier circuit 10 is described. Figure 2As shown, the amplifier circuit 10 includes power amplifiers 11 and 12, inductors L1 and L2, matching circuits (matching networks: MN) 13 to 15, a PA (Power Amplifier) ​​control circuit 16, an RC series circuit 17, and bypass capacitor circuits 18 and 19. The components of the amplifier circuit 10 will be described in order below.

[0065] The power amplifier 11 is configured to amplify a high frequency signal input from a high frequency input terminal 111 and output the amplified signal to the power amplifier 12. Specifically, the power amplifier 11 is disposed at a preceding stage (driver stage) of the power amplifier 12 and includes an amplification transistor T1.

[0066] In the present embodiment, the amplifier transistor T1 is a bipolar transistor having a base terminal, a collector terminal, and an emitter terminal. The base terminal of the amplifier transistor T1 is connected to the high-frequency input terminal 111 via a matching circuit 13. The collector terminal of the amplifier transistor T1 is connected to the power supply voltage terminal 112 via an inductor L1, and is connected to the input end of the power amplifier 12 via a matching circuit 14. The emitter terminal of the amplifier transistor T1 is connected to the ground. In addition, the amplifier transistor T1 is not limited to a bipolar transistor. For example, the amplifier transistor T1 may also be a field effect transistor. In this case, the base terminal, the collector terminal, and the emitter terminal are replaced by a gate terminal, a drain terminal, and a source terminal.

[0067] The power amplifier 12 is configured to further amplify the high frequency signal amplified by the power amplifier 11 and output the amplified signal to the filter 20. Specifically, the power amplifier 12 is disposed at a subsequent stage (power stage) of the power amplifier 11 and includes an amplification transistor T2.

[0068] In the present embodiment, the amplifier transistor T2 is a bipolar transistor having a base terminal, a collector terminal, and an emitter terminal. The base terminal of the amplifier transistor T2 is connected to the output terminal of the power amplifier 11 via the matching circuit 14. The collector terminal of the amplifier transistor T2 is connected to the power supply voltage terminal 112 via the inductor L2, and is connected to the filter 20 via the matching circuit 15. The emitter terminal of the amplifier transistor T2 is connected to the ground. In addition, the amplifier transistor T2 is not limited to a bipolar transistor. For example, the amplifier transistor T2 may also be a field effect transistor. In this case, the base terminal, the collector terminal, and the emitter terminal are replaced by a gate terminal, a drain terminal, and a source terminal.

[0069] The inductor L1 is a so-called choke inductor connected in series to the voltage supply path P1 between the power supply voltage terminal 112 and the power amplifiers 11 and 12. Specifically, both ends of the inductor L1 are connected to the collector terminal of the amplifier transistor T1 and the power supply voltage terminal 112, respectively.

[0070] The inductor L2 is connected in series to the voltage supply path P1 and is a so-called choke inductor. Specifically, both ends of the inductor L2 are connected to the collector terminal of the amplifier transistor T2 and the power supply voltage terminal 112, respectively.

[0071] The matching circuit 13 includes, for example, an inductor and / or a capacitor, and is connected between the high-frequency input terminal 111 and the input end of the power amplifier 11. The matching circuit 13 can achieve impedance matching between the high-frequency input terminal 111 and the power amplifier 11.

[0072] The matching circuit 14 includes, for example, an inductor and / or a capacitor, and is connected between the output terminal of the power amplifier 11 and the input terminal of the power amplifier 12. The matching circuit 14 can achieve impedance matching between the power amplifiers 11 and 12.

[0073] The matching circuit 15 includes, for example, an inductor and / or a capacitor, and is connected between the output terminal of the power amplifier 12 and the filter 20. The matching circuit 15 can achieve impedance matching between the power amplifier 12 and the filter 20.

[0074] The PA control circuit 16 is a power amplifier controller (PAC) that controls the power amplifiers 11 and 12. The PA control circuit 16 controls, for example, bias currents supplied to base terminals of the amplifier transistors T1 and T2. The PA control circuit 16 may not be included in the amplifier circuit 10.

[0075] The RC series circuit 17 includes a resistor R1, a capacitor C1, and a switch SW1 connected in series between the voltage supply path P1 and the ground, and functions as an RC snubber that can be switched on and off. That is, the RC series circuit 17 is configured to suppress transient voltage in the voltage supply path P1 when in the on state.

[0076] The resistor R1 is connected between the voltage supply path P1 and the ground, and is connected in series with the capacitor C1 and the switch SW1. In this embodiment, the resistor R1 is connected between the voltage supply path P1 and the capacitor C1. That is, one end of the resistor R1 is connected to the voltage supply path P1, and the other end of the resistor R1 is connected to one of the electrodes of the capacitor C1.

[0077] The capacitor C1 is an example of a first capacitor, connected between the voltage supply path P1 and the ground, and connected in series with the resistor R1 and the switch SW1. In this embodiment, the capacitor C1 is connected between the resistor R1 and the switch SW1. That is, one end of the electrode of the capacitor C1 is connected to the other end of the resistor R1, and the other end of the electrode of the capacitor C1 is connected to the switch SW1.

[0078] The switch SW1 is an example of a first switch, connected between the voltage supply path P1 and the ground, and connected in series with the resistor R1 and the capacitor C1. In the present embodiment, the switch SW1 is connected between the capacitor C1 and the ground. That is, the switch SW1 includes a terminal connected to the capacitor C1 and a terminal connected to the ground. By switching the connection / disconnection between the two terminals, the voltage supply path P1 is switched to be connected / disconnected to the ground via the resistor R1 and the capacitor C1. Thus, the connection / disconnection of the RC series circuit 17 is switched.

[0079] More specifically, in a situation where a plurality of discrete voltages are supplied to the power amplifiers 11 and 12 in one frame based on the digital ET mode, the switch SW1 connects the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1. On the other hand, in a situation where a plurality of discrete voltages are supplied to the power amplifiers 11 and 12 in units of one frame based on the APT mode, and in a situation where a continuous voltage is supplied to the power amplifiers 11 and 12 based on the analog ET mode, the switch SW1 does not connect the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1.

[0080] also, Figure 2 The circuit structure of the RC series circuit 17 shown is an example and is not limited thereto. For example, the connection order of the resistor R1, the capacitor C1, and the switch SW1 may be changed, and the switch SW1 may be connected between the voltage supply path P1 and the resistor R1. In addition, for example, the switch SW1 may not be included in the RC series circuit 17, and the RC series circuit 17 may not be switched on / off. In addition, a plurality of RC series circuits 17 may be connected in parallel to the voltage supply path P1.

[0081] The bypass capacitor circuit 18 is an example of a first bypass capacitor circuit, includes a capacitor C2 and a switch SW2 connected in series between the voltage supply path P1 and the ground, and functions as a bypass capacitor that can be switched on and off.

[0082] Capacitor C2 is an example of a second capacitor, connected between the voltage supply path P1 and the ground, and connected in series with the switch SW2. In this embodiment, capacitor C2 is connected between the voltage supply path P1 and the switch SW2. That is, one side of the electrode of capacitor C2 is connected to the voltage supply path P1, and the other side of the electrode of capacitor C2 is connected to the switch SW2.

[0083] As the electrostatic capacitance of the capacitor C2, for example, 1 microfarad is used. Thus, when a plurality of discrete voltages are supplied from the tracker circuit in units of one frame of the high-frequency signal or in units larger than one frame, it can contribute to stabilization of the voltage within the unit. In addition, the electrostatic capacitance of the capacitor C2 is not limited to 1 microfarad, and can be appropriately changed according to the required specifications of the amplifier circuit 10, etc.

[0084] The switch SW2 is an example of a second switch, connected between the voltage supply path P1 and the ground, and connected in series with the capacitor C2. In the present embodiment, the switch SW2 is connected between the capacitor C2 and the ground. That is, the switch SW2 includes a terminal connected to the capacitor C2 and a terminal connected to the ground. By switching the connection / disconnection between the two terminals, the voltage supply path P1 is switched to be connected / disconnected to the ground via the capacitor C2. Thus, the bypass capacitor circuit 18 is switched on / off.

[0085] More specifically, in a situation where a plurality of discrete voltages are supplied to the power amplifiers 11 and 12 in units of one frame or in units larger than one frame based on the APT mode, the switch SW2 connects the voltage supply path P1 to the ground via the capacitor C2. On the other hand, in a situation where a plurality of discrete voltages are supplied to the power amplifiers 11 and 12 in one frame based on the digital ET mode, and in a situation where a continuous voltage is supplied to the power amplifiers 11 and 12 based on the analog ET mode, the switch SW2 does not connect the voltage supply path P1 to the ground via the capacitor C2.

[0086] The bypass capacitor circuit 18 is connected between the voltage supply path P1 between the RC series circuit 17 and the power amplifiers 11 and 12 and the ground. In other words, the bypass capacitor circuit 18 is connected to a point on the voltage supply path P1 that is closer to the power amplifiers 11 and 12 than the RC series circuit 17. That is, the point P12 of the voltage supply path P1 to which the bypass capacitor circuit 18 is connected is closer to the power amplifiers 11 and 12 than the point P11 of the voltage supply path P1 to which the RC series circuit 17 is connected. In other words, the point P11 is closer to the tracker circuit 5 than the point P12.

[0087] In addition, the connection positions of the RC series circuit 17 and the bypass capacitor circuit 18 to the voltage supply path P1 are not limited thereto. For example, the RC series circuit 17 may be connected to the point P12, and the bypass capacitor circuit 18 may be connected to the point P11. In addition, for example, the RC series circuit 17 and the bypass capacitor circuit 18 may be connected to the same point (for example, one of the points P11 and P12).

[0088] in addition, Figure 2The circuit configuration of the bypass capacitor circuit 18 shown is an example and is not limited thereto. For example, the connection order of the capacitor C2 and the switch SW2 may be changed, and the switch SW2 may be connected between the voltage supply path P1 and the capacitor C2.

[0089] The bypass capacitor circuit 19 is an example of a second bypass capacitor circuit, includes a capacitor C3 and a switch SW3 connected in series between the voltage supply path P1 and the ground, and functions as a bypass capacitor capable of switching on and off.

[0090] Capacitor C3 is an example of a third capacitor, connected between the voltage supply path P1 and the ground, and connected in series with switch SW3. In this embodiment, capacitor C3 is connected between voltage supply path P1 and switch SW3. That is, one side of the electrode of capacitor C3 is connected to voltage supply path P1, and the other side of the electrode of capacitor C3 is connected to switch SW3.

[0091] As the electrostatic capacitance of the capacitor C3, for example, 10 nanofarads are used. Thus, when a plurality of discrete voltages are supplied from the tracker circuit within one frame of the high-frequency signal, a balance between voltage stabilization and responsiveness can be achieved. In addition, the electrostatic capacitance of the capacitor C3 is not limited to 10 nanofarads, and can be appropriately changed according to the required specifications of the amplifier circuit 10, etc.

[0092] The switch SW3 is an example of a third switch, connected between the voltage supply path P1 and the ground, and connected in series with the capacitor C3. In the present embodiment, the switch SW3 is connected between the capacitor C3 and the ground. That is, the switch SW3 includes a terminal connected to the capacitor C3 and a terminal connected to the ground. By switching the connection / disconnection between the two terminals, the voltage supply path P1 is switched to be connected / disconnected to the ground via the capacitor C3. Thus, the on / off of the bypass capacitor circuit 18 is switched.

[0093] More specifically, the switch SW3 connects the voltage supply path P1 to the ground via the capacitor C3 when a plurality of discrete voltages are supplied to the power amplifiers 11 and 12 in units of one frame or in units larger than one frame based on the APT mode, and when a plurality of discrete voltages are supplied to the power amplifiers 11 and 12 in one frame based on the digital ET mode. On the other hand, when a continuous voltage is supplied to the power amplifiers 11 and 12 based on the analog ET mode, the switch SW3 does not connect the voltage supply path P1 to the ground via the capacitor C3.

[0094] The bypass capacitor circuit 19 is connected between the voltage supply path P1 between the RC series circuit 17 and the power amplifiers 11 and 12 and the ground. In other words, the bypass capacitor circuit 19 is connected to a point on the voltage supply path P1 that is closer to the power amplifiers 11 and 12 than the RC series circuit 17. That is, the point P12 of the voltage supply path P1 to which the bypass capacitor circuit 19 is connected is closer to the power amplifiers 11 and 12 than the point P11 of the voltage supply path P1 to which the RC series circuit 17 is connected. In other words, the point P11 is closer to the tracker circuit 5 than the point P12.

[0095] In addition, the connection positions of the RC series circuit 17 and the bypass capacitor circuit 19 to the voltage supply path P1 are not limited thereto. For example, the RC series circuit 17 may be connected to the point P12, and the bypass capacitor circuit 19 may be connected to the point P11. In addition, for example, the RC series circuit 17 and the bypass capacitor circuit 19 may be connected to the same point (for example, one of the points P11 and P12).

[0096] in addition, Figure 2 The circuit structure of the bypass capacitor circuit 19 shown is an example and is not limited thereto. For example, the connection order of the capacitor C3 and the switch SW3 may be changed, and the switch SW3 may be connected between the voltage supply path P1 and the capacitor C3. In addition, for example, the switch SW3 may not be included in the bypass capacitor circuit 19.

[0097] The capacitor C4 is an example of a fourth capacitor and functions as a bypass capacitor. The capacitor C4 is connected between the voltage supply path P1 and the ground. That is, the capacitor C4 has two electrodes connected to the voltage supply path P1 and the ground, respectively.

[0098] As the electrostatic capacitance of the capacitor C4, for example, 100 picofarads is used. This can suppress a decrease in responsiveness when a continuous voltage is supplied from the tracker circuit based on the analog ET mode. In addition, the electrostatic capacitance of the capacitor C4 is not limited to 100 picofarads, and can be appropriately changed according to the required specifications of the amplifier circuit 10, etc.

[0099] The capacitance of the capacitors C1 to C4 can be measured using an LCR meter. In this case, an automatic balancing bridge method can be used as a measurement method.

[0100] In the amplifier circuit 10 of the present embodiment, the bypass capacitor circuits 18 and 19, the inductors L1 and L2, the capacitor C4, and the matching circuits 13 to 15 can be appropriately deleted or replaced with other circuit elements according to the required specifications of the amplifier circuit 10, and are not essential components. For example, when the tracker circuit 5 can supply only the power supply voltage based on the digital ET mode, the bypass capacitor circuit 18 and the capacitor C4 may not be included in the amplifier circuit 10, and the switches SW1 and SW3 may not be included in the RC series circuit 17 and the bypass capacitor circuit 19.

[0101] In addition, as necessary, an inductor, a capacitor, or a resistor may be inserted into the amplifier circuit 10. For example, an inductor may be inserted between the emitter terminal of the amplifier transistor T1 and / or T2 and the ground.

[0102] In addition, one of the power amplifiers 11 and 12 may not be included in the amplifier circuit 10. In addition, the amplifier circuit 10 may include at least one power amplifier in addition to the power amplifiers 11 and 12. In this case, the at least one power amplifier may be connected to the power amplifier 11 or 12 continuously or in parallel with the power amplifier 11 or 12.

[0103] [1.3 Enlargement method]

[0104] Next, refer to Figure 3 A method of amplifying a high-frequency signal by the amplifier circuit 10 configured as described above will be described. Figure 3 : is a flowchart showing the enlargement method of this embodiment.

[0105] The amplifier circuit 10 receives a supply of voltage from the tracker circuit 5 ( S101 ).

[0106] In the case where the voltage received in step S101 is a power supply voltage based on the digital ET mode ("Yes" in S103), the RC series circuit 17 is turned on (S105). Specifically, the switch SW1 connects the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1. Thus, when a plurality of discrete voltages are received within one frame of the high-frequency signal, the amplifier circuit 10 can use the RC series circuit 17 to attenuate the ringing of the plurality of discrete voltages. In addition, the bypass capacitor circuit 18 is turned off (S107), and the bypass capacitor circuit 19 is turned on (S109).

[0107] In the case where the voltage received in step S101 is a power supply voltage based on the APT mode ("No" in S103 and "Yes" in S113), the RC series circuit 17 is disconnected (S115). Specifically, the switch SW1 does not connect the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1. Thus, in the case where a plurality of discrete voltages are received in units of one frame of a high-frequency signal or in units larger than one frame, the amplifier circuit 10 can prohibit the use of the RC series circuit 17. In addition, the bypass capacitor circuit 18 is turned on (S117), and the bypass capacitor circuit 19 is turned on (S119).

[0108] When the voltage received in step S101 is based on the power supply voltage of the simulated ET mode (No in S103 and No in S113), the RC series circuit 17 is disconnected (S121). Specifically, the switch SW1 does not connect the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1. Thus, the amplifier circuit 10 can prohibit the use of the RC series circuit 17 when receiving a continuous voltage. In addition, the bypass capacitor circuit 18 is disconnected (S123), and the bypass capacitor circuit 19 is disconnected (S125).

[0109] Finally, the amplifier circuit 10 amplifies the high-frequency signal using the supplied voltage ( S111 ).

[0110] also, Figure 3 The amplification method shown is an example, and the steps and the order of the steps are not limited thereto. For example, when the voltage is not supplied from the tracker circuit 5 based on the APT mode and the analog ET mode but only based on the digital ET mode, steps S103, S107, S109, and S113 to S125 may be omitted as long as the ringing of the plurality of discrete voltages is attenuated using the RC series circuit 17 in step S105.

[0111] [1.4 Components configuration of high frequency module 1M]

[0112] Next, as an example of mounting the high-frequency circuit 1 configured as above, refer to Figure 4 as well as Figure 5 The high-frequency module 1M will be described.

[0113] Figure 4 It is a plan view of a high-frequency module 1M according to the present embodiment. Figure 5 1 is a plan view of the high-frequency module 1M according to the present embodiment, and is a view showing the main surface 90 b side of the module substrate 90 as viewed from the positive z-axis side.

[0114] In addition, Figure 4 as well as Figure 5 In FIG. 9 , wiring for connecting a plurality of circuit components arranged on the module substrate 90 is omitted. Figure 4 as well as Figure 5 In FIG. 1 , the shaded blocks represent any circuit components or electromechanical components that are not essential to the present invention. Figure 4 as well as Figure 5 In order to facilitate understanding of the configuration relationship of each component, text indicating the built-in circuit or element is added to each component, but such text may not be added to the actual components.

[0115] High frequency module 1M is equipped with Figure 2 The module substrate 90 includes an amplifier circuit 10 , a filter 20 , a switch 30 , an antenna connection terminal 100 , a high-frequency input terminal 111 , a power supply voltage terminal 112 , and a control terminal 113 .

[0116] The module substrate 90 has main surfaces 90a and 90b facing each other. A via conductor, wiring, a ground electrode layer, etc. are formed in the module substrate 90 and on the main surface 90a. Figure 4 as well as Figure 5 In the embodiment, the module substrate 90 has a rectangular shape in a plan view, but is not limited to this shape.

[0117] As the module substrate 90, for example, a low temperature co-fired ceramic (LTCC: Low Temperature Co-fired Ceramics) substrate or a high temperature co-fired ceramic (HTCC: High Temperature Co-fired Ceramics) substrate having a stacked structure of multiple dielectric layers, a component-embedded substrate, a substrate having a redistribution layer (RDL: Redistribution Layer), or a printed circuit substrate can be used, but it is not limited to these.

[0118] Power amplifiers 11 and 12 (PA), matching circuits 13 to 15 (MN), an integrated circuit including a PA control circuit 16 (PAC) and switches SW1 to SW3, capacitors C1 to C4, inductors L1 and L2, a resistor R1, a filter 20 (Filter), and a switch 30 (ANTSW) are arranged on the main surface 90a.

[0119] The integrated circuit including the PA control circuit 16 and the switches SW1 to SW3 is formed using, for example, CMOS (Complementary Metal Oxide Semiconductor), and specifically, can be manufactured by SOI (Silicon on Insulator) process. The integrated circuit is not limited to CMOS.

[0120] Capacitors C1 to C4 are mounted as chip capacitors. Chip capacitors refer to surface mount devices (SMD: Surface Mount Device) that constitute capacitors. In addition, the mounting of capacitors C1 to C4 is not limited to chip capacitors. For example, part or all of capacitors C1 to C4 may also be included in an integrated passive device (IPD: Integrated Passive Device) or an integrated circuit.

[0121] Inductors L1 and L2 are mounted as chip inductors, respectively. A chip inductor refers to an SMD that constitutes an inductor. In addition, mounting of inductors L1 and L2 is not limited to chip inductors. For example, inductors L1 and L2 may also be included in an IPD.

[0122] The resistor R1 is mounted as a chip resistor. A chip resistor refers to an SMD that constitutes a resistor. In addition, the mounting of the resistor R1 is not limited to a chip resistor. For example, the resistor R1 may also be included in an IPD.

[0123] On the main surface 90b, in addition to the antenna connection terminal 100, the high-frequency input terminal 111, the power supply voltage terminal 112, and the control terminal 113, a plurality of external connection terminals including a ground terminal are arranged. These plurality of external connection terminals are respectively connected to input / output terminals and / or ground terminals arranged on a mother substrate (not shown) in the negative direction of the z-axis of the high-frequency module 1M. As the plurality of external connection terminals, for example, copper electrodes and solder electrodes can be used.

[0124] also, Figure 4 as well as Figure 5 The structure of the high-frequency module 1M shown is an example and is not limited thereto. For example, part or all of the circuit components arranged on the main surface 90a may be formed in the module substrate 90. In addition, part of the circuit components arranged on the main surface 90a may not be included in the high-frequency module 1M, and may not be arranged on the module substrate 90. For example, the filter 20 and the switch 30 may not be included in the high-frequency module 1M. In this case, the high-frequency module 1M is called an amplifier module. In addition, the high-frequency module 1M may also include a resin member covering the components on the main surface 90a, and may also include a shielding electrode layer covering the resin member.

[0125] [1.5 Effects, etc.]

[0126] As described above, the amplifier circuit 10 of the present embodiment is configured to amplify the high-frequency signal using a plurality of discrete voltages supplied from the tracker circuit 5 within one frame of the high-frequency signal, and the amplifier circuit 10 comprises: a power amplifier 12; and an RC series circuit 17, including a resistor R1 and a capacitor C1 connected in series between a voltage supply path P1 between the tracker circuit 5 and the power amplifier 12 and a ground.

[0127] According to this, when a plurality of discrete voltages are supplied within one frame of a high-frequency signal, high-frequency noise, particularly ringing, included in the plurality of discrete voltages can be attenuated by the RC series circuit 17. Therefore, the quality of the high-frequency signal amplified using the plurality of discrete voltages can be improved. In particular, when a plurality of discrete voltages are switched within one frame, the frequency of ringing is high, and therefore the noise attenuation effect brought about by the RC series circuit 17 is large.

[0128] In addition, for example, the amplifier circuit 10 of the present embodiment may further include a bypass capacitor circuit 18 including a capacitor C2 connected between the voltage supply path P1 and the ground.

[0129] According to this, high-frequency noise included in the plurality of discrete voltages can be further attenuated.

[0130] In addition, the amplifier circuit 10 of this embodiment includes: a power amplifier 12; an RC series circuit 17, including a resistor R1 and a capacitor C1 connected in series between a voltage supply path P1 for the power amplifier 12 and ground; and a bypass capacitor circuit 18, including a capacitor C2 connected between the voltage supply path P1 and ground.

[0131] According to this, the high-frequency noise included in the power supply voltage supplied to the power amplifier 12 via the voltage supply path P1 can be attenuated by the RC series circuit 17 and the bypass capacitor circuit 18. For example, when a plurality of discrete voltages are supplied to the amplifier circuit 10 in the digital ET mode, the ringing can be attenuated by the RC series circuit 17 and the bypass capacitor circuit 18, and the quality of the high-frequency signal amplified by the amplifier circuit 10 can be improved.

[0132] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, the resistor R1 of the RC series circuit 17 may be connected between the capacitor C1 of the RC series circuit 17 and the voltage supply path P1 .

[0133] According to this, the resistor R1 is connected to the voltage supply path P1 without the capacitor C1 , so the resistor R1 can more effectively convert the high-frequency noise into heat and absorb it.

[0134] In addition, for example, in the amplifier circuit 10 of the present embodiment, the RC series circuit 17 may further include a switch SW1 connected in series with the resistor R1 and the capacitor C1 .

[0135] According to this, the voltage supply path P1 can be switched to be connected to the ground through the resistor R1 and the capacitor C1 and disconnected by the switch SW1. Therefore, for example, by turning off the switch SW1 in the analog ET mode, it is possible to suppress the degradation of the responsiveness caused by the RC series circuit 17. In addition, for example, by turning off the switch SW1 in the APT mode, it is possible to suppress the reduction of the power supply voltage caused by the RC series circuit 17.

[0136] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, the switch SW1 may be connected between the resistor R1 and the capacitor C1 and the ground.

[0137] Accordingly, when the switch SW1 is composed of a field effect transistor, the source of the field effect transistor can be connected to the ground. Therefore, when a voltage is applied to the gate of the field effect transistor to turn on the switch SW1, the potential difference between the gate and the source can be increased. As a result, the impedance between the drain and the source can be reduced, and the RC series circuit 17 can function more effectively.

[0138] In addition, for example, in the amplifier circuit 10 of the present embodiment, when a plurality of discrete voltages are supplied to the power amplifier 12 based on the digital ET mode, the switch SW1 connects the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1, and when a plurality of discrete voltages are supplied to the power amplifier 12 based on the APT mode, the switch SW1 does not connect the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1.

[0139] Accordingly, in the digital ET mode, the voltage supply path P1 is connected to the ground via the resistor R1 and the capacitor C1. Therefore, the ringing can be attenuated by the RC series circuit 17, and the quality of the high-frequency signal amplified by the power amplifier 12 can be improved. In addition, in the APT mode, the voltage supply path P1 is not connected to the ground via the resistor R1 and the capacitor C1. Therefore, the voltage drop caused by the RC series circuit 17 can be suppressed, and the efficiency can be improved.

[0140] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, when a continuous voltage is supplied to the power amplifier 12 in the pseudo ET mode, the switch SW1 may not connect the voltage supply path P1 to the ground via the resistor R1 and the capacitor C1 .

[0141] Thus, in the pseudo ET mode, the voltage supply path P1 is not connected to the ground via the resistor R1 and the capacitor C1. Therefore, degradation of responsiveness due to the RC series circuit 17 can be suppressed, and reduction in tracking performance of the power supply voltage with respect to the envelope of the high-frequency signal can be suppressed.

[0142] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, the bypass capacitor circuit 18 may be connected between the voltage supply path P1 between the RC series circuit 17 and the power amplifier 12 and the ground.

[0143] According to this, the wiring length between the bypass capacitor circuit 18 and the power amplifier 12 can be shortened, and the impedance, especially the inductance, of the wiring between the bypass capacitor circuit 18 and the power amplifier 12 can be suppressed. As a result, the degradation of the characteristics of the bypass capacitor caused by the increase in the impedance of the wiring between the bypass capacitor circuit 18 and the power amplifier 12 can be suppressed, and the noise reduction effect can be improved.

[0144] In addition, for example, in the amplifier circuit 10 of the present embodiment, the bypass capacitor circuit 18 may further include a switch SW2 connected between the capacitor C2 and the voltage supply path P1 or the ground.

[0145] Accordingly, the voltage supply path P1 can be switched to be connected to the ground and disconnected via the capacitor C2 by the switch SW2. Therefore, the on / off of the bypass capacitor can be switched according to the type of tracking mode. As a result, the bypass capacitor suitable for the tracking mode can be made to function. For example, in the APT mode, the voltage supply path P1 is connected to the ground via the capacitor C2, so that the noise can be reduced and the voltage can be stabilized by the capacitor C2. In addition, for example, in the digital ET mode and the analog ET mode, the voltage supply path P1 is not connected to the ground via the capacitor C2, so that the reduction in responsiveness caused by the capacitor C2 can be suppressed.

[0146] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, the switch SW2 may be connected between the capacitor C2 and the ground.

[0147] Accordingly, when the switch SW2 is composed of a field effect transistor, the source of the field effect transistor can be connected to the ground. Therefore, when a voltage is applied to the gate of the field effect transistor to turn on the switch SW2, the potential difference between the gate and the source can be increased. As a result, the impedance between the drain and the source can be reduced, and the bypass capacitor circuit 18 can function more effectively.

[0148] In addition, for example, in the amplifier circuit 10 of the present embodiment, when a plurality of discrete voltages are supplied to the power amplifier 12 based on the digital ET mode, the switch SW2 does not connect the voltage supply path P1 to the ground via the capacitor C2, and when a plurality of discrete voltages are supplied to the power amplifier 12 based on the APT mode, the switch SW2 connects the voltage supply path P1 to the ground via the capacitor C2.

[0149] Accordingly, in the APT mode, the voltage supply path P1 is connected to the ground via the capacitor C2. Therefore, the noise can be reduced and the voltage can be stabilized by the capacitor C2, and the degradation of the PAE and the quality of the high-frequency signal in the APT mode can be suppressed. In addition, in the digital ET mode, the voltage supply path P1 is not connected to the ground via the capacitor C2. Therefore, the degradation of the responsiveness caused by the capacitor C2 can be suppressed, and the degradation of the tracking performance in the digital ET mode can be suppressed.

[0150] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, when a continuous voltage is supplied to the power amplifier 12 in the pseudo ET mode, the switch SW2 may not connect the voltage supply path P1 to the ground via the capacitor C2 .

[0151] According to this, in the pseudo ET mode, the voltage supply path P1 is not connected to the ground via the capacitor C2. Therefore, it is possible to suppress a decrease in responsiveness due to the capacitor C2, and to suppress a decrease in tracking performance in the pseudo ET mode.

[0152] In addition, for example, the amplifier circuit 10 of this embodiment may further include a bypass capacitor circuit 19 including a capacitor C3 connected in series between the voltage supply path P1 and the ground, and the electrostatic capacitance of the capacitor C3 may be smaller than the electrostatic capacitance of the capacitor C2.

[0153] According to this, the capacitor C3 having a smaller electrostatic capacitance than the capacitor C2 can be used as a bypass capacitor, and a bypass capacitor suitable for the tracking mode can be used.

[0154] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, the bypass capacitor circuit 19 may be connected between the voltage supply path P1 between the RC series circuit 17 and the power amplifier 12 and the ground.

[0155] According to this, the wiring length between the bypass capacitor circuit 19 and the power amplifier 12 can be shortened, and the impedance, especially the inductance, of the wiring between the bypass capacitor circuit 19 and the power amplifier 12 can be suppressed. As a result, the degradation of the bypass capacitor characteristics caused by the increase in the impedance of the wiring between the bypass capacitor circuit 19 and the power amplifier 12 can be suppressed, and the noise reduction effect can be improved.

[0156] In addition, for example, in the amplifier circuit 10 of the present embodiment, the bypass capacitor circuit 19 may also include a switch SW3 connected between the capacitor C3 and the voltage supply path P1 or the ground, the amplifier circuit 10 may also include a capacitor C4 connected between the voltage supply path P1 and the ground, and the electrostatic capacitance of the capacitor C4 may be smaller than the electrostatic capacitance of each of the capacitors C2 and C3.

[0157] According to this, the capacitors C2 to C4 having different electrostatic capacitances can be used in combination as bypass capacitors, and the electrostatic capacitance of the bypass capacitors suitable for the tracking mode can be realized.

[0158] Furthermore, for example, in the amplifier circuit 10 of the present embodiment, the switch SW3 may be connected between the capacitor C3 and the ground.

[0159] Accordingly, when the switch SW3 is composed of a field effect transistor, the source of the field effect transistor can be connected to the ground. Therefore, when a voltage is applied to the gate of the field effect transistor to turn on the switch SW3, the potential difference between the gate and the source can be increased. As a result, the impedance between the drain and the source can be reduced, and the bypass capacitor circuit 19 can function more effectively.

[0160] In addition, for example, in the amplifier circuit 10 of the present embodiment, when a plurality of discrete voltages are supplied to the power amplifier 12 based on the digital ET mode and the APT mode, the switch SW3 connects the voltage supply path P1 to the ground via the capacitor C3, and when a continuous voltage is supplied to the power amplifier 12 based on the analog ET mode, the switch SW3 does not connect the voltage supply path P1 to the ground via the capacitor C3.

[0161] According to this, in the digital ET mode and the APT mode, the voltage supply path P1 is connected to the ground via the capacitor C3. Therefore, the noise can be reduced and the voltage can be stabilized by the capacitor C3, and the degradation of the PAE and the quality of the high-frequency signal in the digital ET mode and the APT mode can be suppressed. In addition, in the analog ET mode, the voltage supply path P1 is not connected to the ground via the capacitor C3. Therefore, the degradation of the responsiveness caused by the capacitor C3 can be suppressed, and the degradation of the tracking performance in the analog ET mode can be suppressed.

[0162] In addition, the amplification method of the present embodiment is an amplification method for amplifying a high-frequency signal. In this amplification method, a plurality of discrete voltages are supplied within one frame of the high-frequency signal, and the ringing of the plurality of discrete voltages is attenuated using an RC series circuit 17, and the high-frequency signal is amplified using the plurality of discrete voltages after the ringing is attenuated.

[0163] According to this, when a plurality of discrete voltages are supplied within one frame of a high-frequency signal, the ringing included in the plurality of discrete voltages can be attenuated using the RC series circuit 17. Therefore, the quality of the high-frequency signal amplified using the plurality of discrete voltages can be improved. In particular, when a plurality of discrete voltages are switched within one frame, the frequency of the ringing is high, and therefore the noise attenuation effect brought about by the RC series circuit 17 is large.

[0164] In addition, for example, the amplification method involved in this embodiment may also accept the supply of multiple discrete voltages in units of one frame of the high-frequency signal or in units larger than one frame, or may use the RC series circuit 17 to attenuate the ringing of the multiple discrete voltages when the supply of multiple discrete voltages is accepted within one frame of the high-frequency signal, or may not use the RC series circuit 17 to attenuate the ringing of the multiple discrete voltages when the supply of multiple discrete voltages is accepted in units of one frame of the high-frequency signal or in units larger than one frame.

[0165] According to this, when a plurality of discrete voltages are supplied in one frame and the frequency of ringing is high, the ringing can be attenuated by using the RC series circuit 17, and the quality of the high-frequency signal can be improved. On the other hand, when a plurality of discrete voltages are supplied in units of one frame or in units larger than one frame and the frequency of ringing is low, the RC series circuit 17 is not used, and thus the voltage drop caused by the RC series circuit 17 can be suppressed.

[0166] (Other embodiments)

[0167] The amplifier circuit and the amplifier method of the present invention have been described above based on the embodiments, but the amplifier circuit and the amplifier method of the present invention are not limited to the above embodiments. Other embodiments implemented by combining any of the constituent elements in the above embodiments, modified examples obtained by applying various modifications that can be conceived by those skilled in the art to the above embodiments within the scope of the present invention, and various devices in which the above amplifier circuit is built-in are also included in the present invention.

[0168] For example, in the circuit structures of the amplifier circuit, high-frequency circuit, and communication device of the above-mentioned embodiments, other circuit elements and wirings may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, a filter and / or matching circuit may be inserted between the switch 30 and the antenna connection terminal 100.

[0169] In addition, in the above-mentioned embodiment, the tracker circuit 5 can cope with the analog ET mode, the digital ET mode and the APT mode, but is not limited to this. For example, the tracker circuit 5 may only cope with the digital ET mode. In this case, the tracker circuit 5 may not include the analog ET7 and the mode switching switch 8. In addition, the amplifier circuit 10 may not include the bypass capacitor circuit 18, and the RC series circuit 17 and the bypass capacitor circuit 19 may not include the switches SW1 and SW3. In addition, for example, the tracker circuit 5 may only cope with the digital ET mode and the APT mode. In this case, the tracker circuit 5 may not include the analog ET7 and the mode switching switch 8. In addition, the bypass capacitor circuit 19 may not include the switch SW3.

[0170] In addition, the modes that the tracker circuit 5 can handle are not limited to the analog ET mode, the digital ET mode, and the APT mode. For example, the tracker circuit 5 can also handle the SPT mode. In the SPT mode, the amplifier circuit 10 can handle the same as the digital ET mode. That is, in the SPT mode, the amplifier circuit 10 can turn on the switch SW1, turn off the switch SW2, and turn on the switch SW3, thereby improving the amplification characteristics of the high-frequency signal.

[0171] In the above embodiment, the on / off state of the bypass capacitor circuits 18 and 19 is switched according to the type of tracking mode, but the present invention is not limited thereto. For example, the on / off state of the bypass capacitor circuits 18 and 19 may be switched according to the channel bandwidth of the high frequency signal.

[0172] Features of the tracker circuit, tracker module, and voltage supply method described in the above embodiments are described below.

[0173] <1> An amplifier circuit configured to amplify a high-frequency signal using a plurality of discrete voltages supplied from a tracker circuit within one frame of the high-frequency signal, wherein:

[0174] The above-mentioned amplifier circuit has:

[0175] power amplifier; and

[0176] The RC series circuit includes a resistor and a first capacitor connected in series between a voltage supply path between the tracker circuit and the power amplifier and ground.

[0177] <2> An amplifier circuit according to <1>, wherein:

[0178] The amplifier circuit further includes a first bypass capacitor circuit including a second capacitor connected between the voltage supply path and ground.

[0179] <3> An amplifier circuit, comprising:

[0180] Power amplifier;

[0181] an RC series circuit including a resistor and a first capacitor connected in series between a voltage supply path for the power amplifier and ground; and

[0182] The first bypass capacitor circuit includes a second capacitor connected between the voltage supply path and ground.

[0183] <4> The amplifier circuit according to any one of <1> to <3>, wherein:

[0184] In the RC series circuit, the resistor is connected between the first capacitor and the voltage supply path.

[0185] <5> The amplifier circuit according to any one of <1> to <4>, wherein:

[0186] The RC series circuit further includes a first switch, and the first switch is connected in series with the resistor and the first capacitor.

[0187] <6> An amplifier circuit according to <5>, wherein:

[0188] The first switch is connected between the resistor and the first capacitor and ground.

[0189] <7> The amplifier circuit according to <5> or <6>, wherein:

[0190] In a condition where the plurality of discrete voltages are supplied to the power amplifier based on the digital ET mode, the first switch connects the voltage supply path to the ground via the resistor and the first capacitor.

[0191] In a state where the plurality of discrete voltages are supplied to the power amplifier based on an APT mode, the first switch does not connect the voltage supply path to the ground via the resistor and the first capacitor.

[0192] <8> An amplifier circuit according to <7>, wherein:

[0193] In a state where a continuous voltage is supplied to the power amplifier based on a pseudo ET mode, the first switch does not connect the voltage supply path to the ground via the resistor and the first capacitor.

[0194] <9> The amplifier circuit according to <2> or <3>, wherein:

[0195] The first bypass capacitor circuit is connected between a path between the RC series circuit and the power amplifier and ground.

[0196] <10> The amplifier circuit according to any one of <2>, <3> and <9>, wherein:

[0197] The first bypass capacitor circuit further includes a second switch connected between the second capacitor and the voltage supply path or ground.

[0198] <11> The amplifier circuit according to <10>, wherein:

[0199] The second switch is connected between the second capacitor and ground.

[0200] <12> The amplifier circuit according to <10> or <11>, wherein:

[0201] In a condition where the plurality of discrete voltages are supplied to the power amplifier based on the digital ET mode, the second switch does not connect the voltage supply path to the ground via the second capacitor.

[0202] In a state where the plurality of discrete voltages are supplied to the power amplifier based on an APT mode, the second switch connects the voltage supply path to the ground via the second capacitor.

[0203] <13> The amplifier circuit according to <12>, wherein:

[0204] In a condition where a continuous voltage is supplied to the power amplifier based on a pseudo ET mode, the second switch does not connect the voltage supply path to the ground via the second capacitor.

[0205] <14> The amplifier circuit according to any one of <10> to <13>, wherein:

[0206] The amplifier circuit further includes a second bypass capacitor circuit, the second bypass capacitor circuit including a third capacitor connected in series between the voltage supply path and ground.

[0207] The electrostatic capacitance of the third capacitor is smaller than the electrostatic capacitance of the second capacitor.

[0208] <15> The amplifier circuit according to <14>, wherein:

[0209] The second bypass capacitor circuit is connected between a path between the RC series circuit and the power amplifier and ground.

[0210] <16> The amplifier circuit according to <14> or <15>, wherein:

[0211] The second bypass capacitor circuit further includes a third switch connected between the third capacitor and the voltage supply path or ground.

[0212] The amplifier circuit further includes a fourth capacitor connected between the voltage supply path and ground.

[0213] The electrostatic capacitance of the fourth capacitor is smaller than the electrostatic capacitance of the second capacitor and the electrostatic capacitance of the third capacitor.

[0214] <17> An amplifier circuit according to <16>, wherein:

[0215] The third switch is connected between the third capacitor and ground.

[0216] <18> The amplifier circuit according to <16> or <17>, wherein:

[0217] In a condition where the plurality of discrete voltages are supplied to the power amplifier based on the digital ET mode and the APT mode, the third switch connects the voltage supply path to the ground via the third capacitor.

[0218] In a condition where a continuous voltage is supplied to the power amplifier based on the pseudo ET mode, the third switch does not connect the voltage supply path to the ground via the third capacitor.

[0219] <19> An amplification method is a method for amplifying a high-frequency signal, wherein in the amplification method,

[0220] In one frame of the high frequency signal, multiple discrete voltages are supplied.

[0221] Use RC series circuit to attenuate the ringing of the above multiple discrete voltages.

[0222] The high frequency signal is amplified using the plurality of discrete voltages after the ringing is attenuated.

[0223] <20> The amplification method according to <19>, wherein:

[0224] The amplification method further receives a plurality of discrete voltages in units of one frame of the high frequency signal or in units larger than one frame.

[0225] In a state where a plurality of discrete voltages are supplied within one frame of the high frequency signal, the RC series circuit is used to attenuate the ringing of the plurality of discrete voltages.

[0226] In a situation where a plurality of discrete voltages are supplied in units of one frame of the high frequency signal or in units larger than one frame, the ringing of the plurality of discrete voltages is attenuated without using the RC series circuit.

[0227] Industrial Applicability

[0228] The present invention can be widely used in communication devices such as mobile phones as an amplifier circuit disposed in a front end portion.

[0229] Explanation of the reference numerals: 1...high frequency circuit; 1M...high frequency module; 2...antenna; 3...RFIC; 4...BBIC; 5...tracker circuit; 6...digital ET / APT; 7...analog ET; 8...mode switching switch; 9...communication device; 10...amplifier circuit; 11, 12...power amplifier; 13, 14, 15...matching circuit; 16...PA control circuit; 17...RC series circuit; 18, 19...bypass capacitor circuit; 20...filter; 30, SW1, SW2, SW3...switch; 90...module substrate; 90a, 90b...main surface; 100...antenna connection terminal; 111...high frequency input terminal; 112...power supply voltage terminal; 113...control terminal; C1, C2, C3, C4...capacitor; L1, L2...inductor; P1...voltage supply path; P11, P12...point; R1...resistor; T1, T2...amplifier transistor.

Claims

1. An amplifier circuit configured to amplify a high-frequency signal using a plurality of discrete voltages supplied from a tracker circuit within one frame of the high-frequency signal, wherein: The amplifier circuit has: Power amplifier; as well as The RC series circuit includes a resistor and a first capacitor connected in series between a voltage supply path between the tracker circuit and the power amplifier and ground.

2. The amplifier circuit according to claim 1, wherein: The amplifier circuit further includes a first bypass capacitor circuit including a second capacitor connected between the voltage supply path and ground.

3. An amplifier circuit, wherein: have: Power amplifier; an RC series circuit including a resistor and a first capacitor connected in series between a voltage supply path for the power amplifier and ground; and The first bypass capacitor circuit includes a second capacitor connected between the voltage supply path and ground.

4. The amplifier circuit according to any one of claims 1 to 3, wherein: In the RC series circuit, the resistor is connected between the first capacitor and the voltage supply path.

5. The amplifier circuit according to any one of claims 1 to 4, wherein: The RC series circuit further includes a first switch connected in series with the resistor and the first capacitor.

6. The amplifier circuit according to claim 5, wherein: The first switch is connected between the resistor and the first capacitor and ground.

7. The amplifier circuit according to claim 5 or 6, wherein: In a condition where the plurality of discrete voltages are supplied to the power amplifier based on a digital ET mode, the first switch connects the voltage supply path to ground via the resistor and the first capacitor. In a condition where the plurality of discrete voltages are supplied to the power amplifier based on an APT mode, the first switch does not connect the voltage supply path to the ground via the resistor and the first capacitor.

8. The amplifier circuit according to claim 7, wherein: In a condition where a continuous voltage is supplied to the power amplifier based on an analog ET mode, the first switch does not connect the voltage supply path to the ground via the resistor and the first capacitor.

9. The amplifier circuit according to claim 2 or 3, wherein: The first bypass capacitor circuit is connected between a path between the RC series circuit and the power amplifier and ground.

10. The amplifier circuit according to any one of claims 2, 3 and 9, wherein: The first bypass capacitor circuit also includes a second switch connected between the second capacitor and the voltage supply path or ground.

11. The amplifier circuit according to claim 10, wherein: The second switch is connected between the second capacitor and ground.

12. The amplifier circuit according to claim 10 or 11, wherein: In a condition where the plurality of discrete voltages are supplied to the power amplifier based on a digital ET mode, the second switch does not connect the voltage supply path to ground via the second capacitor, In a condition where the plurality of discrete voltages are supplied to the power amplifier based on an APT mode, the second switch connects the voltage supply path to ground via the second capacitor.

13. The amplifier circuit according to claim 12, wherein: In a condition where a continuous voltage is supplied to the power amplifier based on an analog ET mode, the second switch does not connect the voltage supply path to the ground via the second capacitor.

14. The amplifier circuit according to any one of claims 10 to 13, wherein: The amplifier circuit further includes a second bypass capacitor circuit including a third capacitor connected in series between the voltage supply path and ground. The electrostatic capacitance of the third capacitor is smaller than the electrostatic capacitance of the second capacitor.

15. The amplifier circuit according to claim 14, wherein: The second bypass capacitor circuit is connected between a path between the RC series circuit and the power amplifier and ground.

16. The amplifier circuit according to claim 14 or 15, wherein: The second bypass capacitor circuit further includes a third switch connected between the third capacitor and the voltage supply path or ground. The amplifier circuit further includes a fourth capacitor connected between the voltage supply path and ground. The electrostatic capacitance of the fourth capacitor is smaller than the electrostatic capacitance of the second capacitor and the electrostatic capacitance of the third capacitor.

17. The amplifier circuit according to claim 16, wherein: The third switch is connected between the third capacitor and ground.

18. The amplifier circuit according to claim 16 or 17, wherein: In a condition where the plurality of discrete voltages are supplied to the power amplifier based on the digital ET mode and the APT mode, the third switch connects the voltage supply path to the ground via the third capacitor. In a condition where a continuous voltage is supplied to the power amplifier based on an analog ET mode, the third switch does not connect the voltage supply path to the ground via the third capacitor.

19. An amplification method is a method for amplifying a high-frequency signal, wherein: In the amplification method, receiving a plurality of discrete voltages within one frame of the high frequency signal, Using an RC series circuit to attenuate the ringing of the plurality of discrete voltages, The high frequency signal is amplified using the plurality of discrete voltages after the ringing is attenuated.

20. The amplification method according to claim 19, wherein: In the amplification method, a plurality of discrete voltages are supplied in units of one frame of the high frequency signal or in units larger than one frame. When a plurality of discrete voltages are supplied within one frame of the high frequency signal, the RC series circuit is used to attenuate the ringing of the plurality of discrete voltages. In a situation where a plurality of discrete voltages are supplied in units of one frame of the high-frequency signal or in units larger than one frame, the ringing of the plurality of discrete voltages is attenuated without using the RC series circuit.

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