Video data encoder and encoding method

Abstract

Examples disclosed herein include a video data encoder. The video data encoder may encode 4 * 4 data blocks into a bitstream according to context adaptive variable length coding. The 4 * 4 data block may represent video data. The video data encoder may ignore at least some of the coefficients of the 4 * 4 data block when encoding the 4 * 4 data block. In some examples, the video data encoder may ignore the at least some coefficients of the 4 * 4 data block by setting the at least some coefficients of the 4 * 4 data block to zero prior to encoding the 4 * 4 data block. Related devices, systems, and methods are also disclosed.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the priority date of Indian Provisional Patent Application No. 202241030058 filed on May 25, 2022 and entitled “IMPROVEMENTS TO CONTEXT ADAPTIVE VARIABLE LENGTH CODING”, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various examples generally relate to encoding video, image and / or audio data in a digital format. More specifically, some examples relate to improvements related to context-adaptive variable length coding (CAVLC). CAVLC can be used in accordance with Recommendation H.264: Advanced Video Coding for General Audiovisual Services (H.264), which is also known in the art as Moving Picture Experts Group (MPEG)-4 Advanced Video Coding (AVC). H.264 is a video coding format for recording and / or distributing video, images and / or audio. Unless otherwise specified herein, references to "H.264" should be understood to include MPEG--4 AVC. In addition, devices, systems and methods are disclosed. Background Art

[0004] CAVLC may be used for video coding, such as video coding according to recommendation H.264, but not limited thereto. CAVLC may encode blocks of coefficients into a bitstream. CAVLC may exploit several characteristics of blocks of quantized coefficients. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] While the present disclosure concludes with claims that particularly point out and distinctly claim specific examples, the various features and advantages of examples within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0006] Figure 1 is a functional block diagram illustrating an apparatus according to one or more examples.

[0007] Figure 2 is a functional block diagram illustrating an apparatus according to one or more examples.

[0008] Figure 3 is a functional block diagram illustrating an apparatus according to one or more examples.

[0009] Figure 4 is a flowchart of a method according to one or more examples.

[0010] Figure 5A and Figure 5B Collectively, are flow diagrams of methods according to one or more examples.

[0011] Fig. 6A and Figure 6B Collectively, is a flow chart of a method 600 according to one or more examples.

[0012] Figure 7 is a block diagram of a device that, in one or more examples, can be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0013] H.264 describes a video compression algorithm for compressing video data (e.g., video data formatted in a red-green-blue (RGB) format or in a luminance or brightness, blue projection, and red projection (YUV) format (but not limited thereto)) into a compressed format. H.264 may operate on blocks of data, e.g., one block of data at a time. H.264 includes operations for prediction, transform, and quantization. After the operations for prediction, transform, and quantization, the blocks of data are typically sparse, e.g., most of the blocks of data may contain mostly zeros.

[0014] CAVLC is an entropy coding scheme used in H.264 video compression after prediction, transform and quantization. CAVLC encodes 4x4 data blocks into a bitstream by exploiting the characteristics of the quantized 4x4 data blocks, including, for example, but not limited to, the sparse nature of the 4x4 data blocks.

[0015] The contents of a 4×4 data block (e.g., the values ​​of a 4×4 data block) are often referred to as “coefficients”. After prediction, transformation, and quantization, the coefficients may include non-zero coefficients, +1, -1, and zero. After prediction, transformation, and quantization, the 4×4 data block may be scanned according to a zigzag scanning pattern, for example, ordering the coefficients from the first coefficient to the last coefficient. The ordering of the coefficients may correspond to an ordering from low frequencies to high frequencies according to the transform coefficients. As non-limiting examples, the transform may be an integer transform or a cosine transform. The +1 and -1 corresponding to high frequencies (e.g., the subsequent coefficient) according to the transform may be referred to as “trailing 1s”, “T1s”, or “trailing ones”.

[0016] CAVLC encoding of a 4×4 data block consists of the following five stages:

[0017] Stage 1 - Encode the total non-zero coefficients. The non-zero coefficients are encoded using a standard lookup table with the count of non-zero coefficients in the 4×4 data block and the count of trailing ones. The choice of lookup table is determined by the count of non-zero coefficients in neighboring blocks. Stage 1 of CAVLC usually takes

[0018] 1 clock cycle.

[0019] Phase 2 - Encode the trailing one's sign. Bits are allocated based on each trailing one's sign, where 0 corresponds to +1 and 1 corresponds to -1. Phase 2 of CAVLC typically takes 1 clock cycle.

[0020] Stage 3 - Encode the levels of the remaining non-zero coefficients. In this stage, each non-zero coefficient takes one clock cycle. Stage 3 of CAVLC may take up to 16 clock cycles. As a non-limiting example, in the case of a 4×4 data block including 16 non-zero coefficients, this stage of CAVLC typically takes 16 clock cycles.

[0021] Stage 4 - Encodes the total number of zeros before the last non-zero coefficient. Stage 4 of CAVLC typically takes 1 clock cycle.

[0022] Stage 5 - Encode each run of zeros. In stage 5 of CAVLC, typically each zero before the last non-zero coefficient takes one clock cycle. This stage may take up to 15 clock cycles. As a non-limiting example, in the case where a 4x4 block includes a non-zero coefficient in the last position (according to a zigzag scan pattern) and includes 15 zeros before the last coefficient, this stage will take 15 clock cycles.

[0023] The running times of stage 3 and stage 5 can be complementary. For example, stage 3 takes one clock cycle for each non-zero coefficient, and stage 5 takes one clock cycle for each zero before the last non-zero coefficient. Thus, more non-zero coefficients means that stage 3 will be longer and stage 5 will be shorter, and more zero coefficients (before the last non-zero coefficient) will result in stage 5 being longer and stage 3 being shorter.

[0024] Some implementations of CAVLC involve running stage 3 and stage 5 in parallel, so that the encoded output of stage 5 is available at the end of stage 4. Such implementations of CAVLC may take up to 19 clock cycles to process a 4x4 block of data.

[0025] As an example of the processing time for all five stages, where a 4×4 data block includes 6 non-zero coefficients including 2 trailing ones, with the last non-zero coefficient located at the tenth position, CAVLC may take one clock cycle for stage 1, one clock cycle for stage 2, four clock cycles for stage 3 (each of the non-zero coefficients except the trailing one takes one clock cycle), one clock cycle for stage 4, and four clock cycles for stage 5 (each zero before the last non-zero coefficient located at the tenth position takes one clock cycle) (stage 5 may run in parallel with stage 3 without adding clock cycles because stages 3 and 5 may run in parallel), for a total of seven clock cycles.

[0026] As an example of processing time for all five stages, where a 4×4 data block includes 16 non-zero coefficients (none of which are trailing ones) (where stage 3 will take the longest time), CAVLC may take one clock cycle for stage 1, one clock cycle for stage 2, 16 clock cycles for stage 3, one clock cycle for stage 4, and zero clock cycles for stage 5 (stage 5 may be skipped since there are no zero coefficients), for a total of 19 clock cycles.

[0027] As another example of processing time for all five stages, where a 4×4 data block includes 15 zeros and a single non-zero coefficient is located in the last position (the non-zero coefficient is not a trailing one, i.e., the case where stage 5 will take the longest time), CAVLC may take one clock cycle for stage 1, one clock cycle for stage 2, one clock cycle for stage 3 (stage 3 can run in parallel with stage 5 without adding clock cycles because stages 3 and 5 can run in parallel), one clock cycle for stage 4, and 15 clock cycles for stage 5, for a total of 18 clock cycles.

[0028] CAVLC may receive one coefficient per clock cycle, for example, one coefficient may be stored in a buffer per clock cycle, but is not limited thereto. As a non-limiting example, if CAVLC takes 19 clock cycles to encode a 4×4 data block of 16 coefficients into a bitstream, CAVLC takes longer to process the block than the time it takes to receive the 4×4 data block. This may cause delays in the video encoding process. As a non-limiting example, the input may need to wait 3 clock cycles per 16 clock cycles for CAVLC to complete all 5 encoding stages. This wait introduces an overhead wait time of 18.75% for each block and therefore for the entire video frame.

[0029] This will affect the bandwidth and frame rate of the entire H.264 encoder. An alternative solution to avoid latency is to run CAVLC at a higher clock frequency (e.g., 1.1875 times the clock frequency of the quantization module). However, this will increase the power consumption of CAVLC and will involve clock domain crossing (CDC), which may require a CDC first-in first-out circuit (FIFO).

[0030] Some examples set the coefficients of the 4×4 data block to zero to reduce the number of clock cycles required for CAVLC in the longest case. Some examples may set at least some of the coefficients of the 4×4 data block to zero before, at the beginning, or during the operation of CAVLC. Some examples may set two coefficients to zero. Some examples may set the last two coefficients to zero (according to a zigzag scan pattern). Alternatively, some examples may ignore one or more coefficients during one or more operations of CAVLC.

[0031] In H.264, after prediction, transform, and quantization, 4×4 data blocks are generally sparse. Specifically, most coefficients of most 4×4 data blocks are zero. In addition, based on a transform (e.g., an integer transform, but not limited thereto), most 4×4 data blocks have zeros as the last two coefficients (e.g., high-frequency coefficients). Therefore, setting the last two coefficients of most 4×4 data blocks to zero may not affect the values ​​of the coefficients of most 4×4 data blocks. In addition, because the last two coefficients represent high-frequency data (e.g., according to an integer transform), setting the last two coefficients to zero may not result in a visually perceptible impact on video quality.

[0032] Setting two coefficients of a 4×4 data block to zero will cause stage 3 of CAVLC to take up to 14 clock cycles. For example, a 4×4 data block that will take the longest processing time of stage 3 of CAVLC will be a 4×4 data block that includes 16 non-zero coefficients, none of which are trailing ones. Using typical CAVLC, 16 non-zero coefficients will take 16 clock cycles to encode in CAVLC stage 3. According to various examples, by setting the last two coefficients to zero, stage 3 will take up to 14 clock cycles, because there will be a maximum of 14 non-zero coefficients to encode in stage 3.

[0033] In some non-limiting examples, where a 4×4 data block includes 16 non-zero coefficients, none of which are trailing ones, various examples may compute stage 1 and stage 2 in the same clock cycle. Various examples may compute stage 3 in 14 clock cycles because there are 14 non-zero coefficients in the 4×4 data block after two coefficients of the 4×4 data block are set to zero. Stage 4 may be computed in one clock cycle. Stage 5 may be omitted because there are no runs of zeros to be encoded at stage 5 in the case of 14 non-zero coefficients (e.g., after the last two coefficients are set to zero according to various examples), alternatively, stage 5 may be processed in parallel with stage 3 and may not add any clock cycles to the total run time of CAVLC. Therefore, even in the case where a 4×4 data block includes 16 non-zero coefficients (none of which are trailing ones), various examples may take 16 clock cycles to process the 4×4 data block according to CAVLC.

[0034] In the case of a 4×4 data block including 15 zeros and a last non-zero coefficient (which may be the 4×4 data block that takes the longest processing time for stage 5), various examples may set the last coefficient to zero. In the case of 16 zeros, stages 1 and 2 may take one clock cycle, stage 3 may take no clock cycles (because there are no non-zero coefficients to be encoded), alternatively, stage 3 may be processed in parallel with stage 5 and may not add any clock cycles to the total runtime of the CAVLC, stage 4 may take one clock cycle, and stage 5 may take no clock cycles (because there are no zeros before the last non-zero coefficient).

[0035] In the case of a 4×4 data block including 13 zeros and a non-zero coefficient in the 14th position (which may be the 4×4 data block for which stage 5 takes the longest processing time after setting the last two coefficients to zero), various examples may set the last two coefficients to zero. In the case of 13 zeros, stages 1 and 2 may take one clock cycle, stage 3 may take one clock cycle (for the non-zero coefficient in the 14th position), stage 4 may take one clock cycle, and stage 5 may take 13 clock cycles (for the 13 zeros before the 14th non-zero coefficient). Because stages 3 and 5 may be processed in parallel, stages 1 to 5 of CAVLC may be completed in 15 clock cycles.

[0036] Therefore, setting the last two coefficients of a 4x4 data block to zero may enable CAVLC to process the entire 4x4 data block in 16 clock cycles or less.

[0037] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of example specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0038] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0039] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary", "by way of example", and "for example" means that the relevant description is illustrative, and while the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the examples of the present disclosure to the specified components, steps, features, functions, etc.

[0040] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0041] In addition, the specific implementations shown and described are only examples and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Components, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only examples and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the partitioning of logic between the block definitions and the individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0042] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout this specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. For clarity of presentation and description, some of the accompanying drawings may illustrate signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal. Those of ordinary skill in the art will appreciate that the present disclosure encompasses the transmission of quantum information and qubits used to represent quantum information.

[0043] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer executes computing instructions (e.g., software code, but not limited thereto) associated with the examples disclosed herein.

[0044] Examples can be described according to a process depicted as a flow chart, a flow diagram, a structure diagram, or a block diagram. Although a flow chart can describe an operable action as a continuous process, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the actions can be rearranged. A process can correspond to a method, a thread, a function, a procedure, a subroutine, or a subprogram, but is not limited thereto. In addition, the methods disclosed herein can be implemented by hardware, software, or both. If implemented in software, a function can be stored or transmitted to a computer-readable medium as one or more instructions or codes. Computer-readable media includes both computer storage media and communication media, and the communication media includes any medium that is conducive to transferring a computer program from one location to another.

[0045] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to or with another element, the elements may be in direct physical or electrical contact, or there may be one or more intervening elements or layers. In contrast, when an element is described as being "directly coupled" to or with another element, there are no intervening elements or layers. It should be understood that when an element is referred to as being "coupled" to a first element and a second element, the element is coupled to the first element and the element is coupled to the second element.

[0046] Figure 1 is a functional block diagram illustrating apparatus 100 according to one or more examples. Apparatus 100 may compress video data 104 into compressed video data 106 in 16 clock cycles or less.

[0047] The apparatus 100 may include a video data encoder 102. The video data encoder 102 may encode video data 104 to generate compressed video data 106. Encoding the video data 104 to generate the compressed video data 106 may include encoding a 4×4 data block 110 into a bitstream 118 according to CAVLC 120. The 4×4 data block 110 may represent the video data 104. Encoding the video data 104 to generate the compressed video data 106 may include ignoring at least some coefficients 112 of the 4×4 data block 110 when encoding the 4×4 data block 110. In some non-limiting examples, ignoring at least some coefficients 112 of the 4×4 data block 110 may include setting at least some of the coefficients 112 of the 4×4 data block 110 to zero before encoding the 4×4 data block 110.

[0048] The video data encoder 102 may be or may include logic that performs operations to compress the video data 104 into compressed video data 106. The video data encoder 102 may be or may include a video codec.

[0049] Video data 104 may be or may include video data, image data, and / or audio data according to any suitable format, including, for example, but not limited to, video data consisting of an image including RGB data or YUV data.

[0050] Compressed video data 106 may represent video data 104. Compressed video data 106 may be capable of being expanded to recover data that is substantially the same as video data 104. Some of the recovered data may not include high frequency aspects present in video data 104. However, the recovered data may be substantially the same as video data 104.

[0051] The 4×4 data block 110 may be or may include 16 coefficients 112. The coefficients 112 of the 4×4 data block 110 may have corresponding positions in the 4×4 matrix. Additionally or alternatively, the coefficients 112 of the 4×4 data block 110 may have a zigzag scanning pattern ( Figure 1 The order is not shown in the example.

[0052] The 4×4 data block 110 may represent the video data 104. As a non-limiting example, the 4×4 data block 110 may represent pixels of an image of the video data 104. As a non-limiting example, a block of 16 pixels of the image of the video data 104 may be identified or selected. Prediction may be performed with respect to the pixels. The values ​​associated with the identified 16 pixels may be transformed, for example, using an integer transform, but is not limited thereto. The transformed values ​​may be quantized. The 4×4 data block 110 may be a quantized value.

[0053] The video data encoder 102 may encode the 4x4 data block 110 into a bitstream 118 according to CAVLC 120. As a non-limiting example, the video data encoder 102 may encode the 4x4 data block 110 into a bitstream 118 according to the 5-phase CAVLC described above.

[0054] However, according to some non-limiting examples, the video data encoder 102 may ignore at least some of the coefficients 112 of the 4×4 data block 110 when encoding the 4×4 data block 110 into the bitstream 118. For example, when performing the operation of the CAVLC 120, the video data encoder 102 may ignore at least two coefficients of the coefficients 112 of the 4×4 data block 110. In one or more examples, the video data encoder 102 may ignore the last two coefficients of the coefficients 112 of the 4×4 data block 110 according to a zigzag scan pattern.

[0055] Additionally or alternatively, according to some non-limiting examples, the video data encoder 102 may set at least some of the coefficients 112 of the 4×4 data block 110 to zero before or at the beginning of encoding the 4×4 data block 110 into the bitstream 118. For example, the video data encoder 102 may set at least two of the coefficients 112 of the 4×4 data block 110 to zero before performing the operation of the CAVLC 120. The video data encoder 102 may set the last two coefficients of the coefficients 112 of the 4×4 data block 110 (i.e., the last two coefficients traversed according to the zigzag scan pattern) to zero (i.e., set the value to zero) according to the zigzag scan pattern. Setting at least some of the coefficients 112 to zero may be an example of ignoring at least some of the coefficients 112.

[0056] Figure 2 2 is a functional block diagram illustrating an apparatus 200 according to one or more examples. The apparatus 200 may compress the video data 204 into compressed video data 206 in 16 clock cycles 222 or less.

[0057] The device 200 may be Figure 1 Specifically, the video data encoder 202 may be Figure 1 For example, the video data encoder 102 may be Figure 1 For example, the compressed video data 206 may be Figure 1 For example, the 4×4 data block 210 of the compressed video data 106 may be Figure 1 For example of a 4×4 data block 110, the coefficients 212 may be Figure 1 For example, the coefficients 112, the bit stream 218 may be Figure 1 An example of a bitstream 118 and a CAVLC 220 may be Figure 1An example of CAVLC 120.

[0058] in addition, Figure 2 A zigzag scan pattern 214 is illustrated. The zigzag scan pattern 214 may define a path that traverses the 4×4 data block 210 to sort the coefficients 212 of the 4×4 data block 210. The zigzag scan pattern 214 may sort the coefficients 212 from the lowest frequency coefficient to the highest lowest frequency coefficient according to a transformation of values ​​of a pixel block forming the 4×4 data block 210. Specifically, the upper left coefficient of the 4×4 data block 210 may be the lowest frequency coefficient of the coefficients 212, and the lower right coefficient of the 4×4 data block 210 may be the highest frequency coefficient of the coefficients 212.

[0059] When encoding the 4×4 data block 210 into the bitstream 218 according to CAVLC 220, the video data encoder 202 may ignore at least some of the coefficients 212 of the 4×4 data block 210. When performing the operation of CAVLC 220, the video data encoder 202 may ignore at least two coefficients of the coefficients 212 of the 4×4 data block 210. The video data encoder 202 may ignore the last two coefficients 216 of the 4×4 data block 210 according to the zigzag scan pattern 214.

[0060] Additionally or alternatively, the video data encoder 202 may set at least some of the coefficients 212 of the 4×4 data block 210 to zero before or at the beginning of encoding the 4×4 data block 210 into the bitstream 218 according to CAVLC 220. The video data encoder 202 may set at least two of the coefficients 212 of the 4×4 data block 210 to zero. The video data encoder 202 may set the last two coefficients 216 of the 4×4 data block 210 to zero according to the zigzag scan pattern 214. Setting at least some of the coefficients 212 to zero may be an example of ignoring at least some of the coefficients 212.

[0061] Figure 3 is a functional block diagram illustrating an apparatus 300 according to one or more examples. The apparatus 300 may compress video data into compressed video data in 16 clock cycles or less.

[0062] The device 300 may be Figure 1 Specifically, the video data encoder 302 may be Figure 1 For example, the video data encoder 102 may be Figure 1 For example of video data 104, a 4×4 data block 310 may be Figure 1 For example of a 4×4 data block 110, coefficients 312 may be Figure 1 For example, the coefficients 112, the bit stream 318 may be Figure 1An example of a bitstream 118 and a CAVLC 320 may be Figure 1 An example of CAVLC 120.

[0063] The apparatus 300 may include a video data encoder 302. The video data encoder 302 may encode a 4×4 data block 310 into a bitstream 318 according to CAVLC 320. The 4×4 data block 310 may represent the video data 304 (e.g., the 4×4 data block 310 may include data of the video data 304 that has been selected, predicted, transformed, and / or quantized). When encoding the 4×4 data block 310, the video data encoder 302 may ignore at least some coefficients 312 of the 4×4 data block 310. In some non-limiting examples, ignoring at least some coefficients 312 of the 4×4 data block 310 may include setting at least some of the coefficients 312 of the 4×4 data block 310 to zero before encoding the 4×4 data block 310.

[0064] When encoding the 4×4 data block 310 into the bitstream 318 according to CAVLC 320, the video data encoder 302 may ignore at least some of the coefficients 312 of the 4×4 data block 310. When performing the operation of CAVLC 320, the video data encoder 302 may ignore at least two coefficients of the coefficients 312 of the 4×4 data block 310. The video data encoder 302 may ignore the last two coefficients of the 4×4 data block 310 according to the zigzag scan mode.

[0065] Additionally or alternatively, the video data encoder 302 may set at least some of the coefficients 312 of the 4×4 data block 310 to zero before or at the beginning of encoding the 4×4 data block 310 into the bitstream 318 according to CAVLC 320. The video data encoder 302 may set at least two of the coefficients 312 of the 4×4 data block 310 to zero. The video data encoder 302 may set the last two coefficients of the 4×4 data block 310 to zero according to the zigzag scan pattern. Setting at least some of the coefficients 312 of the 4×4 data block 310 to zero may be an example of ignoring at least some of the coefficients 312 of the 4×4 data block 310.

[0066] Figure 4 4 is a flow chart of a method 400 according to one or more examples. In some non-limiting examples, at least a portion of the method 400 may be performed by a device or system such as Figure 1 The device 100, Figure 1 The device video data encoder 102, Figure 2 The device 200, Figure 2 The video data encoder 202, Figure 3 The device 300, Figure 3Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0067] In operation 402, video data may be encoded to generate compressed video data. As a non-limiting example, Figure 1 The video data 104 is compressed into Figure 1 The compressed video data 106. One or more of the operations 404 and 406 may be performed when the operation 402 is performed. In other words, one or more of the operations 404 and 406 may be sub-steps of the operation 402.

[0068] In operation 404, the 4×4 data block may be encoded into a bitstream according to CAVLC. The 4×4 data block may represent video data. As a non-limiting example, data in the video data may have been identified, predicted, transformed, and / or quantized to generate the 4×4 data block. The bitstream may represent compressed video data. As a non-limiting example of operation 404, the 4×4 data block may be encoded into a bitstream according to CAVLC. The 4×4 data block may represent video data. As a non-limiting example, data in the video data may have been identified, predicted, transformed, and / or quantized to generate the 4×4 data block. The bitstream may represent compressed video data. Figure 1 The CAVLC 120 encodes the 4×4 data block 110 into Figure 1 The bit stream 118.

[0069] In operation 406, at least some of the coefficients of the 4×4 data block may be ignored when encoding the 4×4 data block. As a non-limiting example of operation 404, at least some of the coefficients of the 4×4 data block 110 may be ignored when encoding the data block 110 into the bitstream 118. Figure 1 At least some of the coefficients 112 of the 4×4 data block. In some non-limiting examples, at least two coefficients of the coefficients of the 4×4 data block may be ignored. In some non-limiting examples, the last two coefficients of the 4×4 data block may be ignored according to a zigzag scanning pattern.

[0070] Setting coefficients to zero may be an example of ignoring coefficients. For example, at least some coefficients (eg, two, but not limited thereto, such as the last two coefficients, but not limited thereto) may be set to zero in operation 406.

[0071] Figure 5A and Figure 5B 5 is a flowchart of a method 500 according to one or more examples. In some non-limiting examples, at least a portion of the method 500 may be performed by a device or system such as Figure 1 The device 100, Figure 1 The device video data encoder 102, Figure 2 The device 200, Figure 2 The video data encoder 202, Figure 3 The device 300, Figure 3Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0072] In operation 502, video data may be encoded to generate compressed video data. As a non-limiting example, Figure 1 The video data 104 is compressed into Figure 1 One or more of operations 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, and 524 may be performed when operation 502 is performed. In other words, one or more of operations 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, and 524 may be sub-steps of operation 502.

[0073] In operation 504, a data block representing video data may be transformed using an integer transform. As a non-limiting example, a data block may represent a group of pixels of an image of video data. As a non-limiting example of operation 504, a data block representing video data 104 may be transformed using an integer transform.

[0074] In operation 506, the transformed data block may be quantized to generate a 4×4 data block. As a non-limiting example, the data block transformed in operation 504 may be quantized to generate Figure 1 The 4×4 data block 110 is formed.

[0075] In operation 508, at least some of the coefficients of the 4×4 data block may be set to zero. The 4×4 data block may represent video data. Data in the video data may have been identified, predicted, transformed (e.g., in operation 504), and / or quantized (e.g., in operation 506) to generate the 4×4 data block. As a non-limiting example of operation 508, the coefficients of the 4×4 data block 110 may be set to zero. Figure 1 At least some of the coefficients 112 of the 4×4 data block may be set to zero. In some non-limiting examples, at least two of the coefficients of the 4×4 data block may be set to zero. In some non-limiting examples, the last two coefficients of the 4×4 data block may be set to zero according to a zigzag scan pattern.

[0076] In operation 510, the 4×4 data block may be encoded into a bitstream according to CAVLC. The bitstream may represent compressed video data. As a non-limiting example of operation 510, the bitstream may be encoded according to Figure 1 The CAVLC 120 encodes the 4×4 data block 110 into Figure 1One or more of operation 512, operation 514, operation 516, operation 518, operation 520, operation 522, and operation 524 may be performed when operation 510 is performed. In other words, one or more of operation 512, operation 514, operation 516, operation 518, operation 520, operation 522, and operation 524 may be sub-steps of operation 510.

[0077] In operation 512, a number of non-zero coefficients of the 4x4 data block may be counted according to CAVLC.

[0078] In operation 514, a number of trailing ones of the 4x4 data block may be counted according to CAVLC.

[0079] In operation 516, the plurality of non-zero coefficients and the plurality of trailing ones may be encoded according to CAVLC. Operation 512, operation 514, and operation 516 may be performed according to stage 1 of CAVLC.

[0080] In operation 518, the symbols of each of the trailing ones may be encoded according to CAVLC. Operation 518 may be performed according to stage 2 of CAVLC.

[0081] In some non-limiting examples, operation 512, operation 514, operation 516, and operation 518 may be performed during the same clock cycle. In some non-limiting examples, stage 1 and stage 2 of CAVLC may be performed during the same clock cycle.

[0082] In operation 520, the levels of the remaining non-zero coefficients may be encoded according to CAVLC. Operation 520 may be performed according to stage 3 of CAVLC.

[0083] In operation 522, a count of zeros before the last non-zero coefficient may be encoded according to CAVLC. Operation 522 may be performed according to stage 4 of CAVLC.

[0084] In operation 524, the zeros before the last non-zero coefficient may be encoded according to CAVLC. Operation 524 may be performed according to stage 5 of CAVLC.

[0085] In some non-limiting examples, operation 520 may be performed in parallel with operation 524. In some non-limiting examples, stage 3 and stage 5 of CAVLC may be performed in parallel.

[0086] Fig. 6A and Figure 6B 600 according to one or more examples. In some non-limiting examples, at least a portion of the method 600 may be performed by a device or system such as Figure 1 The device 100, Figure 1 The device video data encoder 102, Figure 2 The device 200, Figure 2 The video data encoder 202, Figure 3 The device 300, Figure 3 Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0087] In operation 602, video data may be encoded to generate compressed video data. As a non-limiting example, Figure 1 The video data 104 is compressed into Figure 1 One or more of operations 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, and 634 may be performed when operation 602 is performed. In other words, one or more of operations 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, and 634 may be sub-steps of operation 602.

[0088] In operation 604, a data block representing video data may be transformed using an integer transform. As a non-limiting example, a data block may represent a group of pixels of an image of video data. As a non-limiting example of operation 604, a data block representing video data 104 may be transformed using an integer transform.

[0089] In operation 606, the transformed data block may be quantized to generate a 4×4 data block. As a non-limiting example, the data block transformed in operation 604 may be quantized to generate Figure 1 The 4×4 data block 110 is formed.

[0090] In operation 608, the 4×4 data block may be encoded into a bitstream according to CAVLC. The bitstream may represent compressed video data. As a non-limiting example of operation 608, the bitstream may be encoded according to Figure 1 The CAVLC 120 encodes the 4×4 data block 110 into Figure 1One or more of operations 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, and 634 may be performed when operation 610 is performed. In other words, one or more of operations 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, and 634 may be sub-steps of operation 608.

[0091] In operation 610, at least some of the coefficients of the 4×4 data block may be ignored when encoding the 4×4 data block (e.g., in operation 608). The 4×4 data block may represent video data. As a non-limiting example, data in the video data may have been identified, predicted, transformed (e.g., in operation 604), and / or quantized (e.g., in operation 606) to generate the 4×4 data block. As a non-limiting example, at least some of the coefficients of the 4×4 data block 110 may be ignored. Figure 1 At least some of the coefficients in coefficients 112 of the 4×4 data block may be ignored. In some non-limiting examples, at least two coefficients of the coefficients of the 4×4 data block may be ignored. In some non-limiting examples, the last two coefficients of the 4×4 data block may be ignored according to a zigzag scan pattern. Any or all of operations 614, 618, 622, 628, and 630 may be examples of operation 612 of ignoring coefficients at various stages of CAVLC.

[0092] In operation 612, a number of non-zero coefficients of the 4x4 data block may be counted according to CAVLC.

[0093] In operation 614, when counting non-zero coefficients according to CAVLC (e.g., in operation 612), the last two coefficients may not be counted as non-zero coefficients regardless of whether they are non-zero coefficients. In other words, when counting non-zero coefficients according to CAVLC (e.g., in operation 612), the last two coefficients may be ignored.

[0094] In operation 616, a number of trailing ones of the 4x4 data block may be counted according to CAVLC.

[0095] In operation 618, when the trailing ones are counted according to CAVLC (e.g., in operation 616), the last two coefficients may not be counted as trailing ones, regardless of whether the last two coefficients are one. In other words, when the trailing ones are counted according to CAVLC (e.g., in operation 616), the last two coefficients may be ignored.

[0096] In operation 620, the plurality of non-zero coefficients and the plurality of trailing ones may be encoded according to CAVLC. Operation 612, operation 616, and operation 620 may be performed according to stage 1 of CAVLC. Operation 614 and operation 618 may be modifications affecting stage 1 of CAVLC.

[0097] In operation 622, the symbols of each of the trailing ones may be encoded according to CAVLC. Operation 622 may be performed according to stage 2 of CAVLC.

[0098] In operation 624, when the trailing one symbol is encoded according to CAVLC (e.g., in operation 622), the symbols of the last two coefficients may not be encoded. In other words, when the trailing one symbol is encoded according to CAVLC, the last two coefficients may be ignored. Operation 624 may be a modification that affects stage 2 of CAVLC.

[0099] In some non-limiting examples, one or more of operation 612, operation 616, operation 620, and operation 622 may be performed during the same clock cycle. As a non-limiting example, stage 1 of CAVLC and stage 2 of CAVLC may be performed during the same clock cycle. Additionally, in some non-limiting examples, one or more of operation 614, operation 618, and operation 624 may be performed during the same clock cycle, i.e., during the same clock cycle during which one or more of operation 612, operation 616, operation 620, and operation 622 are performed.

[0100] In operation 626, the levels of the remaining non-zero coefficients may be encoded according to CAVLC. Operation 626 may be performed according to stage 3 of CAVLC.

[0101] In operation 628, when the level is encoded according to CAVLC (e.g., in operation 626), the level of the last two coefficients may not be encoded. In other words, when the level of the remaining non-zero coefficients is encoded according to CAVLC, the last two coefficients may be ignored. Operation 628 may be a modification that affects stage 3 of CAVLC.

[0102] In operation 630, a count of zeros before the last non-zero coefficient may be encoded according to CAVLC. Operation 630 may be performed according to stage 4 of CAVLC.

[0103] In operation 632, zeros before the last non-zero coefficient may be encoded according to CAVLC. Operation 632 may be performed according to stage 5 of CAVLC.

[0104] In some non-limiting examples, one or both of operation 626 and operation 628 may be performed in parallel with operation 632. As a non-limiting example, stage 3 and stage 5 of CAVLC may be performed in parallel.

[0105] In operation 634, when the last non-zero coefficient is identified according to CAVLC (e.g., the last non-zero coefficient of one or both of operation 630 and operation 632), the last two coefficients may not be considered. In other words, when the last non-zero coefficient is identified according to CAVLC, the last two coefficients may be ignored. Operation 634 may be a modification that affects one or both of stage 4 and stage 5 of CAVLC.

[0106] Without departing from the scope of the present disclosure, modifications, additions, or omissions may be made to method 400, method 500, and / or method 600. For example, the operations of method 400, method 500, and / or method 600 may be implemented in a different order. Furthermore, the operations and actions outlined are provided only as examples, and some of these operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without departing from the essence of the disclosed examples.

[0107] Figure 7 700 is a block diagram of a device 700 that, in one or more examples, can be used to implement various functions, operations, actions, processes, or methods disclosed herein. The device 700 includes one or more processors 702 (sometimes referred to herein as "processors 702") operably coupled to one or more devices such as a data storage device (sometimes referred to herein as "storage device 704"), but is not limited to such. The storage device 704 includes machine executable code 706 stored thereon (e.g., stored on a computer readable memory, but is not limited to such), and the processor 702 includes logic circuitry 708. The machine executable code 706 includes information describing functional elements that can be implemented by (e.g., executed by) the logic circuitry 708. The logic circuitry 708 implements (e.g., executes) the functional elements described by the machine executable code 706. When the functional elements described by the machine executable code 706 are executed, the device 700 should be considered as dedicated hardware that performs the functional elements disclosed herein. In one or more examples, processor 702 may execute the functional elements described by machine executable code 706 sequentially, concurrently (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0108] When implemented by the logic circuit 708 of the processor 702, the machine executable code 706 may adapt the processor 702 to perform the operations of the examples disclosed herein. For example, the machine executable code 706 may adapt the processor 702 to perform Figure 4Method 400, Figure 5A and Figure 5B Method 500 and Fig. 6A and Figure 6B For example, the machine executable code 706 may cause the processor 702 to execute at least a portion or all of the method 600. Figure 1 The device 100, Figure 1 The video data encoder 102, Figure 2 The device 200, Figure 2 The video data encoder 202, Figure 3 The device 300 or Figure 3 At least a portion or all of the operations discussed above for the video data encoder 302 .

[0109] Processor 702 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general-purpose computer including a processor executes computing instructions (e.g., software code, but not limited to this) related to the example, the general-purpose computer is considered to be a special-purpose computer. It should be noted that a general-purpose processor (also referred to as a host processor or simply a host in this article) can be a microprocessor, but in an alternative, processor 702 may include any conventional processor, controller, microcontroller or state machine. Processor 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0110] In one or more examples, the storage device 704 includes a volatile data storage device (e.g., a random access memory (RAM), but not limited thereto), a non-volatile data storage device (e.g., a flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), but not limited thereto). In one or more examples, the processor 702 and the storage device 704 may be implemented as a single device (e.g., a semiconductor device product, a system on a chip (SOC), but not limited thereto). In one or more examples, the processor 702 and the storage device 704 may be implemented as separate devices.

[0111] In one or more examples, the machine executable code 706 may include computer readable instructions (e.g., software code, firmware code, but not limited thereto). By way of non-limiting example, the computer readable instructions may be stored by the storage device 704, directly accessed by the processor 702, and executed by the processor 702 using at least the logic circuit 708. Also by way of non-limiting example, the computer readable instructions may be stored on the storage device 704, sent to a memory device (not shown) for execution, and executed by the processor 702 using at least the logic circuit 708. Thus, in one or more examples, the logic circuit 708 includes a logic circuit that can be configured in an electrically manner.

[0112] In one or more examples, machine executable code 706 may describe hardware (e.g., circuits, but not limited to) to be implemented in logic circuit 708 to perform a functional element. The hardware may be described at any of a variety of abstraction levels from low-level transistor layout to a high-level description language. At a high level of abstraction, a hardware description language (HDL) may be used, such as, but not limited to, an Institute of Electrical and Electronics Engineers (IEEE) standard hardware description language (HDL). As a non-limiting example, Verilog TM 、SystemVerilog TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL TM ).

[0113] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, micro-operations to be performed by hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 708 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic component, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in one or more examples, the machine executable code 706 may include an HDL, RTL, GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0114] In examples where the machine executable code 706 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 704) may implement the hardware description described by the machine executable code 706. By way of non-limiting example, the processor 702 may include a programmable logic device (e.g., an FPGA or a PLC, but not limited thereto), and the logic circuit 708 may be electrically controlled to implement circuits corresponding to the hardware description into the logic circuit 708. Also by way of non-limiting example, the logic circuit 708 may include hard-wired logic components manufactured by a manufacturing system (not shown, but including the storage device 704) according to the hardware description of the machine executable code 706.

[0115] Regardless of whether the machine executable code 706 includes computer readable instructions or a hardware description, the logic circuit 708, when implementing the functional elements of the machine executable code 706, performs the functional elements described by the machine executable code 706. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0116] As used herein, the term "substantially" in reference to a given parameter, property, or condition means and includes to the extent that one skilled in the art would understand that the given parameter, property, or condition is satisfied with minor variations (such as within acceptable manufacturing tolerances). For example, a substantially satisfied parameter may be at least about 90% satisfied, at least about 95% satisfied, or even at least about 99% satisfied.

[0117] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that can perform the actions of a module or component or software object or software routine that can be stored on or executed by general hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In one or more examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads, but not limited thereto). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on or executed by general hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0118] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0119] Terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims), are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including but not limited to," but not limited to). As used herein, "each" means "some or all." As used herein, "each" means "all."

[0120] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to an example containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" or "an" means "at least one" or "one or more"); the same is true when a definite article is used to introduce a claim recitation.

[0121] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the unmodified recitation "two recitations" means at least two recitations, or two or more recitations, in the absence of other modifying elements). In addition, in those instances where conventional phrases like "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" are used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but are not limited thereto.

[0122] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0123] Additional non-limiting embodiments of the present disclosure may include:

[0124] Embodiment 1: A device, comprising: a video data encoder, wherein the video data encoder is used to: encode a 4×4 data block into a bit stream according to context adaptive variable length decoding, wherein the 4×4 data block represents video data; and when encoding the 4×4 data block, ignore at least some coefficients of the 4×4 data block.

[0125] Embodiment 2: The apparatus according to embodiment 1, wherein the video data encoder ignores the at least some coefficients of the 4×4 data block by setting the at least some coefficients of the 4×4 data block to zero before encoding the 4×4 data block.

[0126] Embodiment 3: A device according to embodiments 1 and 2, wherein after at least some of the coefficients of the 4×4 data block are set to zero, in order to encode the 4×4 data block into the bit stream, the video data encoder is used to perform the following operations: counting multiple non-zero coefficients of the 4×4 data block; counting multiple trailing ones of the 4×4 data block; encoding the multiple non-zero coefficients and the multiple trailing ones according to the context adaptive variable length decoding; encoding the sign of each of the trailing ones according to the context adaptive variable length decoding; encoding the hierarchy of coefficients according to the context adaptive variable length decoding; encoding the count of zeros before the last non-zero coefficient according to the context adaptive variable length decoding; and encoding the zeros before the last non-zero coefficient according to the context adaptive variable length decoding.

[0127] Embodiment 4: An apparatus according to embodiments 1 to 3, wherein in order to ignore at least some coefficients of the 4×4 data block when encoding the 4×4 data block, the video data encoder is used to perform one or more of the following operations: when counting non-zero coefficients according to the context adaptive variable length decoding, the at least some coefficients are not counted as non-zero coefficients; when counting trailing ones according to the context adaptive variable length decoding, the at least some coefficients are not counted as trailing ones; when encoding the sign of the trailing ones according to the context adaptive variable length decoding, the signs of the at least some coefficients are not encoded; when encoding the levels according to the context adaptive variable length decoding, the levels of the at least some coefficients are not encoded; and when the last non-zero coefficient is identified according to the context adaptive variable length decoding, the at least some coefficients are not included.

[0128] Embodiment 5: The apparatus of embodiments 1 to 4, wherein the at least some coefficients include at least two coefficients.

[0129] Embodiment 6: The apparatus according to embodiments 1 to 5, wherein the at least some of the coefficients include the last two coefficients of the 4×4 data block according to a zigzag scanning pattern of the coefficients in the 4×4 data block.

[0130] Embodiment 7: The device of Embodiments 1-6, wherein the video data encoder encodes the plurality of non-zero coefficients and the plurality of trailing ones and encodes a sign of each of the trailing ones during a same clock cycle.

[0131] Embodiment 8: The apparatus of Embodiments 1 to 7, wherein the video data encoder encodes the 4×4 data block into the bitstream in 16 clock cycles or less.

[0132] Embodiment 9: A device, comprising: a video data encoder, wherein the video data encoder is used to: encode a 4×4 data block into a bit stream according to context adaptive variable length decoding, wherein the 4×4 data block represents video data; and when encoding the 4×4 data block, ignore at least some coefficients of the 4×4 data block, thereby encoding the video data to generate compressed video data.

[0133] Embodiment 10: The apparatus according to Embodiment 9, wherein the video data encoder sets at least some coefficients of the 4×4 data block to zero before encoding the 4×4 data block so as to ignore the at least some coefficients of the 4×4 data block.

[0134] Embodiment 11: A device according to embodiments 9 and 10, wherein the video data encoder performs the following operations after setting at least some of the coefficients of the 4×4 data block to zero: counting multiple non-zero coefficients of the 4×4 data block according to the context adaptive variable length decoding; counting multiple trailing ones of the 4×4 data block according to the context adaptive variable length decoding; encoding the multiple non-zero coefficients and the multiple trailing ones according to the context adaptive variable length decoding; encoding the sign of each of the trailing ones according to the context adaptive variable length decoding; encoding the hierarchy of coefficients according to the context adaptive variable length decoding; encoding the count of zeros before the last non-zero coefficient according to the context adaptive variable length decoding; and encoding the zeros before the last non-zero coefficient according to the context adaptive variable length decoding, thereby encoding the 4×4 data block into the bit stream.

[0135] Embodiment 12: A device according to embodiments 9 to 11, wherein the video data encoder is used to perform one or more of the following operations: when counting non-zero coefficients according to the context adaptive variable length decoding, at least some of the coefficients are not counted as non-zero coefficients; when counting trailing ones according to the context adaptive variable length decoding, at least some of the coefficients are not counted as trailing ones; when encoding the sign of the trailing one according to the context adaptive variable length decoding, the signs of the at least some of the coefficients are not encoded; when encoding the levels according to the context adaptive variable length decoding, the levels of the at least some of the coefficients are not encoded; and when the last non-zero coefficient is identified according to the context adaptive variable length decoding, the at least some of the coefficients are not included, thereby ignoring at least some of the coefficients of the 4×4 data block when encoding the 4×4 data block.

[0136] Embodiment 13: The apparatus of embodiments 9 to 12, wherein the at least some coefficients include at least two coefficients.

[0137] Embodiment 14: The apparatus of embodiments 9 to 13, wherein the at least two coefficients include last two coefficients of the 4×4 data block that are zero according to a zigzag scanning pattern of the coefficients in the 4×4 data block.

[0138] Embodiment 15: The apparatus according to embodiments 9 to 14, wherein the video data encoder is configured to perform the following operations: transform a data block of a group of pixels representing an image of the video data using an integer transform; and quantize the transformed data block to generate the 4×4 data block.

[0139] Embodiment 16: A method, comprising: encoding video data to generate compressed video data, the encoding comprising: encoding 4×4 data blocks into a bit stream according to context adaptive variable length decoding, the 4×4 data blocks representing the video data; and when encoding the 4×4 data blocks, ignoring at least some coefficients of the 4×4 data blocks.

[0140] Embodiment 17: The method of Embodiment 16, wherein ignoring the at least some coefficients of the 4×4 data block comprises setting the at least some coefficients of the 4×4 data block to zero prior to encoding the 4×4 data block.

[0141] Embodiment 18: A method according to embodiments 16 and 17, wherein encoding the 4×4 data block into the bitstream includes performing the following operations after setting at least some of the coefficients of the 4×4 data block to zero: counting multiple non-zero coefficients of the 4×4 data block according to the context adaptive variable length decoding; counting multiple trailing ones of the 4×4 data block according to the context adaptive variable length decoding; encoding the multiple non-zero coefficients and the multiple trailing ones according to the context adaptive variable length decoding; encoding the sign of each of the trailing ones according to the context adaptive variable length decoding; encoding the hierarchy of coefficients according to the context adaptive variable length decoding; encoding the count of zeros before the last non-zero coefficient according to the context adaptive variable length decoding; and encoding the zeros before the last non-zero coefficient according to the context adaptive variable length decoding.

[0142] Embodiment 19: A method according to embodiments 16 to 18, wherein encoding the 4×4 data block into the bitstream while ignoring the at least some coefficients of the 4×4 data block includes one or more of the following operations: when counting non-zero coefficients according to the context adaptive variable length decoding, not counting the at least some coefficients as non-zero coefficients; when counting trailing ones according to the context adaptive variable length decoding, not counting the at least some coefficients as trailing ones; when encoding the sign of the trailing ones according to the context adaptive variable length decoding, not encoding the signs of the at least some coefficients; when encoding the levels according to the context adaptive variable length decoding, not encoding the levels of the at least some coefficients; and when identifying the last non-zero coefficient according to the context adaptive variable length decoding, not including the at least some coefficients.

[0143] Embodiment 20: The method according to embodiments 16 to 19 further comprises: transforming a data block of a group of pixels representing an image of the video data using an integer transform; and quantizing the transformed data block to generate the 4×4 data block.

[0144] Although the present disclosure has been described with respect to certain illustrative examples, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. In addition, features from one example may be combined with features of another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: A video data encoder, the video data encoder being configured to: encoding 4×4 data blocks into a bitstream according to context adaptive variable length coding, the 4×4 data blocks representing video data; and At least some coefficients of the 4x4 data block are ignored when encoding the 4x4 data block.

2. The apparatus of claim 1, wherein the video data encoder ignores the at least some coefficients of the 4x4 data block by setting the at least some coefficients of the 4x4 data block to zero prior to encoding the 4x4 data block.

3. The apparatus of claim 2, wherein after setting the at least some coefficients of the 4×4 data block to zero, to encode the 4×4 data block into the bitstream, the video data encoder is to: Counting a plurality of non-zero coefficients of the 4×4 data block; Counting a number of trailing ones of the 4×4 data block; encoding the plurality of non-zero coefficients and the plurality of trailing ones according to the context adaptive variable length coding; encoding a symbol of each of the trailing ones according to the context adaptive variable length coding; encoding a level of coefficients according to the context adaptive variable length coding; encoding a count of zeros preceding a last non-zero coefficient according to the context adaptive variable length coding; as well as Zeros preceding the last non-zero coefficient are encoded according to the context adaptive variable length coding.

4. The apparatus of claim 1 , wherein in order to ignore at least some coefficients of the 4×4 data block when encoding the 4×4 data block, the video data encoder is configured to perform one or more of the following operations: When counting non-zero coefficients according to the context adaptive variable length coding, not counting the at least some coefficients as non-zero coefficients; not counting the at least some coefficients as trailing ones when counting trailing ones according to the context adaptive variable length coding; when encoding the sign of a trailing one according to the context adaptive variable length coding, not encoding the signs of the at least some coefficients; when encoding the level according to the context adaptive variable length coding, not encoding the level of the at least some coefficients; as well as When a last non-zero coefficient is identified according to the context adaptive variable length coding, the at least some coefficients are not included.

5. The apparatus of claim 1, wherein the at least some coefficients include at least two coefficients.

6. The apparatus of claim 1, wherein the at least some of the coefficients include last two coefficients of the 4x4 data block according to a zigzag scanning pattern of the coefficients in the 4x4 data block.

7. The device of claim 1, wherein the video data encoder encodes the plurality of non-zero coefficients and the plurality of trailing ones and encodes the sign of each of the trailing ones during a same clock cycle.

8. The apparatus of claim 1, wherein the video data encoder encodes the 4x4 data block into the bitstream in 16 clock cycles or less.

9. A device, comprising: A video data encoder, the video data encoder being configured to: encoding a 4×4 data block into a bitstream according to context adaptive variable length coding, the 4×4 data block representing video data; as well as When encoding the 4×4 data block, at least some coefficients of the 4×4 data block are ignored, thereby encoding the video data to generate compressed video data.

10. The apparatus of claim 9, wherein the video data encoder sets at least some coefficients of the 4x4 data block to zero before encoding the 4x4 data block so as to ignore the at least some coefficients of the 4x4 data block.

11. The apparatus of claim 10, wherein after setting the at least some coefficients of the 4x4 data block to zero, the video data encoder is to: counting a plurality of non-zero coefficients of the 4×4 data block according to the context adaptive variable length decoding; counting a number of trailing ones of the 4×4 data block according to the context adaptive variable length decoding; encoding the plurality of non-zero coefficients and the plurality of trailing ones according to the context adaptive variable length coding; encoding a symbol of each of the trailing ones according to the context adaptive variable length coding; encoding a level of coefficients according to the context adaptive variable length coding; encoding a count of zeros preceding a last non-zero coefficient according to the context adaptive variable length coding; as well as encoding zeros preceding the last non-zero coefficient according to the context adaptive variable length coding, The 4×4 data block is thereby encoded into the bit stream.

12. The device of claim 9, wherein the video data encoder is configured to perform one or more of the following operations: When counting non-zero coefficients according to the context adaptive variable length coding, not counting the at least some coefficients as non-zero coefficients; not counting the at least some coefficients as trailing ones when counting trailing ones according to the context adaptive variable length coding; when encoding the sign of a trailing one according to the context adaptive variable length coding, not encoding the signs of the at least some coefficients; when encoding the level according to the context adaptive variable length coding, not encoding the level of the at least some coefficients; as well as when a last non-zero coefficient is identified according to the context adaptive variable length coding, not including the at least some coefficients, Thereby at least some coefficients of the 4x4 data block are ignored when encoding the 4x4 data block.

13. The apparatus of claim 9, wherein the at least some coefficients include at least two coefficients.

14. The apparatus of claim 13, wherein the at least two coefficients include last two coefficients of the 4x4 data block that are zero according to a zigzag scanning pattern of the coefficients in the 4x4 data block.

15. The apparatus of claim 9, wherein the video data encoder is configured to: transforming a data block of a group of pixels representing an image of the video data using an integer transform; and The transformed data block is quantized to generate the 4×4 data block.

16. A method comprising: Encoding the video data to generate compressed video data, the encoding comprising: encoding 4×4 data blocks into a bitstream according to context adaptive variable length coding, the 4×4 data blocks representing video data; and At least some coefficients of the 4x4 data block are ignored when encoding the 4x4 data block.

17. The method of claim 16, wherein ignoring the at least some coefficients of the 4x4 data block comprises setting at least some coefficients of the 4x4 data block to zero prior to encoding the 4x4 data block.

18. The method of claim 17, wherein encoding the 4x4 data block into the bitstream comprises, after setting the at least some coefficients of the 4x4 data block to zero: counting a plurality of non-zero coefficients of the 4×4 data block according to the context adaptive variable length decoding; counting a number of trailing ones of the 4×4 data block according to the context adaptive variable length decoding; encoding the plurality of non-zero coefficients and the plurality of trailing ones according to the context adaptive variable length coding; encoding a symbol of each of the trailing ones according to the context adaptive variable length coding; encoding a level of coefficients according to the context adaptive variable length coding; encoding a count of zeros preceding a last non-zero coefficient according to the context adaptive variable length coding; as well as Zeros preceding the last non-zero coefficient are encoded according to the context adaptive variable length coding.

19. The method of claim 16, wherein encoding the 4x4 data block into the bitstream while ignoring the at least some coefficients of the 4x4 data block comprises one or more of the following operations: When counting non-zero coefficients according to the context adaptive variable length coding, not counting the at least some coefficients as non-zero coefficients; not counting the at least some coefficients as trailing ones when counting trailing ones according to the context adaptive variable length coding; when encoding the sign of a trailing one according to the context adaptive variable length coding, not encoding the signs of the at least some coefficients; when encoding the level according to the context adaptive variable length coding, not encoding the level of the at least some coefficients; as well as When a last non-zero coefficient is identified according to the context adaptive variable length coding, the at least some coefficients are not included.

20. The method according to claim 16, further comprising: transforming a data block of a group of pixels representing an image of the video data using an integer transform; as well as The transformed data block is quantized to generate the 4×4 data block.

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