Jitter test circuit and jitter test method for buck circuit

Abstract

The present invention relates to the field of jitter testing technology, and discloses a jitter testing circuit and a jitter testing method for a buck circuit, the method comprising: constructing different first jitter calculation formulas and second jitter calculation formulas based on the jitter generation mechanisms of buck circuits in different control modes, calculating the first jitter value of the buck circuit in the pulse width modulation control mode and the second jitter value of the buck circuit in the constant on-time control mode according to the rising edge moment, falling edge moment, first jitter calculation formula and second jitter calculation formula of the pulse width modulation waveform of the buck circuit in different control modes; respectively comparing the first jitter value and the second jitter value with a preset threshold value to judge the stability of the buck circuit control system in different control modes. By constructing different jitter calculation formulas for the buck circuits in different control modes, and comparing the jitter value with the set threshold value, the stability of the buck circuit control system can be judged.

Description

Technical Field

[0001] The present invention relates to the technical field of jitter testing, and in particular to a jitter testing circuit and a jitter testing method for a step-down circuit. Background Art

[0002] The jitter of the buck circuit refers to the edge jitter of the pulse-width modulation (PWM) waveform at the switch pin of the buck circuit control chip. For the buck circuit in PWM control mode, each PWM cycle is fixed. The microcontroller unit (MCU) changes the duty cycle by adjusting the duration of the high level to achieve the purpose of changing the output voltage. Then the change in duty cycle corresponds to the change in the falling edge time of the PWM waveform, and the change in the falling edge time of the PWM waveform means that jitter has occurred. The smaller the jitter, the more stable the output voltage and load current of the buck circuit, and the more stable the control system. If the jitter is too large, it usually means that the phase margin of the control system is insufficient and the control system is unstable.

[0003] For the buck circuit in the constant on-time (COT) control mode, the duration of the PWM high level is fixed. The MCU changes the duty cycle in disguise by adjusting the duration of the PWM cycle, thereby achieving the purpose of changing the output voltage. The change in the PWM cycle corresponds to the change in the rising edge time of the PWM waveform, and the change in the rising edge time of the PWM waveform means that jitter is generated. Similarly, the smaller the jitter, the more stable the output voltage and load current of the buck circuit, and the more stable the control system. If the jitter is too large, it usually means that the phase margin of the control system is insufficient and the control system is unstable. Therefore, by testing the jitter of the buck circuit, the stability of the buck circuit control system can be monitored.

[0004] However, there is currently no suitable jitter testing solution to test the jitter to monitor the stability of the buck circuit control system. Summary of the invention

[0005] In view of this, the present invention provides a jitter test circuit and a jitter test method for a buck circuit to solve the problem of lack of a suitable jitter test solution at present.

[0006] In a first aspect, the present invention provides a jitter test method for a buck circuit, the method comprising:

[0007] Based on the jitter generation mechanism of the buck circuit in the pulse width modulation control mode, a first jitter calculation formula is constructed, and according to the rising edge time and falling edge time of the pulse width modulation waveform of the buck circuit in the pulse width modulation control mode and the first jitter calculation formula, a first jitter value of the buck circuit in the pulse width modulation control mode is calculated;

[0008] Based on the jitter generation mechanism of the buck circuit in constant on-time control mode, a second jitter calculation formula is constructed, and according to the rising edge time and falling edge time of the pulse width modulation waveform of the buck circuit in constant on-time control mode and the second jitter calculation formula, a second jitter value of the buck circuit in constant on-time control mode is calculated;

[0009] Comparing the first jitter value with a first preset threshold value to determine the stability of the step-down circuit control system in the pulse width modulation control mode;

[0010] The second jitter value is compared with a second preset threshold value to determine the stability of the buck circuit control system in the constant on-time control mode.

[0011] The present invention provides a buck circuit jitter test method, which constructs different jitter calculation formulas based on the buck circuit jitter generation mechanisms of PWM and COT control modes, and compares the jitter value with a set threshold value to judge the stability of the buck circuit control system.

[0012] In an optional implementation, the first jitter value of the step-down circuit in the pulse width modulation control mode is calculated according to the rising edge time, the falling edge time and the first jitter calculation formula of the pulse width modulation waveform of the step-down circuit in the pulse width modulation control mode, including:

[0013] Obtaining the rising edge time, falling edge time and switching period of the pulse width modulation waveform of the step-down circuit in the pulse width modulation control mode;

[0014] According to the rising edge time and the falling edge time, the maximum value, the minimum value and the average value of the high level duration in the pulse width modulation waveform are calculated;

[0015] The maximum value, the minimum value and the average value of the switching period and the high-level duration are substituted into the first jitter calculation formula to calculate the first jitter value.

[0016] In an optional implementation, the step of calculating the second jitter value of the buck circuit in constant on-time control mode according to the rising edge time, the falling edge time of the pulse width modulation waveform of the buck circuit in constant on-time control mode and the second jitter calculation formula includes:

[0017] Obtaining the rising edge time, falling edge time and high level duration of the pulse width modulation waveform of the buck circuit in constant on-time control mode;

[0018] Calculate the maximum value, minimum value and average value of the switching cycle according to the rising edge time and the falling edge time;

[0019] The high level duration, the maximum value, the minimum value and the average value of the switching period are substituted into the second jitter calculation formula to obtain the second jitter value.

[0020] In an optional implementation manner, the first jitter calculation formula is as follows:

[0021]

[0022] in, jitter 1 is the first jitter value; is the maximum value of the high level duration, ; is the switching cycle, is the minimum value of the high level duration, ; is the average value of the high level duration, ; and are the current rising edge moment and the adjacent falling edge moment respectively. , n is the total number of rising edge times and falling edge times.

[0023] In an optional implementation manner, the second jitter calculation formula is as follows:

[0024]

[0025] in, jitter 2 is the second jitter value; is the minimum value of the switching period, ; is the maximum value of the switching cycle, ; is the high level duration; is the average value of the switching cycle, ; and They are the current rising edge moment and the next adjacent rising edge moment respectively. , n is the total number of rising edge times and falling edge times.

[0026] In an optional implementation, the process of acquiring the rising edge time and the falling edge time includes:

[0027] Detecting the rising edge and falling edge of the pulse width modulation waveform according to the start detection signal, starting timing when the first rising edge is detected, and timing the subsequently detected rising edges and falling edges to obtain the rising edge time and the falling edge time;

[0028] When the stop detection signal is received, it is determined whether the most recent level jump is a rising edge or a falling edge;

[0029] When the most recent level jump is a rising edge, the next level falling edge is timed and detection is stopped;

[0030] When the most recent level transition is a falling edge, detection stops.

[0031] In an optional implementation, the method further includes: storing the rising edge time and the falling edge time in a rolling storage manner.

[0032] By adopting rolling storage to store the rising edge time and the falling edge time, the demand for continuous array acquisition is met, and the new array is prevented from being unable to be saved due to full storage space.

[0033] In an optional implementation, the method further includes: aligning the rising edge time and the falling edge time.

[0034] By aligning the rising edge time and the falling edge time, it is further ensured that the number of data stored in the array is an even number.

[0035] In an optional implementation, comparing the first jitter value with a first preset threshold value to determine the stability of the step-down circuit control system in the pulse width modulation control mode includes:

[0036] When the first jitter value is greater than a first preset threshold, it is determined that the stability of the buck circuit control system does not meet the requirement;

[0037] When the first jitter value is not greater than the first preset threshold, it is determined that the stability of the buck circuit control system meets the requirement.

[0038] In an optional implementation manner, comparing the second jitter value with a second preset threshold value to determine the stability of the buck circuit control system in the constant on-time control mode includes:

[0039] When the second jitter value is greater than a second preset threshold, it is determined that the stability of the buck circuit control system does not meet the requirement;

[0040] When the second jitter value is not greater than the second preset threshold, it is determined that the stability of the buck circuit control system meets the requirement.

[0041] In a second aspect, the present invention provides a jitter test circuit for a buck circuit, the jitter test circuit comprising: a microcontroller and a timer, the microcontroller and the timer being communicatively connected with each other, the microcontroller storing computer instructions, the microcontroller and the timer executing the computer instructions to execute the jitter test method for the buck circuit of the first aspect or any corresponding embodiment thereof.

[0042] The present invention provides a step-down circuit jitter test circuit. The microcontroller and timer in the circuit can determine the stability of the step-down circuit control system by executing the step-down circuit jitter test method.

[0043] In an optional implementation, the jitter test circuit further includes: a step-down circuit control chip and a voltage divider circuit, wherein:

[0044] The enable end of the microcontroller receives a test enable signal, the input end of the microcontroller is connected to the switch pin of the buck circuit control chip through the voltage divider circuit, the timing end of the microcontroller is connected to the timer, and the power supply end of the buck circuit control chip is connected to a DC power supply.

[0045] In an optional implementation, the voltage divider circuit includes a first resistor and a second resistor, wherein:

[0046] One end of the first resistor is connected to the switch pin of the buck circuit control chip, the other end of the first resistor is respectively connected to the input end of the microcontroller and one end of the second resistor, and the other end of the second resistor is grounded.

[0047] By setting the resistor of the voltage divider circuit, it is ensured that the input voltage of the microcontroller is within the rated voltage range.

[0048] In a third aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the jitter testing method for a buck circuit according to the first aspect or any corresponding embodiment thereof.

[0049] In a fourth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the jitter testing method for a buck circuit according to the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 is a flow chart of a jitter testing method for a buck circuit according to an embodiment of the present invention;

[0052] Figure 2 is a PWM waveform diagram at a switch pin of a buck circuit according to an embodiment of the present invention;

[0053] Figure 3 4 is a jitter test circuit diagram of a buck circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0055] The present invention provides a jitter test method for a buck circuit, by constructing different jitter calculation formulas for buck circuits in PWM and COT control modes respectively, and comparing the jitter value with a set threshold value, thereby judging the stability of the buck circuit control system.

[0056] According to an embodiment of the present invention, an embodiment of a jitter test method for a buck circuit is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0057] In this embodiment, a jitter test method for a buck circuit is provided. Figure 1 is a flow chart of a jitter testing method for a buck circuit according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0058] Step S1, based on the jitter generation mechanism of the buck circuit in pulse width modulation control mode, construct a first jitter calculation formula, and calculate the first jitter value of the buck circuit in pulse width modulation control mode according to the rising edge time and falling edge time of the pulse width modulation waveform of the buck circuit in pulse width modulation control mode and the first jitter calculation formula.

[0059] Specifically, for the buck circuit in PWM control mode, its switching period Tsw1 is fixed, and the duty cycle D1=Ton1 / Tsw1, so the jitter of Ton1 means the jitter of the duty cycle. Based on the jitter generation mechanism of the buck circuit in PWM control mode, a first jitter calculation formula is constructed. The rising edge time and falling edge time of the PWM waveform of the buck circuit in PWM control mode are obtained, and are brought into the first jitter calculation formula to calculate the first jitter value.

[0060] Step S2, based on the jitter generation mechanism of the buck circuit in constant on-time control mode, construct a second jitter calculation formula, and calculate the second jitter value of the buck circuit in constant on-time control mode according to the rising edge time, falling edge time of the pulse width modulation waveform of the buck circuit in constant on-time control mode and the second jitter calculation formula.

[0061] Specifically, for the buck circuit in the COT control mode, the high-level duration Ton2 of the PWM waveform is fixed, D2=Ton2 / Tsw2, so the jitter of Tsw2 means the jitter of the duty cycle. Based on the jitter generation mechanism of the buck circuit in the COT control mode, a second jitter calculation formula is constructed. The rising edge time and falling edge time of the PWM of the buck circuit in the COT control mode are obtained, and a second jitter calculation formula is constructed for the buck circuit in the COT control mode, and the second jitter calculation formula is substituted into the second jitter calculation formula to calculate the second jitter value.

[0062] Step S3, comparing the first jitter value with a first preset threshold value to determine the stability of the buck circuit control system in the pulse width modulation control mode.

[0063] Specifically, since the jitter value can characterize the stability of the buck circuit control system, the first jitter value is compared with the first preset threshold value, and the stability of the buck circuit control system is determined according to the comparison result of the two. If the first jitter value exceeds the first preset threshold value, it means that the jitter is too large, the system is not stable enough, and the test fails. Otherwise, it means that the jitter is within an acceptable range, the system is stable enough, and the test is successful.

[0064] Step S4, comparing the second jitter value with the second preset threshold value to determine the stability of the buck circuit control system in the constant on-time control mode.

[0065] Specifically, the second jitter value is compared with the second preset threshold value, and the stability of the buck circuit control system is determined according to the comparison result of the two. If the second jitter value exceeds the second preset threshold value, it means that the jitter is too large, the system is not stable enough, and the test fails. Otherwise, it means that the jitter is within an acceptable range, the system is stable enough, and the test succeeds.

[0066] The present invention provides a jitter test method for a buck circuit, comprising: constructing a first jitter calculation formula based on the jitter generation mechanism of the buck circuit in a pulse width modulation control mode, and calculating the first jitter value of the buck circuit in the pulse width modulation control mode according to the rising edge moment, the falling edge moment and the first jitter calculation formula of the pulse width modulation waveform of the buck circuit in the pulse width modulation control mode; constructing a second jitter calculation formula based on the jitter generation mechanism of the buck circuit in a constant on-time control mode, and calculating the second jitter value of the buck circuit in the constant on-time control mode according to the rising edge moment, the falling edge moment and the second jitter calculation formula of the pulse width modulation waveform of the buck circuit in the constant on-time control mode; comparing the first jitter value with the first preset threshold value to determine the stability of the buck circuit control system in the pulse width modulation control mode; comparing the second jitter value with the second preset threshold value to determine the stability of the buck circuit control system in the constant on-time control mode. Constructing different jitter calculation formulas based on the jitter generation mechanisms of the buck circuit in the PWM and COT control modes, and comparing the jitter value with the set threshold value, so as to determine the stability of the buck circuit control system.

[0067] In an optional implementation, step S1 includes:

[0068] Step S11, obtaining the rising edge time, falling edge time and switching period of the pulse width modulation waveform of the buck circuit in the pulse width modulation control mode.

[0069] Specifically, the PWM waveform at the switch pin of the buck circuit is as follows: Figure 2 As shown, it consists of a series of high and low levels. Among them, Tsw is the switching period, and Ton is the duration of the high level. For the buck circuit in PWM control mode, each PWM switching period is fixed. The microcontroller changes the duty cycle by adjusting the duration of the high level, thereby achieving the purpose of changing the output voltage. So for the buck circuit in PWM control mode, the jitter should be tested by the duration jitter of the high level of the PWM waveform.

[0070] Therefore, based on the above analysis, the embodiment of the present invention needs to collect the rising edge time, falling edge time and switching period of the PWM waveform. Further, the rising edge time and falling edge time collection process of the PWM waveform is as follows:

[0071] Step S1101, detecting the rising edge and falling edge of the pulse width modulation waveform according to the start detection signal, starting timing when the first rising edge is detected, and timing the subsequent detected rising edges and falling edges to obtain the rising edge time and the falling edge time.

[0072] Step S1102, after receiving the stop detection signal, determine whether the most recent level jump is a rising edge or a falling edge.

[0073] Step S1103, when the most recent level jump is a rising edge, the next level falling edge is timed and the detection is stopped.

[0074] Step S1104, when the most recent level jump is a falling edge, stop detecting.

[0075] In the embodiment of the present invention, Figure 3 Taking the detection circuit shown as an example, after receiving the test enable high level signal, the microcontroller starts to detect the rising edge of the waveform at the switch pin SW. When the first rising edge is detected, the test officially starts and the enable timer starts timing from 0. Among them, the start detection signal is the test enable high level signal.

[0076] In the SRAM (Static Random-Access Memory) area inside the microcontroller, an array is allocated to store the timer count value. The array name is Array1. The timer count value of the first rising edge of the waveform at the switch pin SW is saved in Array1[0], where Array1[0] represents the first element of the array. Then the waveform at the switch pin SW generates a falling edge, and the timer count value at this time is saved in Array1[1], and the subsequent data is deduced in the same way. In this way, when the array subscript is an even number, the saved data is the time of the rising edge of the waveform at the switch pin SW, and when the array subscript is an odd number, the saved data is the time of the falling edge of the waveform at the switch pin SW.

[0077] When the microcontroller receives a low-level signal to enable the test, or the timer exceeds the maximum test time, the microcontroller first determines whether the most recent waveform level jump at the switch pin SW is a rising edge or a falling edge. If the most recent waveform level jump at the switch pin SW is a falling edge, the test ends immediately and the timer stops. If the most recent waveform level jump at the switch pin SW is a rising edge, then continue to wait for the next falling edge of the waveform level at the switch pin SW, and save the falling edge time to the array Array1, then end the test and stop the timer. The purpose of this is to ensure that the number of arrays saved is an even number, which is convenient for data alignment processing.

[0078] After the test is completed, assuming that the number of data stored in array Array1 is n, then the data corresponding to the rising edge and falling edge of the waveform at the switch pin SW are n / 2 respectively. Among them, the stop detection signal is a test enable low level signal or a signal triggered by the timer timing exceeding the maximum test time.

[0079] Step S12, calculating the maximum value, minimum value and average value of the high level duration in the pulse width modulation waveform according to the rising edge time and the falling edge time.

[0080] Specifically, for the buck circuit in PWM control mode, firstly calculate the maximum value, minimum value and average value of the high level duration of the waveform at the switch pin SW:

[0081] (1)

[0082] in, is the maximum value of the high level duration, is the minimum value of the high level duration, is the average value of the high level duration, and They are the current rising edge moment and the adjacent falling edge moment, and the difference between them represents the duration of the high level Ton1. , n is the total number of rising edge times and falling edge times.

[0083] Step S13, bringing the maximum value, minimum value and average value of the switching cycle and the high level duration into a first jitter calculation formula to calculate a first jitter value.

[0084] Specifically, for the PWM control mode, the switching period Tsw1 is fixed, and the duty cycle D1 = Ton1 / Tsw1, so the jitter of Ton1 means the jitter of the duty cycle. When the jitter is 0, that is, there is no jitter, Ton1 should be stable at T MEAN1 That is, Ton1 should be equal to the average on-time. In fact, Ton1 is MIN1 and T MAX1 If the jitter is between 0 and 1, then this jitter can be expressed by the rate of change of the duty cycle:

[0085] (2)

[0086] in, jitter 1 is the first jitter value, T MAX1 / T SW1 Indicates the maximum duty cycle, T MIN1 / T SW1 Indicates the minimum duty cycle, T MEAN1 / T SW1Represents the average duty cycle.

[0087] In an optional implementation, step S2 includes:

[0088] Step S21, obtaining the rising edge time, falling edge time and high level duration of the pulse width modulation waveform of the buck circuit in constant on-time control mode.

[0089] Specifically, for the buck circuit in COT control mode, the PWM high level duration is fixed. The microcontroller changes the duty cycle in disguise by adjusting the duration of the PWM cycle, thereby achieving the purpose of changing the output voltage. So for the buck circuit in COT control mode, the jitter should be tested by the interval time jitter between two adjacent rising edges of the PWM waveform.

[0090] Therefore, based on the above analysis, the embodiment of the present invention needs to collect the rising edge time, falling edge time and switching period of the PWM waveform. Further, the rising edge time and falling edge time collection process of the PWM waveform is as follows:

[0091] Step S1111, detecting the rising edge and falling edge of the pulse width modulation waveform according to the start detection signal, starting timing when the first rising edge is detected, and timing the subsequently detected rising edges and falling edges to obtain the rising edge time and the falling edge time.

[0092] Step S1112, after receiving the stop detection signal, determine whether the most recent level jump is a rising edge or a falling edge.

[0093] Step S1113, when the most recent level jump is a rising edge, the next level falling edge is timed and the detection is stopped.

[0094] Step S1114, when the most recent level jump is a falling edge, stop detecting.

[0095] In the embodiment of the present invention, Figure 3 Taking the detection circuit shown as an example, after receiving the test enable high level signal, the microcontroller starts to detect the rising edge of the waveform at the switch pin SW. When the first rising edge is detected, the test officially starts and the enable timer starts timing from 0. Among them, the start detection signal is the test enable high level signal.

[0096] In the SRAM area inside the microcontroller, an array is applied to save the count value of the timer. The array name is Array2. The timer count value of the first rising edge of the waveform at the switch pin SW is saved in Array2[0], where Array2[0] represents the first element of the array. Then the waveform at the switch pin SW generates a falling edge, and the timer count value at this time is saved in Array2[1], and the subsequent data is deduced in the same way. In this way, when the array subscript is an even number, the saved data is the time of the rising edge of the waveform at the switch pin SW, and when the array subscript is an odd number, the saved data is the time of the falling edge of the waveform at the switch pin SW.

[0097] When the microcontroller receives a low-level signal to enable the test, or the timer exceeds the maximum test time, the microcontroller first determines whether the most recent waveform level jump at the switch pin SW is a rising edge or a falling edge. If the most recent waveform level jump at the switch pin SW is a falling edge, the test ends immediately and the timer stops. If the most recent waveform level jump at the switch pin SW is a rising edge, then continue to wait for the next falling edge of the waveform level at the switch pin SW, and save the time of the falling edge to the array Array2, then end the test and stop the timer. The purpose of this is to ensure that the number of arrays saved is an even number, which is convenient for data alignment processing.

[0098] After the test is completed, assuming that the number of data stored in array Array2 is n, then the data corresponding to the rising edge and falling edge of the waveform at the switch pin SW are n / 2 respectively. Among them, the stop detection signal is a test enable low level signal or a signal triggered by the timer timing exceeding the maximum test time.

[0099] Step S22, calculating the maximum value, minimum value and average value of the switching cycle according to the rising edge time and the falling edge time.

[0100] Specifically, for the buck circuit in COT control mode, the maximum, minimum and average values ​​of the waveform switching period at the switch pin SW are first calculated:

[0101] (3)

[0102] in, is the maximum value of the switching cycle, is the minimum value of the switching period, is the average value of the switching cycle, and are the current rising edge moment and the next adjacent rising edge moment respectively, and the difference between the two represents the duration Tsw2 of the switching cycle. , n is the total number of rising edge times and falling edge times.

[0103] Step S23, bringing the high level duration, the maximum value, the minimum value and the average value of the switching period into a second jitter calculation formula to calculate a second jitter value.

[0104] Specifically, for the COT control mode, the high level duration Ton2 is fixed, and the duty cycle D2 = Ton2 / Tsw2, so the jitter of Tsw2 means the jitter of the duty cycle. When the jitter is 0, that is, there is no jitter, Tsw2 should be stable at T MEAN2 That is, Tsw2 should be equal to the average switching period. In fact, Tsw2 is T MIN2 and T MAX2 If the jitter is between 0 and 1, then this jitter can be expressed by the rate of change of the duty cycle:

[0105] (4)

[0106] in, jitter 2 is the second jitter value, Ton2 / T MIN2 Indicates the maximum duty cycle, Ton2 / T MAX2 Indicates the minimum duty cycle, Ton2 / T MEAN2 Represents the average duty cycle.

[0107] In an optional implementation, the method further includes: storing the rising edge time and the falling edge time in a rolling storage manner.

[0108] Specifically, the rolling storage method is to save the array to the microcontroller in chronological order. When the storage space is full, the new array overwrites the earliest array. By adopting the rolling storage method to store the rising edge time and the falling edge time, the demand for continuous acquisition of the array is met, and the new array cannot be saved due to the full storage space. Furthermore, after the array is stored in the microcontroller, the rising edge time and the falling edge time are aligned. By aligning the rising edge time and the falling edge time, it is further ensured that the number of data stored in the array is an even number.

[0109] In an optional implementation, step S3 includes:

[0110] Step S31: when the first jitter value is greater than the first preset threshold, it is determined that the stability of the buck circuit control system does not meet the requirement.

[0111] Step S32: when the first jitter value is not greater than the first preset threshold, it is determined that the stability of the buck circuit control system meets the requirement.

[0112] Specifically, after obtaining the first jitter value by the first jitter calculation formula, it is compared with the first preset threshold value. If the first jitter value exceeds the first preset threshold value, it means that the jitter is too large, the system is not stable enough, and the test fails. If the first jitter value does not exceed the first preset threshold value, it means that the jitter is within an acceptable range, the system is stable enough, and the test succeeds.

[0113] In an optional implementation, step S4 includes:

[0114] Step S41: when the second jitter value is greater than the second preset threshold, it is determined that the stability of the buck circuit control system does not meet the requirement.

[0115] Step S42: when the second jitter value is not greater than the second preset threshold, it is determined that the stability of the buck circuit control system meets the requirement.

[0116] Specifically, after obtaining the second jitter value by the second jitter calculation formula, it is compared with the second preset threshold value. If the second jitter value exceeds the second preset threshold value, it means that the jitter is too large, the system is not stable enough, and the test fails. If the second jitter value does not exceed the second preset threshold value, it means that the jitter is within an acceptable range, the system is stable enough, and the test succeeds. The first preset threshold value and the second preset threshold value may be the same or different.

[0117] The present invention also provides a jitter test circuit for a step-down circuit, such as Figure 3 As shown, the jitter test circuit includes: a microcontroller, a timer, a buck circuit control chip and a voltage divider circuit. The enable end of the microcontroller receives a test enable signal. The input end of the microcontroller is connected to the switch pin SW of the buck circuit control chip through the voltage divider circuit. The power supply end of the buck circuit control chip is connected to the DC power supply VIN. The microcontroller and the timer are connected to each other for communication. Computer instructions are stored in the microcontroller. The microcontroller and the timer execute the above-mentioned buck circuit jitter test method by executing the computer instructions.

[0118] Specifically, the voltage divider circuit includes a first resistor R1 and a second resistor R2, wherein one end of the first resistor R1 is connected to the switch pin SW of the step-down circuit control chip, the other end of the first resistor R1 is connected to the input end of the microcontroller and one end of the second resistor R2, respectively, and the other end of the second resistor R2 is grounded. The purpose of the resistor voltage divider is to meet the input voltage range of the microcontroller.

[0119] The embodiment of the present invention is tested by taking the buck circuit of COT control mode as an example. The switch pin SW of the buck circuit is connected to the input terminal of the MCU after voltage division by resistors R1 and R2. The selection of resistors R1 and R2 makes the high level of the signal at the switch pin SW to be 3.3V after voltage division, which meets the input range of the MCU input terminal.

[0120] After receiving the test enable high level signal, the microcontroller starts to detect the rising edge of the waveform at the switch pin SW. When the first rising edge is detected, the test officially starts and the enable timer starts timing from 0.

[0121] In the SRAM area inside the microcontroller, an array is applied to save the count value of the timer. The array name is Array2. The timer count value of the first rising edge of the waveform at the switch pin SW is saved in Array2[0], where Array2[0] represents the first element of the array. Then the waveform at the switch pin SW generates a falling edge, and the timer count value at this time is saved in Array2[1], and the subsequent data is deduced in the same way. In this way, when the array subscript is an even number, the saved data is the time of the rising edge of the waveform at the switch pin SW, and when the array subscript is an odd number, the saved data is the time of the falling edge of the waveform at the switch pin SW.

[0122] When the microcontroller receives a low-level signal to enable the test, or the timer exceeds the maximum test time, the microcontroller first determines whether the most recent waveform level jump at the switch pin SW is a rising edge or a falling edge. If the most recent waveform level jump at the switch pin SW is a falling edge, the test ends immediately and the timer stops. If the most recent waveform level jump at the switch pin SW is a rising edge, then continue to wait for the next falling edge of the waveform level at the switch pin SW, and save the time of the falling edge to the array Array2, then end the test and stop the timer. The purpose of this is to ensure that the number of arrays saved is an even number, which is convenient for data alignment processing.

[0123] After the test, assuming that the number of data stored in array Array2 is n, then the corresponding data for the rising and falling edges of the waveform at the switch pin SW is n / 2 each. Use formula (3) to calculate the maximum, minimum and average values ​​of the switching cycle of the waveform at the switch pin SW. For the COT control mode, the high level duration Ton2 is fixed, and the duty cycle D2 = Ton2 / Tsw2, so the jitter of Tsw2 means the jitter of the duty cycle. When the jitter is 0, that is, there is no jitter, Tsw2 should be stable at T MEAN2 That is, Tsw2 should be equal to the average switching period. In fact, Tsw2 is T MIN2 and T MAX2 If the jitter is between 0 and 1, then this jitter can be expressed by the change rate of the duty cycle, that is, substitute it into formula (4) to obtain the second jitter value.

[0124] After the second jitter value is obtained by formula (4), it is compared with the second preset threshold. If the second jitter value exceeds the second preset threshold, it means that the jitter is too large, the system is not stable enough, and the test fails. Otherwise, it means that the jitter is within an acceptable range, the system is stable enough, and the test succeeds.

[0125] The present invention provides a step-down circuit jitter test circuit. The microcontroller and timer in the circuit can determine the stability of the step-down circuit control system by executing the step-down circuit jitter test method.

[0126] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0127] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0128] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A jitter test method for a buck circuit, characterized in that: The method comprises: Based on the jitter generation mechanism of the buck circuit in the pulse width modulation control mode, a first jitter calculation formula is constructed, and according to the rising edge time and falling edge time of the pulse width modulation waveform of the buck circuit in the pulse width modulation control mode and the first jitter calculation formula, a first jitter value of the buck circuit in the pulse width modulation control mode is calculated; Based on the jitter generation mechanism of the buck circuit in constant on-time control mode, a second jitter calculation formula is constructed, and according to the rising edge time and falling edge time of the pulse width modulation waveform of the buck circuit in constant on-time control mode and the second jitter calculation formula, a second jitter value of the buck circuit in constant on-time control mode is calculated; Comparing the first jitter value with a first preset threshold value to determine the stability of the step-down circuit control system in the pulse width modulation control mode; Comparing the second jitter value with a second preset threshold value to determine the stability of the buck circuit control system in the constant on-time control mode; The first jitter calculation formula is as follows: in, jitter 1 is the first jitter value; is the maximum value of the high level duration, ; is the switching cycle, is the minimum value of the high level duration, ; is the average value of the high level duration, ; and are the current rising edge moment and the adjacent falling edge moment respectively. , n is the total number of rising edge time and falling edge time; The second jitter calculation formula is as follows: in, jitter 2 is the second jitter value; is the minimum value of the switching period, ; is the maximum value of the switching cycle, ; is the high level duration; is the average value of the switching cycle, ; and They are the current rising edge moment and the next adjacent rising edge moment respectively. , n is the total number of rising edge times and falling edge times.

2. The jitter test method of the buck circuit according to claim 1, characterized in that: The step of calculating the first jitter value of the step-down circuit in the pulse width modulation control mode according to the rising edge time, the falling edge time of the pulse width modulation waveform of the step-down circuit in the pulse width modulation control mode and the first jitter calculation formula comprises: Obtaining the rising edge time, falling edge time and switching period of the pulse width modulation waveform of the step-down circuit in the pulse width modulation control mode; According to the rising edge time and the falling edge time, the maximum value, the minimum value and the average value of the high level duration in the pulse width modulation waveform are calculated; The maximum value, the minimum value and the average value of the switching period and the high-level duration are substituted into the first jitter calculation formula to calculate the first jitter value.

3. The jitter test method of the buck circuit according to claim 2, characterized in that: The step of calculating the second jitter value of the buck circuit in constant on-time control mode according to the rising edge time, the falling edge time of the pulse width modulation waveform of the buck circuit in constant on-time control mode and the second jitter calculation formula comprises: Obtaining the rising edge time, falling edge time and high level duration of the pulse width modulation waveform of the buck circuit in constant on-time control mode; Calculate the maximum value, minimum value and average value of the switching cycle according to the rising edge time and the falling edge time; The high level duration, the maximum value, the minimum value and the average value of the switching period are substituted into the second jitter calculation formula to obtain the second jitter value.

4. The jitter test method of the buck circuit according to claim 3, characterized in that: The process of obtaining the rising edge time and the falling edge time includes: Detecting the rising edge and falling edge of the pulse width modulation waveform according to the start detection signal, starting timing when the first rising edge is detected, and timing the subsequently detected rising edges and falling edges to obtain the rising edge time and the falling edge time; When the stop detection signal is received, it is determined whether the most recent level jump is a rising edge or a falling edge; When the most recent level jump is a rising edge, the next level falling edge is timed and detection is stopped; When the most recent level transition is a falling edge, detection stops.

5. The jitter test method of the buck circuit according to claim 4, characterized in that: The method further comprises: storing the rising edge time and the falling edge time in a rolling storage manner.

6. The jitter test method of the buck circuit according to claim 5, characterized in that: The method further includes: aligning the rising edge time and the falling edge time.

7. The jitter test method of the buck circuit according to claim 1, characterized in that: The step of comparing the first jitter value with a first preset threshold value to determine the stability of the step-down circuit control system in the pulse width modulation control mode includes: When the first jitter value is greater than a first preset threshold, it is determined that the stability of the buck circuit control system does not meet the requirement; When the first jitter value is not greater than the first preset threshold, it is determined that the stability of the buck circuit control system meets the requirement.

8. The jitter testing method of a buck circuit according to claim 1, characterized in that: The step of comparing the second jitter value with a second preset threshold value to determine the stability of the buck circuit control system in the constant on-time control mode includes: When the second jitter value is greater than a second preset threshold, it is determined that the stability of the buck circuit control system does not meet the requirement; When the second jitter value is not greater than the second preset threshold, it is determined that the stability of the buck circuit control system meets the requirement.

9. A jitter test circuit for a buck circuit, characterized in that: The jitter test circuit includes: a microcontroller and a timer, the microcontroller and the timer are in communication with each other, the microcontroller stores computer instructions, and the microcontroller and the timer execute the jitter test method for the buck circuit described in any one of claims 1 to 8 by executing the computer instructions.

10. The jitter test circuit of the buck circuit according to claim 9, characterized in that: The jitter test circuit also includes: a step-down circuit control chip and a voltage divider circuit, wherein: The enable end of the microcontroller receives a test enable signal, the input end of the microcontroller is connected to the switch pin of the buck circuit control chip through the voltage divider circuit, the timing end of the microcontroller is connected to the timer, and the power supply end of the buck circuit control chip is connected to a DC power supply.

11. The jitter test circuit of the buck circuit according to claim 10, characterized in that: The voltage divider circuit includes a first resistor and a second resistor, wherein: One end of the first resistor is connected to the switch pin of the buck circuit control chip, the other end of the first resistor is respectively connected to the input end of the microcontroller and one end of the second resistor, and the other end of the second resistor is grounded.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the jitter test method for a buck circuit according to any one of claims 1 to 8.

13. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the jitter test method for a buck circuit according to any one of claims 1 to 8.

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