Adjustable voltage divider circuit and method of operation

Abstract

An embodiment of the invention provides a circuit comprising a first capacitive device connected between a first node and a second node, a second capacitive device connected between a third node and a fourth node, a first switching device connected between the first node and a voltage node, a second switching device connected between the second node and a reference voltage node, a third switching device connected between the third node and the voltage node, a fourth switching device connected between the fourth node and the reference current node, fifth to eighth switching devices connected between the respective first to fourth nodes and the output node, and first and second variable capacitance devices, the first variable capacitance device and the second variable capacitance device each include a first terminal connected to respective first and third nodes or respective second and fourth nodes. The embodiment of the invention also provides a method for operating the circuit.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to adjustable voltage divider circuits and operating methods. Background Art

[0002] In many analog and digital circuit applications, multiple voltage levels are required. To provide a given voltage level, some approaches rely on an independent target voltage in addition to the power supply and reference voltage. In other approaches, a charge pump voltage divider is used to provide a given voltage level based on the power supply and reference voltage levels, independent of the received target voltage level. Summary of the invention

[0003] An embodiment of the present invention provides a circuit, comprising: a first capacitive device connected between a first node and a second node; a second capacitive device connected between a third node and a fourth node; a first switching device connected between the first node and a voltage node; a second switching device connected between the second node and a reference voltage node; a third switching device connected between the third node and the voltage node; a fourth switching device connected between the fourth node and the reference voltage node; a fifth switching device to an eighth switching device connected between the corresponding first node to the fourth node and an output node; and a first variable capacitive device and a second variable capacitive device, comprising a first terminal connected to the corresponding first node and the third node or the corresponding second node and the fourth node.

[0004] Another embodiment of the present invention provides a circuit, comprising: a first capacitive device connected between a first node and a second node; a second capacitive device connected between a third node and a fourth node; a first switching device connected between the first node and a voltage node; a second switching device connected between the second node and a reference voltage node; a third switching device connected between the third node and the voltage node; a fourth switching device connected between the fourth node and the reference voltage node; a fifth switching device to an eighth switching device connected between the corresponding first node to the fourth node and an output node; and a first variable capacitive device and a second variable capacitive device connected between the output node and the corresponding first node and the third node or the corresponding second node and the fourth node.

[0005] Another embodiment of the present invention provides a method of operating a circuit, the method comprising: receiving an input voltage at a voltage node of the circuit, the circuit further comprising: a first capacitive device connected between a first node and a second node; a second capacitive device connected between a third node and a fourth node; a first switching device connected between the first node and the voltage node; a second switching device connected between the second node and a reference voltage node; a third switching device connected between the third node and the voltage node; a fourth switching device connected between the fourth node and the reference voltage node; a fifth switching device to an eighth switching device connected between the corresponding first node to the fourth node and an output node; and a first variable capacitive device and a second variable capacitive device, comprising a first terminal connected to the corresponding first node and the third node or the corresponding second node and the fourth node; and alternately switching the second switching device, the third switching device, the fifth switching device and the eighth switching device with the first switching device, the fourth switching device, the sixth switching device and the seventh switching device, thereby generating an output voltage on the output node BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1C is a schematic diagram of an adjustable voltage divider circuit according to some embodiments.

[0008] Figure 1D is a schematic diagram of operating parameters of an adjustable voltage divider circuit according to some embodiments.

[0009] FIG. 2A to FIG. 2C is a schematic diagram of an adjustable voltage divider circuit according to some embodiments.

[0010] Figure 2D is a schematic diagram of operating parameters of an adjustable voltage divider circuit according to some embodiments.

[0011] Figure 3 is a schematic diagram of operating parameters of an adjustable voltage divider circuit according to some embodiments.

[0012] Figure 4 is a schematic diagram of a variable capacitance device according to some embodiments.

[0013] Figure 5 is a flow chart of a method of operating an adjustable voltage divider circuit according to some embodiments. DETAILED DESCRIPTION

[0014] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] In various embodiments, an adjustable voltage divider circuit and method include: a capacitive device connected between a first and a second node and between a third and a fourth node; a switching device connected between each of the first and third nodes and a voltage node, between each of the second and fourth nodes and a reference node, and between each of the first to fourth nodes and an output node; and a variable capacitive device, the variable capacitive device including a first terminal connected to the first node or the third node or to the second node or the fourth node and a second terminal connected to the output node or the reference node. The switching device is configured to alternately switch the order of the capacitive devices, thereby generating an output voltage by dividing the voltage difference between the voltage and reference nodes.

[0017] By thus including a variable capacitance device configured to share charge with a capacitive device, the circuit is able to generate an output voltage having an adjustable value based on the voltage difference and the value of the variable capacitance device. Compared to other methods, for example, a voltage divider circuit that does not include a variable capacitance device or a series regulator circuit, the circuit is therefore able to generate an adjustable output voltage value without relying on a target voltage or discharge circuit that is independently powered.

[0018] Figures 1A to 1C and FIG. 2A to FIG. 2CEach of the diagrams is a schematic diagram of some or all of the adjustable voltage divider circuits 100, 100S, 200, or 200S according to some embodiments. In some embodiments, the adjustable voltage divider circuits 100, 100S, 200, and 200S are also referred to as circuits 100, 100S, 200, and 200S, voltage dividers 100, 100S, 200, and 200S, or charge pump voltage dividers 100, 100S, 200, and 200S.

[0019] In some embodiments, one or more of the circuits 100, 100S, 200 or 200S are some or all of an integrated circuit (IC). In some embodiments, one or more of the circuits 100, 100S, 200 or 200S are included in another IC circuit, such as a digital circuit, an analog circuit and / or a memory circuit.

[0020] Each of the circuits 100, 100S, 200, and 200S includes a voltage node Nvdd and a reference voltage node Nvss. The voltage node Nvdd, also referred to as a power supply voltage node Nvdd in some embodiments, includes one or more conductive paths configured to distribute a voltage Vdd, also referred to as a power supply voltage Vdd in some embodiments. In some embodiments, the voltage Vdd is the voltage of a power domain including the circuits 100, 100S, 200, and / or 200S, and has a level of the power domain.

[0021] The reference voltage node Nvss, also referred to as a reference node Nvs or a ground node Nvss in some embodiments, includes one or more conductive paths configured to distribute a reference voltage Vss, which is also referred to as a ground Vss or a ground voltage Vss in some embodiments. In some embodiments, the reference voltage Vss is a reference voltage of a power domain including the circuits 100, 100S, 200, and / or 200S, and has a reference voltage level of the power domain.

[0022] like Figures 1A to 1C and FIG. 2A to FIG. 2C As shown, each of the circuits 100 , 100S, 200 , and 200S further includes nodes N1 to N4 , an output node OUT, switching devices S1 to S8 , capacitance devices C0 to C2 , and variable capacitance devices Ca and Cb.

[0023] For illustration purposes, Figures 1A to 1C and FIG. 2A to FIG. 2C In some embodiments, one or more of the circuits 100, 100S, 200, or 200S may be simplified. Figures 1A to 1C and FIG. 2A to FIG. 2CIn addition to the components shown in the figure, other components are included, for example, one or more control and / or clock circuits, configured to generate one or more control and / or clock signals, and / or one or more control or clock signal paths, which are connected to the control terminals of switches S1 to S8 and / or variable capacitor elements Ca and Cb and are configured to propagate one or more control and / or clock signals.

[0024] The switching device S1 is connected between the node N1 and the voltage node Nvdd, the switching device S2 is connected between the node N2 and the reference voltage node Nvss, the switching device S3 is connected between the node N3 and the voltage node Nvdd, the switching device S4 is connected between the node N4 and the reference voltage node Nvss, and the switching device S5 to the switching device S8 are connected between the corresponding nodes N1 to N4 and the output node OUT.

[0025] The capacitive device C0 is connected between the output node OUT and the reference voltage node Nvss, the capacitive device C1 is connected between the nodes N1 and N2, and the capacitive device C2 is connected between the nodes N3 and N4.

[0026] like Figure 1A and Figure 1B As shown, the circuit 100 includes variable capacitance devices Ca and Cb connected between respective nodes N2 and N4 and an output node OUT. Figure 1C As shown, the circuit 100S includes shunting means of variable capacitance devices Ca and Cb connected between respective nodes N1 and N3 and a reference voltage node Nvss.

[0027] like Figure 2A and Figure 2B As shown, the circuit 200 includes variable capacitance devices Ca and Cb connected between corresponding nodes N1 and N3 and the output node OUT. Figure 2C As shown, the circuit 200S includes shunting means of variable capacitance devices Ca and Cb connected between corresponding nodes N2 and N4 and a reference voltage node Nvss.

[0028] A connection of two or more circuit elements is considered to be an electrical connection based on a direct electrical connection or including one or more additional circuit element connections, thereby being controllable (eg, made resistive or open circuit) by one or more transistors or other switching devices.

[0029] The switch device, such as the switch device S1 to the switch device S8, is an electronic or electromechanical device, such as an IC device, configured to provide a resistive path or an open circuit between two path terminals (not labeled) in response to one or more signals received at one or more control terminals (not shown). In some embodiments, the switch device includes an n-type or p-type transistor, a transmission gate, etc.

[0030] Capacitive devices, such as capacitive devices C0 to C2, are electronic devices, such as IC devices, configured to provide a predetermined capacitance level between two terminals (not labeled). In some embodiments, the capacitive devices include metal-insulator-metal (MIM) capacitors, n-type or p-type transistors configured as capacitors, etc.

[0031] A variable capacitance device, such as a variable capacitance device Ca or Cb, is an electronic or electromechanical device, such as an IC device, configured to provide a plurality of predetermined capacitance levels between two terminals (not labeled) in response to one or more signals received at one or more control terminals (not shown). In some embodiments, the variable capacitance device includes a single configurable capacitance device or an arrangement of multiple capacitance devices and a switching device. In some embodiments, the variable capacitance device includes the following reference Figure 4 A variable capacitance device 400 is discussed.

[0032] Each of the circuits 100 , 100S, 200 and 200S is configured to control the switching devices S1 to S8 in operation, whereby the switching devices S1 , S4 , S6 and S7 are alternately turned on and off together with the switching devices S2 , S3 , S5 and S8 .

[0033] Figure 1A , Figure 1C , Figure 2A and Figure 2C Each of illustrative embodiments depicts a first state of the respective circuit 100 , 100S, 200 , or 200S, wherein each of the switching devices S1 , S4 , S6 , and S7 is closed, and each of the switching devices S2 , S3 , S5 , and S8 is open. Figure 1B and Figure 2B Each of illustrative embodiments depicts a second state of the corresponding circuit 100 or 200, wherein each of the switching devices S1, S4, S6 and S7 is open and each of the switching devices S2, S3, S5 and S8 is closed.

[0034] In the first state, the capacitive device C1 is thus configured to be connected between the voltage node Nvdd and the output node OUT through the switching devices S1 and S6, and the capacitive device C2 is thus configured to be connected between the output node OUT and the reference voltage node Nvss through the switching devices S7 and S4. In operation, the first state thus corresponds to a first voltage divider arrangement, in which the capacitive devices C1 and C2 are connected in series in a first order between the voltage node Nvdd and the reference voltage node Nvss, and the output node OUT is connected to the respective first terminals of the capacitive devices C1 and C2.

[0035] In the second state, the capacitive device C2 is thus configured to be connected between the voltage node Nvdd and the output node OUT through the switching devices S3 and S8, and the capacitive device C1 is thus configured to be connected between the output node OUT and the reference voltage node Nvss through the switching devices S5 and S2. In operation, the second state thus corresponds to a second voltage divider arrangement, in which the capacitive devices C1 and C2 are connected in series in a second order between the voltage node Nvdd and the reference voltage node Nvss, and the output node OUT is connected to the respective second terminals of the capacitive devices C2 and C1.

[0036] In operation, when the corresponding circuit 100, 100S, 200 or 200S alternates between the first and second states, the capacitive device C0 connected between the output node OUT and the reference voltage node Nvss maintains the voltage level of the output voltage Vout on the output node OUT by storing charge on the output node OUT.

[0037] In some embodiments, in order to be able to maintain the voltage level of the output voltage Vout, the capacitance value of the capacitive device C0 is at least one order of magnitude greater than one or more capacitance values ​​of the capacitive devices C1 and C2 .

[0038] Therefore, each of the circuits 100, 100S, 200 and 200S includes switching devices S1 to S8, which are configured to alternately switch the order of capacitive devices C1 and C2 in operation, thereby generating an output voltage Vout by dividing the voltage difference between the voltage Vdd and the reference voltage Vss.

[0039] Without variable capacitive devices Ca and Cb, each of circuits 100, 100S, 200 and 200S is thus configured to generate an output voltage Vout having a default fractional value of the voltage difference based on the capacitance values ​​of capacitive devices C1 and C2 and the duty cycle of the first and second states.

[0040] In some embodiments, one or more of the circuits 100 , 100S, 200 , or 200S are configured to generate an output voltage Vout having a default fractional value equal to ½ Vdd (relative to voltage Vss).

[0041] In some embodiments, one or more of the circuits 100 , 100S, 200 , or 200S include capacitive devices C1 and C2 configured to have the same capacitance value or unequal capacitance values.

[0042] In some embodiments, one or more of circuits 100, 100S, 200 or 200S is configured to alternate between the first and second states based on a 50% (%) duty cycle (e.g., relative to one of the first and second states, based on one or more clock signals having a duty cycle of 50%, or based on a duty cycle greater than 50%).

[0043] like Figure 1A As shown, in the first state of the circuit 100, the closing of the switching device S6 causes the node N2 to be connected to the output node OUT, thereby connecting the two end terminals of the variable capacitor device Ca to each other, and the combination of the closing of the switching device S7 and the opening of the switching device S8 causes the variable capacitor device Cb to be connected in parallel with the capacitive device C2 between the output node OUT and the reference voltage node Nvss.

[0044] like Figure 1B As shown, in the second state of the circuit 100, the combination of the closing of the switching device S5 and the opening of the switching device S6 causes the variable capacitor device Ca to be connected in parallel with the capacitive device C1 between the output node OUT and the reference voltage node Nvss, and the closing of the switching device S8 causes the node N4 to be connected to the output node OUT, thereby connecting the two end terminals of the variable capacitor device Cb to each other.

[0045] Therefore, the circuit 100 is configured to selectively connect each of the variable capacitance devices Ca and Cb in parallel with the corresponding capacitance device C1 or C2 during the corresponding first or second state in operation, in which the corresponding capacitance device C1 or C2 is connected between the output node OUT and the reference voltage node Nvss, otherwise the variable capacitance devices Ca and Cb become meaningless based on the connection of their two end terminals together. Therefore, compared with the total capacitance between the output node OUT and the voltage node Nvdd, the total capacitance between the output node OUT and the reference voltage node Nvss is selectively increased, so that the value of the output voltage Vout is reduced compared with the default fractional value (e.g., 1 / 2Vdd).

[0046] The amount of reduction in the value of the output voltage Vout is a function of the capacitance value of each of the capacitive devices C1 and C2 and the variable capacitive devices Ca and Cb. In some embodiments, each of the variable capacitive devices Ca and Cb has a capacitance value of the same order of magnitude as one or more capacitance values ​​of the capacitive devices C1 and C2. In some embodiments, the variable capacitive devices Ca and Cb have the same capacitance value or unequal capacitance values.

[0047] In an embodiment where each of the capacitive devices C1 and C2 has the same capacitance value C12 and each of the variable capacitor devices Ca and Cb has the same capacitance value Cab, the balance of electrostatic energy in the first and second states of the circuit 100 is represented by the following equation:

[0048] 1 / 2C12*(Vdd - Vout) 2 =1 / 2(C12 + Cab)*Vout 2 (1)

[0049] By representing the fractional value of the output voltage Vout with respect to the voltage Vdd as x (0 < x < 0.5), Vout = x*Vdd, the approximate value of Cab with respect to C12 is given by the following equation:

[0050] Cab=[(1 - 2x) / x 2 *C12(2)

[0051] In this non - restrictive example, an output voltage Vout having a value equal to 0.45*Vdd (x = 0.45) thus corresponds to Cab = 0.494*C12, while an output voltage Vout having a value equal to 0.40*Vdd (x = 0.40) thus corresponds to Cab = 1.25*C12.

[0052] As Figure 1C shown, in the first state of the circuit 100S, the closing of the switch device S1 causes the node N1 to be connected to the voltage node Nvdd, thereby causing the first series arrangement of the capacitive devices C1 and C2 between the variable capacitor device Ca and the voltage node Nvdd and the reference voltage node Nvss to be connected in parallel. The closing of the switch device S7 causes the node N3 to be connected to the output node OUT, and the variable capacitor device Cb is connected in parallel with the capacitive device C2 between the output node OUT and the reference voltage node Nvss.

[0053] Similarly, in the second state (not shown) of the circuit 100S, the closing of the switch device S3 causes the node N3 to be connected to the voltage node Nvdd, thereby causing the second series arrangement of the capacitive devices C1 and C2 between the variable capacitor device Cb and the voltage node Nvdd and the reference voltage node Nvss to be connected in parallel. The closing of the switch device S5 causes the node N1 to be connected to the output node OUT, and the variable capacitor device Ca is connected in parallel with the capacitive device C2 between the output node OUT and the reference voltage node Nvss.

[0054] The circuit 100S is thus configured to selectively connect each of the variable capacitive devices Ca and Cb in parallel with the corresponding capacitive device C1 or C2 during the respective first or second states in operation, in which the respective capacitive device C1 or C2 is connected between the output node OUT and the reference voltage node Nvss, otherwise connected between the respective series arrangements of the capacitive devices C1 and C2. Thus, the total capacitance between the output node OUT and the reference voltage node Nvss is selectively increased compared to the total capacitance between the output node OUT and the voltage node Nvdd, so that the value of the output voltage Vout is reduced compared to a default fractional value (e.g., 1 / 2 Vdd).

[0055] Circuit 100S is less efficient than circuit 100 based on variable capacitance elements Ca and Cb being connected in parallel with the series arrangement of capacitive elements C1 and C2 rather than variable capacitance elements Ca and Cb being connected together in vain.

[0056] In each of the circuits 100 and 100S, the amount of reduction in the Vout value compared to the default fractional value is adjustable based on the capacitance value of the variable capacitance device Ca and / or Cb. In some embodiments, the circuit 100 or 100S includes a measurement circuit, a control circuit, or other circuit (not shown) configured to monitor or receive an indication of the value of the output voltage Vout and adjust the capacitance value of the variable capacitance device Ca and / or Cb based on the measured value, thereby adjusting the amount of reduction in the output voltage Vout value compared to the default fractional value.

[0057] The circuits 100 and 100S are configured to reduce the value of the output voltage Vout compared to the default fractional value by selectively and adjustably increasing the total capacitance between the output node OUT and the reference voltage node Nvss compared to the total capacitance between the output node OUT and the voltage node Nvdd, which is a non-limiting example. Other configurations in which the total capacitance between the output node OUT and the reference voltage node Nvss is selectively and adjustably increased compared to the total capacitance between the output node OUT and the voltage node Nvdd are also within the scope of the present disclosure.

[0058] Figure 1D Operational parameters of circuits 100 and 100S according to some embodiments are described. Figure 1D Includes voltage Vdd, reference voltage Vss, and output voltage Vout plotted against time t.

[0059] like Figure 1D As shown, as the capacitive device C0 charges in response to the first and second states alternating with time t, the output voltage Vout increases from an initial value equal to the reference voltage Vss and increases to a steady-state value.

[0060] exist Figure 1D In the non-limiting example shown, the alternating first and second states have a 50% duty cycle, and the steady-state value of the output voltage Vout is less than or equal to a default fractional value of ½ Vdd.

[0061] like Figure 2A As shown, in the first state of the circuit 200, the combination of the closing of the switching device S6 and the opening of the switching device S5 causes the variable capacitor device Ca to be connected in parallel with the capacitive device C1 between the voltage node Nvdd and the output node OUT, and the closing of the switching device S7 causes the node N3 to be connected to the output node OUT, thereby connecting the two end terminals of the variable capacitor device Cb to each other.

[0062] like Figure 2B As shown, in the second state of the circuit 200, the closing of the switching device S5 causes the node N1 to be connected to the output node OUT, thereby connecting the two end terminals of the variable capacitor device Ca to each other, and the combination of the closing of the switching device S8 and the opening of the switching device S7 causes the variable capacitor device Cb to be connected in parallel with the capacitive device C2 between the voltage node Nvdd and the output node OUT.

[0063] Therefore, the circuit 200 is configured to selectively connect each of the variable capacitance devices Ca and Cb in parallel with the corresponding capacitive device C1 or C2 during the corresponding first or second state in operation, in which the corresponding capacitive device C1 or C2 is connected between the voltage node Nvdd and the output node OUT, otherwise the variable capacitance devices Ca and Cb become meaningless based on the connection of their two end terminals together. Therefore, compared with the total capacitance between the output node OUT and the reference voltage node Nvss, the total capacitance between the voltage node Nvdd and the output node OUT is selectively increased, so that the value of the output voltage Vout is increased compared with the default fractional value (e.g., 1 / 2Vdd).

[0064] The amount of increase in the value of the output voltage Vout is a function of the capacitance value of each of the capacitive devices C1 and C2 and the variable capacitive devices Ca and Cb. In some embodiments, each of the variable capacitive devices Ca and Cb has a capacitance value of the same order of magnitude as one or more capacitance values ​​of the capacitive devices C1 and C2. In some embodiments, the variable capacitive devices Ca and Cb have the same capacitance value or unequal capacitance values.

[0065] In an embodiment where each of the capacitive devices C1 and C2 has the same capacitance value C12 and each of the variable capacitance devices Ca and Cb has the same capacitance value Cab, the balance of electrostatic energy in the first and second states of the circuit 200 is represented by:

[0066] 1 / 2(C12 + Cab)*(Vdd - Vout) 2 =1 / 2C12*Vout 2

[0067] By expressing the fractional value of the output voltage Vout relative to the voltage Vdd as x (0.5 < x < 1.0), Vout = x*Vdd. Thus, the approximate value of Cab relative to C12 is given by:

[0068] Cab = [(2x - 1) / (1 - x) 2 *C12(4)

[0069] In this non - limiting example, an output voltage Vout having a value equal to 0.55*Vdd (x = 0.55) thus corresponds to Cab = 0.494*C12, and an input voltage Vout having a value equal to 0.60*Vdd (x = 0.60) thus corresponds to Cab = 1.25*C12.

[0070] As Figure 2C shown, in the first state of circuit 200S, the closing of switch device S6 causes node N2 to be connected to the output node OUT, thereby causing the variable capacitor device Ca to be connected in parallel with the capacitive device C2 between the output node OUT and the reference voltage node Nvss. The closing of switch device S4 causes node N4 to be connected to the reference voltage node Nvss, thereby connecting the two terminals of the variable capacitor device Cb to each other.

[0071] Similarly, in the second state (not shown) of circuit 200S, the closing of switch device S2 causes node N2 to be connected to the reference voltage node Nvss, thereby connecting the two terminals of the variable capacitor device Ca to each other. The closing of switch device S8 causes node N4 to be connected to the output node OUT, thereby causing the variable capacitor device Cb to be connected in parallel with the capacitive device C1 between the output node OUT and the reference voltage node Nvss.

[0072] Circuit 200S is thus configured such that, in operation, during the respective first or second state, each of the variable capacitor devices Ca and Cb is selectively connected in series with the respective capacitive device C1 or C2. In these states, the respective capacitive device C1 or C2 is connected between the output node OUT and the reference voltage node Nvss. Otherwise, the variable capacitor devices Ca and Cb become meaningless based on their connected terminals. Thus, the total capacitance between the voltage node Nvdd and the reference voltage node Nvss is selectively reduced, such that the value of the output voltage Vout increases compared to the default fractional value (e.g., 1 / 2Vdd).

[0073] Compared to the circuit 200 , the circuit 200S has a lower efficiency based on that both end terminals of the variable capacitance elements Ca and Cb are connected together at the reference voltage node instead of at the output voltage node.

[0074] In each of the circuits 200 and 200S, the amount of increase in the value of Vout compared to the default fractional value is adjustable based on the capacitance values ​​of the variable capacitance devices Ca and Cb. In some embodiments, the circuit 200 or 200S includes a measurement circuit, a control circuit, or other circuit (not shown) configured to monitor or receive an indication of the value of the output voltage Vout and adjust the capacitance values ​​of the variable capacitance devices Ca and / or Cb based on the measured value, thereby adjusting the amount of increase in the value of the output voltage Vout compared to the default fractional value.

[0075] The circuits 200 and 200S are configured to increase the value of the output voltage Vout compared to a default fractional value by selectively and adjustably increasing the total capacitance between the voltage node Nvdd and the output node OUT or reducing the total capacitance between the voltage node Nvdd and the reference voltage node Nvss compared to the total capacitance between the output node OUT and the reference voltage node Nvss, and these circuits are non-limiting examples. Other configurations in which the total capacitance between the voltage node Nvdd and the output node OUT is selectively and adjustably increased, or the total capacitance between the voltage node Nvdd and the reference voltage node Nvss is selectively and adjustably reduced, compared to the total capacitance between the output node OUT and the reference voltage node Nvss, are also within the scope of the present disclosure.

[0076] Figure 2D Operational parameters of circuits 200 and 200S are depicted according to some embodiments. Figure 2D Includes voltage Vdd, reference voltage Vss, and output voltage Vout plotted against time t.

[0077] like Figure 2D As shown, as the capacitive device C0 charges in response to the first and second states alternating with time t, the output voltage Vout increases from an initial value equal to the reference voltage Vss and increases to a steady-state value.

[0078] exist Figure 2D In the non-limiting example shown, the alternating first and second states have a 50% duty cycle, and the steady-state value of the output voltage Vout is greater than a default fractional value equal to ½ Vdd.

[0079] Figure 3 Operational parameters of circuits 100 , 100S, 200 , and 200S are depicted according to some embodiments. Figure 3 The output voltage Vout reaches a steady-state value over time t in three cases.

[0080] In Figure 3 In the non - limiting example shown, the first case corresponds to circuits 100 and 100S, where 0.0 < x < 0.5 and the steady - state value is less than the default fractional value 1 / 2Vdd. The second case shows a steady - state value equal to the default fractional value 1 / 2Vdd. The third case corresponds to circuits 200 and 200S, where 0.5 < x < 1.0 and the steady - state value is greater than the default fractional value 1 / 2Vdd.

[0081] With the above configuration, each of circuits 100, 100S, 200, and 200S is an adjustable voltage - divider circuit, including capacitive devices C1 and C2 connected between nodes N1 and N2 and between nodes N3 and N4, switching devices S1 to S8 connected between nodes N1 and N3 and the voltage node Nvdd, between nodes N2 and N4 and the reference - voltage node Nvss, and between nodes N1 to N4 and the output node OUT, and variable capacitor devices Ca and Cb including a first terminal connected to nodes N1 and N3 or N2 and N4 and a second terminal connected to the output node OUT or the reference - voltage node Nvss.

[0082] Because the switching devices S1 to S8 are configured to alternately switch the order of the capacitive devices C1 and C2, including the variable capacitor devices Ca and Cb configured as described above, each of circuits 100, 100S, 200, and 200S is capable of generating an output voltage Vout with an adjustable value based on the voltage Vdd, the reference voltage Vss, and the values of the variable capacitor devices Ca and Cb. Compared with other methods, for example, a voltage - divider circuit that does not include variable capacitor devices or a series - regulator circuit, circuits 100, 100S, 200, and 200S can thus generate an adjustable output - voltage value without relying on an independent target voltage or a discharge circuit.

[0083] Figure 4 is a schematic diagram of a variable capacitor device 400 according to some embodiments. The variable capacitor device 400 can be used as one or both of the variable capacitor devices Ca or Cb discussed above with respect to Figures 1A to 3 discussion.

[0084] As Figure 4 shown, the variable capacitor device 400 includes nodes N5 and N6, switching devices S9 to S12, and capacitor devices C3 to C6. The switching devices S9 to S12 and the corresponding capacitor devices C3 to C6 are connected in series between nodes N5 and N6, and each of the switching devices S9 to S12 includes a control terminal (not shown) that is configured to receive a control signal that is configured to place the corresponding one of the switching devices S9 to S12 in an open or closed state during operation.

[0085] exist Figure 4 In the illustrated embodiment, the variable capacitor device 400 includes a total of four switching devices S9 to S12 arranged in series and capacitor devices C3 to C6 connected in parallel between nodes N5 and N6. In various embodiments, the variable capacitor device 400 includes a total of less than or more than four switching devices arranged in series and capacitor devices connected in parallel between nodes N5 and N6.

[0086] In some embodiments, the capacitive devices, such as capacitive devices C3 to C6 , have the same or different capacitance values.

[0087] In operation, the total capacitance value of variable capacitive device 400 is the sum of the capacitance values ​​of instances of capacitive devices (eg, capacitive devices C3 to C6) connected in series with instances of switching devices (eg, switching devices S9 to S12) in a closed state.

[0088] Thus, the circuit 100 , 100S, 200 , or 200S including the variable capacitance device 400 as one or both of the variable capacitance devices Ca or Cb can achieve the benefits discussed above with respect to the circuits 100 , 100S, 200 , and 200S.

[0089] Figure 5 5 is a flow chart of a method 500 of operating a circuit according to some embodiments. The method 500, also referred to in some embodiments as a method 500 of generating an output voltage, may be used in an adjustable voltage divider circuit, such as described above with respect to Figures 1A to 4 The circuit 100, 100S, 200 or 200S in question.

[0090] Figure 5 The order in which the operations of method 500 are described is for illustration only; the operations of method 500 may be performed in any order. Figure 5 In some embodiments, Figure 5 Perform the following operations before, between, during, and / or after the operations shown: Figure 5 In some embodiments, the operations of method 500 are a subset of a method of operating a digital or analog circuit (eg, a memory circuit).

[0091] At operation 502, an input voltage is received at a voltage node. The voltage node is included in a circuit that also includes a first capacitive device connected between a first and a second node, a second capacitive device connected between a third and a fourth node, a first switching device connected between the first node and the voltage node, a second switching device connected between the second node and a reference voltage node, a third switching device connected between the third node and the voltage node, a fourth switching device connected between the fourth node and the reference voltage node, fifth to eighth switching devices connected between the respective first to fourth nodes and an output node, and a first variable capacitive device and a second variable capacitive device including first terminals connected to the respective first and third nodes or the respective second and fourth nodes.

[0092] In some embodiments, as described above with respect to Figures 1A to 4 As described, receiving the input voltage at the voltage node includes receiving the voltage Vdd at the voltage node Nvdd and receiving the reference voltage Vss at the reference voltage node Nvss.

[0093] At operation 504, an output voltage is generated by alternately switching the order of a pair of capacitive devices, wherein each capacitive device is connected to a variable capacitor device, thereby dividing the input voltage. In some embodiments, generating the output voltage includes generating the output voltage Vout by alternately switching the order of capacitive devices C1 and C2 connected to the corresponding variable capacitor device Ca or Cb, thereby dividing Vdd relative to the reference voltage Vss, as described above with respect to Figures 1A to 4 discussed.

[0094] In some embodiments, the sequence of alternately switching the pair of capacitive devices includes alternately switching the second, third, fifth, and eighth switching devices with the first, fourth, sixth, and seventh switching devices.

[0095] In some embodiments, alternately switching the second, third, fifth, and eighth switching devices with the first, fourth, sixth, and seventh switching devices includes alternately connecting the output node to the reference node through a first parallel arrangement of a first capacitive device and a first variable capacitive device or a second parallel arrangement of a second capacitive device and a second variable capacitive device, for example, as described above with respect to circuits 100 and Figures 1A to 1D , Figure 3 and Figure 4 described.

[0096] In some embodiments, alternately switching the second, third, fifth, and eighth switching devices with the first, fourth, sixth, and seventh switching devices includes alternately connecting the output node to the voltage node through a first parallel arrangement of a first capacitive device and a first variable capacitive device or a second parallel arrangement of a second capacitive device and a second variable capacitive device, for example, as described above with respect to circuits 200 and Figures 2A to 4 described.

[0097] In some embodiments, generating the output voltage includes setting one or more values ​​of the variable capacitance device, for example, as described above with respect to the variable capacitance devices Ca, Cb, and 400 and Figures 1A to 4 described.

[0098] At operation 506, in some embodiments, the output voltage is measured. In some embodiments, measuring the output voltage includes measuring the output voltage as described above. Figures 1A to 4 Discuss the output voltage Vout.

[0099] At operation 508 , in some embodiments, the output voltage is adjusted by adjusting the capacitance value of one or both variable capacitive devices. In some embodiments, adjusting the output voltage is responsive to the value of the output voltage measured at operation 506 .

[0100] In some embodiments, as described above with respect to Figures 1A to 4 As described above, adjusting the capacitance value of one or both variable capacitance devices includes adjusting the capacitance value of one or both variable capacitance devices Ca or Cb.

[0101] In some embodiments, adjusting the capacitance value of one or both variable capacitors includes changing the number of capacitors arranged in parallel, for example, changing the number of capacitors C3 to C6 of the variable capacitor 400 arranged in parallel, as described above with respect to Figure 4 discussed.

[0102] By performing some or all of the operations of method 500 , the circuit generates an output voltage having an adjustable value based on input and reference voltages and the value of the variable capacitance device, thereby achieving the benefits discussed above with respect to circuits 100 , 100S, 200 , and 200S.

[0103] In some embodiments, a circuit includes a first capacitive device connected between a first and a second node, a second capacitive device connected between a third and a fourth node, a first switching device connected between the first node and a voltage node, a second switching device connected between the second node and a reference voltage node, a third switching device connected between the third node and the voltage node, a fourth switching device connected between the fourth node and the reference voltage node, and a fifth to eighth switching device connected between the corresponding first to fourth nodes and an output node, and the first and second variable capacitors include first terminals connected to the corresponding first and third nodes or the corresponding second and fourth nodes. In some embodiments, the first terminals of the first and second variable capacitors are connected to the corresponding second and fourth nodes, and each of the first and second variable capacitors includes a second terminal connected to the output node. In some embodiments, the first terminals of the first and second variable capacitors are connected to the corresponding first and third nodes, and each of the first and second variable capacitors includes a second terminal connected to the output node. In some embodiments, each of the first and second variable capacitors includes a second terminal connected to the reference voltage node. In some embodiments, the first, fourth, sixth, and seventh switching devices are configured to be turned on and off alternately with the second, third, fifth, and eighth switching devices. In some embodiments, the duty cycle of the first, fourth, sixth and seventh switching devices that are alternately turned on and off with the second, third, fifth and eighth switching devices is about 50%. In some embodiments, the first and second capacitive devices are configured to have the same capacitance value. In some embodiments, the first and second variable capacitor devices are configured to have the same variable capacitance value. In some embodiments, each of the first and second variable capacitor devices includes a parallel arrangement of a capacitor device connected in series with the switching device. In some embodiments, the circuit includes a third capacitive device connected between the output node and the reference voltage node.

[0104] In some embodiments, a circuit includes a first capacitive device connected between a first and a second node, a second capacitive device connected between a third and a fourth node, a first switching device connected between the first node and a voltage node, a second switching device connected between the second node and a reference voltage node, a third switching device connected between the third node and the voltage node, a fourth switching device connected between the fourth node and the reference voltage node, a fifth to an eighth switching device connected between the corresponding first to fourth nodes and an output node, and a first and a first variable capacitive device connected between the output node and the corresponding first and third nodes or the corresponding second and fourth nodes. In some embodiments, the first to the eighth switching devices are configured to alternately connect the output node to the reference node through a first parallel arrangement of the first capacitive device and the first variable capacitive device or a second parallel arrangement of the second capacitive device and the second variable device capacitive device. In some embodiments, the first to the eighth switching devices are configured to alternately connect the output node to the voltage node through a first parallel arrangement of the first capacitive device and the first variable capacitive device or a second parallel arrangement of the second capacitive device and the second variable device capacitive device. In some embodiments, the first and second capacitive devices are configured to have the same capacitance value, the first and second variable capacitive devices are configured to have the same variable capacitance value, and the same capacitance value and the same variable capacitance value have the same order of magnitude. In some embodiments, the circuit includes a third capacitive device connected between the output node and the reference voltage node, wherein the capacitance value of the third capacitive device is at least one order of magnitude greater than the capacitance values ​​of the first and second capacitive devices and the first and third variable capacitive devices.

[0105] In some embodiments, a method of operating a circuit includes receiving an input voltage at a voltage node of the circuit, the circuit including a first capacitive device connected between a first and a second node, a second capacitive device connected between a third and a fourth node, a first switching device connected between the first node and the voltage node, a second switching device connected between the second node and a reference voltage node, a third switching device connected between the third node and the voltage node, a fourth switching device connected between the fourth node and the reference voltage node, fifth to eighth switching devices connected between the respective first to fourth nodes and an output node, and a first variable capacitive device and a second variable capacitive device including first terminals connected to the respective first and third nodes or the respective second and fourth nodes, and alternately switching the second, third, fifth, and sixth switching devices with the first, fourth, sixth, and seventh switching devices to generate an output voltage at the output node. In some embodiments, alternately switching the second, third, fifth, and eighth switching devices with the first, fourth, sixth, and seventh switching devices includes alternately connecting the output node to the reference node through a first parallel arrangement of the first capacitive device and the first variable capacitive device or a second parallel arrangement of the second capacitive device and the second variable capacitive device. In some embodiments, alternatingly switching the first, fourth, sixth, and seventh switching devices with the second, third, fifth, and eighth switching devices includes alternately connecting the output node to the voltage node through a first parallel arrangement of a first capacitive device and a first variable capacitive device or a second parallel arrangement of a second capacitive device and a second variable capacitive device. In some embodiments, the method includes measuring the output voltage and adjusting the capacitance value of each variable capacitive device in response to the measured output voltage. In some embodiments, adjusting the capacitance value of each variable capacitive device includes changing the number of capacitive devices arranged in parallel.

[0106] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit comprising: a first capacitive device connected between the first node and the second node; a second capacitive device connected between the third node and the fourth node; A first switching device connected between the first node and a voltage node; a second switch device connected between the second node and a reference voltage node; a third switching device connected between the third node and the voltage node; a fourth switch device connected between the fourth node and the reference voltage node; fifth to eighth switching devices connected between the corresponding first to fourth nodes and an output node; as well as The first variable capacitance device and the second variable capacitance device include first terminals connected to the respective first and third nodes or the respective second and fourth nodes.

2. The circuit according to claim 1, wherein middle, The first terminals of the first variable capacitive element and the second variable capacitive element are connected to the second node and the fourth node, respectively, and Each of the first variable capacitance device and the second variable capacitance device includes a second terminal connected to the output node.

3. The circuit according to claim 1, wherein: The first terminals of the first variable capacitive element and the second variable capacitive element are connected to the corresponding first node and the third node, and Each of the first variable capacitance device and the second variable capacitance device includes a second terminal connected to the output node.

4. The circuit according to claim 1, wherein: Each of the first variable capacitance device and the second variable capacitance device includes a second terminal connected to the reference voltage node.

5. The circuit according to claim 1, wherein: The first, fourth, sixth, and seventh switching devices are configured to be turned on and off alternately with the second, third, fifth, and eighth switching devices.

6. The circuit according to claim 5, wherein: The duty ratio of the first, fourth, sixth and seventh switching devices, which are alternately turned on and off with the second, third, fifth and eighth switching devices, is 50%.

7. A circuit comprising: a first capacitive device connected between the first node and the second node; a second capacitive device connected between the third node and the fourth node; A first switching device connected between the first node and a voltage node; a second switch device connected between the second node and a reference voltage node; a third switching device connected between the third node and the voltage node; a fourth switch device connected between the fourth node and the reference voltage node; fifth to eighth switching devices connected between the corresponding first to fourth nodes and an output node; as well as A first variable capacitance device and a second variable capacitance device are connected between the output node and the first node and the third node respectively or between the second node and the fourth node respectively.

8. The circuit according to claim 7, wherein: The first to eighth switching devices are configured to alternately connect the output node to the reference node in the following manner: a first parallel arrangement of the first capacitive device and the first variable capacitive device, or A second parallel arrangement of the second capacitive device and the second variable capacitive device.

9. A method of operating a circuit, the method comprising: receiving an input voltage at a voltage node of the circuit, the circuit further comprising: a first capacitive device connected between the first node and the second node; a second capacitive device connected between the third node and the fourth node; A first switching device connected between the first node and the voltage node; a second switch device connected between the second node and a reference voltage node; a third switching device connected between the third node and the voltage node; a fourth switch device connected between the fourth node and the reference voltage node; fifth to eighth switching devices connected between the corresponding first to fourth nodes and the output node; and A first variable capacitance device and a second variable capacitance device include first terminals connected to the first node and the third node, respectively, or the second node and the fourth node, respectively; and The second, third, fifth and eighth switching devices are switched alternately with the first, fourth, sixth and seventh switching devices to generate an output voltage at the output node.

10. The method according to claim 9, wherein: Alternatingly switching the second, third, fifth, and eighth switching devices with the first, fourth, sixth, and seventh switching devices includes alternately connecting the output node to the reference node by: a first parallel arrangement of the first capacitive device and the first variable capacitive device, or A second parallel arrangement of the second capacitive device and the second variable capacitive device.

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