Voltage stabilizer and control method, device and equipment thereof

Abstract

The invention discloses a voltage stabilizer and a control method, device and equipment thereof, and relates to the technical field of electronic circuits, the voltage stabilizer comprises an operational amplifier, a voltage stabilization output circuit and a mode switching control circuit; wherein the mode switching control circuit is used for controlling the voltage stabilization output circuit so as to adjust and switch the working mode of the voltage stabilizer; the working modes comprise a first working mode when the power supply voltage is the first voltage and a second working mode when the power supply voltage is the second voltage, and the voltage stabilization output circuit is used for converting the first voltage into the second voltage to be output under the action of the operational amplifier when the working mode is the first working mode; when the working mode is a second working mode, a second voltage is output through the voltage stabilization output end; wherein the first voltage is greater than the second voltage; according to the invention, the switching of the working modes of the LDO under different power supply voltage conditions can be realized, so that the LDO can output stable voltage under two power supply voltage conditions, and the applicability of the LDO in different application scenes is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a voltage stabilizer and a control method, device and equipment thereof. Background Art

[0002] Voltage regulator is a common power management chip, among which low dropout regulator (LDO) is widely used in portable and communication devices due to its advantages such as low static power consumption, low cost and no output ripple. The output voltage expression of traditional LDO can be as follows:

[0003] ;

[0004] From the above expression of traditional LDO output voltage, we can know that the output voltage (V OUT ) is determined by the feedback resistor ratio (R2 / R3) and the reference voltage (V ref ); although it seems to be unrelated to the power supply voltage, the key parameter of LDO is the leakage voltage V drop It limits the minimum value of the power supply voltage (VDD); when the LDO is working normally, the MOS tube works in the linear region, which is equivalent to a linear resistor, and a voltage drop will inevitably occur across its source and drain. The dropout voltage refers to the minimum value of the voltage drop that ensures the normal operation of the LDO under full load conditions; therefore, the LDO will specify the input voltage range when applied, and its application environment is thus limited, such as Figure 1 As shown in the figure, the power supply voltage needs to be greater than 2.4V to ensure that the LDO can normally output a 1.8V voltage. Therefore, how to enable the LDO to output a stable voltage under different power supply voltages and improve the applicability of the LDO in different application scenarios is an urgent problem to be solved today. Summary of the invention

[0005] The purpose of the present invention is to provide a voltage stabilizer and a control method, device and equipment thereof, so that the LDO can output a stable voltage under different power supply voltages, thereby improving the applicability of the LDO in different application scenarios.

[0006] In order to solve the above technical problems, the present invention provides a voltage stabilizer, comprising: an operational amplifier, a voltage stabilization output circuit and a mode switching control circuit; wherein the in-phase input terminal and the output terminal of the operational amplifier are connected to the voltage stabilization output circuit;

[0007] The mode switching control circuit is used to control the voltage stabilization output circuit to adjust and switch the working mode of the voltage stabilizer; wherein the working mode includes a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage;

[0008] The voltage-stabilized output circuit is used to convert the first voltage into a second voltage output under the action of the operational amplifier when the operating mode is the first operating mode; and output the second voltage when the operating mode is the second operating mode; wherein the first voltage is greater than the second voltage.

[0009] On the other hand, the mode switching control circuit includes a level converter, a logic gate, and a control output terminal; wherein the level converter is connected to the logic gate, and the logic gate is connected to the control output terminal.

[0010] On the other hand, the voltage-stabilized output circuit includes: a first drive output circuit and a second drive output circuit; wherein the input end of the first drive output circuit is connected to the input end of the second drive output circuit, and the common end of the connections is connected to the power input end; the output end of the first drive output circuit is connected to the output end of the second drive output circuit, and the common end of the connections serves as the voltage-stabilized output end; the control end of the first drive output circuit and the control end of the second drive output circuit are respectively connected to the mode switching control circuit;

[0011] The first drive output circuit is used to, under the control of the mode switching control circuit, be turned on when the working mode is the first working mode, and under the action of the operational amplifier, convert the first voltage input from the power input terminal into the second voltage, and output the second voltage through the voltage stabilization output terminal;

[0012] The second drive output circuit is used to be turned on when the working mode is the second working mode according to the control of the mode switching control circuit, so as to turn on the connection between the input terminal and the output terminal of the second drive output circuit, and output the second voltage input by the power supply input terminal through the voltage stabilizing output terminal.

[0013] On the other hand, the operating mode also includes a third operating mode when a second voltage is input to the power input terminal; wherein, in the third operating mode, the voltage regulator supports the voltage stabilization output terminal to be connected to an external input voltage, and the external input voltage is less than or equal to the second voltage.

[0014] On the other hand, the first drive output circuit includes: a first switch unit, a second switch unit, a first PMOS tube, a first resistor and a second resistor;

[0015] Wherein, the source of the first PMOS tube is connected to the second end of the first switch unit, and the first end of the first switch unit is connected to the power input end; the drain of the first PMOS tube is connected to the first end of the second switch unit, and the common end of the connections is used as the voltage stabilization output end; the second end of the second switch unit is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the common end of the connections is connected to the in-phase input end of the operational amplifier; the second end of the second resistor is grounded; the gate of the first PMOS tube is connected to the output end of the operational amplifier;

[0016] The control ends of the first switch unit and the second switch unit are both connected to the mode switching control circuit; when the working mode is the first working mode, the first switch unit and the second switch unit are both turned on, and under the action of the operational amplifier, the first voltage received at the first end of the first switch unit is converted into the second voltage and output through the voltage stabilization output end; when the working mode is the second working mode or the third working mode, the first switch unit and the second switch unit are both turned off.

[0017] On the other hand, the second drive output circuit includes: a second PMOS transistor, a third PMOS transistor and a first NMOS transistor;

[0018] Wherein, the source of the second PMOS tube is connected to the source of the third PMOS tube, and the common end of the connections is connected to the power input end; the drain of the second PMOS tube is connected to the gate of the third PMOS tube, and the common end of the connections is connected to the drain of the first NMOS tube; the source of the first NMOS tube is grounded; the drain of the second PMOS tube serves as the voltage stabilization output end; the control output end of the mode switching control circuit includes a first control output end and a second control output end;

[0019] The gate of the second PMOS tube is connected to the first control output end, and the gate of the first NMOS tube is connected to the second control output end; when the working mode is the first working mode or the third working mode, the mode switching control circuit controls the second PMOS tube to be turned on and the first NMOS tube to be turned off, so as to disconnect the third PMOS tube; when the working mode is the second working mode, the mode switching control circuit controls the second PMOS tube to be turned off and the first NMOS tube to be turned on, so as to turn on the third PMOS tube and output the second voltage input from the power input end to the voltage stabilization output end.

[0020] In another aspect, the second drive output circuit further includes:

[0021] An isolation circuit is arranged between the drain of the second PMOS tube and the drain of the first NMOS tube, and is used for isolating the first voltage output from the drain of the second PMOS tube and converting it into a preset voltage to output to the drain of the first NMOS tube when the operating mode is the first operating mode; wherein the preset voltage is less than or equal to the second voltage.

[0022] On the other hand, the isolation circuit includes: a third resistor, a fourth resistor and a second NMOS transistor;

[0023] Among them, the common end of the drain of the second PMOS tube and the gate of the third PMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is connected to the drain of the first NMOS tube, and the first end of the third resistor is connected to the power input end; the second end of the third resistor is connected to the first end of the fourth resistor, and the common end thereof is connected to the gate of the second NMOS tube, and the second end of the fourth resistor is grounded.

[0024] On the other hand, the first switch unit includes a fourth PMOS tube, the second switch unit includes a fifth PMOS tube, and the control output end of the mode switching control circuit includes a first control output end, a second control output end, a third control output end and a fourth control output end; wherein the source of the fourth PMOS tube is connected to the power input end, the drain of the fourth PMOS tube is connected to the source of the first PMOS tube, and the gate of the fourth PMOS tube is connected to the third control output end as the control end of the first switch unit; the source of the fifth PMOS tube is connected to the drain of the first PMOS tube, the drain of the fifth PMOS tube is connected to the first end of the first resistor, and the gate of the fifth PMOS tube is connected to the fourth control output end as the control end of the second switch unit;

[0025] The first control output terminal, the second control output terminal, the third control output terminal and the fourth control output terminal are all used to control the conduction or shutdown of the MOS tubes connected to them respectively by outputting the first control level and / or the second control level.

[0026] The present invention further provides a control method for a voltage stabilizer, which is applied to the voltage stabilizer as described in any one of the above items, comprising:

[0027] Acquire power supply voltage configuration information of the voltage regulator; wherein the power supply voltage configuration information includes the power supply voltage of the power supply input terminal in the voltage stabilization output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage;

[0028] Determine the working mode of the voltage regulator according to the power supply voltage configuration information; wherein the working mode includes a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage;

[0029] The voltage regulator is controlled by the mode switching control circuit of the voltage regulator to adjust and switch the voltage regulator to the working mode.

[0030] The present invention further provides a control device for a voltage stabilizer, which is applied to any of the voltage stabilizers described above, comprising:

[0031] An acquisition module, used for acquiring power supply voltage configuration information of the voltage regulator; wherein the power supply voltage configuration information includes the power supply voltage of the power supply input terminal in the voltage stabilization output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage;

[0032] A determination module, configured to determine an operating mode of the voltage regulator according to the power supply voltage configuration information; wherein the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage;

[0033] The control module is used to control the voltage stabilization output circuit through the mode switching control circuit of the voltage stabilizer, so as to adjust and switch the voltage stabilizer to the working mode.

[0034] In addition, the present invention also provides a control device for a voltage stabilizer, comprising:

[0035] Memory for storing computer programs;

[0036] A processor is used to implement the steps of the control method of the voltage regulator as described above when executing the computer program.

[0037] A voltage stabilizer provided by the present invention comprises: an operational amplifier, a voltage stabilization output circuit and a mode switching control circuit; wherein the in-phase input terminal and the output terminal of the operational amplifier are connected to the voltage stabilization output circuit, and the inverting input terminal of the operational amplifier is connected to a reference voltage; the mode switching control circuit is used to control the voltage stabilization output circuit to adjust the working mode of the switching voltage stabilizer; wherein the working mode comprises a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage, and the voltage stabilization output circuit is used to convert the first voltage into a second voltage output under the action of the operational amplifier when the working mode is the first working mode; and output the second voltage through the voltage stabilization output terminal when the working mode is the second working mode; wherein the first voltage is greater than the second voltage;

[0038] It can be seen that the present invention can realize the switching of the working mode of LDO under different power supply voltages through the setting of the mode switching control circuit and the voltage stabilization output circuit, so that LDO can output stable voltage under two power supply voltages, realize the power switchable LDO under advanced technology, and improve the applicability of LDO in different application scenarios. In addition, the present invention also provides a control method, device and equipment of a voltage stabilizer, which also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0040] Figure 1 A schematic diagram showing the corresponding relationship between the input and output voltages of the LDO;

[0041] Figure 2 A structural block diagram of a voltage stabilizer provided by an embodiment of the present invention;

[0042] Figure 3 A partial circuit diagram of another voltage stabilizer provided by an embodiment of the present invention;

[0043] Figure 4 A flow chart of a control method of a voltage stabilizer provided by an embodiment of the present invention;

[0044] Figure 5 A structural block diagram of a control device for a voltage stabilizer provided by an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of the structure of a control device for a voltage stabilizer provided by an embodiment of the present invention;

[0046] Figure 7 A schematic diagram of the structure of a computer-readable storage medium provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] Please refer to Figure 2 , Figure 2 The structure block diagram of a voltage stabilizer provided by an embodiment of the present invention. The voltage stabilizer may include: an operational amplifier 10, a voltage stabilization output circuit 20 and a mode switching control circuit 30; wherein the in-phase input terminal and the output terminal of the operational amplifier 10 are connected to the voltage stabilization output circuit 20, and the inverting input terminal of the operational amplifier 10 is connected to a reference voltage (Vref);

[0049] The mode switching control circuit 30 is used to control the voltage stabilization output circuit 20 to adjust the working mode of the switching regulator; wherein the working mode includes a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage;

[0050] The voltage stabilizing output circuit 20 is used to convert the first voltage into the second voltage output under the action of the operational amplifier 10 when the working mode is the first working mode; and output the second voltage when the working mode is the second working mode; wherein the first voltage is greater than the second voltage.

[0051] It can be understood that the voltage-stabilized output circuit 20 in this embodiment can switch the working mode of the LDO according to the control of the mode switching control circuit 30, so that when the power supply voltage connected to the power supply input terminal of the voltage-stabilized output circuit 20 is the first voltage or the second voltage, the voltage-stabilized output terminal of the voltage-stabilized output circuit 20 in the LDO working in the first working mode or the second working mode can output a stable second voltage, ensuring that the LDO can output a stable voltage under the conditions of the first voltage or the second voltage. For example, the voltage-stabilized output circuit 20 is used to convert the first voltage input to the power supply input terminal into the second voltage under the feedback control of the operational amplifier 10 when the working mode is the first working mode, and output the second voltage through the voltage-stabilized output terminal; when the working mode is the second working mode, the second voltage input to the power supply input terminal is output through the voltage-stabilized output terminal; wherein, in this embodiment, the first voltage can be greater than the second voltage and less than or equal to 2 times the second voltage, such as the first voltage can be 3.3V, and the second voltage can be 1.8V.

[0052] Correspondingly, the specific structure of the mode switching control circuit 30 in this embodiment can be set by the designer according to the practical scenario and user needs. The mode switching control circuit 30 includes a level converter, a logic gate, and a control output terminal; wherein the level converter is connected to the logic gate, and the logic gate is connected to the control output terminal. The specific logic gate circuit can be set according to the practical scenario and user needs, as long as it can cooperate with the level converter and output a control output signal at the control output terminal that can control the voltage stabilizing output circuit 20 to switch the working mode.

[0053] Correspondingly, the specific structure of the voltage-stabilized output circuit 20 in this embodiment can also be set by the designer according to the practical scenario. For example, the voltage-stabilized output circuit 20 may include: a first drive output circuit and a second drive output circuit; wherein the input end of the first drive output circuit is connected to the input end of the second drive output circuit, and the common end of the connections is connected to the power input end; the output end of the first drive output circuit is connected to the output end of the second drive output circuit, and the common end of the connections is used as the voltage-stabilized output end; the control end of the first drive output circuit and the control end of the second drive output circuit are respectively connected to the mode switching control circuit 30; the first drive output circuit is used to be turned on when the working mode is the first working mode according to the control of the mode switching control circuit 30, and under the action of the operational amplifier 10, the first voltage input to the power input end is converted into a second voltage, and the second voltage is output through the voltage-stabilized output end; the second drive output circuit is used to be turned on when the working mode is the second working mode according to the control of the mode switching control circuit 30, so as to conduct the connection between the input end and the output end of the second drive output circuit, and output the second voltage input to the power input end through the voltage-stabilized output end.

[0054] That is to say, in this embodiment, by setting the first drive output circuit and the second drive output circuit, when the working mode is the first working mode, the first drive output circuit is turned on and the second drive output circuit is turned off, so that the first drive output circuit can use the feedback control of the operational amplifier 10 to convert the first voltage input to the power input end into the second voltage and output it through the voltage stabilizing output end; when the working mode is the second working mode, the first drive output circuit is turned off and the second drive output circuit is turned on, so that the second drive output circuit can output the second voltage input to the power input end through the voltage stabilizing output end.

[0055] Furthermore, in this embodiment, the working mode of the LDO may not only include a first working mode when the power input terminal is connected to the first voltage and a second working mode when the power input terminal is connected to the second voltage, but may also include a third working mode when the power input terminal is connected to the second voltage, so that the LDO supports the voltage-regulated output terminal to be connected to an external input voltage in the third working mode, and the external input voltage is less than or equal to the second voltage, such as the external input voltage can be the second voltage.

[0056] Among them, this embodiment does not limit the specific circuit structure of the above-mentioned first drive output circuit. The first drive output circuit may include not only a first PMOS tube, a first resistor and a second resistor for realizing the conversion from the first voltage to the second voltage through feedback control of the operational amplifier 10, but also a switch unit (i.e., a first switch unit and a second switch unit) respectively connected to the source and drain of the first PMOS tube, so as to switch the on-off state of the first drive output circuit according to the control of the mode switching control circuit 30.

[0057] For example, if Figure 3 As shown, the first drive output circuit may include: a first switch unit (PM4), a second switch unit (PM5), a first PMOS tube (PM1), a first resistor (R1) and a second resistor (R1); wherein the source of the first PMOS tube is connected to the second end of the first switch unit, and the first end of the first switch unit is connected to the power input end (VDD3318); the drain of the first PMOS tube is connected to the first end of the second switch unit, and the common end of the connections serves as the voltage stabilization output end (LDOOUT18); the second end of the second switch unit is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the connection The common end of the first switching unit and the second switching unit is connected to the in-phase input end (VF end) of the operational amplifier 10; the second end of the second resistor is grounded; the gate of the first PMOS tube is connected to the output end (OP_OUT end) of the operational amplifier 10; the control ends of the first switching unit and the second switching unit are both connected to the mode switching control circuit 30; when the working mode is the first working mode, the first switching unit and the second switching unit are both turned on, and under the action of the operational amplifier 10, the first voltage received by the first end of the first switching unit is converted into a second voltage and output through the voltage stabilization output end; when the working mode is the second working mode or the third working mode, the first switching unit and the second switching unit are both turned off.

[0058] That is to say, the operational amplifier 10 (such as the error amplifier EA) in this embodiment can, in the first working mode, amplify the difference between the feedback voltage connected to the non-inverting input terminal (i.e., the voltage between the first resistor and the second resistor) and the reference voltage connected to the inverting input terminal and output it to the gate of the first PMOS tube, thereby realizing feedback control of the operational amplifier 10, so that the first voltage input to the power input terminal can be converted into the second voltage output by the regulated output terminal.

[0059] Similarly, this embodiment does not limit the specific circuit structure of the second drive output circuit. For example, the second drive output circuit may only include a third switch unit (such as a MOS tube) directly controlled by the mode switching control circuit 30 to correspondingly turn on or off the connection between the power input terminal and the voltage stabilization output terminal. In order to facilitate the configuration of the mode switching control circuit 30 and the withstand voltage configuration of the circuit elements, the second drive output circuit may also include a third switch unit for turning on or off the connection between the power input terminal and the voltage stabilization output terminal, and other switch units for correspondingly controlling the turning on and off of the third switch unit according to the control of the mode switching control circuit 30.

[0060] like Figure 3As shown, the second drive output circuit may include a second PMOS tube (PM2), a third PMOS tube (PM3) and a first NMOS tube (NM1); that is, the mode switching control circuit 30 may control the conduction or shutdown of the second PMOS tube and the first NMOS tube, and correspondingly control the conduction or shutdown of the third PMOS tube, so as to realize the on-off control of the connection between the power input terminal and the voltage stabilization output terminal. Among them, the source of the second PMOS tube is connected to the source of the third PMOS tube, and the common end of the connection is connected to the power input terminal; the drain of the second PMOS tube is connected to the gate of the third PMOS tube, and the common end of the connection is connected to the drain of the first NMOS tube; the source of the first NMOS tube is grounded; the drain of the second PMOS tube serves as the voltage stabilization output terminal; the control output terminal of the mode switching control circuit includes a first control output terminal (hiz_enb terminal) and a second control output terminal (bypass_en18 terminal);

[0061] The gate of the second PMOS tube is connected to the first control output terminal of the mode switching control circuit 30, and the gate of the first NMOS tube is connected to the second control output terminal of the mode switching control circuit 30; when the working mode is the first working mode or the third working mode, the mode switching control circuit 30 controls the second PMOS tube to be turned on and the first NMOS tube to be turned off, so as to disconnect the third PMOS tube; when the working mode is the second working mode, the mode switching control circuit 30 controls the second PMOS tube to be turned off and the first NMOS tube to be turned on, so as to turn on the third PMOS tube and output the second voltage input from the power input terminal to the voltage stabilization output terminal.

[0062] Furthermore, in order to avoid the withstand voltage problem of the first NMOS tube when the working mode is the first working mode, the second driving output circuit may also include: an isolation circuit arranged between the drain of the second PMOS tube and the drain of the first NMOS tube, for isolating the first voltage output from the drain of the second PMOS tube and converting it into a preset voltage to output to the drain of the first NMOS tube when the working mode is the first working mode; wherein the preset voltage is less than or equal to the second voltage, such as the preset voltage may be the second voltage. That is to say, in this embodiment, by setting the isolation circuit, the drain of the first NMOS tube can be prevented from being directly connected to the first voltage when the working mode is the first working mode, so that the first NMOS tube can use a lower withstand voltage value (such as the second voltage) without the risk of overvoltage.

[0063] like Figure 3As shown, the isolation circuit may include a third resistor (R3), a fourth resistor (R4) and a second NMOS tube (NM2); wherein the common end of the drain of the second PMOS tube and the gate of the third PMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is connected to the drain of the first NMOS tube, the first end of the third resistor is connected to the power input end; the second end of the third resistor is connected to the first end of the fourth resistor, the common end thereof is connected to the gate of the second NMOS tube, and the second end of the fourth resistor is grounded. In other words, through the voltage division of the third resistor and the fourth resistor, a suitable bias voltage can be obtained to be given to the gate of the second NMOS tube, so that the voltage connected to the drain of the first NMOS tube (i.e., the preset voltage) can be reduced to a lower level.

[0064] It should be noted that the MOS tubes in the circuit provided in this embodiment can all be low-voltage devices, and the withstand voltage of the low-voltage devices is relatively low. The withstand voltage of the MOS tubes in the circuit can be less than or equal to the second voltage, and the first voltage can be less than or equal to 2 times the second voltage; Figure 3 As shown, when the first voltage is 3.3V and the second voltage is 1.8V, the withstand voltage of the MOS tubes in the circuit can be 1.8V (i.e., the second voltage). When the working mode is the first working mode, if there is no second NMOS tube (NM2), the source-drain voltage of the first NMOS tube (NM1) in this mode will reach 3.3V when the second PMOS tube (PM2) is turned on, causing NM1 to be over-voltage; and after NM2 is set, the drain voltage of NM1 is equal to the gate voltage of NM2 minus the VGS (gate voltage relative to the source) of NM2. The gate voltage of NM2 can be appropriately biased by the setting of the third resistor (R3) and the fourth resistor (R4) to reduce the drain voltage of NM1 to a lower level, so that the source-drain voltage of NM1 is not greater than 1.8V, thereby avoiding the over-voltage of NM1.

[0065] Correspondingly, the mode switching control circuit 30 can control the conduction or shutdown of the connected MOS tube through the first control level and / or the second control level output by each control output terminal; for example, if the first control level is greater than the second control level, then the first control level can be equal to the second voltage (such as 1.8V) or float in a small range around the second voltage, and the second control level can be equal to the third voltage (such as 0) or float in a small range around the third voltage, and the third voltage is less than the second voltage.

[0066] For example, if Figure 3As shown, the first switch unit includes a fourth PMOS tube (PM4), the second switch unit includes a fifth PMOS tube (PM5), and the control output end of the mode switching control circuit 30 includes a first control output end, a second control output end, a third control output end and a fourth control output end; wherein the source of the fourth PMOS tube is connected to the power input end), the drain of the fourth PMOS tube is connected to the source of the first PMOS tube, and the gate of the fourth PMOS tube is connected to the third control output end (n1 end) of the mode switching control circuit 30 as the control end of the first switch unit; the source of the fifth PMOS tube is connected to the first PMOS tube The drain of the fifth PMOS tube is connected to the first end of the first resistor, and the gate of the fifth PMOS tube is connected to the fourth control output terminal (n2 terminal) of the mode switching control circuit 30 as the control terminal of the second switch unit; the first control output terminal (hiz_enb terminal), the second control output terminal (bypass_en18 terminal), the third control output terminal (n1 terminal) and the fourth control output terminal (n2 terminal) of the mode switching control circuit 30 can all be connected by outputting the first control level or the second control level, corresponding to the on and off of the connected MOS tubes (such as PM2, NM1, PM4 and PM5). As the process is becoming more and more advanced, the characteristic size of the MOS tube is reduced, the tube threshold is reduced, the circuit area power consumption is reduced, the speed is faster and the chip cost is reduced, which brings about the reduction of the withstand voltage value of the MOS tube. In order to ensure that the MOS tube has no overvoltage risk when the voltage conversion circuit such as LDO is powered by a higher first voltage, the relatively high level (i.e., the first control level) output by the mode switching control circuit 30 in this embodiment can be greater than or equal to half of the first voltage and less than the first voltage, such as the first control level can be the second voltage.

[0067] Correspondingly, the specific structure of the mode switching control circuit 30 in this embodiment can be set by the designer according to the practical scenario and user needs. For example, when the first control level is the second voltage, Figure 3As shown, the voltage stabilizing output terminal (LDOOUT18 terminal) of the voltage stabilizing output circuit 20 can be connected to the mode switching control circuit 30. The mode switching control circuit 30 is used to control the first control output terminal and the third control output terminal to output the first control level, and control the second control output terminal and the fourth control output terminal to output the second control level when the working mode is the first working mode; when the working mode is the second working mode, control the first control output terminal, the second control output terminal, the third control output terminal and the fourth control output terminal to output the first control level; when the working mode is the third working mode, control the first control output terminal and the second control output terminal to output the second control level, and control the third control output terminal and the fourth control output terminal to output the first control level. As long as the mode switching control circuit 30 can adjust the working mode of the switching regulator by outputting the first control level and the second control level, this embodiment does not impose any restrictions on this.

[0068] For example, if Figure 3 As shown, the voltage regulated output circuit 20 may include a first level converter (LS 1), a second level converter (LS 2), an NOR gate (G4), a first NOT gate (G1), a second NOT gate (G2), a third NOT gate (G3), a first NAND gate (G5) and a second NAND gate (G6);

[0069] The first input end of the first level converter and the second level converter are connected to the regulated output end (LDOOUT18 end) of the regulated output circuit 20, and the second input end (DVDD09 end) of the first level converter and the second level converter receives the fourth voltage; the control input end of the first level converter receives the first enable signal (hiz_en), which is used to control the first level converter to output the first control level or the second control level according to the first enable signal; the control input end of the second level converter receives the second enable signal (bypas_en), which is used to control the first level converter to output the first control level or the second control level according to the first enable signal; the output end of the first level converter is connected to the input end of the first NOT gate, the output end of the first NOT gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate is connected to the input end of the second NOT gate. They are respectively connected to the first input end of the NOR gate and the first input end of the first NAND gate; the output end of the second level converter is connected to the input end of the third NAND gate, the output end of the third NAND gate is respectively connected to the second input end of the NOR gate and the first input end of the second NAND gate, the output end of the NOR gate is connected to the second input end of the first NAND gate, and the second input end of the second NAND gate is connected to the output end of the first NAND gate; the output end of the first NAND gate serves as the first control output end (hiz_enb end), the output end of the first NAND gate serves as the third control output end (n1 end), the output end of the NOR gate serves as the second control output end (bypass_en18 end), and the output end of the second NAND gate serves as the fourth control output end (n2 end); wherein the fourth voltage is less than the second voltage and greater than the third voltage, such as the fourth voltage can be half of the second voltage.

[0070] Correspondingly, the processor can control the output of the first enable signal and the second enable signal, and control the MOS tube in the voltage stabilization output circuit 20 through the mode switching control circuit 30 to adjust the voltage regulator to switch to the desired working mode; for example, when the working mode is the first working mode, the first enable signal and the second enable signal are both 0, and the first level converter and the second level converter both output the second control level; when the working mode is the second working mode, the first enable signal is 0 and the second enable signal is 1, the first level converter outputs the second control level and the second level converter outputs the first control level; when the working mode is the third working mode, the first enable signal and the second enable signal are both 1, and the first level converter and the second level converter both output the first control level.

[0071] That is to say, Figure 3As shown, the first voltage can be 3.3V, the second voltage can be 1.8V, the third voltage can be 0V, and the fourth voltage can be 0.9V. The LOD working modes can include 3.3V LOD mode (i.e., the first working mode), 1.8V bypass mode (i.e., the second working mode) and the third working mode. The voltage resistance problem occurs in the 3.3 V LDO mode. The high-voltage power supplies of the first level converter (LS 1) and the second level converter (LS 2) both use the output voltage of the LDO (LDOOUT18). The structure is divided into two power tube drives, PM1 and PM3, which can be selected through different configurations. The gate of PM1 is connected to the output of the operational amplifier. Figure 3 The circuit of the operational amplifier 10 is omitted, and the load is driven by the PM1 branch in the 3.3 V LDO mode; and the PM3 branch drives the load in the 1.8 V bypass mode.

[0072] Correspondingly, when the LDO works in 3.3 V LDO mode, the input voltage of VDD3318 (i.e., the power input terminal) is 3.3 V (i.e., the first voltage), hiz_en and bypas_en are both set to 0 by the register, so that hiz_enb and n1 signals are the first control level (1.8 V), so PM2 and PM4 are both turned on, and the gate of PM3 is pulled up to 3.3 V; bypass_en18 and n2 signals are the second control level (0), PM5 is turned on, and NM1 is turned off; at this time, the PM3 branch is turned off, and the PM1 branch is stabilized at 1.8 V through the LDO loop; since the gates of PM2 and PM4 are 1.8 V, the voltage difference between the poles of PM2 and PM4 will not exceed the withstand voltage value of 1.8 V, so there is no overvoltage risk. NM2 is used to solve the voltage resistance problem of NM1. If there is no NM2, the voltage difference between the source and drain of NM1 in this mode is 3.3V. After setting NM2, the drain voltage of NM1 is equal to the gate voltage of NM2 minus one VGS. The gate voltage of NM2 is appropriately biased by adjusting R3 and R4, which can reduce the drain voltage of NM1 to a lower level.

[0073] When the LDO works in 1.8 V bypass mode, VDD3318 is 1.8 V, hiz_en is set to 0, bypas_en is set to 1, hiz_enb and n1 signals are still high, but the voltage is already 1.8 V, so PM2 and PM4 are both cut off; bypass_en18 and n2 signals are high, PM5 is cut off, and NM1 is turned on; the PM1 branch is turned off, the PM3 gate is pulled down to 0, PM3 is turned on, and the drain is pulled up to the power supply to ensure that the output is still 1.8 V.

[0074] When the LDO works in the third working mode, it is only allowed to configure when the voltage input to the power input terminal is 1.8 V, hiz_en is set to 1, bypas_en is set to 1, at this time, hiz_enb and bypass_en18 signals are 0, PM2 is turned on, NM1 is turned off, PM3 gate is pulled up to 1.8 V power supply, n1 signal is still high level 1.8 V, so PM1, PM3 branches are turned off, and n2 signal is high level, the path from feedback resistor to ground is also turned off, to ensure that the output will not leak when connected to the 1.8V external input voltage. Figure 3 The circuit setting shown realizes a switchable LDO under advanced technology (i.e., low-voltage device), is compatible with 1.8 V and 3.3 V power supply voltages, and outputs a stable 1.8 V voltage. In the absence of a 3.3 V power supply, a 1.8 V power supply can still output a stable 1.8 V, and supports external output voltage. The high level of the gate control voltage of all MOS tubes is 1.8 V, and the voltage difference between the poles of the MOS tube in the three working modes will not exceed the withstand voltage value, effectively avoiding overvoltage. The gate of PM2 is 1.8 V in both the 3.3 V LDO mode and the 1.8 V bypass mode. Under the condition that the gate voltage remains unchanged, PM2 can achieve two different working states, namely, realize the switching control of the first working mode and the second working mode, thereby realizing the switching of circuit functions.

[0075] In this embodiment, the embodiment of the present invention can realize the switching of the working mode of the LDO under different input voltage conditions through the setting of the mode switching control circuit 30 and the voltage stabilizing output circuit 20, so that the LDO can output a stable voltage under two input voltage conditions, realize the LDO with switchable power supply under advanced technology, and improve the applicability of the LDO in different application scenarios.

[0076] Corresponding to the above voltage stabilizer embodiment, an embodiment of the present invention further provides a voltage stabilizer control method. The voltage stabilizer control method described below and the voltage stabilizer described above can be referred to each other.

[0077] Please refer to Figure 4 , Figure 4 This is a flow chart of a control method for a voltage stabilizer provided by an embodiment of the present invention. The method is applied to the voltage stabilizer provided by the above embodiment and may include:

[0078] Step 101: Obtain power supply voltage configuration (ie, power supply configuration information) information of a voltage regulator; wherein the power supply voltage configuration information includes a power supply voltage at a power supply input terminal in a voltage stabilization output circuit of the voltage regulator; and the power supply voltage includes a first voltage and a second voltage.

[0079] It can be understood that the power supply voltage configuration information of the voltage regulator in this embodiment may include configuration information of the LDO power supply voltage in the above-mentioned embodiment, such as the power supply voltage at the power supply input terminal in the voltage stabilization output circuit of the LDO, that is, the processor can detect whether the power supply voltage at the power supply input terminal in the voltage stabilization output circuit of the LDO is the first voltage (for example, 3.3V) or the second voltage (for example, 1.8V), thereby correspondingly determining the working mode of the LDO.

[0080] Step 102: determining an operating mode of a voltage regulator according to the power supply voltage configuration information; wherein the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage;

[0081] It should be noted that in this step, the processor can determine the working mode of the LDO based on the obtained power supply voltage configuration information of the LDO. For example, the processor can determine that the working mode of the LDO is the first working mode when the power supply voltage at the power input terminal in the voltage regulated output circuit of the LDO is the first voltage; when the power supply voltage at the power input terminal in the voltage regulated output circuit of the LDO is the second voltage, the working mode of the LDO is determined to be the second working mode. The working mode can also be a third working mode powered by the second voltage to support the LDO external output voltage. For example, when the power supply voltage at the power input terminal in the voltage regulated output circuit of the LDO is the second voltage, the processor can determine that the working mode of the LDO is the second working mode or the third working mode according to the user setting information.

[0082] Step 103: Control the voltage stabilization output circuit through the mode switching control circuit of the voltage stabilizer to adjust and switch the voltage stabilizer to the working mode.

[0083] It can be understood that in this embodiment, the processor can control the MOS tube in the voltage stabilization output circuit through the LDO mode switching control circuit to adjust the LDO to switch to a certain working mode; Figure 3 As shown, the processor can configure the first enable signal (hiz_en) and the second enable signal (bypas_en) connected to the control input terminals of the first level converter (Level shifter1) and the second level converter (Level shifter2) in the adjustment mode switching control circuit through the register, control the level signals output by the first level converter and the second level converter, so as to adjust the level signals output by the first control output terminal, the second control output terminal and the third control output terminal of the mode switching control circuit, thereby controlling the on and off of the corresponding MOS tube in the voltage stabilization output circuit, and adjusting the voltage regulator to switch to the corresponding working mode.

[0084] In this embodiment, the embodiment of the present invention can switch the working mode of the LDO according to the power supply voltage of the LDO through the setting of the mode switching control circuit and the voltage stabilization output circuit of the LDO, so that the LDO can output a stable voltage under two power supply voltages, realizes a power switchable LDO under advanced technology, and improves the applicability of the LDO in different application scenarios.

[0085] Corresponding to the above method embodiment, an embodiment of the present invention further provides a control device for a voltage stabilizer. The control device for a voltage stabilizer described below and the control method for a voltage stabilizer described above can refer to each other.

[0086] Please refer to Figure 5 , Figure 5 This is a structural block diagram of a control device for a voltage stabilizer provided in an embodiment of the present invention. The device is applied to the voltage stabilizer provided in the above embodiment and may include:

[0087] The acquisition module 100 is used to acquire the power supply voltage configuration information of the voltage stabilizer; wherein the power supply voltage configuration information includes the power supply voltage of the power supply input terminal in the voltage stabilization output circuit of the voltage stabilizer; the power supply voltage includes a first voltage and a second voltage;

[0088] The determination module 200 is used to determine the working mode of the voltage regulator according to the power supply voltage configuration information; wherein the working mode includes a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage;

[0089] The control module 300 is used to control the voltage stabilization output circuit through the mode switching control circuit of the voltage stabilizer, and adjust the voltage stabilizer to switch to the working mode.

[0090] In this embodiment, the embodiment of the present invention can switch the working mode of the LDO according to the power supply voltage of the LDO through the setting of the mode switching control circuit and the voltage stabilization output circuit of the LDO, so that the LDO can output a stable voltage under two power supply voltages, realizes a power switchable LDO under advanced technology, and improves the applicability of the LDO in different application scenarios.

[0091] Corresponding to the above method embodiment, an embodiment of the present invention further provides a control device for a voltage stabilizer. The control device for a voltage stabilizer described below and the control method for a voltage stabilizer described above can refer to each other.

[0092] Please refer to Figure 6 , Figure 6 A schematic diagram of a control device for a voltage stabilizer provided in an embodiment of the present invention. The device is applied to the voltage stabilizer provided in the above embodiment and may include:

[0093] A memory D1, for storing computer programs;

[0094] The processor D2 is used to implement the steps of the voltage regulator control method provided by the above method embodiment when executing the computer program.

[0095] Corresponding to the above method embodiment, an embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium described below and the control method of a voltage regulator described above can be referred to each other.

[0096] Please refer to Figure 7 , Figure 7 The computer readable storage medium 40 stores a computer program 41, which implements the steps of the voltage regulator control method provided in the above method embodiment when executed by a processor.

[0097] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the methods, devices, equipment, and computer-readable storage media disclosed in the embodiments, since they correspond to the voltage regulator disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the voltage regulator part.

[0098] The above is a detailed introduction to a voltage stabilizer and a control method, device and equipment provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A voltage stabilizer, characterized in that: include: An operational amplifier, a voltage-stabilizing output circuit and a mode switching control circuit; wherein the in-phase input terminal and the output terminal of the operational amplifier are connected to the voltage-stabilizing output circuit; The mode switching control circuit is used to control the voltage stabilization output circuit to adjust and switch the working mode of the voltage stabilizer; wherein the working mode includes a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage; The voltage-stabilized output circuit is used to, when the operating mode is the first operating mode, convert the first voltage into the second voltage output under the action of the operational amplifier; when the operating mode is the second operating mode, output the second voltage; wherein the first voltage is greater than the second voltage.

2. The voltage stabilizer according to claim 1, characterized in that: The mode switching control circuit includes a level converter, a logic gate, and a control output terminal; wherein the level converter is connected to the logic gate, and the logic gate is connected to the control output terminal.

3. The voltage stabilizer according to claim 1, characterized in that: The voltage-stabilized output circuit comprises: a first drive output circuit and a second drive output circuit; wherein the input end of the first drive output circuit is connected to the input end of the second drive output circuit, and the common end of the connections is connected to the power input end; the output end of the first drive output circuit is connected to the output end of the second drive output circuit, and the common end of the connections is used as the voltage-stabilized output end; the control end of the first drive output circuit and the control end of the second drive output circuit are respectively connected to the mode switching control circuit; The first drive output circuit is used to, under the control of the mode switching control circuit, be turned on when the working mode is the first working mode, and under the action of the operational amplifier, convert the first voltage input from the power input terminal into the second voltage, and output the second voltage through the voltage stabilization output terminal; The second drive output circuit is used to be turned on when the working mode is the second working mode according to the control of the mode switching control circuit, so as to turn on the connection between the input terminal and the output terminal of the second drive output circuit, and output the second voltage input by the power supply input terminal through the voltage stabilizing output terminal.

4. The voltage stabilizer according to claim 1, characterized in that: The working mode also includes a third working mode when the power input terminal inputs a second voltage; wherein, in the third working mode, the voltage regulator supports the voltage stabilization output terminal to be connected to an external input voltage, and the external input voltage is less than or equal to the second voltage.

5. The voltage stabilizer according to claim 3, characterized in that: The first drive output circuit includes: a first switch unit, a second switch unit, a first PMOS tube, a first resistor and a second resistor; Wherein, the source of the first PMOS tube is connected to the second end of the first switch unit, and the first end of the first switch unit is connected to the power input end; the drain of the first PMOS tube is connected to the first end of the second switch unit, and the common end of the connections is used as the voltage stabilization output end; the second end of the second switch unit is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the common end of the connections is connected to the in-phase input end of the operational amplifier; the second end of the second resistor is grounded; the gate of the first PMOS tube is connected to the output end of the operational amplifier; The control ends of the first switch unit and the second switch unit are both connected to the mode switching control circuit; when the working mode is the first working mode, the first switch unit and the second switch unit are both turned on, and under the action of the operational amplifier, the first voltage received at the first end of the first switch unit is converted into the second voltage and output through the voltage stabilization output end; when the working mode is the second working mode or the third working mode, the first switch unit and the second switch unit are both turned off.

6. The voltage stabilizer according to claim 2 or 3, characterized in that: The second drive output circuit includes: a second PMOS tube, a third PMOS tube and a first NMOS tube; Wherein, the source of the second PMOS tube is connected to the source of the third PMOS tube, and the common end of the connections is connected to the power input end; the drain of the second PMOS tube is connected to the gate of the third PMOS tube, and the common end of the connections is connected to the drain of the first NMOS tube; the source of the first NMOS tube is grounded; the drain of the second PMOS tube serves as the voltage stabilization output end; the control output end of the mode switching control circuit includes a first control output end and a second control output end; The gate of the second PMOS tube is connected to the first control output end, and the gate of the first NMOS tube is connected to the second control output end; when the working mode is the first working mode or the third working mode, the mode switching control circuit controls the second PMOS tube to be turned on and the first NMOS tube to be turned off, so as to disconnect the third PMOS tube; when the working mode is the second working mode, the mode switching control circuit controls the second PMOS tube to be turned off and the first NMOS tube to be turned on, so as to turn on the third PMOS tube and output the second voltage input from the power input end to the voltage stabilization output end.

7. The voltage stabilizer according to claim 6, characterized in that: The second drive output circuit further includes: An isolation circuit is arranged between the drain of the second PMOS tube and the drain of the first NMOS tube, and is used for isolating the first voltage output from the drain of the second PMOS tube and converting it into a preset voltage to output to the drain of the first NMOS tube when the operating mode is the first operating mode; wherein the preset voltage is less than or equal to the second voltage.

8. The voltage stabilizer according to claim 7, characterized in that: The isolation circuit comprises: a third resistor, a fourth resistor and a second NMOS tube; Among them, the common end of the drain of the second PMOS tube and the gate of the third PMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is connected to the drain of the first NMOS tube, and the first end of the third resistor is connected to the power input end; the second end of the third resistor is connected to the first end of the fourth resistor, and the common end thereof is connected to the gate of the second NMOS tube, and the second end of the fourth resistor is grounded.

9. The voltage stabilizer according to claim 2 or 5, characterized in that: The first switch unit includes a fourth PMOS tube, the second switch unit includes a fifth PMOS tube, and the control output end of the mode switching control circuit includes a first control output end, a second control output end, a third control output end and a fourth control output end; wherein the source of the fourth PMOS tube is connected to the power input end, the drain of the fourth PMOS tube is connected to the source of the first PMOS tube, and the gate of the fourth PMOS tube is connected to the third control output end as the control end of the first switch unit; the source of the fifth PMOS tube is connected to the drain of the first PMOS tube, the drain of the fifth PMOS tube is connected to the first end of the first resistor, and the gate of the fifth PMOS tube is connected to the fourth control output end as the control end of the second switch unit; The first control output terminal, the second control output terminal, the third control output terminal and the fourth control output terminal are all used to control the conduction or shutdown of the MOS tubes connected to them respectively by outputting the first control level and / or the second control level.

10. A control method for a voltage stabilizer, characterized in that: The voltage stabilizer according to any one of claims 1 to 9 comprises: Acquire power supply voltage configuration information of the voltage regulator; wherein the power supply voltage configuration information includes the power supply voltage of the power supply input terminal in the voltage stabilization output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage; Determine the working mode of the voltage regulator according to the power supply voltage configuration information; wherein the working mode includes a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage; The voltage regulator is controlled by the mode switching control circuit of the voltage regulator to adjust and switch the voltage regulator to the working mode.

11. A control device for a voltage stabilizer, characterized in that: The voltage stabilizer according to any one of claims 1 to 9 comprises: An acquisition module, used for acquiring power supply voltage configuration information of the voltage regulator; wherein the power supply voltage configuration information includes the power supply voltage of the power supply input terminal in the voltage stabilization output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage; A determination module, configured to determine an operating mode of the voltage regulator according to the power supply voltage configuration information; wherein the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; The control module is used to control the voltage stabilization output circuit through the mode switching control circuit of the voltage stabilizer, so as to adjust and switch the voltage stabilizer to the working mode.

12. A control device for a low voltage regulator, characterized in that: include: Memory for storing computer programs; A processor is used to implement the steps of the control method of the voltage regulator as claimed in claim 10 when executing the computer program.

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