A voltage stabilizer and a control method, device and equipment thereof

Abstract

The application discloses a voltage stabilizer and a control method, device and equipment thereof, and relates to the technical field of electronic circuits.The voltage stabilizer comprises an operational amplifier, a voltage stabilizing output circuit and a mode switching control circuit.The mode switching control circuit is used for controlling the voltage stabilizing output circuit to adjust the working mode of the voltage stabilizer.The working mode comprises a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage.The voltage stabilizing output circuit is used for converting the first voltage into the second voltage under the action of the operational amplifier when the working mode is the first working mode and outputting the second voltage through a voltage stabilizing output end when the working mode is the second working mode.The first voltage is greater than the second voltage.The application can realize the switching of the working mode of the LDO under different power supply voltages, can make the LDO output stable voltage under two power supply voltages, and improves the applicability of the LDO in different application scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a voltage regulator and a control method, device and equipment thereof. BACKGROUND

[0002] The voltage regulator is a common power management chip, and a low dropout regulator (LDO) has a wide application in portable and communication devices due to low static power consumption, low cost and no output ripple. The output voltage expression of the traditional LDO can be as follows:

[0003] ;

[0004] It can be known from the output voltage expression of the traditional LDO that the output voltage (V OUT ) is determined by the feedback resistance ratio (R2 / R3) and the reference voltage (V ref ); although it seems to be irrelevant to the power supply voltage, the minimum value of the power supply voltage (VDD) is limited by the key parameter index of the LDO, the drain loss voltage V drop ; when the LDO works normally, the MOS tube works in the linear region, which is equivalent to a linear resistor, and a voltage drop will be generated at the source and drain of the MOS tube; the drain loss voltage refers to the minimum value of the voltage drop under the condition of ensuring the normal work of the LDO under full load; therefore, the LDO will specify the input voltage range when applied, and the application environment is thus limited, as shown in Figure 1 , the power supply voltage needs to be greater than 2.4V to ensure that the LDO can normally output a 1.8V voltage. Therefore, how to enable the LDO to output stable voltage under different power supply voltages and improve the applicability of the LDO in different application scenarios is a problem to be solved at present. SUMMARY

[0005] The purpose of the present application is to provide a voltage regulator and a control method, device and equipment thereof, so as to enable the LDO to output stable voltage under different power supply voltages and improve the applicability of the LDO in different application scenarios.

[0006] To solve the above technical problems, the present application provides a voltage regulator, comprising: an operational amplifier, a voltage stabilizing output circuit and a mode switching control circuit; wherein the non-inverting input terminal and the output terminal of the operational amplifier are connected with the voltage stabilizing output circuit;

[0007] The mode switching control circuit is used for controlling the voltage stabilizing output circuit to adjust the working mode of the voltage regulator; wherein the working mode comprises a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage;

[0008] The voltage stabilizing output circuit is configured to convert the first voltage into a second voltage under the action of the operational amplifier when the working mode is the first working mode, and output the second voltage when the working mode is the second working mode; wherein the first voltage is greater than the second voltage.

[0009] In another aspect, the mode switching control circuit includes a level shifter, a logic gate, and a control output terminal; wherein the level shifter is connected to the logic gate, and the logic gate is connected to the control output terminal.

[0010] In another aspect, the voltage stabilizing output circuit includes a first driving output circuit and a second driving output circuit; wherein the input terminal of the first driving output circuit is connected to the input terminal of the second driving output circuit, and the connected common terminal is connected to the power input terminal; the output terminal of the first driving output circuit is connected to the output terminal of the second driving output circuit, and the connected common terminal serves as the voltage stabilizing output terminal; the control terminal of the first driving output circuit and the control terminal of the second driving output circuit are respectively connected to the mode switching control circuit.

[0011] The first driving output circuit is configured to be turned on when the working mode is the first working mode according to the control of the mode switching control circuit, and convert the first voltage input by the power input terminal into the second voltage under the action of the operational amplifier, and output the second voltage through the voltage stabilizing output terminal.

[0012] The second driving output circuit is configured to be turned on when the working mode is the second working mode according to the control of the mode switching control circuit, to turn on the connection between the input terminal and the output terminal of the second driving output circuit, and output the second voltage input by the power input terminal through the voltage stabilizing output terminal.

[0013] In another aspect, the working mode further includes a third working mode when the power input terminal inputs a second voltage; wherein the voltage stabilizer supports the voltage stabilizing output terminal to access an external voltage in the third working mode, and the external voltage is less than or equal to the second voltage.

[0014] In another aspect, the first driving output circuit includes a first switch unit, a second switch unit, a first PMOS tube, a first resistor, and a second resistor.

[0015] The source of the first PMOS tube is connected with the second end of the first switch unit, and the first end of the first switch unit is connected with the power input end; the drain of the first PMOS tube is connected with the first end of the second switch unit, and the common end of the connection is as the voltage stabilizing output end; the second end of the second switch unit is connected with the first end of the first resistor, the second end of the first resistor is connected with the first end of the second resistor, and the common end of the connection is connected with the non-inverting input end of the operational amplifier; the second end of the second resistor is grounded; the gate of the first PMOS tube is connected with the output end of the operational amplifier;

[0016] The control ends of the first switch unit and the second switch unit are connected with the mode switching control circuit; when the working mode is the first working mode, the first switch unit and the second switch unit are both turned on, and under the action of the operational amplifier, the first voltage received by the first end of the first switch unit is converted into the second voltage and output through the voltage stabilizing output end; when the working mode is the second working mode or the third working mode, the first switch unit and the second switch unit are both turned off.

[0017] In another aspect, the second driving output circuit comprises a second PMOS tube, a third PMOS tube and a first NMOS tube.

[0018] The source of the second PMOS tube is connected with the source of the third PMOS tube, and the common end of the connection is connected with the power input end; the drain of the second PMOS tube is connected with the gate of the third PMOS tube, and the common end of the connection is connected with the drain of the first NMOS tube; the source of the first NMOS tube is grounded; the drain of the second PMOS tube is as the voltage stabilizing output end; the control output end of the mode switching control circuit comprises a first control output end and a second control output end;

[0019] The gate of the second PMOS tube is connected with the first control output end, and the gate of the first NMOS tube is connected with the second control output end; when the working mode is the first working mode or the third working mode, the mode switching control circuit controls the second PMOS tube to be turned on and the first NMOS tube to be turned off, so as to disconnect the third PMOS tube; when the working mode is the second working mode, the mode switching control circuit controls the second PMOS tube to be turned off and the first NMOS tube to be turned on, so as to turn on the third PMOS tube and output the second voltage input by the power input end to the voltage stabilizing output end.

[0020] In another aspect, the second driving output circuit further comprises:

[0021] An isolation circuit is arranged between the drain of the second PMOS tube and the drain of the first NMOS tube, and is configured to isolate and convert the first voltage output by the drain of the second PMOS tube into a preset voltage and output the preset voltage to the drain of the first NMOS tube when the working mode is the first working mode; wherein the preset voltage is less than or equal to the second voltage.

[0022] In another aspect, the isolation circuit comprises a third resistor, a fourth resistor and a second NMOS tube.

[0023] The drain of the second PMOS tube is connected to the gate of the third PMOS tube, and the drain of the second PMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is connected to the drain of the first NMOS tube, the first end of the third resistor is connected to the power input end, the second end of the third resistor is connected to the first end of the fourth resistor, the common end of the third resistor and the fourth resistor is connected to the gate of the second NMOS tube, and the second end of the fourth resistor is grounded.

[0024] In another aspect, the first switch unit comprises a fourth PMOS tube, the second switch unit comprises a fifth PMOS tube, the control output end of the mode switching control circuit comprises a first control output end, a second control output end, a third control output end and a fourth control output end; wherein the source of the fourth PMOS tube is connected to the power input end, the drain of the fourth PMOS tube is connected to the source of the first PMOS tube, and the gate of the fourth PMOS tube is connected to the third control output end as the control end of the first switch unit; the source of the fifth PMOS tube is connected to the drain of the first PMOS tube, the drain of the fifth PMOS tube is connected to the first end of the first resistor, and the gate of the fifth PMOS tube is connected to the fourth control output end as the control end of the second switch unit.

[0025] The first control output end, the second control output end, the third control output end and the fourth control output end are configured to control the conduction or turn-off of the MOS tubes connected thereto by outputting a first control level and / or a second control level.

[0026] The application further provides a control method of a voltage stabilizer, which is applied to the voltage stabilizer as described in any one of the preceding aspects, and comprises the following steps of:

[0027] obtaining power voltage configuration information of the voltage stabilizer; wherein the power voltage configuration information comprises a power voltage of a power input end in a voltage stabilizing output circuit of the voltage stabilizer; and the power voltage comprises a first voltage and a second voltage;

[0028] According to the power voltage configuration information, a working mode of the voltage stabilizer is determined, wherein the working mode comprises a first working mode when the power voltage is a first voltage and a second working mode when the power voltage is a second voltage;

[0029] The mode switching control circuit of the voltage stabilizer is used to control the voltage stabilizing output circuit to switch the voltage stabilizer to the working mode.

[0030] The application further provides a control device of a voltage stabilizer, which is applied to the voltage stabilizer as described in any one of the above embodiments and comprises:

[0031] The acquisition module is used to acquire power voltage configuration information of the voltage stabilizer, wherein the power voltage configuration information comprises a power voltage of a power input end in a voltage stabilizing output circuit of the voltage stabilizer, and the power voltage comprises a first voltage and a second voltage.

[0032] The determination module is used to determine a working mode of the voltage stabilizer according to the power voltage configuration information, wherein the working mode comprises a first working mode when the power voltage is the first voltage and a second working mode when the power voltage is the second voltage.

[0033] The control module is used to control the voltage stabilizing output circuit to switch the voltage stabilizer to the working mode through the mode switching control circuit of the voltage stabilizer.

[0034] In addition, the application further provides a control device of a voltage stabilizer, which comprises:

[0035] The memory is used to store a computer program.

[0036] The processor is used to execute the computer program to realize the steps of the control method of the voltage stabilizer as described above.

[0037] The voltage stabilizer provided by the application comprises an operational amplifier, a voltage stabilizing output circuit and a mode switching control circuit, wherein a non-inverting input end and an output end of the operational amplifier are connected with the voltage stabilizing output circuit, and an inverting input end of the operational amplifier is connected with a reference voltage; the mode switching control circuit is used to control the voltage stabilizing output circuit to switch a working mode of the voltage stabilizer; wherein the working mode comprises a first working mode when a power voltage is a first voltage and a second working mode when the power voltage is a second voltage, the voltage stabilizing output circuit is used to convert the first voltage into the second voltage under the action of the operational amplifier when the working mode is the first working mode, and output the second voltage through the voltage stabilizing output end when the working mode is the second working mode; wherein the first voltage is greater than the second voltage.

[0038] It can be seen that the mode switching control circuit and the stable voltage output circuit are arranged, so that the working mode of the LDO under different power supply voltages can be switched, the LDO can output stable voltage under two power supply voltages, the LDO with switchable power supply under advanced process is realized, and the applicability of the LDO in different application scenarios is improved. In addition, the application also provides a control method, device and equipment of a voltage stabilizer, which also have the beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute a part of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0040] Figure 1 A schematic diagram of the corresponding relationship between the input and output voltages of the LDO;

[0041] Figure 2 A structural block diagram of a voltage stabilizer provided by the embodiment of the present application;

[0042] Figure 3 A partial circuit display diagram of a voltage stabilizer provided by the embodiment of the present application;

[0043] Figure 4 A flowchart of a control method of a voltage stabilizer provided by the embodiment of the present application;

[0044] Figure 5 A structural block diagram of a control device of a voltage stabilizer provided by the embodiment of the present application;

[0045] Figure 6 A structural schematic diagram of a control equipment of a voltage stabilizer provided by the embodiment of the present application;

[0046] Figure 7 A structural schematic diagram of a computer readable storage medium provided by the embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0048] Please refer toFigure 2 , Figure 2 A structure block diagram of a voltage regulator is provided in the embodiments of the present application. The voltage regulator can include an operational amplifier 10, a voltage output circuit 20, and a mode switching control circuit 30; wherein the non-inverting input terminal and the output terminal of the operational amplifier 10 are connected with the voltage output circuit 20, and the inverting input terminal of the operational amplifier 10 is connected with a reference voltage (Vref);

[0049] The mode switching control circuit 30 is configured to control the voltage output circuit 20 to adjust the working mode of the voltage regulator; wherein the working mode includes a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage.

[0050] The voltage output circuit 20 is configured to, under the action of the operational amplifier 10, convert the first voltage into the second voltage and output the second voltage when the working mode is the first working mode; and output the second voltage when the working mode is the second working mode; wherein the first voltage is greater than the second voltage.

[0051] It can be understood that the voltage output circuit 20 in the embodiments can switch the working mode of the LDO according to the control of the mode switching control circuit 30, so that the voltage output terminal of the voltage output circuit 20 can output a stable second voltage in the LDO working in the first working mode or the second working mode when the power supply voltage input into the voltage output circuit 20 is the first voltage or the second voltage, thereby ensuring that the LDO can output a stable voltage under the condition of the first voltage or the second voltage. For example, the voltage output circuit 20 is configured to, under the feedback control of the operational amplifier 10, convert the first voltage input into the second voltage when the working mode is the first working mode, and output the second voltage through the voltage output terminal; and output the second voltage input into the voltage output terminal through the voltage output terminal when the working mode is the second working mode; wherein the first voltage in the embodiments can be greater than the second voltage and less than or equal to twice the second voltage, such as 3.3V for the first voltage and 1.8V for the second voltage.

[0052] Correspondingly, the specific structure of the mode switching control circuit 30 in the embodiments can be set by the designer according to the practical scene and user demand, and the mode switching control circuit 30 includes a level shifter, a logic gate, and a control output terminal; wherein the level shifter is connected with the logic gate, and the logic gate is connected with the control output terminal. The specific logic gate circuit can be set by the designer according to the practical scene and user demand, as long as it can cooperate with the level shifter to output a control output signal at the control output terminal that can control the voltage output circuit 20 to switch the working mode.

[0053] Correspondingly, for the specific structure of the voltage stabilizing output circuit 20 in the embodiment, the designer can also set it according to the practical scene, such as the voltage stabilizing output circuit 20 can include: a first driving output circuit and a second driving output circuit; wherein the input end of the first driving output circuit is connected with the input end of the second driving output circuit, and the common end of the connection is connected with the power input end; the output end of the first driving output circuit is connected with the output end of the second driving output circuit, and the common end of the connection is used as the voltage stabilizing output end; the control end of the first driving output circuit and the control end of the second driving output circuit are respectively connected with the mode switching control circuit 30; the first driving output circuit is used for turning on under the first working mode according to the control of the mode switching control circuit 30, and under the action of the operational amplifier 10, converting the first voltage input by the power input end into the second voltage and outputting the second voltage through the voltage stabilizing output end; the second driving output circuit is used for turning on under the second working mode according to the control of the mode switching control circuit 30, so as to turn on the connection between the input end and the output end of the second driving output circuit, and output the second voltage input by the power input end through the voltage stabilizing output end.

[0054] That is to say, in the embodiment, the first driving output circuit and the second driving output circuit can be set to turn on the first driving output circuit and turn off the second driving output circuit when the working mode is the first working mode, so that the first driving output circuit can convert the first voltage input by the power input end into the second voltage through the feedback control of the operational amplifier 10 and output the second voltage through the voltage stabilizing output end; and turn off the first driving output circuit and turn on the second driving output circuit when the working mode is the second working mode, so that the second driving output circuit can output the second voltage input by the power input end through the voltage stabilizing output end.

[0055] Further, in the embodiment, the working mode of the LDO can not only include the first working mode when the power input end is connected with the first voltage and the second working mode when the power input end is connected with the second voltage, but also include a third working mode when the power input end is connected with the second voltage, so that the LDO supports the voltage stabilizing output end to be connected with an external voltage in the third working mode, and the external voltage is less than or equal to the second voltage, such as the external voltage can be the second voltage.

[0056] In the embodiment, the specific circuit structure of the first driving output circuit is not limited, and the first driving output circuit can include not only the first PMOS tube, the first resistor and the second resistor for converting the first voltage into the second voltage through the feedback control of the operational amplifier 10, but also a switch unit (i.e. a first switch unit and a second switch unit) connected between the source and the drain of the first PMOS tube, so as to switch the on-off state of the first driving output circuit according to the control of the mode switching control circuit 30.

[0057] For example, as shown in Figure 3 The first driving output circuit can include a first switch unit (PM4), a second switch unit (PM5), a first PMOS tube (PM1), a first resistor (R1), and a second resistor (R1). The source of the first PMOS tube is connected to the second end of the first switch unit, and the first end of the first switch unit is connected to the power input end (VDD3318). The drain of the first PMOS tube is connected to the first end of the second switch unit, and the common end of the connection is the voltage stabilizing output end (LDOOUT18). The second end of the second switch unit is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the common end of the connection is connected to the non-inverting input end (VF end) of the operational amplifier 10. The second end of the second resistor is grounded. The gate of the first PMOS tube is connected to the output end (OP_OUT end) of the operational amplifier 10. The control ends of the first switch unit and the second switch unit are both connected to the mode switching control circuit 30. When the working mode is the first working mode, the first switch unit and the second switch unit are both turned on, and under the action of the operational amplifier 10, the first voltage received by the first end of the first switch unit is converted into a second voltage and output through the voltage stabilizing output end. When the working mode is the second working mode or the third working mode, the first switch unit and the second switch unit are both turned off.

[0058] That is, the operational amplifier 10 (such as the error amplifier EA) in the embodiment can amplify the difference between the feedback voltage (i.e., the voltage between the first resistor and the second resistor) input at the non-inverting input end and the reference voltage input at the inverting input end and output to the gate of the first PMOS tube when the first working mode, realizing feedback control of the operational amplifier 10, so that the first voltage input by the power input end can be converted into the second voltage output by the voltage stabilizing output end.

[0059] Similarly, the embodiment does not limit the specific circuit structure of the second driving output circuit. For example, the second driving output circuit can only include a third switch unit (such as a MOS tube) directly controlled by the mode switching control circuit 30 to correspondingly turn on or turn off the connection between the power input end and the voltage stabilizing output end. In order to facilitate the configuration of the mode switching control circuit 30 and the voltage resistance configuration of the circuit elements, the second driving output circuit can also include a third switch unit for turning on or turning off the connection between the power input end and the voltage stabilizing output end, and other switch units for controlling the turning on and turning off of the third switch unit according to the control of the mode switching control circuit 30.

[0060] For example, as shown in Figure 3As shown, the second driving output circuit can include a second PMOS tube (PM2), a third PMOS tube (PM3) and a first NMOS tube (NM1); that is, the mode switching control circuit 30 can control the conduction or turn-off of the second PMOS tube and the first NMOS tube, and correspondingly control the conduction or turn-off of the third PMOS tube, to realize the on-off control of the connection between the power input end and the voltage stabilizing output end. The source of the second PMOS tube is connected with the source of the third PMOS tube, and the common end of the connection is connected with the power input end; the drain of the second PMOS tube is connected with the gate of the third PMOS tube, and the common end of the connection is connected with the drain of the first NMOS tube; the source of the first NMOS tube is grounded; the drain of the second PMOS tube serves as the voltage stabilizing output end; the control output end of the mode switching control circuit includes a first control output end (hiz_enb end) and a second control output end (bypass_en18 end);

[0061] The gate of the second PMOS tube is connected with the first control output end of the mode switching control circuit 30, and the gate of the first NMOS tube is connected with the second control output end of the mode switching control circuit 30; when the working mode is the first working mode or the third working mode, the mode switching control circuit 30 controls the second PMOS tube to be turned on and the first NMOS tube to be turned off, to disconnect the third PMOS tube; when the working mode is the second working mode, the mode switching control circuit 30 controls the second PMOS tube to be turned off and the first NMOS tube to be turned on, to turn on the third PMOS tube and output the second voltage input by the power input end to the voltage stabilizing output end.

[0062] Further, in order to avoid the withstand voltage problem of the first NMOS tube when the working mode is the first working mode, the second driving output circuit can further include an isolation circuit arranged between the drain of the second PMOS tube and the drain of the first NMOS tube, for isolating and converting the first voltage output by the drain of the second PMOS tube into a preset voltage and outputting the preset voltage to the drain of the first NMOS tube when the working mode is the first working mode; wherein the preset voltage is less than or equal to the second voltage, and for example, the preset voltage can be the second voltage. That is, by arranging the isolation circuit in the embodiment, the drain of the first NMOS tube can be prevented from being directly connected with the first voltage when the working mode is the first working mode, so that the first NMOS tube can adopt a lower withstand voltage value (such as the second voltage) without overvoltage risk.

[0063] As Figure 3As shown, the isolation circuit can include a third resistor (R3), a fourth resistor (R4) and a second NMOS tube (NM2); wherein the common end of the drain of the second PMOS tube and the gate of the third PMOS tube is connected with the drain of the second NMOS tube, the source of the second NMOS tube is connected with the drain of the first NMOS tube, the first end of the third resistor is connected with the power input end; the second end of the third resistor and the first end of the fourth resistor are connected, and the common end thereof is connected with the gate of the second NMOS tube, and the second end of the fourth resistor is grounded. That is, through the voltage division of the third resistor and the fourth resistor, a suitable bias voltage can be obtained for the gate of the second NMOS tube, so that the voltage (i.e. the preset voltage) inputted by the drain of the first NMOS tube can be reduced to a lower level.

[0064] It should be noted that the MOS tubes in the circuit provided in the embodiment can all be low-voltage devices, and the withstand voltage of the low-voltage device is relatively low, and the withstand voltage of the MOS tubes in the circuit can all be less than or equal to the second voltage, and the first voltage can be less than or equal to 2 times the second voltage; for example, Figure 3 As shown, when the first voltage is 3.3V and the second voltage is 1.8V, the withstand voltage of the MOS tubes in the circuit can all be 1.8V (i.e. the second voltage), and in the case that the working mode is the first working mode, if there is no second NMOS tube (NM2), the source-drain voltage of the first NMOS tube (NM1) in this mode will reach 3.3V when the second PMOS tube (PM2) is turned on, causing NM1 to overvoltage; and after setting NM2, the drain voltage of NM1 is equal to the gate voltage of NM2 minus the VGS (gate voltage relative to source voltage) of NM2, and the gate voltage of NM2 can be appropriately biased through the setting of the third resistor (R3) and the fourth resistor (R4) to reduce the drain voltage of NM1 to a lower level, so that the source-drain voltage of NM1 is not greater than 1.8V, avoiding the overvoltage of NM1.

[0065] Correspondingly, the mode switching control circuit 30 can control the conduction or turn-off of the connected MOS tubes through the first control level and / or the second control level outputted by each control output end thereof; for example, if the first control level is greater than the second control level, then the first control level can be equal to the second voltage (such as 1.8V) or float in a small range around the second voltage, and the second control level can be equal to the third voltage (such as 0) or float in a small range around the third voltage, and the third voltage is less than the second voltage.

[0066] For example, as shown in FIG. 3, the mode switching control circuit 30 can include a first PMOS tube (PM1), a second PMOS tube (PM2), a first NMOS tube (NM1) and a second NMOS tube (NM2); wherein the source of the first PMOS tube is connected with the power input end, the drain of the first PMOS tube is connected with the gate of the second PMOS tube, the source of the second PMOS tube is connected with the gate of the first NMOS tube, the drain of the first NMOS tube is connected with the gate of the second NMOS tube, the source of the second NMOS tube is connected with the gate of the second PMOS tube, and the drain of the second PMOS tube is connected with the ground. Figure 3As shown, the first switch unit includes a fourth PMOS tube (PM4), the second switch unit includes a fifth PMOS tube (PM5), the control output end of the mode switching control circuit 30 includes a first control output end, a second control output end, a third control output end and a fourth control output end; wherein the source of the fourth PMOS tube is connected with the power input end, the drain of the fourth PMOS tube is connected with the source of the first PMOS tube, the gate of the fourth PMOS tube is connected with the third control output end (n1 end) of the mode switching control circuit 30 as the control end of the first switch unit; the source of the fifth PMOS tube is connected with the drain of the first PMOS tube, the drain of the fifth PMOS tube is connected with the first end of the first resistor, and the gate of the fifth PMOS tube is connected with the fourth control output end (n2 end) of the mode switching control circuit 30 as the control end of the second switch unit; the first control output end (hiz_enb end), the second control output end (bypass_en18 end), the third control output end (n1 end) and the fourth control output end (n2 end) of the mode switching control circuit 30 can output the first control level or the second control level, so as to control the conduction and turn-off of the connected MOS tubes (such as PM2, NM1, PM4 and PM5). Due to the increasingly advanced process, the feature size of MOS tube is reduced, the threshold of the tube is reduced, the circuit area and power consumption are reduced, the speed is increased and the chip cost is reduced, which leads to the reduction of the withstand voltage of the MOS tube. In order to ensure that the LDO voltage conversion circuit has no overvoltage risk when supplied with a high first voltage, the relatively high level (i.e. the first control level) output by the mode switching control circuit 30 in the embodiment can be greater than or equal to half of the first voltage and less than the first voltage, such as the first control level can be the second voltage.

[0067] Correspondingly, for the specific structure of the mode switching control circuit 30 in the embodiment, the designer can set it according to the practical scene and user demand, such as when the first control level is the second voltage, such as Figure 3As shown, the regulated output terminal (LDOOUT18 terminal) of the regulated output circuit 20 can be connected to the mode switching control circuit 30. The mode switching control circuit 30 is used to control the first and third control output terminals to output a first control level and the second and fourth control output terminals to output a second control level when the operating mode is the first operating mode; to control the first, second, third, and fourth control output terminals to output the first control level when the operating mode is the second operating mode; and to control the first and second control output terminals to output the second control level and the third and fourth control output terminals to output the first control level when the operating mode is the third operating mode. This embodiment does not impose any limitations on the mode switching control circuit 30 as long as it can adjust the operating mode of the voltage regulator by outputting the first and second control levels.

[0068] For example, such as Figure 3 As shown, the regulated output circuit 20 may include a first level converter (LS 1), a second level converter (LS 2), a NOR gate (G4), a first NOT gate (G1), a second NOT gate (G2), a third NOT gate (G3), a first NAND gate (G5), and a second NAND gate (G6).

[0069] The first input end of the first level shifter and the second level shifter is connected with the voltage stabilizing output end (LDOOUT18 end) of the voltage stabilizing output circuit 20, the second input end (DVDD09 end) of the first level shifter and the second level shifter receives the fourth voltage; the control input end of the first level shifter receives the first enable signal (hiz_en), for controlling the first level shifter to output the first control level or the second control level according to the first enable signal; the control input end of the second level shifter receives the second enable signal (bypas_en), for controlling the first level shifter to output the first control level or the second control level according to the first enable signal; the output end of the first level shifter is connected with the input end of the first non-inverter, the output end of the first non-inverter is connected with the input end of the second non-inverter, the output end of the second non-inverter is connected with the first input end of the NAND gate and the first input end of the first NAND gate respectively; the output end of the second level shifter is connected with the input end of the third non-inverter, the output end of the third non-inverter is connected with the second input end of the NAND gate and the first input end of the second NAND gate respectively, the output end of the NAND gate is connected with the second input end of the first NAND gate, the second input end of the second NAND gate is connected with the output end of the first non-inverter; the output end of the first non-inverter is the first control output end (hiz_enb end), the output end of the first NAND gate is the third control output end (n1 end), the output end of the NAND gate is the second control output end (bypass_en18 end), the output end of the second NAND gate is the fourth control output end (n2 end); wherein, the fourth voltage is less than the second voltage and greater than the third voltage, for example, the fourth voltage can be half of the second voltage.

[0070] Correspondingly, the processor can control the MOS tube in the voltage stabilizing output circuit 20 through the mode switching control circuit 30 by controlling the output of the first enable signal and the second enable signal, and adjust the switching of the voltage stabilizer to the required working mode; for example, when the working mode is the first working mode, the first enable signal and the second enable signal are both 0, the first level shifter and the second level shifter both output the second control level; when the working mode is the second working mode, the first enable signal is 0 and the second enable signal is 1, the first level shifter outputs the second control level and the second level shifter outputs the first control level; when the working mode is the third working mode, the first enable signal and the second enable signal are both 1, the first level shifter and the second level shifter both output the first control level.

[0071] That is, for example, Figure 3As shown, the first voltage can be 3.3V, the second voltage can be 1.8V, the third voltage can be 0V, the fourth voltage can be 0.9V, the working mode of the LOD can have three working modes of 3.3V LOD mode (i.e. the first working mode), 1.8V bypass mode (i.e. the second working mode) and the third working mode, the voltage problem occurs in the 3.3V LDO mode, the high voltage power supply of the first level shifter (LS 1) and the second level shifter (LS 2) uses the output voltage (LDOOUT 18) of the LDO, the structure is divided into PM1 and PM3 two-way power tube driving, which can be selected by different configurations, the gate of PM1 is connected to the output of the operational amplifier, Figure 3 The circuit part of the operational amplifier 10 is omitted, and the 3.3V LDO mode is driven by the PM1 branch to load; the PM3 branch drives the load in the 1.8V bypass mode.

[0072] Correspondingly, when the LDO works in the 3.3V LDO mode, the input voltage of VDD3318 (i.e. the power input end) is 3.3V (i.e. the first voltage), hiz_en and bypass_en are both configured as 0 by the register, so that hiz_enb and n1 signal are the first control level (1.8V), so PM2 and PM4 are both turned on, and the gate of PM3 is pulled up to 3.3V; bypass_en18 and n2 signal are the second control level (0), PM5 is turned on, and NM1 is cut off; at this time, the PM3 branch is turned off, and the PM1 branch is stabilized at 1.8V by the LDO loop; since the gate of PM2 and PM4 is 1.8V, the voltage difference between each pole of PM2 and PM4 will not exceed the voltage resistance value 1.8V, so there is no overvoltage risk. NM2 is used to solve the voltage resistance problem of NM1, if there is no NM2, the voltage difference between the source and drain of NM1 in this mode is 3.3V; after setting NM2, the drain voltage of NM1 is equal to the gate voltage of NM2 minus a VGS, and the gate voltage of NM2 is adjusted by R3 and R4 to a suitable bias, which can reduce the drain voltage of NM1 to a lower level.

[0073] When the LDO works in the 1.8V bypass mode, VDD3318 is 1.8V, hiz_en is configured as 0, bypass_en is configured as 1, hiz_enb and n1 signal are still high level, but the voltage is 1.8V at this time, so PM2 and PM4 are both cut off; bypass_en18 and n2 signal are high level, PM5 is cut off, and NM1 is turned on; PM1 branch is turned off, PM3 gate is pulled down to 0, PM3 is turned on, drain is pulled up to power supply, and the output is still 1.8V.

[0074] When the LDO operates in the third operating mode, configuration is only allowed when the input voltage at the power supply terminal is 1.8V. `hiz_en` is set to 1, `bypass_en` is set to 1, and at this time, `hiz_enb` and `bypass_en18` signals are 0. PM2 is turned on, NM1 is turned off, and the gate of PM3 is pulled high to the 1.8V power supply. The `n1` signal remains high at 1.8V, so both PM1 and PM3 branches are turned off. Furthermore, the `n2` signal is high, and the path from the feedback resistor to ground is also closed, ensuring no leakage current when the output is connected to an external 1.8V voltage. Figure 4 The circuit setup shown enables a switchable power supply LDO for advanced processes (i.e., low-voltage devices). It is compatible with both 1.8V and 3.3V power supplies, providing a stable 1.8V output. Even without a 3.3V power supply, it can still output a stable 1.8V using a 1.8V power supply and supports external voltage input. The gate control voltage of all MOSFETs is 1.8V at high level, and the voltage difference between the terminals of the MOSFETs in all three operating modes will not exceed the withstand voltage, effectively preventing overvoltage. In both the 3.3V LDO mode and the 1.8V bypass mode, the gate voltage of PM2 is 1.8V. With the gate voltage unchanged, PM2 can achieve two different operating states, enabling switching control between the first and second operating modes, thereby switching the circuit function.

[0075] In this embodiment, the present invention enables the LDO to switch its operating mode under different input voltage conditions by setting up the mode switching control circuit 30 and the voltage regulation output circuit 20. This allows the LDO to output a stable voltage under both input voltage conditions, realizing a power-switchable LDO under advanced technology and improving the applicability of the LDO in different application scenarios.

[0076] Corresponding to the voltage regulator embodiment above, this invention also provides a voltage regulator control method. The voltage regulator control method described below can be referred to in correspondence with the voltage regulator described above.

[0077] Please refer to Figure 4 , Figure 3 This is a flowchart illustrating a control method for a voltage regulator provided in an embodiment of the present invention. The method, applied to the voltage regulator provided in the above embodiment, may include:

[0078] Step 101: Obtain the power supply voltage configuration (i.e. power supply configuration information) of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage.

[0079] It can be understood that the power voltage configuration information of the voltage stabilizer in the embodiment can include the configuration information of the LDO power voltage in the above-mentioned embodiment, such as the power voltage of the power input end in the LDO voltage stabilizing output circuit, that is, the processor can detect whether the power voltage of the power input end in the LDO voltage stabilizing output circuit is the first voltage (for example, 3.3V) or the second voltage (for example, 1.8V), thereby corresponding to determine the working mode of the LDO.

[0080] Step 102: determining the working mode of the voltage stabilizer according to the power voltage configuration information; wherein the working mode includes a first working mode when the power voltage is the first voltage and a second working mode when the power voltage is the second voltage;

[0081] It should be noted that the processor can determine the working mode of the LDO according to the obtained power voltage configuration information of the LDO. For example, the processor can determine the working mode of the LDO as the first working mode when the power voltage of the power input end in the LDO voltage stabilizing output circuit is the first voltage, and determine the working mode of the LDO as the second working mode when the power voltage of the power input end in the LDO voltage stabilizing output circuit is the second voltage. The working mode can also be a third working mode for the second voltage power supply to support the LDO external pouring output voltage. For example, when the power voltage of the power input end in the LDO voltage stabilizing output circuit is the second voltage, the processor can determine the working mode of the LDO as the second working mode or the third working mode according to the user setting information.

[0082] Step 103: controlling the voltage stabilizing output circuit to adjust and switch the voltage stabilizer to the working mode through the mode switching control circuit of the voltage stabilizer.

[0083] It can be understood that the processor in the embodiment can control the MOS tube in the voltage stabilizing output circuit through the mode switching control circuit of the LDO to adjust and switch the LDO to the determined working mode; for example, Figure 5 As shown in the figure, the processor can control the level signals output by the first level shifter and the second level shifter by configuring the first enable signal (hiz_en) and the second enable signal (bypas_en) connected to the control input ends of the first level shifter (Level shifter1) and the second level shifter (Level shifter2) in the mode switching control circuit, to adjust the level signals output by the first control output end, the second control output end and the third control output end of the mode switching control circuit, thereby controlling the on-off of the corresponding MOS tube in the voltage stabilizing output circuit, and adjusting and switching the voltage stabilizer to the corresponding working mode.

[0084] In the embodiment, the mode switching control circuit and the voltage stabilizing output circuit of the LDO are set, the working mode of the LDO is switched according to the power supply voltage of the LDO, the LDO can output stable voltage in the two power supply voltages, the LDO with switchable power supply under advanced process is realized, and the applicability of the LDO in different application scenarios is improved.

[0085] Corresponding to the above method embodiment, the embodiment of the application further provides a control device of a voltage stabilizer. The control device of a voltage stabilizer described below can be referred to in correspondence with the control method of a voltage stabilizer described above.

[0086] Please refer to Figure 5 , Figure 6 A structural block diagram of a control device of a voltage stabilizer provided by the embodiment of the application is shown in FIG. 1. The device is applied to the voltage stabilizer provided by the above embodiment and can include:

[0087] The acquisition module 100 is configured to acquire power supply voltage configuration information of the voltage stabilizer. The power supply voltage configuration information includes the power supply voltage of the power supply input end in the voltage stabilizing output circuit of the voltage stabilizer. The power supply voltage includes a first voltage and a second voltage.

[0088] The determination module 200 is configured to determine the working mode of the voltage stabilizer according to the power supply voltage configuration information. The working mode includes a first working mode when the power supply voltage is the first voltage and a second working mode when the power supply voltage is the second voltage.

[0089] The control module 300 is configured to control the voltage stabilizing output circuit through the mode switching control circuit of the voltage stabilizer, and adjust and switch the voltage stabilizer to the working mode.

[0090] In the embodiment, the mode switching control circuit and the voltage stabilizing output circuit of the LDO are set, the working mode of the LDO is switched according to the power supply voltage of the LDO, the LDO can output stable voltage in the two power supply voltages, the LDO with switchable power supply under advanced process is realized, and the applicability of the LDO in different application scenarios is improved.

[0091] Corresponding to the above method embodiment, the embodiment of the application further provides a control device of a voltage stabilizer. The control device of a voltage stabilizer described below can be referred to in correspondence with the control method of a voltage stabilizer described above.

[0092] Please refer to Figure 6 , Figure 7 A structural block diagram of a control device of a voltage stabilizer provided by the embodiment of the application is shown in FIG. 1. The device is applied to the voltage stabilizer provided by the above embodiment and can include:

[0093] A memory D1 is configured to store a computer program.

[0094] A processor D2 is configured to execute the computer program to implement the steps of the control method of the voltage stabilizer provided by the above method embodiments.

[0095] Corresponding to the above method embodiments, the embodiments of the present application also provide a computer readable storage medium. The computer readable storage medium described below can be referred to the control method of the voltage stabilizer described above.

[0096] Please refer to Figure 7 , ​ The structure of the computer readable storage medium provided by the embodiments of the present application is shown in the figure. The computer readable storage medium 40 stores a computer program 41. The computer program 41 is executed by the processor to implement the steps of the control method of the voltage stabilizer provided by the above method embodiments.

[0097] The embodiments in the description are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other. For the method, device, equipment and computer readable storage medium disclosed by the embodiments, since they correspond to the voltage stabilizer disclosed by the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the voltage stabilizer.

[0098] The voltage stabilizer and its control method, device and equipment provided by the present application are described in detail above. The principle and implementation of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary skilled in the art, without departing from the principle of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A voltage regulator, characterized in that, include: An operational amplifier, a regulated output circuit, and a mode switching control circuit are included; wherein the non-inverting input and output terminals of the operational amplifier are connected to the regulated output circuit. The mode switching control circuit is used to control the voltage regulator output circuit to adjust and switch the operating mode of the voltage regulator; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; The voltage regulator output circuit is used to convert the first voltage into the second voltage output under the action of the operational amplifier when the operating mode is the first operating mode; and to output the second voltage when the operating mode is the second operating mode; wherein the first voltage is greater than the second voltage; The voltage-regulated output circuit includes: a first drive output circuit and a second drive output circuit; wherein, the input terminal of the first drive output circuit is connected to the input terminal of the second drive output circuit, and the common terminal of the connection is connected to the power input terminal; the output terminal of the first drive output circuit is connected to the output terminal of the second drive output circuit, and the common terminal of the connection serves as the voltage-regulated output terminal; the control terminal of the first drive output circuit and the control terminal of the second drive output circuit are respectively connected to the mode switching control circuit. The first drive output circuit is used to conduct when the working mode is the first working mode according to the control of the mode switching control circuit, and under the action of the operational amplifier, convert the first voltage input at the power input terminal into the second voltage, and output the second voltage through the regulated output terminal; The second drive output circuit is configured to be turned on when the working mode is the second working mode, according to the control of the mode switching control circuit, so as to connect the input and output terminals of the second drive output circuit and output the second voltage input by the power input terminal through the regulated output terminal.

2. The voltage regulator according to claim 1, characterized in that, The mode switching control circuit includes a level converter, a logic gate, and a control output terminal; wherein the level converter is connected to the logic gate, and the logic gate is connected to the control output terminal.

3. The voltage regulator according to claim 1, characterized in that, The operating mode also includes a third operating mode when the power input terminal receives a second voltage; wherein, in the third operating mode, the voltage regulator supports the connection of an external voltage to the regulated output terminal, and the external voltage is less than or equal to the second voltage.

4. The voltage regulator according to claim 1, characterized in that, The first drive output circuit includes: a first switching unit, a second switching unit, a first PMOS transistor, a first resistor, and a second resistor; In this configuration, the source of the first PMOS transistor is connected to the second terminal of the first switching unit, and the first terminal of the first switching unit is connected to the power input terminal; the drain of the first PMOS transistor is connected to the first terminal of the second switching unit, and the common terminal of the connection serves as the regulated output terminal; the second terminal of the second switching unit is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the first terminal of the second resistor, and the common terminal of the connection is connected to the non-inverting input terminal of the operational amplifier; the second terminal of the second resistor is grounded; and the gate of the first PMOS transistor is connected to the output terminal of the operational amplifier. The control terminals of both the first and second switching units are connected to the mode switching control circuit. When the operating mode is the first operating mode, both the first and second switching units are turned on. Under the action of the operational amplifier, the first voltage received at the first terminal of the first switching unit is converted into the second voltage and output through the regulated output terminal. When the operating mode is the second or third operating mode, both the first and second switching units are turned off. The third operating mode is the operating mode when the second voltage is input to the power input terminal. In the third operating mode, the voltage regulator supports the connection of an external sink voltage to the regulated output terminal, wherein the external sink voltage is less than or equal to the second voltage.

5. The voltage regulator according to claim 1 or 2, characterized in that, The second drive output circuit includes: a second PMOS transistor, a third PMOS transistor, and a first NMOS transistor; In this configuration, the source of the second PMOS transistor is connected to the source of the third PMOS transistor, and the common terminal of the connection is connected to the power input terminal; the drain of the second PMOS transistor is connected to the gate of the third PMOS transistor, and the common terminal of the connection is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded; the drain of the second PMOS transistor serves as the regulated output terminal; the control output terminals of the mode switching control circuit include a first control output terminal and a second control output terminal. The gate of the second PMOS transistor is connected to the first control output terminal, and the gate of the first NMOS transistor is connected to the second control output terminal. When the operating mode is either the first or third operating mode, the mode switching control circuit controls the second PMOS transistor to turn on and the first NMOS transistor to turn off, thereby disconnecting the third PMOS transistor. When the operating mode is the second operating mode, the mode switching control circuit controls the second PMOS transistor to turn off and the first NMOS transistor to turn on, thereby turning on the third PMOS transistor and outputting the second voltage input at the power input terminal to the regulated output terminal. The third operating mode is the operating mode when the second voltage is input at the power input terminal. In the third operating mode, the voltage regulator supports external voltage input to the regulated output terminal, where the external voltage is less than or equal to the second voltage.

6. The voltage regulator according to claim 5, characterized in that, The second drive output circuit also includes: An isolation circuit is provided between the drain of the second PMOS transistor and the drain of the first NMOS transistor, which is used to isolate the first voltage output from the drain of the second PMOS transistor and convert it into a preset voltage output to the drain of the first NMOS transistor when the operating mode is the first operating mode; wherein the preset voltage is less than or equal to the second voltage.

7. The voltage regulator according to claim 6, characterized in that, The isolation circuit includes: a third resistor, a fourth resistor, and a second NMOS transistor; In this configuration, the common terminal of the drain of the second PMOS transistor and the gate of the third PMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the first terminal of the third resistor is connected to the power input terminal, the second terminal of the third resistor is connected to the first terminal of the fourth resistor, their common terminal is connected to the gate of the second NMOS transistor, and the second terminal of the fourth resistor is grounded.

8. The voltage regulator according to claim 4, characterized in that, The first switching unit includes a fourth PMOS transistor, the second switching unit includes a fifth PMOS transistor, and the control output terminals of the mode switching control circuit include a first control output terminal, a second control output terminal, a third control output terminal, and a fourth control output terminal; wherein, the source of the fourth PMOS transistor is connected to the power input terminal, the drain of the fourth PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the fourth PMOS transistor serves as the control terminal of the first switching unit and is connected to the third control output terminal; the source of the fifth PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the fifth PMOS transistor is connected to the first end of the first resistor, and the gate of the fifth PMOS transistor serves as the control terminal of the second switching unit and is connected to the fourth control output terminal; The first control output terminal, the second control output terminal, the third control output terminal and the fourth control output terminal are all used to control the conduction or cutoff of their respective connected MOS transistors by outputting the first control level and / or the second control level.

9. A control method for a voltage regulator, characterized in that, Applied to the voltage regulator as described in any one of claims 1 to 8, comprising: Obtain the power supply voltage configuration information of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator's regulated output circuit; the power supply voltage includes a first voltage and a second voltage; The operating mode of the voltage regulator is determined based on the power supply voltage configuration information; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; The voltage regulator's mode switching control circuit controls the voltage regulator output circuit to switch the voltage regulator to the operating mode.

10. A control device for a voltage regulator, characterized in that, Applied to the voltage regulator as described in any one of claims 1 to 8, comprising: The acquisition module is used to acquire the power supply voltage configuration information of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage; The determining module is used to determine the operating mode of the voltage regulator based on the power supply voltage configuration information; wherein the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; The control module is used to control the regulated output circuit through the mode switching control circuit of the voltage regulator to adjust the voltage regulator to switch to the working mode.

11. A control device for a voltage regulator, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the control method for the voltage regulator as described in claim 9 when executing the computer program.

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