Digital LDO circuit suitable for large voltage difference and its voltage stabilization method

Abstract

The present invention discloses a digital LDO circuit suitable for large voltage differentials and a voltage stabilization method thereof. To address the problem that the switching characteristics of the power tubes of existing digital LDOs cannot achieve a large voltage differential and cannot meet the application scenarios where large SoCs require a low power supply voltage, the digital LDO circuit includes a mode control circuit, a coarse adjustment loop, and a fine adjustment loop. Both the coarse adjustment loop and the fine adjustment loop include an on-off controller, a decoder, a gate voltage control module, and a PMOS array. The on-off controller outputs a signal indicating the number of PMOS arrays that are turned off based on the state of the output voltage. This signal outputs a PMOS bit control signal to the gate voltage control module through the decoder. The gate voltage control module uses resistor voltage division to reduce the reference voltage as the digital ground terminal of the buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the decoder and connecting it to the PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increased voltage differential.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital LDO, and in particular relates to a digital LDO circuit suitable for large voltage difference and a voltage stabilization method thereof. Background Art

[0002] The voltage difference of common digital LDOs is relatively small, usually between 50mV and 200mV. When the voltage difference increases to around 400mV, the ripple of the digital LDO is too large and the output accuracy will be reduced.

[0003] Due to their low operating voltage, low static power consumption, and fast response, digital LDOs are widely used in systems-on-chip (SoCs) such as wearable devices, effectively improving battery life. Traditional digital LDOs utilize the switching characteristics of power transistor arrays to significantly improve their response speed and current efficiency. However, their switching characteristics also limit the gate-source voltage (Vgs) of the enabled power transistor to the power supply voltage. This results in increased current per power transistor under large voltage drops (VDO), reduced output accuracy, and excessive limit cycle oscillation (LCO) ripple in steady state, making them unsuitable for large SoC applications requiring a stable low power supply voltage.

[0004] Existing technologies typically achieve multi-precision control across low, medium, and high voltage ranges by further expanding the control loop of digital LDOs, further reducing steady-state ripple under large voltage differentials. However, this additional control loop complicates the digital LDO's control loop, increasing power consumption and settling time. Furthermore, achieving high precision under large voltage differentials requires a power transistor with a very small width-to-length ratio, resulting in a larger length and a correspondingly larger area.

[0005] Alternatively, an analog LDO can be added to a hybrid LDO architecture as a low-current analog auxiliary circuit. The analog LDO's negative feedback loop can adaptively adjust the Vgs of the power tube to accommodate increases in VDO, keeping the power tube operating in the saturation region and achieving low ripple under large voltage differentials. However, this analog LDO requires customized stability adjustment for different performance requirements and process nodes, making it difficult to quickly generate designs and process migrations. Furthermore, the addition of an analog loop increases area and power consumption, reducing LDO efficiency. Summary of the Invention

[0006] The purpose of the present invention is to provide a digital LDO circuit suitable for large voltage difference, which compensates for the increase of voltage difference by reducing the gate-source voltage, so as to solve the problem of large LCO ripple of digital LDO under large voltage difference.

[0007] In order to solve the above problems, the technical solution of the present invention is:

[0008] A digital LDO circuit suitable for large voltage difference, comprising: a mode control circuit, a coarse adjustment loop and a fine adjustment loop;

[0009] The mode control circuit is used to control the digital LDO to enter a coarse adjustment loop or a fine adjustment loop;

[0010] At least one of the coarse adjustment loop and / or the fine adjustment loop includes a coarse adjustment / fine adjustment advance and retreat controller, a first / second decoder, a first / second gate voltage control module and a PMOS switch array;

[0011] The coarse / fine adjustment controller is used to detect the state of the output voltage of the digital LDO and output a signal indicating the number of closed states of the corresponding PMOS switch array. The signal is output through the first / second decoder to output a PMOS bit control signal to the first / second gate voltage control module.

[0012] The first / second gate voltage control module is configured to use resistor voltage division to reduce the reference voltage as the digital ground of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the adapted decoder, and access the adapted PMOS switch array bit by bit to raise the gate voltage that turns on the adapted PMOS switch, thereby reducing the gate-source voltage to compensate for the increase in the voltage difference.

[0013] According to an embodiment of the present invention, the mode control circuit includes a dynamic comparator, an undershoot detection circuit, and a mode detector;

[0014] The negative phase terminal of the dynamic comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO by a resistor, and the output terminal is connected to the first input terminal of the mode detector;

[0015] The input end of the undershoot detection circuit is connected to the output voltage of the digital LDO, and the output end thereof is connected to the second input end of the mode detector;

[0016] The output end of the mode detector is connected to the coarse adjustment loop and the fine adjustment loop, and is used to control the digital LDO to enter the coarse adjustment loop or the fine adjustment loop.

[0017] According to one embodiment of the present invention, the output end of the dynamic comparator is also connected to the input end of the coarse-adjustment advance and retreat controller, and the coarse-adjustment advance and retreat controller is further configured to determine whether to change the step size for controlling the number of large-size PMOS arrays based on the output signal of the dynamic comparator in multiple consecutive clock cycles.

[0018] According to an embodiment of the present invention, the mode detector is configured to: detect the output voltage of the digital LDO in real time and adjust it; when the load current changes, the output voltage changes accordingly, causing the output voltage to deviate from the fine loop stable state. At this time, the mode detector controls the digital LDO to maintain the fine adjustment loop, that is, the fine adjustment advance and retreat method adjustment;

[0019] When the output voltage change is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the fine loop bits are exhausted. This indicates that the fine loop has entered a stable oscillation state. The fine loop is kept in slow adjustment and there is no need to activate the coarse loop.

[0020] When the output voltage change exceeds the maximum adjustment range of the fine loop, even if the fine loop adjustment bits are exhausted, the output voltage cannot be adjusted to a stable oscillation state of the fine loop. Therefore, the digital LDO is controlled to enter the coarse adjustment loop, that is, the coarse adjustment advance and retreat method.

[0021] In the coarse-tuning loop, when the output voltage oscillates continuously above and below the reference voltage for m clock cycles, it indicates that the coarse-tuning loop has entered a stable oscillation state, and the digital LDO is controlled to enter the fine-tuning loop.

[0022] According to one embodiment of the present invention, the mode control circuit is configured as follows: when the mode detector detects that the load current jumps upward by more than 10 times, the undershoot detection circuit outputs 1, directly turns on half of the thick-ring large-size PMOS, and provides current to prevent the undershoot voltage from being too large.

[0023] According to an embodiment of the present invention, the first gate voltage control module includes a buffer array, a first resistor, and a second resistor;

[0024] The input end of the buffer array is connected to the output end of the first decoder, and the output end of the buffer array is connected to the gate of the large-size PMOS array;

[0025] The source end of the buffer array is connected to the input voltage of the digital LDO, and the ground end of the buffer array is connected to the feedback voltage obtained by dividing the reference voltage by the first resistor and the second resistor.

[0026] According to an embodiment of the present invention, the coarse adjustment advance and retreat controller is configured to: detect the output signal of the dynamic comparator in the mode control circuit in real time, and when the dynamic comparator outputs 0, the coarse adjustment advance and retreat controller outputs a coarse ring PMOS shutdown quantity that decreases by a step size x;

[0027] When the output state of the dynamic comparator does not change for n consecutive clock cycles, the coarse-loop PMOS shutdown quantity is increased to a decreasing step size y, and the adjustment is continued until the output of the dynamic comparator flips, and the coarse-loop PMOS shutdown quantity is changed to an increasing step size, and the increasing step size is updated to the minimum step size x.

[0028] According to an embodiment of the present invention, the fine adjustment loop includes a fine adjustment advance and retreat controller, a second decoder, a second gate voltage control module and a small-size PMOS array connected in sequence;

[0029] The fine-tuning advance and retreat controller outputs a signal indicating the number of small-size PMOS arrays that are turned off based on the state of the digital LDO's output voltage. This signal is transmitted through the second decoder to output a PMOS bit control signal to the second gate voltage control module. The second gate voltage control module uses resistor voltage division to reduce the reference voltage as the digital ground terminal of the buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the decoder and connecting it to the small-size PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increase in the voltage difference.

[0030] A voltage stabilization method for a digital LDO circuit with a large voltage difference, comprising:

[0031] Before each load change, the digital LDO is initially in a thin-loop stable state;

[0032] When the output voltage of the digital LDO deviates from the fine-loop stable state due to load changes, the mode detector controls the digital LDO to maintain the fine-loop adjustment. If the current output voltage VOUT is less than the reference voltage VREF, the dynamic comparator outputs a signal Comp_out = 0, which controls the fine-loop controller to close the number of PMOS transistors in the output fine-loop by a step size x. After the second decoder and the corresponding second gate voltage control module, the corresponding PMOS array is controlled to open one more, performing a fine-loop slow adjustment.

[0033] If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction has not changed, the fine loop fast adjustment mode is entered, and the decrement step size of the number of fine loop PMOS shutdowns is increased to y. Adjustment is continued until Comp_out is flipped. The control direction of the fine adjustment advance and retreat controller is correspondingly changed to add, and the add step size is updated to the minimum step size x. Until Comp_out does not change for n consecutive clock cycles, the add step size is increased to y, and fine loop fast adjustment is performed;

[0034] If the digital LDO output voltage change is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the fine loop bits are exhausted. This indicates that the fine loop has entered a stable oscillation state and the fine loop is maintained at a slow adjustment speed without activating the coarse loop.

[0035] According to one embodiment of the present invention, when a load change causes the output voltage of a digital LDO to deviate from a fine-loop stable state, a mode detector initially controls the digital LDO to enter a fine-loop adjustment loop. When the load change exceeds the maximum adjustment range of the fine loop, the output voltage cannot be adjusted to a fine-loop stable oscillation state even after exhausting the fine-loop adjustment bits. Therefore, the number of fine-loop PMOS shutdowns is reset to a, and the mode detector controls the digital LDO to enter a coarse-loop adjustment loop.

[0036] In the coarse adjustment loop, if the current output voltage VOUT is less than the reference voltage VREF, the dynamic comparator outputs a signal Comp_out = 0, and the number of PMOS transistors closed in the coarse adjustment controller's output coarse adjustment is reduced by a step size x. After passing through the first decoder and the corresponding first gate voltage control module, the corresponding PMOS array is controlled to open one more, performing coarse loop slow adjustment.

[0037] If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction has not changed, the decrement step size of the number of coarse loop PMOS shutdowns is increased to y, and the adjustment is continued until Comp_out is reversed. The control direction of the coarse adjustment advance and retreat controller is correspondingly changed to add, and the add step size is updated to the minimum step size x. When Comp_out does not change for n consecutive clock cycles, the add step size is increased to y, and the coarse loop fast adjustment is entered;

[0038] When the pattern detector detects that the output voltage oscillates above and below the reference voltage for m clock cycles, it indicates that the output voltage has entered the coarse loop stable oscillation state, and the digital LDO is controlled to enter the fine loop.

[0039] When entering the fine-tuning loop, the number of PMOS transistors turned off in the coarse loop is set to the larger value of the number of PMOS transistors turned off in the coarse loop during the stable oscillation period, ensuring that the number of PMOS transistors turned off is reduced when entering the fine-tuning loop again; since the number of PMOS transistors turned off in the fine loop is initialized to a, there is enough room to ensure that the fine loop adjustment enters a steady state, thereby ensuring low ripple.

[0040] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0041] A digital LDO circuit suitable for large voltage differentials, according to one embodiment of the present invention, addresses the problem that the switching characteristics of existing digital LDO power transistors cannot achieve large voltage differentials, making them incapable of meeting the requirements of large SoC applications requiring low power supply voltages. By reducing the gate-source voltage to compensate for the increased voltage differential, the digital LDO circuit solves the problem of large LCO ripple under large voltage differentials. The digital LDO circuit includes a mode control circuit, a coarse adjustment loop, and a fine adjustment loop. Each of the coarse adjustment loop and the fine adjustment loop includes an on-off controller, a decoder, a gate voltage control module, and a PMOS array. The on-off controller outputs a signal indicating the number of PMOS arrays to be turned off based on the output voltage state. This signal, through the decoder, outputs a PMOS bit control signal to the gate voltage control module. The gate voltage control module uses resistor voltage division to reduce a reference voltage as the digital ground of a buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the decoder. The signal is then connected to the PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increased voltage differential.

[0042] Furthermore, by initializing the number of closed thin-ring transistors to a large value, sufficient margin is left to ensure that the thin-ring regulation enters a steady state, thus ensuring low ripple. Simultaneously, because the gate voltage control module raises the gate voltage of the large-size PMOS array when it is turned on, the corresponding drain-source current is reduced, increasing the regulation accuracy per unit power transistor and effectively reducing coarse and thin-ring ripple under large VOD voltage differentials. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a circuit diagram of a digital LDO suitable for large voltage difference in one embodiment of the present invention;

[0044] Figure 2 FIG. 4 is a flow chart of voltage regulation control for a digital LDO circuit suitable for large voltage difference in one embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following is a detailed description of a digital LDO circuit suitable for large voltage difference and its voltage stabilization method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0046] This embodiment provides a digital LDO circuit suitable for large voltage differentials. The large voltage differential is defined as a voltage between 200mV and VIN / 2, where VIN is the source voltage of the PMOS array. This circuit addresses the issue of large LCO ripple in digital LDOs operating under large voltage differentials by reducing the gate-source voltage to compensate for the increased voltage differential.

[0047] This digital LDO circuit, suitable for large voltage differentials, includes: a mode control circuit, a coarse adjustment loop, and a fine adjustment loop. The mode control circuit is used to control the digital LDO to enter the coarse adjustment loop or the fine adjustment loop. At least one of the coarse adjustment loop and / or the fine adjustment loop includes a coarse adjustment / fine adjustment advance / retreat controller, a first / second decoder, a first / second gate voltage control module, and a PMOS switch array. The coarse adjustment / fine adjustment advance / retreat controller is used to detect the state of the digital LDO's output voltage and output a signal indicating the number of PMOS switch arrays that are closed. This signal, through the adapted first / second decoder, outputs a PMOS bit control signal to the adapted first / second gate voltage control module. The coarse adjustment loop and / or fine adjustment loop here refer to the fact that sometimes the output voltage of the digital LDO requires both the coarse adjustment loop and the fine adjustment loop to adjust the output voltage, while sometimes only one of the coarse adjustment loop or the fine adjustment loop is required, depending on the actual situation.

[0048] The first / second gate voltage control module is configured to use resistor voltage division to reduce the reference voltage to serve as the digital ground of the buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the adapted decoder, and accessing the adapted PMOS switch array bit by bit to raise the gate voltage that turns on the adapted PMOS switch, thereby reducing the gate-source voltage to compensate for the increase in the voltage difference.

[0049] For details, please see Figure 1 The mode control circuit of the digital LDO circuit includes a dynamic comparator, a mode detector, and an undershoot detection circuit. The dynamic comparator is controlled by a clock signal CLK. The negative phase terminal of the dynamic comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO by a resistor, and the output terminal of the dynamic comparator is connected to the first input terminal of the mode detector. The input terminal of the undershoot detection circuit is connected to the output voltage of the digital LDO, and the output terminal of the undershoot detection circuit is connected to the second input terminal of the mode detector. The output terminal of the mode detector is connected to a coarse adjustment loop and a fine adjustment loop, thereby controlling the digital LDO to enter the coarse adjustment loop or the fine adjustment loop.

[0050] The output of the dynamic comparator is also connected to the input of the coarse-adjustment advance-backward controller, which is further configured to determine whether to change the step size for controlling the number of large-size PMOS arrays based on the output signal of the dynamic comparator in multiple consecutive clock cycles.

[0051] The pattern detector monitors the output voltage of the digital LDO in real time and adjusts it accordingly. When the load current changes, the output voltage changes accordingly, causing it to deviate from the fine-loop stable state. At this point, the pattern detector controls the digital LDO to maintain the fine-loop adjustment loop, using the fine-loop adjustment method. If the output voltage change is less than the maximum fine-loop adjustment range, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the fine-loop adjustment bits are exhausted. This indicates that the fine-loop stable oscillation state has been reached, and the fine-loop slow adjustment is maintained, eliminating the need to activate the coarse-loop adjustment loop. If the output voltage change exceeds the maximum fine-loop adjustment range, the output voltage cannot be adjusted to the fine-loop stable oscillation state even if the fine-loop adjustment bits are exhausted. Therefore, the digital LDO is controlled to enter the coarse-loop adjustment loop, using the coarse-loop adjustment method. In the coarse-loop adjustment loop, if the output voltage oscillates continuously above and below the reference voltage for m clock cycles, the coarse-loop stable oscillation state has been reached, and the digital LDO is controlled to enter the fine-loop adjustment loop.

[0052] Furthermore, when the mode detector detects that the load current jumps upward by more than 10 times, the undershoot detection circuit outputs 1, directly turning on half of the thick-ring large-size PMOS to provide current to prevent excessive undershoot voltage.

[0053] The coarse adjustment loop is used to quickly adjust the output voltage of the digital LDO to maintain a stable output voltage. The coarse adjustment loop includes a coarse adjustment advance / retreat controller, a first decoder, a first gate voltage control module, and a large-scale PMOS array, all connected in sequence. The coarse adjustment advance / retreat controller outputs a signal indicating the number of PMOS arrays to be closed based on the output voltage. This signal, passed through the first decoder, outputs a PMOS bit control signal to the first gate voltage control module. The first gate voltage control module uses resistor voltage division to reduce the reference voltage to serve as the digital ground of the buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the decoder. This signal is then connected to the large-scale PMOS array bit by bit, raising the gate voltage of the turned-on PMOS and reducing the gate-source voltage to compensate for the increased voltage difference.

[0054] Among them, the coarse-adjustment advance and retreat controller detects the output signal of the dynamic comparator in the mode control circuit in real time. When the dynamic comparator outputs 0, the coarse-adjustment advance and retreat controller outputs the coarse-loop PMOS shutdown quantity decreasing by step size x; when the output state of the dynamic comparator does not change for n consecutive clock cycles, the coarse-loop PMOS shutdown quantity decreasing step size is increased to y, and the adjustment is continued until the output of the dynamic comparator is flipped, and the coarse-loop PMOS shutdown quantity is changed to increasing, and the increasing step size is updated to the minimum step size x.

[0055] The first gate voltage control module includes a buffer array, a first resistor (R3), and a second resistor (R4); the input end of the buffer array is connected to the output end of the first decoder, and the output end of the buffer array is connected to the gate of the large-size PMOS array; the source end of the buffer array is connected to the input voltage of the digital LDO, and the ground end of the buffer array is connected to the feedback voltage obtained by dividing the reference voltage by the first resistor and the second resistor.

[0056] A fine-tuning loop is used to reduce LCO ripple in digital LDOs under large voltage differentials. The fine-tuning loop includes a sequentially connected fine-tuning on / off controller, a second decoder, a second gate voltage control module, and a small-size PMOS array. The fine-tuning on / off controller outputs a signal indicating the number of PMOS arrays to be turned off based on the output voltage. This signal, passed through the second decoder, outputs a PMOS bit control signal to the second gate voltage control module. The second gate voltage control module uses resistor voltage division to reduce the reference voltage to serve as the digital ground of the buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the decoder. This signal is then connected to the small-size PMOS array bit by bit, raising the gate voltage of the turned-on PMOS and reducing the gate-source voltage to compensate for the increased voltage differential.

[0057] As mentioned above, both the coarse-tuning loop and the fine-tuning loop include an advance-backward controller, a decoder, a gate voltage control module, and a PMOS array. The difference is that the coarse-tuning loop corresponds to a large-scale 2^M-bit proportional PMOS array, while the fine-tuning loop corresponds to a small-scale 2^N-bit proportional PMOS array.

[0058] When the output voltage of the digital LDO described above changes due to load changes, the following methods can be used to stabilize the output voltage:

[0059] Specifically, when the mode detector detects a change in the output voltage state, it outputs a steady-state Mode signal to control the DLDO to enter the coarse or fine adjustment loop. In the coarse or fine adjustment loop, the coarse / fine step controller detects the output voltage state and outputs M or N bit signals to indicate the number of PMOS arrays turned off. After passing through the adapted first / second decoder, 2^M or 2^N bit PMOS bit control signals are output. The first / second gate voltage control module uses resistor voltage division to step down the reference voltage as the digital ground terminal of the buffer array to raise the logical 0 voltage of the bit control signal from the decoder, and accesses the PMOS array bit by bit to raise the gate voltage of the turned-on PMOS, reducing Vgs to compensate for the increase in the voltage difference VDO. When the mode detector detects that the output voltage oscillates continuously around the reference voltage for m clock cycles, the fine adjustment loop is enabled for precise adjustment. When the fine step controller detects that the comparator output does not change for n consecutive clock cycles, the step size for controlling the number of PMOS arrays is increased from x to y to avoid misjudgment caused by logic delay.

[0060] For the voltage stabilization control process of the above digital LDO circuit, please refer to Figure 2 . Before each load change occurs, the DLDO is initially in the fine-loop stable state.

[0061] When the load current changes, the output voltage changes accordingly, causing the output voltage to deviate from the fine-loop stable state. At this time, the mode detector controls the digital LDO to maintain the fine adjustment loop, that is, the fine step adjustment.

[0062] In the fine adjustment loop, if VOUT < VREF at this time, the dynamic comparator outputs '0', and the Comp_out signal controls the output signal (the number of PMOS arrays turned off) Ctrl_F of the fine step controller to decrease by one step at a time. After passing through the second decoder and the corresponding second gate voltage control module, one more small-size PMOS array is controlled to be turned on for slow fine-loop adjustment. If VOUT is still less than VREF, this process is repeated in the next clock cycle. If the output state of the dynamic comparator does not change for 8 consecutive clock cycles, indicating that the adjustment direction has not changed, then the fine-loop fast adjustment mode is entered, and the decreasing step size of Ctrl_F is increased to 4. Continue to adjust until Comp_out flips, and the control direction of the step method changes to addition, and the addition step size also returns to the minimum step size of 1 until Comp_out does not change for 8 consecutive clock cycles and the addition step size is increased to 4. When the mode detector detects that the output voltage oscillates continuously around the reference voltage for 3 clock cycles, it indicates that the fine-loop stable oscillation state has been entered, and Mode outputs '1' to maintain the slow fine-loop adjustment.

[0063] If the digital LDO output voltage change is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for three clock cycles before the fine loop bits are exhausted. This indicates that the fine loop has entered a stable oscillation state. The fine loop is maintained at a slow adjustment speed and there is no need to enable the coarse adjustment loop.

[0064] The maximum adjustment range of the thin ring here can be obtained according to the following formula:

[0065]

[0066] Among them, V DS Refers to the maximum adjustment range of the thin ring output voltage, I DM This is the load current carried by all PMOS transistors in a thin-ring array when they are fully turned on. 2^M refers to the number of PMOS transistors in the thin-ring array, and W / L refers to the array size. All other values ​​are constants. This formula is derived from PMOS transistors operating in the linear region.

[0067] In addition, the maximum adjustment range of the thin loop will change due to many variables. When the thin loop is not enough to pull the output voltage back to the stable state of the thin loop, the coarse loop will be turned on.

[0068] When the VOUT variation exceeds the maximum fine loop regulation range, even if all fine loop regulation bits are exhausted, the output voltage cannot be regulated to a stable fine loop oscillation state. Therefore, the number of fine loop PMOS transistors turned off is reset to 24, and the mode detector controls the DLDO to enter the coarse loop. In the coarse loop, regulation is performed using the same step-and-step method as the fine loop. Once the mode detector detects stable output oscillation, the fine loop is re-entered. At this point, the coarse loop PMOS array turn-off count Ctrl_C is set to a larger value, ensuring that the number of transistors turned off is reduced when fine loop regulation is re-entered. This larger value refers to the larger of the several values ​​that the coarse loop will jump back and forth during stable oscillation. For example, if the jump is 23 -> 24 -> 23 -> 24, 24 is used. Furthermore, since the number of transistors turned off in the fine loop is always initialized to 24, sufficient margin is left to ensure that the fine loop regulation reaches a stable state, thereby ensuring low ripple.

[0069] When the mode detector detects a load current jump of more than 10 times, such as from 10uA to 100uA, the undershoot detection circuit outputs a '1', directly turning on half of the large-scale PMOS transistors in the thick ring to provide current and prevent large undershoot voltages. Simultaneously, because the gate voltage control module raises the gate voltage of the enabled large-scale PMOS array, the corresponding drain-source current is reduced, increasing the regulation accuracy of each power transistor and reducing the ripple of the thick and thin rings under large voltage differences.

[0070] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the scope of protection of the present invention.

Claims

1. A digital LDO circuit suitable for large voltage difference, characterized in that: include: Mode control circuit, coarse adjustment loop and fine adjustment loop; The mode control circuit is used to control the digital LDO to enter a coarse adjustment loop or a fine adjustment loop; At least one of the coarse adjustment loop and / or the fine adjustment loop includes a coarse adjustment / fine adjustment advance and retreat controller, a first / second decoder, a first / second gate voltage control module and a PMOS switch array; The coarse / fine adjustment advance / retreat controller is used to detect the state of the output voltage of the digital LDO and output a signal indicating the number of closed states of the corresponding PMOS switch array. The signal is output through the adapted first / second decoder to output a PMOS bit control signal to the adapted first / second gate voltage control module; The first / second gate voltage control module is configured to use resistor voltage division to reduce the reference voltage as the digital ground of the buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the adapted first / second decoder, and accessing the adapted PMOS switch array bit by bit to raise the gate voltage for turning on the adapted PMOS switch, thereby reducing the gate-source voltage to compensate for the increase in the voltage difference.

2. The digital LDO circuit suitable for large voltage difference according to claim 1, characterized in that: The mode control circuit includes a dynamic comparator, an undershoot detection circuit and a mode detector; The negative phase terminal of the dynamic comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO by a resistor, and the output terminal is connected to the first input terminal of the mode detector; The input end of the undershoot detection circuit is connected to the output voltage of the digital LDO, and the output end thereof is connected to the second input end of the mode detector; The output end of the mode detector is connected to the coarse adjustment loop and the fine adjustment loop, and is used to control the digital LDO to enter the coarse adjustment loop or the fine adjustment loop.

3. The digital LDO circuit suitable for large voltage difference according to claim 2, characterized in that: The coarse adjustment loop includes a coarse adjustment advance and retreat controller, a first decoder, a first gate voltage control module and a large-size PMOS array connected in sequence; The output end of the dynamic comparator is also connected to the input end of the coarse-adjustment advance and retreat controller, and the coarse-adjustment advance and retreat controller is further configured to determine whether to change the step size of controlling the number of large-size PMOS arrays based on the output signal of the dynamic comparator in multiple consecutive clock cycles.

4. The digital LDO circuit suitable for large voltage difference according to claim 2, characterized in that: The mode detector is configured to: detect the output voltage of the digital LDO in real time and adjust it; when the load current changes, the output voltage changes accordingly, causing the output voltage to leave the fine loop stable state, at which time the mode detector controls the digital LDO to maintain the fine loop; When the output voltage change is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the fine loop bits are exhausted. This indicates that the fine loop has entered a stable oscillation state. The fine loop is kept in slow adjustment and there is no need to activate the coarse loop. When the output voltage change exceeds the maximum adjustment range of the fine loop, even if the fine loop adjustment bits are exhausted, the output voltage cannot be adjusted to a stable oscillation state of the fine loop, so the digital LDO is controlled to enter the coarse adjustment loop; In the coarse-tuning loop, when the output voltage oscillates continuously above and below the reference voltage for m clock cycles, it indicates that the coarse-tuning loop has entered a stable oscillation state, and the digital LDO is controlled to enter the fine-tuning loop.

5. The digital LDO circuit suitable for large voltage difference according to claim 2, characterized in that: The mode control circuit is configured such that when the mode detector detects that the load current jumps upward by more than 10 times, the undershoot detection circuit outputs 1, directly turning on half of the thick-ring large-size PMOS to provide current to prevent excessive undershoot voltage.

6. The digital LDO circuit suitable for large voltage difference according to claim 3, characterized in that: The first gate voltage control module includes a buffer array, a first resistor, and a second resistor; The input end of the buffer array is connected to the output end of the first decoder, and the output end of the buffer array is connected to the gate of the large-size PMOS array; The source end of the buffer array is connected to the input voltage of the digital LDO, and the ground end of the buffer array is connected to the feedback voltage obtained by dividing the reference voltage by the first resistor and the second resistor.

7. The digital LDO circuit suitable for large voltage difference according to claim 3, characterized in that: The coarse adjustment advance and retreat controller is configured to: detect the output signal of the dynamic comparator in the mode control circuit in real time, and when the dynamic comparator outputs 0, the coarse adjustment advance and retreat controller outputs a coarse ring PMOS shutdown quantity that decreases by a step size x; When the output state of the dynamic comparator does not change for n consecutive clock cycles, the coarse-loop PMOS shutdown quantity is increased to a decreasing step size y, and the adjustment is continued until the output of the dynamic comparator flips, and the coarse-loop PMOS shutdown quantity is changed to an increasing step size, and the increasing step size is updated to the minimum step size x.

8. The digital LDO circuit suitable for large voltage difference according to claim 1, wherein: The fine adjustment loop includes a fine adjustment advance and retreat controller, a second decoder, a second gate voltage control module and a small-size PMOS array connected in sequence; The fine-tuning advance and retreat controller outputs a signal indicating the number of small-size PMOS arrays that are turned off based on the state of the digital LDO's output voltage. This signal is transmitted through the second decoder to output a PMOS bit control signal to the second gate voltage control module. The second gate voltage control module uses resistor voltage division to reduce the reference voltage as the digital ground terminal of the buffer array, thereby raising the logic 0 voltage of the PMOS bit control signal from the decoder and connecting it to the small-size PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increase in the voltage difference.

9. The voltage stabilization method for a digital LDO circuit with a large voltage difference according to any one of claims 1 to 8, wherein: include: Before each load change, the digital LDO is initially in a thin-loop stable state; When the output voltage of the digital LDO deviates from the fine-loop stable state due to load changes, the mode detector controls the digital LDO to maintain the fine-loop adjustment. If the current output voltage VOUT is less than the reference voltage VREF, the dynamic comparator outputs a signal Comp_out = 0, which controls the fine-loop controller to close the number of PMOS transistors in the output fine loop by a step size x. After the second decoder and the corresponding second gate voltage control module, the corresponding PMOS array is controlled to open one more, performing a slow fine-loop adjustment. If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction has not changed, the fine loop fast adjustment mode is entered, and the decrement step size of the number of fine loop PMOS shutdowns is increased to y. Adjustment is continued until Comp_out is flipped. The control direction of the fine adjustment advance and retreat controller is correspondingly changed to add, and the add step size is updated to the minimum step size x. Until Comp_out does not change for n consecutive clock cycles, the add step size is increased to y, and fine loop fast adjustment is performed; If the digital LDO output voltage change is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the fine loop bits are exhausted. This indicates that the fine loop has entered a stable oscillation state and the fine loop is maintained at a slow adjustment speed without activating the coarse loop.

10. The voltage stabilization method for a digital LDO circuit with a large voltage difference according to claim 9, wherein: When the output voltage of the digital LDO changes due to load changes and exceeds the maximum adjustment range of the fine loop, the mode detector initially controls the digital LDO to enter the fine adjustment loop. When the fine loop adjustment bits are exhausted and the output voltage cannot be adjusted to the fine loop stable oscillation state, the number of fine loop PMOS shutdowns is reset to a, and the mode detector controls the digital LDO to enter the coarse adjustment loop. In the coarse adjustment loop, if the current output voltage VOUT is less than the reference voltage VREF, the dynamic comparator outputs a signal Comp_out of 0, which controls the coarse adjustment controller to close the number of PMOS transistors in the coarse loop by a step size x. After passing through the first decoder and the corresponding first gate voltage control module, the corresponding PMOS array is controlled to open one more PMOS transistor, thus performing coarse loop slow adjustment. If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction has not changed, the decrement step size of the number of coarse loop PMOS shutdowns is increased to y, and the adjustment is continued until Comp_out is reversed. The control direction of the coarse adjustment advance and retreat controller is correspondingly changed to add, and the add step size is updated to the minimum step size x. When Comp_out does not change for n consecutive clock cycles, the add step size is increased to y, and the coarse loop fast adjustment is entered; When the pattern detector detects that the output voltage oscillates above and below the reference voltage for m clock cycles, it indicates that the output voltage has entered the coarse loop stable oscillation state, and the digital LDO is controlled to enter the fine loop. When entering the fine-tuning loop, the number of PMOS transistors turned off in the coarse loop is set to the larger value of the number of PMOS transistors turned off in the coarse loop during the stable oscillation period, ensuring that the number of PMOS transistors turned off is reduced when entering the fine-tuning loop again; since the number of PMOS transistors turned off in the fine loop is initialized to a, there is enough room to ensure that the fine loop adjustment enters a steady state, thereby ensuring low ripple.

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